Display device

Abstract

There is provided a display device including: a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels arranged on the substrate in the display area; a plurality of driver groups spaced apart from each other in the non-display area; and a dummy driver located between two adjacent driver groups among the plurality of driver groups. A driver group among the plurality of driver groups includes a first driver and a second driver. Each of the at least one first sub-driver of the first driver is connected to m output lines connected to some of the plurality of pixels, and each of the at least one second sub-driver of the second driver is connected to n output lines connected to some of the plurality of pixels. When the least common multiple of m and n is o, the driver group comprises o / m first sub-drivers and o / n second sub-drivers.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0076613, filed with the Korean Intellectual Property Office on June 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device including pixels and drivers. Background Technology

[0004] The display device includes multiple pixels, a gate driving circuit, a data driving circuit, etc. The gate driving circuit includes multiple stages connected to output lines, and the multiple stages supply multiple gate signals to multiple output lines connected to the multiple stages. Summary of the Invention

[0005] A portion of the display device may be flexible. For example, the display device may include rounded corners. That is, corner areas within the outer region of the display device may be flexible. When drive circuitry is positioned along such corner areas, output deviations may occur because the distances between multiple drive circuits or between multiple drivers of each drive circuit may not be constant. Therefore, one or more embodiments include display devices in which such output deviations are mitigated.

[0006] The technical problems to be solved by one or more embodiments are not limited to the technical problems described above, and those skilled in the art can anticipate other technical problems that can be solved by one or more embodiments based on the description of one or more embodiments.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practicing the embodiments proposed in this disclosure.

[0008] According to one or more embodiments, a display device includes a substrate including a display area and a non-display area surrounding the display area, a plurality of pixels arranged on the substrate in the display area, a plurality of driver groups spaced apart from each other in the non-display area, and a dummy driver located between two adjacent driver groups among the plurality of driver groups. One driver group among the plurality of driver groups includes a first driver and a second driver. Each of at least one first sub-driver of the first driver is connected to m output lines connected to some of the plurality of pixels, and each of at least one second sub-driver of the second driver is connected to n output lines connected to some of the plurality of pixels, where m and n are integers greater than 0. When a least common multiple of m and n is o, the one driver group includes o / m first sub-drivers and o / n second sub-drivers.

[0009] In an embodiment, each of the at least one first sub-driver can include a control stage and m output stages. The control stage can be connected to an input terminal into which a start signal is input, a first voltage input terminal into which a first voltage is input, and a second voltage input terminal into which a second voltage is input, and can control a voltage of a first node and a voltage of a second node. Each of the m output stages can be connected to an output terminal connected to a corresponding output line among the m output lines, and the m output stages can be connected to the first node and the second node and share the control stage.

[0010] In an embodiment, the m output stages can be spaced apart from each other at regular intervals.

[0011] In an embodiment, the control stage can include a first transistor connected to the input terminal and the first node and including a gate connected to a first clock terminal into which one of a plurality of clock signals is input, a second transistor connected to the second node and the first clock terminal and including a gate connected to the first node, and a third transistor connected to the second voltage input terminal and the second node and including a gate connected to the first clock terminal.

[0012] In an embodiment, the first transistor can include a 1-1 transistor and a 1-2 transistor. The 1-1 transistor can be connected to the input terminal and the 1-2 transistor, the 1-2 transistor can be connected to the first node and the 1-1 transistor, and the gate of the 1-1 transistor and the gate of the 1-2 transistor can be connected to the first clock terminal.

[0013] In an embodiment, each of the m output stages can include a fourth transistor connected to the first voltage input terminal and the output terminal and including a gate connected to the second node, a fifth transistor connected to the output terminal and a second clock terminal into which another of the plurality of clock signals is input, and including a gate connected to the third node, and a sixth transistor connected to the first node and the third node and including a gate connected to the second voltage input terminal.

[0014] In an embodiment, at least one of the m output stages can further include at least one of a first capacitor connected to the first voltage input terminal and the second node and a second capacitor connected to the output terminal and the third node.

[0015] In an embodiment, o / m can be a natural number greater than or equal to 2, and one of the m output stages of one of the o / m first sub-drivers can be connected to a control stage of another of the o / m first sub-drivers.

[0016] In an embodiment, the non-display area can include a corner area adjacent to a corner of the substrate, and the plurality of driver groups can be arranged in the corner area.

[0017] In an embodiment, at least one of the m output lines connected to the first sub-driver and at least one of the n output lines connected to the second sub-driver can be connected to the same pixel.

[0018] According to one or more embodiments, a display apparatus includes a substrate including a display area and a non-display area surrounding the display area, a plurality of pixels arranged on the substrate in the display area, and a driver group arranged in the non-display area and connected to at least one of the plurality of pixels. A first driver of the driver group can include a control stage and m output stages sharing the control stage, and at least some of the m output stages can be spaced apart from each other at regular intervals. m can be an integer greater than 0.

[0019] In an embodiment, the control stage can be connected to an input terminal into which a start signal is input, a first voltage input terminal into which a first voltage is input, and a second voltage input terminal into which a second voltage is input, and can control a voltage of the first node and a voltage of the second node. Each of the m output stages can be connected to an output terminal configured to output an output signal to a corresponding output line, and the m output stages can be connected to the first node and the second node and share the control stage.

[0020] In an embodiment, the control stage can include a first transistor connected to the input terminal and the first node, and including a gate connected to a first clock terminal to which one of the plurality of clock signals is input, a second transistor connected to the second node and the first clock terminal, and including a gate connected to the first node, and a third transistor connected to the second voltage input terminal and the second node, and including a gate connected to the first clock terminal.

[0021] In an embodiment, each of the m output stages can include a fourth transistor connected to the first voltage input terminal and the output terminal, and including a gate connected to the second node, a fifth transistor connected to the output terminal and a second clock terminal to which another of the plurality of clock signals is input, and including a gate connected to the third node, and a sixth transistor connected to the first node and the third node, and including a gate connected to the second voltage input terminal.

[0022] In an embodiment, at least one of the m output stages can further include at least one of a first capacitor connected to the first voltage input terminal and the second node, and a second capacitor connected to the output terminal and the third node.

[0023] In an embodiment, the driver group can include at least two first sub-drivers, and the output terminal of one of the m output stages of one of the at least two first sub-drivers can be connected to the input terminal of the control stage of another of the at least two first sub-drivers.

[0024] In an embodiment, the non-display area can include a corner area adjacent to a corner of the substrate, and the driver group can be disposed in the corner area.

[0025] In an embodiment, the driver group can include at least one second sub-driver each connected to n output lines connected to some of the plurality of pixels, and n can be an integer greater than 0.

[0026] In an embodiment, when the least common multiple of m and n can be o, the driver group can include o / m first sub-drivers and o / n second sub-drivers.

[0027] In an embodiment, the display apparatus can include a plurality of driver groups including the driver group, and a dummy driver between two adjacent ones of the plurality of driver groups. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0030] Figure 2 is an enlarged plan view of a portion of a display device according to an embodiment.

[0031] Figure 3 is an enlarged plan view of a portion of a display device according to an embodiment.

[0032] Figure 4 is a schematic view of a drive circuit according to an embodiment.

[0033] Figure 5 is an equivalent circuit diagram of a sub-driver according to an embodiment.

[0034] Figure 6 is an equivalent circuit diagram of a sub-driver according to an embodiment.

[0035] Figure 7A and Figure 7B is an equivalent circuit diagram of a sub-driver according to an embodiment.

[0036] Figure 8 is an enlarged plan view of a portion of a display device according to an embodiment.

[0037] Figure 9 is a schematic view of a drive circuit according to an embodiment.

[0038] Figure 10 is an equivalent circuit diagram of a driver according to an embodiment.

[0039] Figure 11 is an equivalent circuit diagram of a driver according to an embodiment.

[0040] Figure 12 is an enlarged plan view of a portion of a display device according to an embodiment.

[0041] Figure 13 is a schematic view of a drive circuit according to an embodiment.

[0042] Figure 14 is an equivalent circuit diagram of a driver according to an embodiment.

[0043] Figure 15 is an equivalent circuit diagram of a driver according to an embodiment. DETAILED DESCRIPTION

[0044] Since the present disclosure allows various changes and numerous implementations, certain implementations will be illustrated in the drawings and described in the written description below. The effects and features of one or more implementations will become apparent from the following detailed description of one or more implementations, given by way of example in conjunction with the accompanying drawings. However, the one or more implementations can have different forms and should not be construed as being limited to the descriptions set forth herein.

[0045] Although such terms as "first" and "second" can be used to describe various elements, the elements are not limited to the above terms. The above terms are used only to distinguish one element from another.

[0046] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] The terms "include," "comprise" and "have," as used herein, specify the presence of stated features or elements but do not preclude the presence or addition of one or more other features or elements.

[0048] When a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly or indirectly on the other layer, region, or element. That is, for example, a further layer, region, or element can be interposed between them. The same applies to expressions such as "below," "on the left of," and "on the right of."

[0049] For ease of explanation, the sizes of the elements in the drawings can be exaggerated or reduced. For example, since the sizes and thicknesses of the elements in the drawings are arbitrarily illustrated for ease of explanation, the following implementations are not limited thereto.

[0050] The expression "A and / or B" means "A," "B," or "A and B." The expression "at least one of A and B" means "A," "B," or "A and B."

[0051] The case where A and B are connected can include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. In this case, A and B can be certain objects (for example, devices, elements, circuits, wires, electrodes, terminals, conductive films, etc.). Thus, the connection is not limited to a specific connection, such as that shown in the drawings or described in the detailed description, and can also include other connections.

[0052] The case where A and B are electrically connected to each other can include, for example, the case where at least one element (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, etc.) capable of achieving electrical connection between A and B is connected between A and B.

[0053] In the following embodiments, the term "on" used in connection with the state of a device can refer to an active state of the device, and the term "off" can refer to an inactive state of the device. The term "on" used in connection with a signal received by a device can refer to a signal that activates the device, and the term "off" can refer to a signal that deactivates the device. A device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Accordingly, it is understood that the "on" voltage for the P-type transistor and the N-type transistor are opposite (low vs. high) voltage levels.

[0054] In the following embodiments, the x-direction, the y-direction, and the z-direction are not limited to directions along three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x-direction, the y-direction, and the z-direction can be orthogonal to each other, or can alternatively refer to different directions that are not orthogonal to each other.

[0055] The display device according to an embodiment can be a device for displaying a moving image or a still image, and can be used not only as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC), but also as a display screen of various products such as a television, a notebook computer, a monitor, a billboard, and an Internet of things (IoT) device. Furthermore, the display device according to an embodiment can be used for a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD). Furthermore, the display device according to an embodiment can be used for an instrument panel of a vehicle, a central information display (CID) arranged on a center console or an instrument panel of a vehicle, a mirror display that replaces a side mirror of a vehicle, or a display arranged on a back of a front seat of a vehicle for entertainment of rear seat passengers in a vehicle. Furthermore, the display device can be a flexible device.

[0056] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0057] Referring to Figure 1 , the display device 10 can include a display area DA in which an image is displayed and a non-display area NDA outside the display area DA. The display area DA can be surrounded by the non-display area NDA.

[0058] In a plan view of the display device 10, the display device 10 can have a substantially rectangular shape. In an embodiment, the display device 10 can have a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, a circular shape, an elliptical shape, or an irregular shape. The display device 10 can have rounded corners. In an embodiment, the display device 10 can have a shape in which a length in the y direction is greater than a length in the x direction, as shown in FIG. 1A. In an embodiment, the display device 10 can have a shape in which a length in the x direction is longer than a length in the y direction. Figure 1

[0059] The display device 10 can include a display panel, and can include a cover window disposed above the display panel to protect the display panel. Various components of the display device 10 can be disposed on the substrate 100. The substrate 100 can include a display area DA and a non-display area NDA surrounding the display area DA.

[0060] A plurality of pixels PX can be disposed in the display area DA. A plurality of scan lines SL, a plurality of data lines DL, and a plurality of pixels PX connected to the plurality of scan lines SL and the plurality of data lines DL can be disposed in the display area DA. The plurality of pixels PX can be arranged in any one of various forms such as a stripe arrangement, a Pentile arrangement, a diamond arrangement, or a mosaic arrangement to implement an image. Each pixel PX includes a light-emitting diode (LED) as a display element (light-emitting device), and the light-emitting diode can be connected to a pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. The pixel PX can emit, for example, red light, green light, blue light, or white light through the light-emitting diode. Each pixel PX can be connected to a corresponding scan line SL among the plurality of scan lines SL and a corresponding data line DL among the plurality of data lines DL.

[0061] The plurality of scan lines SL can each extend in the x direction (row direction) and be connected to a plurality of pixels PX disposed in the same row. The plurality of scan lines SL can each be configured to transmit a scan signal to the plurality of pixels PX in the same row. The plurality of data lines DL can each extend in the y direction (column direction) and be connected to a plurality of pixels PX located in the same column. The plurality of data lines DL can each be configured to transmit a data signal to each of the plurality of pixels PX in the same column in synchronization with the scan signal. Each pixel PX can be connected to a driving voltage line PL to receive a driving voltage. The plurality of driving voltage lines PL can each extend in the y direction (column direction) and be connected to a plurality of pixels PX arranged in the same column. Figure 1 An example in which a pixel PX is connected to one scan line SL is shown, but the disclosure is not limited thereto. A pixel PX can be connected to a plurality of scan lines SL. Each of a plurality of pixel circuits driving a plurality of pixels PX can be electrically connected to a plurality of external circuits arranged in the non-display area NDA. ​

[0062] The non-display area NDA can completely surround the display area DA. An external circuit (a driver circuit) configured to transmit a driving signal to a pixel circuit configured to drive the above-described pixel PX can be arranged in the non-display area NDA. The non-display area NDA can include a side area SA at a side of the display area DA and a corner area CNA at a corner of the display area DA. In an embodiment, the side area SA can include a first side area SA1 in an x direction of the display area DA and a second side area SA2 in a y direction of the display area DA. In an embodiment, the first side area SA1 and the second side area SA2 can contact each other at the corner area CNA. The above-described external circuit (driver circuit) can be arranged in the side area SA (e.g., the first side area SA1 and the second side area SA2) and / or the corner area CNA.

[0063] Figure 2 is a magnified plan view of a portion of the display device according to an embodiment, and in particular, Figure 2 is a magnified plan view of a corner area CNA of the display device 10.

[0064] Referring to Figure 1 and Figure 2 A plurality of driver groups DRS can be arranged in the corner area CNA of the display device 10. In an embodiment, a dummy driver DM can be arranged between two adjacent driver groups DRS. In an embodiment, a dummy driver DM can not be arranged between two adjacent driver groups DRS, and in this case, two adjacent driver groups DRS can be spaced apart from each other.

[0065] In an embodiment, the plurality of driver groups DRS can be connected to the plurality of pixels PX located in the display area DA of the display device 10. In an embodiment, the plurality of driver groups DRS can be connected to the plurality of output lines, and the plurality of output lines can be respectively connected to the plurality of scan lines SL and to the plurality of pixels PX described above. In an embodiment, each first sub-driver (e.g., 1st-1 driver DR1-1 to 1st-p driver DR1-p) in the first driver DR1 of each driver group DRS can be connected to 1st-1 output line 1OL1 to 1st-m output line 1OLm. In an embodiment, each second sub-driver (e.g., 2nd-1 driver DR2-1 to 2nd-q driver DR2-q) in the second driver DR2 of each driver group DRS can be connected to 2nd-1 output line 2OL1 to 2nd-n output line 2OLn. In the present disclosure, the 2nd-1 output line 2OL1 to the 2nd-n output line 2OLn are shown to be within the driver group DRS (or within the corner area CNA), but this is for the convenience of illustration and description, and the present disclosure is not limited thereto. The dummy driver DM can not be connected to the output line (e.g., the first output line or the second output line). The first output line can include 1st-1 output line 1OL1 to 1st-o output line 1OLo, and the second output line can include 2nd-1 output line 2OL1 to 2nd-n output line 2OLn. In the present application, the first can be equivalent to 1st and 1.1-1 can be equivalent to 1st-1, and so on.

[0066] In the following description, o can be the least common multiple (LCM) of m and n, p can be a value obtained by dividing o by m, and q can be a value obtained by dividing o by n. That is, o = lcm{m, n}, p = o / m, and q = o / n, where m, n, and o are positive integers greater than 0.

[0067] In an embodiment, each driver group DRS can include the first driver DR1. In an embodiment, the first driver DR1 of the driver group DRS can include 1st-1 driver DR1-1 to 1st-p driver DR1-p.

[0068] In an embodiment, each first sub-driver in the first driver DR1 can include one control stage and m output stages. For example, the 1st-1 driver DR1-1 can include a first control stage CST1 and first output stage OST1 to m-th output stage OSTm. In another example, the 1st-p driver DR1-p can include p-th control stage CSTp and (m*k+1)-th output stage OSTmk+1 to o-th output stage OSTo. Thus, one driver group DRS can include first control stage CST1 to p-th control stage CSTp and a total of p*m output stages, i.e., first output stage OST1 to o-th output stage OSTo.

[0069] In an embodiment, each output stage of the first drivers DR1 can be connected to a respective first output line. For example, the first output stage OST1 to the mth output stage OSTm of the 1st-1 driver DR1-1 can be connected to the respective 1st-1 output line 1OL1 to the 1st-m output line 1OLm, respectively. In another example, the (mk+1)th output stage OSTmk+1 to the oth output stage OSTo of the 1st-p driver DR1-p can be connected to the respective 1st-mk+1 output line 1OLmk+1 to the 1st-o output line 1OLo, respectively. Thus, one driver group DRS can be connected to the 1st-1 output line 1OL1 to the 1st-o output line 1OLo.

[0070] In an embodiment, the m output stages of each first sub-driver in the first drivers DR1 can be connected to one respective control stage. For example, the first output stage OST1 to the mth output stage OSTm of the 1st-1 driver DR1-1 can be connected to the respective first control stage CST1. In another example, the (mk+1)th output stage OSTmk+1 to the oth output stage OSTo of the 1st-p driver DR1-p can be connected to the respective pth control stage CSTp.

[0071] In an embodiment, the plurality of first sub-drivers in the first drivers DR1 in a driver group DRS can be arranged at regular intervals. For example, at least some of the 1st-1 driver DR1-1 to the 1st-p driver DR1-p of the driver group DRS can be arranged at regular intervals. In an embodiment, the m output stages of each first sub-driver in the first drivers DR1 can be arranged at regular intervals. For example, at least some of the first output stage OST1 to the mth output stage OSTm of the 1st-1 driver DR1-1 can be arranged at regular intervals. In another example, at least some of the (mk+1)th output stage OSTmk+1 to the oth output stage OSTo of the 1st-p driver DR1-p can be arranged at regular intervals.

[0072] In an embodiment, each driver group DRS can include a second driver DR2. In an embodiment, the second drivers DR2 of the driver group DRS can include a 2nd-1 driver DR2-1 to a 2nd-q driver DR2-q.

[0073] In an embodiment, each of the second sub-drivers in the second driver DR2 can be connected to a respective 2nd-1 output line 2OL1 to 2nd-n output line 2OLn. For example, the 2nd-1 driver DR2-1 can be connected to a respective 2nd-1 output line 2OL1 to 2nd-n output line 2OLn. In another example, the 2nd-q driver DR2-q can be connected to a respective 2nd-1 output line 2OL1 to 2nd-n output line 2OLn. Thus, one driver group DRS can be connected to a total of q*n output lines, i.e., o output lines.

[0074] In an embodiment, some of the 1st-1 output line 1OL1 to 1st-m output line 1OLm and the 2nd-1 output line 2OL1 to 2nd-n output line 2OLn connected to the driver group DRS can be connected to the same pixel PX. For example, some of the 1st-1 output line 1OL1 to 1st-m output line 1OLm connected to the 1st-1 driver DR1-1 and some of the 2nd-1 output line 2OL1 to 2nd-n output line 2OLn connected to the 2nd-1 driver DR2-1 can be connected to the same pixel PX.

[0075] In an embodiment, the plurality of driver groups DRS can be arranged along a curve of the corner area CNA. For example, adjacent driver groups DRS can be rotated by a certain angle about a certain axis (e.g., the z-direction axis). In an embodiment, a distance by which the plurality of driver groups DRS are spaced apart from each other in an area away from the display area DA can be greater than a distance by which the plurality of driver groups DRS are spaced apart from each other in an area close to the display area DA. In other words, the distance between the plurality of driver groups DRS can increase away from the display area DA. This can be attributed to the rounded corner shape of the display device 10.

[0076] The above description can be summarized as follows.

[0077] A driver group of a display device of the present disclosure can include at least one first sub-driver and at least one second sub-driver. The first sub-driver can include one control stage and m output stages, and each output stage can be connected to a respective first output line. Thus, the first sub-driver can be connected to m first output lines. The second sub-driver can be connected to n second output lines. A least common multiple of m and n can be defined as o. A value of o / m can be defined as p. A value of o / n can be defined as q. p first sub-drivers and q second sub-drivers can be grouped into one driver group. o first output lines and n second output lines can be connected to one driver group. Within one driver group, the plurality of sub-drivers can be arranged at regular intervals. Each driver group can be spaced apart from another driver group at regular intervals.

[0078] In other words, the idea of the present disclosure is to find the least common multiple of the number of output lines connected to the respective sub-drivers, and then to group a number of sub-drivers into one driver group, which corresponds to the value obtained by dividing the least common multiple by the number of output lines of each sub-driver. The arrangement interval of the plurality of sub-drivers within one driver group can be regular. Thus, the phenomenon of output deviation occurring between the plurality of output lines connected to one sub-driver can be prevented or at least reduced.

[0079] In the present disclosure, a case in which two types of drivers (e.g., the first driver and the second driver) are included in the driver group is shown and described, but this is not intended to exclude a case in which the driver group includes three or more types of drivers. As will be clear to one of ordinary skill in the art from the present disclosure, the idea of the present disclosure can be applied to an embodiment including additional drivers (e.g., a third driver to an i-th driver).

[0080] Hereinafter, some embodiments will be described with reference to the drawings showing a case in which the above-described m, n, o, p, and q have certain values. It is obvious that the present disclosure is not necessarily limited to the embodiments described below.

[0081] Figure 3 is a magnified plan view of a portion of a display device according to an embodiment. Figure 4 is a schematic view of a driving circuit according to an embodiment. Figure 5 to Figure 7A and Figure 7B is an equivalent circuit diagram of a sub-driver according to an embodiment.

[0082] In the embodiments described below, m can be equal to 3, n can be equal to 2, o can be equal to 6, p can be equal to 2, and q can be equal to 3.

[0083] Referring to Figure 3 , the driver group DRS can include the first driver DR1 and the second driver DR2.

[0084] In the present embodiment, the driver group DRS can include the first driver DR1. For example, the first driver DR1 of the driver group DRS can include the 1-1 driver DR1-1 and the 1-2 driver DR1-2. In other words, in the present embodiment, p, which is the number of the first sub-drivers (i.e., the 1-1 driver DR1-1 and the 1-2 driver DR1-2) included in the driver group DRS, can be equal to 2.

[0085] In the present embodiment, the driver group DRS can include a second driver DR2. For example, the second driver DR2 of the driver group DRS can include a 2-1 driver DR2-1, a 2-2 driver DR2-2, and a 2-3 driver DR2-3. In other words, in the present embodiment, q, which is the number of the second sub-drivers (i.e., the 2-1 driver DR2-1, the 2-2 driver DR2-2, and the 2-3 driver DR2-3) included in the driver group DRS, can be equal to 3.

[0086] In the present embodiment, each of the first sub-drivers can include one control stage and three output stages. The 1-1 driver DR1-1 can include a first control stage CST1, a first output stage OST1, a second output stage OST2, and a third output stage OST3. The 1-2 driver DR1-2 can include a second control stage CST2, a fourth output stage OST4, a fifth output stage OST5, and a sixth output stage OST6.

[0087] In the present embodiment, each of the output stages can be connected to a corresponding first output line. For example, the first output stage OST1 can be connected to a 1-1 output line 1OL1, and the sixth output stage OST6 can be connected to a 1-6 output line 1OL6. The second output stage OST2 to the fifth output stage OST5 can also be connected to corresponding first output lines. Accordingly, the 1-1 driver DR1-1 can be connected to three first output lines, and the 1-2 driver DR1-2 can also be connected to three first output lines. In other words, the number m of the first output lines connected to each of the first sub-drivers in the first driver DR1 can be equal to 3. The 1-1 output line 1OL1 to the 1-6 output line 1OL6 can be connected to the plurality of scan lines SL described above with reference to FIG. 1, respectively. Figure 1 The plurality of scan lines SL described above with reference to FIG. 1.

[0088] In the present embodiment, the third output stage OST3 and the second control stage CST2 can be connected to each other. At least a part of the output signal of the third output stage OST3 can be transmitted to the second control stage CST2. That is, at least a part of the output signal of the 1-1 driver DR1-1 can be transmitted to the 1-2 driver DR1-2.

[0089] In the present embodiment, each of the second sub-drivers can be connected to a corresponding second output line. The 2-1 driver DR2-1 can be connected to one 2-1 output line 2OL1 and one 2-2 output line 2OL2. The 2-2 driver DR2-2 can be connected to another 2-1 output line 2OL1 and another 2-2 output line 2OL2. The 2-3 driver DR2-3 can be connected to yet another 2-1 output line 2OL1 and yet another 2-2 output line 2OL2. In other words, the number n of the second output lines connected to one second sub-driver can be equal to 2. Although not shown in FIG. 2, the 2-1 driver DR2-1 can be connected to one 2-1 output line 2OL1 and one 2-3 output line 2OL3. The 2-2 driver DR2-2 can be connected to another 2-1 output line 2OL1 and another 2-3 output line 2OL3. The 2-3 driver DR2-3 can be connected to yet another 2-1 output line 2OL1 and yet another 2-3 output line 2OL3. In other words, the number n of the second output lines connected to one second sub-driver can be equal to 3.Figure 3 The second-1 output line 2OL1 and the second-2 output line 2OL2 can be connected to the first-1 driver DR1-1 and the first-2 driver DR1-2, respectively, as described above with reference to FIG. 1. Figure 1 The plurality of scan lines SL described above can be connected to the plurality of output lines 2OL.

[0090] In the present embodiment, the driver groups DRS can be provided as a plurality, and can be arranged along the curve of the corner area CNA. Dummy drivers DM can be arranged between adjacent driver groups DRS.

[0091] Referring to FIG. 1, the driver groups DRS can include the first-1 driver DR1-1 and the first-2 driver DR1-2. Figure 4 The first-1 driver DR1-1 can include the first control stage CST1, the first output stage OST1, the second output stage OST2, and the third output stage OST3. The first-2 driver DR1-2 can include the second control stage CST2, the fourth output stage OST4, the fifth output stage OST5, and the sixth output stage OST6.

[0092] In the present embodiment, the first control stage CST1, the first output stage OST1, the second output stage OST2, and the third output stage OST3 can be grouped into the first-1 driver DR1-1. In the present embodiment, the second control stage CST2, the fourth output stage OST4, the fifth output stage OST5, and the sixth output stage OST6 can be grouped into the first-2 driver DR1-2.

[0093] At least two output stages can share one control stage. In the present embodiment, the first output stage OST1, the second output stage OST2, and the third output stage OST3 can share the first control stage CST1. For example, the first output stage OST1, the second output stage OST2, and the third output stage OST3 can be connected to the first control stage CST1 through a common node such as the first node Q1 and the second node Q2. In the present embodiment, the fourth output stage OST4, the fifth output stage OST5, and the sixth output stage OST6 can share the second control stage CST2. For example, the fourth output stage OST4, the fifth output stage OST5, and the sixth output stage OST6 can be connected to the second control stage CST2 through a common node such as the first node Q1 and the second node Q2.

[0094] Each of the plurality of output stages can be connected to the first output line described above and can generate and direct an output signal to the connected first output line. In the present embodiment, the first output stage OST1 can be connected to the 1-1st output line 1OL1 and can direct a first output signal OUT1 to the 1-1st output line 1OL1. In the present embodiment, the second output stage OST2 can be connected to the 1-2nd output line 1OL2 and can direct a second output signal OUT2 to the 1-2nd output line 1OL2. In the present embodiment, the third output stage OST3 can be connected to the 1-3rd output line 1OL3 and can direct a third output signal OUT3 to the 1-3rd output line 1OL3. In the present embodiment, the fourth output stage OST4 can be connected to the 1-4th output line 1OL4 and can direct a fourth output signal OUT4 to the 1-4th output line 1OL4. In the present embodiment, the fifth output stage OST5 can be connected to the 1-5th output line 1OL5 and can direct a fifth output signal OUT5 to the 1-5th output line 1OL5. In the present embodiment, the sixth output stage OST6 can be connected to the 1-6th output line 1OL6 and can direct a sixth output signal OUT6 to the 1-6th output line 1OL6.

[0095] The first sub-driver (e.g., the 1-1st driver DR1-1 and the 1-2nd driver DR1-2) can receive the start signal, the plurality of clock signals, the first voltage VGH, and the second voltage VGL to output the plurality of output signals.

[0096] Each control stage can be connected to an input terminal into which the start signal is input, a first clock terminal, a first voltage input terminal into which the first voltage VGH is input, and a second voltage input terminal into which the second voltage VGL is input. In the present embodiment, both the first control stage CST1 and the second control stage CST2 can be connected to an input terminal into which the start signal is input, a first clock terminal, a first voltage input terminal into which the first voltage VGH is input, and a second voltage input terminal into which the second voltage VGL is input.

[0097] Each control stage can control the voltage of the first node Q1 and the voltage of the second node Q2 in response to the start signal input to the input terminal and the clock signal input to the first clock terminal. In the present embodiment, both the first control stage CST1 and the second control stage CST2 can control the voltage of the first node Q1 and the voltage of the second node Q2 in response to the start signal input to the input terminal and the clock signal input to the first clock terminal.

[0098] Each of the plurality of output stages can be connected to the first voltage input terminal, the second voltage input terminal, and the second clock terminal, and can be connected to the first node Q1 and the second node Q2 to output an output signal of the first level voltage or the second level voltage in response to voltages of the first node Q1 and the second node Q2. In the present embodiment, the first output stage OST1 to the sixth output stage OST6 can be connected to the first voltage input terminal, the second voltage input terminal, and the second clock terminal, and can be connected to the first node Q1 and the second node Q2 to output an output signal of the first level voltage or the second level voltage in response to voltages of the first node Q1 and the second node Q2.

[0099] The number of clock signals input to the first sub-driver can be determined according to the number of output stages included in the first sub-driver. For example, when the number of output stages included in one first sub-driver is m, the plurality of clock signals can include m+1 clock signals. The plurality of clock signals can be phase-shifted by 1 / (m+1) cycles. In the present embodiment, the 1-1 driver DR1-1 and the 1-2 driver DR1-2 can each include three output stages. In the present embodiment, the number of clock signals input to the 1-1 driver DR1-1 or the 1-2 driver DR1-2 can be equal to 4. In the present embodiment, the plurality of clock signals can include a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4.

[0100] The clock signal input to the second clock terminal can be one of the remaining clock signals among the plurality of clock signals excluding the clock signal input to the first clock terminal. The clock signal input to the second clock terminal of the plurality of output stages can be sequentially phase-shifted by 1 / (m+1) cycles.

[0101] The control stage and the output stage can start operation by receiving a start signal. The start signal can be an external signal FLM or a previous output signal. The external signal FLM can be input to the first control stage CST1 as the start signal. In the subsequent control stage, the previous output signal can be input as the start signal. For example, the third output signal OUT3 can be input to the second control stage CST2 as the start signal.

[0102] In an embodiment, the first voltage VGH can be a positive voltage, and the second voltage VGL can be a negative voltage. In the present disclosure, the high level voltage and the low level voltage can mean a positive voltage and a negative voltage, respectively, but are not limited thereto. For example, a relatively high voltage among the two voltages can be referred to as a high level voltage (a first level voltage), and a relatively low voltage can be referred to as a low level voltage (a second level voltage).

[0103] A dummy driver DM can be placed between adjacent driver groups DRS. In an embodiment, the dummy driver DM can include a structure similar to that of a first sub-driver (e.g., the 1-1 driver DR1-1 or the 1-2 driver DR1-2). For example, the dummy driver DM can include a control stage CST-DM and a plurality of output stages OST-DM sharing the control stage CST-DM through a first node Q1 and a second node Q2. The dummy driver DM can not receive a start signal, and thus can not output an output signal. In an embodiment, the dummy driver DM can be omitted, and the adjacent driver groups DRS can be spaced apart from each other.

[0104] Referring to Figure 5 The 1-1 driver DR1-1 can include a first control stage CST1, a first output stage OST1, a second output stage OST2, and a third output stage OST3. The first control stage CST1, the first output stage OST1, the second output stage OST2, and the third output stage OST3 can each include at least one transistor. In an embodiment, the at least one transistor can be a P-channel transistor. The P-channel transistor can be a silicon transistor. The silicon transistor can include a silicon semiconductor, and the silicon semiconductor can include amorphous silicon, polysilicon, etc. For example, the silicon transistor can be a low temperature polysilicon (LTPS) thin film transistor. A gate-on voltage of the P-channel transistor can be a low-level voltage, and a gate-off voltage of the P-channel transistor can be a high-level voltage.

[0105] A control stage (e.g., the first control stage CST1) can be connected to an input terminal IN, a first clock terminal CK1, and a second voltage input terminal V2. The first control stage CST1 can include a first transistor T1, a second transistor T2, and a third transistor T3.

[0106] The first transistor T1 can be connected between the input terminal IN and a first node Q1. A gate of the first transistor T1 can be connected to the first clock terminal CK1. The first transistor T1 can be turned on in response to a clock signal input to the first clock terminal CK1, and a start signal STV input to the input terminal IN can be transmitted to the first node Q1.

[0107] The clock signal input to the first clock terminal CK1 can be one of a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4. Figure 5 An embodiment in which the first clock signal CLK1 is input to the first clock terminal CK1 is illustrated.

[0108] The second transistor T2 can be connected to the second node Q2 and the first clock terminal CK1. A gate of the second transistor T2 can be connected to the first node Q1. The second transistor T2 can be turned on in response to a voltage of the first node Q1, and a clock signal (e.g., a first clock signal CLK1) input to the first clock terminal CK1 can be transmitted to the second node Q2.

[0109] The third transistor T3 can be connected to the second voltage input terminal V2 and the second node Q2. A gate of the third transistor T3 can be connected to the first clock terminal CK1. The third transistor T3 can be turned on in response to a clock signal (e.g., a first clock signal CLK1) input to the first clock terminal CK1, and a second voltage VGL input to the second voltage input terminal V2 can be transmitted to the second node Q2.

[0110] The first output stage OST1, the second output stage OST2, and the third output stage OST3 can each be connected to the first voltage input terminal V1, the second voltage input terminal V2, the second clock terminal CK2, and an output terminal OT. The output terminal OT can be connected to the first output line described above. The first output stage OST1, the second output stage OST2, and the third output stage OST3 can each guide a first output signal OUT1, a second output signal OUT2, and a third output signal OUT3, respectively, through the output terminal OT in response to voltages of the second node Q2 and the third node Q3. The first output stage OST1, the second output stage OST2, and the third output stage OST3 can each include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0111] The fourth transistor T4 can be connected between the first voltage input terminal V1 and the output terminal OT. A gate of the fourth transistor T4 can be connected to the second node Q2. The fourth transistor T4 can be a pull-up transistor configured to transmit a high-level voltage to the output terminal OT. The fourth transistor T4 can be turned on in response to a voltage of the second node Q2, and a first voltage VGH, which is a high-level voltage input to the first voltage input terminal V1, can be transmitted to the output terminal OT.

[0112] The fifth transistor T5 can be connected between the output terminal OT and the second clock terminal CK2. A gate of the fifth transistor T5 can be connected to the third node Q3. The fifth transistor T5 can be a pull-down transistor configured to transmit a low-level voltage to the output terminal OT. The fifth transistor T5 can be turned on in response to a voltage of the third node Q3, and a clock signal input to the second clock terminal CK2 can be transmitted to the output terminal OT.

[0113] In addition to the clock signal input to the first clock terminal CK1, the clock signal input to the second clock terminal CK2 can be one of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4. For example, as shown in Figure 5 In addition to the clock signal input to the first clock terminal CK1, the clock signal input to the second clock terminal CK2 can be one of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4. For example, as shown in Figure 5 In addition to the clock signal input to the first clock terminal CK1, the clock signal input to the second clock terminal CK2 can be one of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4. For example, as shown in

[0114] The sixth transistor T6 can be connected between the first node Q1 and the third node Q3. The gate of the sixth transistor T6 can be connected to the second voltage input terminal V2. The sixth transistor T6 can be turned on in response to the second voltage VGL input to the second voltage input terminal V2, and the signal sent to the first node Q1 can be sent to the third node Q3.

[0115] At least one of the first output stage OST1, the second output stage OST2, and the third output stage OST3 can further include at least one of the first capacitor C1 and the second capacitor C2. In Figure 5 In

[0116] The first capacitor C1 can be connected between the first voltage input terminal V1 and the second node Q2. The first capacitor C1 can hold the voltage of the second node Q2 stable.

[0117] The second capacitor C2 can be connected between the output terminal OT and the third node Q3. The second capacitor C2 can change the voltage of the third node Q3 in response to a voltage change of the output terminal OT through coupling when the third node Q3 is in a floating state. When the voltage of the output terminal OT decreases from a high level to a low level, the level of the voltage of the third node Q3 can decrease due to the coupling of the second capacitor C2. When the voltage of the output terminal OT increases from a low level to a high level, the level of the voltage of the third node Q3 can increase due to the coupling of the second capacitor C2.

[0118] Referring to Figure 6, the first transistor T1 can include a series connection of a 1-1 transistor T1-1 and a 1-2 transistor T1-2. The 1-1 transistor T1-1 can be connected between the input terminal IN and the 1-2 transistor T1-2. The 1-2 transistor T1-2 can be connected between the 1-1 transistor T1-1 and the first node Q1. The gate of the 1-1 transistor T1-1 and the gate of the 1-2 transistor T1-2 can be connected to the first clock terminal CK1. The rest of the structure is similar to the reference Figure 5 The described structure is substantially the same, and thus the description thereof is omitted.

[0119] Referring to Figure 7A and Figure 7B In addition, an equivalent circuit diagram of the 1-2 driver DR1-2 is shown. The overall structure of the 1-2 driver DR1-2 can be similar to that of the 1-1 driver DR1-1. As explained below, the start signal, the clock signal, and the output signal of the 1-2 driver DR1-2 can be slightly different from those of the 1-1 driver DR1-1.

[0120] The fourth output stage OST4 can lead the fourth output signal OUT4 to the output terminal OT. The fifth output stage OST5 can lead the fifth output signal OUT5 to the output terminal OT. The sixth output stage OST6 can lead the sixth output signal OUT6 to the output terminal OT.

[0121] The second control stage CST2 of the 1-2 driver DR1-2 can be connected to the input terminal IN. The second control stage CST2 can receive the third output signal OUT3 of the third output stage OST3 of the 1-1 driver DR1-1 as a start signal via the input terminal IN. In an embodiment, the input terminal IN connected to the second control stage CST2 can be connected to the output terminal OT connected to the third output stage OST3. In other words, the second control stage CST2 of the 1-2 driver DR1-2 can be connected to the third output stage OST3 of the 1-1 driver DR1-1.

[0122] The clock signal input to the 1-2 driver DR1-2 can be shifted from the clock signal input to the 1-1 driver DR1-1. In the case of the 1-1 driver DR1-1, as Figure 7A and Figure 7BAs shown in FIG. 1, a first clock signal CLK1 can be input to a first clock terminal CK1 connected to the first control stage CST1, a second clock signal CLK2 can be input to a second clock terminal CK2 connected to the first output stage OST1, a third clock signal CLK3 can be input to the second clock terminal CK2 connected to the second output stage OST2, and a fourth clock signal CLK4 can be input to the second clock terminal CK2 connected to the third output stage OST3. In the case of the 1-2 driver DRS, as shown in FIG. 1, the first clock signal CLK1 can be input to the first clock terminal CK1 connected to the first control stage CST1, the second clock signal CLK2 can be input to the second clock terminal CK2 connected to the first output stage OST1, the third clock signal CLK3 can be input to the second clock terminal CK2 connected to the second output stage OST2, and the fourth clock signal CLK4 can be input to the second clock terminal CK2 connected to the third output stage OST3. Figure 7A and Figure 7B As shown in FIG. 1, a first clock signal CLK1 can be input to a first clock terminal CK1 connected to the first control stage CST1, a second clock signal CLK2 can be input to a second clock terminal CK2 connected to the first output stage OST1, a third clock signal CLK3 can be input to the second clock terminal CK2 connected to the second output stage OST2, and a fourth clock signal CLK4 can be input to the second clock terminal CK2 connected to the third output stage OST3. In the case of the 1-2 driver DRS, as shown in FIG. 1, the first clock signal CLK1 can be input to the first clock terminal CK1 connected to the first control stage CST1, the second clock signal CLK2 can be input to the second clock terminal CK2 connected to the first output stage OST1, the third clock signal CLK3 can be input to the second clock terminal CK2 connected to the second output stage OST2, and the fourth clock signal CLK4 can be input to the second clock terminal CK2 connected to the third output stage OST3.

[0123] Figure 8 is a magnified plan view of a portion of a display device according to an embodiment. Figure 9 is a schematic view of a driving circuit according to an embodiment. Figure 10 and Figure 11 is an equivalent circuit diagram of a driver according to an embodiment.

[0124] In the embodiments described below, m can be equal to 4, n can be equal to 2, o can be equal to 4, p can be equal to 1, and q can be equal to 2.

[0125] Referring to Figure 8 , the driver group DRS can include a first driver DR1 and a second driver DR2.

[0126] In the present embodiment, the driver group DRS can include the first driver DR1. In this case, the first sub-driver can be identical to the first driver DR1. In other words, in the present embodiment, p, which is the number of first sub-drivers included in the driver group DRS, can be equal to 1.

[0127] In the present embodiment, the driver group DRS can include the second driver DR2. For example, the second driver DR2 of the driver group DRS can include a 2-1 driver DR2-1 and a 2-2 driver DR2-2. In other words, in the present embodiment, q, which is the number of second sub-drivers (e.g., the 2-1 driver DR2-1 and the 2-2 driver DR2-2) included in the driver group DRS, can be equal to 2.

[0128] In this embodiment, the first driver DR1 can include one control stage CST (e.g., a first control stage CST1) and four output stages. The first driver DR1 can include the control stage CST, a first output stage OST1, a second output stage OST2, a third output stage OST3, and a fourth output stage OST4.

[0129] In this embodiment, each output stage can be connected to a respective first output line. For example, the first output stage OST1 can be connected to the 1-1st output line 1OL1, and the fourth output stage OST4 can be connected to the 1-4th output line 1OL4. The second output stage OST2 and the third output stage OST3 can also be connected to respective first output lines. Thus, the first driver DR1 can be connected to four first output lines. In other words, the number m of first output lines connected to the first driver DR1 can be equal to 4. The 1-1st output line 1OL1 to the 1-4th output line 1OL4 can be connected to the plurality of scan lines SL described above with reference to Figure 1

[0130] In this embodiment, each second sub-driver can be connected to a respective second output line. The 2-1st driver DR2-1 can be connected to one 2-1st output line 2OL1 and one 2-2nd output line 2OL2. The 2-2nd driver DR2-2 can be connected to another 2-1st output line 2OL1 and another 2-2nd output line 2OL2. In other words, the number n of second output lines connected to one second sub-driver can be equal to 2. Although Figure 8 not shown in FIG. 10, the 2-1st output line 2OL1 and the 2-2nd output line 2OL2 can be connected to the plurality of scan lines SL described above with reference to Figure 1

[0131] In this embodiment, the driver groups DRS can be provided as a plurality, and can be arranged along the curve of the corner area CNA. Dummy drivers DM can be placed between adjacent driver groups DRS.

[0132] Referring to Figure 9 , the driver group DRS can include the first driver DR1. In this embodiment, the control stage CST, the first output stage OST1, the second output stage OST2, the third output stage OST3, and the fourth output stage OST4 can be grouped into the first driver DR1.

[0133] At least two output stages can share one control stage. In this embodiment, the first output stage OST1, the second output stage OST2, the third output stage OST3, and the fourth output stage OST4 can share the control stage CST. For example, the first output stage OST1, the second output stage OST2, the third output stage OST3, and the fourth output stage OST4 can be connected to the control stage CST through common nodes such as the first node Q1 and the second node Q2.​​

[0134] Each of the plurality of output stages can be connected to the first output line described above and can generate and direct an output signal to the connected first output line. In the present embodiment, the first output stage OST1 can be connected to the 1-1st output line 1OL1 and can direct a first output signal OUT1 to the 1-1st output line 1OL1. In the present embodiment, the second output stage OST2 can be connected to the 1-2nd output line 1OL2 and can direct a second output signal OUT2 to the 1-2nd output line 1OL2. In the present embodiment, the third output stage OST3 can be connected to the 1-3rd output line 1OL3 and can direct a third output signal OUT3 to the 1-3rd output line 1OL3. In the present embodiment, the fourth output stage OST4 can be connected to the 1-4th output line 1OL4 and can direct a fourth output signal OUT4 to the 1-4th output line 1OL4.

[0135] The first driver DR1 can receive the start signal, the plurality of clock signals, the first voltage VGH, and the second voltage VGL and can output a plurality of output signals.

[0136] In the present embodiment, the control stage CST can be connected to an input terminal into which the start signal is input, a first clock terminal, a first voltage input terminal into which the first voltage VGH is input, and a second voltage input terminal into which the second voltage VGL is input. In the present embodiment, the control stage CST can control the voltage of the first node Q1 and the voltage of the second node Q2 in response to the start signal input to the input terminal and the clock signal input to the first clock terminal.

[0137] Each of the plurality of output stages can be connected to the first voltage input terminal, the second voltage input terminal, and the second clock terminal and can be connected to the first node Q1 and the second node Q2 to output an output signal of a first level voltage or a second level voltage in response to the voltage of the first node Q1 and the voltage of the second node Q2. In the present embodiment, the first output stage OST1 to the fourth output stage OST4 can all be connected to the first voltage input terminal, the second voltage input terminal, and the second clock terminal and can be connected to the first node Q1 and the second node Q2 to output an output signal of a first level voltage or a second level voltage in response to the voltage of the first node Q1 and the voltage of the second node Q2.

[0138] In the present embodiment, the first driver DR1 can include four output stages. In the present embodiment, the number of clock signals input to the first driver DR1 can be five. In the present embodiment, the plurality of clock signals can include a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, and a fifth clock signal CLK5.

[0139] The control stage CST and the output stages can start operation by receiving a start signal. The start signal can be an external signal FLM. In the present embodiment, the external signal FLM as the start signal can be input to the control stage CST of the first driver DR1.

[0140] A dummy driver DM can be placed between adjacent driver groups DRS. In an embodiment, the dummy driver DM can include a structure similar to that of the first driver DR1. For example, the dummy driver DM can include a control stage CST-DM and a plurality of output stages OST-DM sharing the control stage CST-DM through a first node Q1 and a second node Q2. The dummy driver DM can not receive a start signal, and thus can not output an output signal. In an embodiment, the dummy driver DM can be omitted, and adjacent driver groups DRS can be spaced apart from each other.

[0141] Reference Figure 10 The overall structure of the first driver DR1 can be similar to that of the embodiment of the first sub-driver (e.g., the 1-1 driver DR1-1) described with reference to Figure 5 Therefore, the following description will focus on the differences from the embodiment shown in Figure 5

[0142] Compared to the embodiment shown in Figure 5 The first driver DR1 can further include a fourth output stage OST4. The fourth output stage OST4 can be connected to the first voltage input terminal V1, the second voltage input terminal V2, the second clock terminal CK2, and the output terminal OT. The fourth output stage OST4 can guide a fourth output signal OUT4 through the output terminal OT. The fourth output stage OST4 can be connected to the first node Q1 and the second node Q2. The fourth output stage OST4 can include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second capacitor C2.

[0143] In the present embodiment, the plurality of clock signals input to the first driver DR1 can include five clock signals. In the present embodiment, the five clock signals can include a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, and a fifth clock signal CLK5.

[0144] In addition to the clock signal input to the first clock terminal CK1, the clock signal input to the second clock terminal CK2 can be one of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the fifth clock signal CLK5. In Figure 10 ​In particular, an embodiment is shown in which a first clock signal CLK1 is input to a first clock terminal CK1, a second clock signal CLK2 is input to a second clock terminal CK2 connected to a first output stage OST1, a third clock signal CLK3 is input to a second clock terminal CK2 connected to a second output stage OST2, a fourth clock signal CLK4 is input to a second clock terminal CK2 connected to a third output stage OST3, and a fifth clock signal CLK5 is input to a second clock terminal CK2 connected to a fourth output stage OST4.

[0145] Reference is made to Figure 11 As in the case of Figure 6 In particular, the first transistor T1 can comprise a first transistor T1-1 and a second transistor T1-2 connected in series. The first transistor T1-1 can be connected between the input terminal IN and the second transistor T1-2. The second transistor T1-2 can be connected between the first transistor T1-1 and the first node Q1. The gate of the first transistor T1-1 and the gate of the second transistor T1-2 can be connected to the first clock terminal CK1. The remaining structure is substantially identical to that described with reference to Figure 10 The structure described is substantially identical, and thus the description thereof is omitted.

[0146] Figure 12 is a magnified plan view of a portion of a display device according to an embodiment. Figure 13 is a schematic view of a driving circuit according to an embodiment. Figure 14 and Figure 15 is an equivalent circuit diagram of a driver according to an embodiment.

[0147] In the embodiments described below, m can be equal to 2, n can be equal to 2, o can be equal to 2, p can be equal to 1, and q can be equal to 1.

[0148] Reference is made to Figure 12 , the driver group DRS can comprise a first driver DR1 and a second driver DR2.

[0149] In the present embodiment, the driver group DRS can comprise a first driver DR1. In this case, the first sub-driver can be identical to the first driver DR1. In other words, in the present embodiment, p, which is the number of first sub-drivers comprised in the driver group DRS, can be equal to 1.

[0150] In the present embodiment, the driver group DRS can comprise a second driver DR2. In this case, the second sub-driver can be identical to the second driver DR2. In other words, in the present embodiment, q, which is the number of second sub-drivers comprised in the driver group DRS, can be equal to 1.

[0151] In the present embodiment, the first driver DR1 can include one control stage CST and two output stages. The first driver DR1 can include the control stage CST, a first output stage OST1, and a second output stage OST2.

[0152] In the present embodiment, each output stage can be connected to a corresponding first output line. For example, the first output stage OST1 can be connected to the 1-1st output line 1OL1, and the second output stage OST2 can be connected to the 1-2nd output line 1OL2. Thus, the first driver DR1 can be connected to two first output lines. In other words, the number m of first output lines connected to the first driver DR1 can be equal to 2. The 1-1st output line 1OL1 and the 1-2nd output line 1OL2 can be connected to the plurality of scan lines SL described above with reference to Figure 1

[0153] In the present embodiment, the second driver DR2 can be connected to a corresponding second output line. For example, the second driver DR2 can be connected to the 2-1st output line 2OL1 and the 2-2nd output line 2OL2. In other words, the number n of second output lines connected to one second driver DR2 can be equal to 2. Although Figure 12 not shown in FIG. 1, the 2-1st output line 2OL1 and the 2-2nd output line 2OL2 can be connected to the plurality of scan lines SL described above with reference to Figure 1

[0154] In the present embodiment, the driver groups DRS can be provided as a plurality, and can be arranged along the curve of the corner area CNA. In the present embodiment, dummy drivers DM can or can not be present between the plurality of driver groups DRS. The plurality of driver groups DRS, between which no dummy driver DM is arranged, can be spaced apart from each other. Figure 12 An example in which one dummy driver DM is placed between two driver groups DRS is shown. However, the present disclosure is not limited thereto, and the arrangement relationship between the driver groups DRS and the dummy drivers DM can be changed as long as the spacing between the plurality of drivers in the driver groups DRS and / or the spacing between the plurality of output stages remains constant.

[0155] Referring to Figure 13 , the driver groups DRS can include the first driver DR1. In the present embodiment, the control stage CST, the first output stage OST1, and the second output stage OST2 can be grouped into the first driver DR1.

[0156] In the present embodiment, the first output stage OST1 and the second output stage OST2 can share the control stage CST. For example, the first output stage OST1 and the second output stage OST2 can be connected to the control stage CST through a common node such as a first node Q1 and a second node Q2.

[0157] ​​Each of the plurality of output stages can be connected to the first output line described above and can generate and direct an output signal to the connected first output line. In the present embodiment, the first output stage OST1 can be connected to the 1-1st output line 1OL1 and can direct a first output signal OUT1 to the 1-1st output line 1OL1. In the present embodiment, the second output stage OST2 can be connected to the 1-2nd output line 1OL2 and can direct a second output signal OUT2 to the 1-2nd output line 1OL2.

[0158] The first driver DR1 can receive the start signal, the plurality of clock signals, the first voltage VGH, and the second voltage VGL and can output a plurality of output signals.

[0159] In the present embodiment, the control stage CST can be connected to an input terminal into which the start signal is input, a first clock terminal, a first voltage input terminal into which the first voltage VGH is input, and a second voltage input terminal into which the second voltage VGL is input. In the present embodiment, the control stage CST can control the voltage of the first node Q1 and the voltage of the second node Q2 in response to the start signal input to the input terminal and the clock signal input to the first clock terminal.

[0160] Each of the plurality of output stages can be connected to the first voltage input terminal, the second voltage input terminal, and the second clock terminal and can be connected to the first node Q1 and the second node Q2 to output an output signal of a first level voltage or a second level voltage in response to the voltage of the first node Q1 and the voltage of the second node Q2. In the present embodiment, both the first output stage OST1 and the second output stage OST2 can be connected to the first voltage input terminal, the second voltage input terminal, and the second clock terminal and can be connected to the first node Q1 and the second node Q2 to output an output signal of a first level voltage or a second level voltage in response to the voltage of the first node Q1 and the voltage of the second node Q2.

[0161] In the present embodiment, the first driver DR1 can include two output stages. In the present embodiment, the number of clock signals input to the first driver DR1 can be three. In the present embodiment, the plurality of clock signals can include a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3.

[0162] The control stage CST and the output stage can start operation by receiving a start signal. The start signal can be an external signal FLM. In the present embodiment, the external signal FLM as the start signal can be input to the control stage CST.

[0163] A dummy driver DM can be placed between adjacent driver groups DRS. In an embodiment, the dummy driver DM can include a structure similar to that of the first driver DR1. For example, the dummy driver DM can include a control stage CST-DM and a plurality of output stages OST-DM sharing the control stage CST-DM through a first node Q1 and a second node Q2. The dummy driver DM can not receive a start signal, and thus can not output an output signal. In an embodiment, the dummy driver DM can be omitted, and the adjacent driver groups DRS can be spaced apart from each other.

[0164] Referring to Figure 14 , the overall structure of the first driver DR1 can be similar to that of the embodiment of the first sub-driver (e.g., the 1-1 driver DR1-1) described with reference to Figure 5 . Accordingly, the following description will focus on the differences from the embodiment shown in Figure 5 .

[0165] As compared with the embodiment shown in Figure 5 , the first driver DR1 can include only a first output stage OST1 and a second output stage OST2. The first output stage OST1 and the second output stage OST2 can be connected to the first voltage input terminal V1, the second voltage input terminal V2, the second clock terminal CK2, and the output terminal OT. The first output stage OST1 and the second output stage OST2 can guide the first output signal OUT1 and the second input signal OUT2, respectively, through the output terminal OT. The first output stage OST1 and the second output stage OST2 can be connected to the first node Q1 and the second node Q2. The first output stage OST1 can include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. The second output stage OST2 can include the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the second capacitor C2.

[0166] In the present embodiment, the plurality of clock signals input to the first driver DR1 can include three clock signals. In the present embodiment, the three clock signals can include a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3.

[0167] The clock signal input to the second clock terminal CK2 can be one of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3, in addition to the clock signal input to the first clock terminal CK1. In the present embodiment, the clock signal input to the second clock terminal CK2 can be the first clock signal CLK1, the second clock signal CLK2, or the third clock signal CLK3, in addition to the clock signal input to the first clock terminal CK1. Figure 14The image shows an embodiment in which a first clock signal CLK1 is input to a first clock terminal CK1, a second clock signal CLK2 is input to a second clock terminal CK2 connected to a first output stage OST1, and a third clock signal CLK3 is input to a second clock terminal CK2 connected to a second output stage OST2.

[0168] refer to Figure 15 ,and Figure 6 Similarly, the first transistor T1 may include a first transistor T1-1 and a first transistor T1-2 connected in series. The first transistor T1-1 may be connected between the input terminal IN and the first transistor T1-2. The first transistor T1-2 may be connected between the first transistor T1-1 and the first node Q1. The gates of the first transistor T1-1 and the first transistor T1-2 may be connected to the first clock terminal CK1. The remaining structure is the same as referenced. Figure 14 The structures described are essentially the same, and therefore their descriptions are omitted.

[0169] According to the embodiment described above, a display device is provided in which sub-drivers of a driving circuit are grouped into driver groups based on a specific criterion (e.g., the least common multiple of the number of output lines connected to each sub-driver), and the sub-drivers are spaced apart at regular intervals within the driver groups. Therefore, since multiple sub-drivers within the same driver group are arranged at regular intervals, output deviation between multiple sub-drivers can be reduced.

[0170] Although one or more embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein. Therefore, the scope of this disclosure should be defined by the spirit and scope of the appended claims.

Claims

1. A display device comprising: a substrate including a display region and a non-display region surrounding the display region; a plurality of pixels arranged on the substrate in the display region; a plurality of driver groups spaced apart from each other in the non-display region; and a dummy driver between two adjacent driver groups among the plurality of driver groups, wherein one driver group among the plurality of driver groups includes a first driver and a second driver, each of at least one first sub-driver of the first driver is connected to m output lines connected to some of the plurality of pixels, each of at least one second sub-driver of the second driver is connected to n output lines connected to some of the plurality of pixels, and wherein, when a least common multiple of m and n is o, the one driver group includes o / m first sub-drivers and o / n second sub-drivers, wherein m and n are integers greater than 0.

2. The display device according to claim 1, wherein each of the at least one first sub-driver includes a control stage and m output stages, the control stage is connected to an input terminal into which a start signal is input, a first voltage input terminal into which a first voltage is input, and a second voltage input terminal into which a second voltage is input, and controls a voltage of a first node and a voltage of a second node, each of the m output stages is connected to an output terminal connected to a corresponding output line among the m output lines, and the m output stages are connected to the first node and the second node and share the control stage.

3. The display device according to claim 2, wherein the m output stages are spaced apart from each other at regular intervals.

4. The display device according to claim 2, wherein the control stage includes: a first transistor connected to the input terminal and the first node, and including a gate connected to a first clock terminal into which one of a plurality of clock signals is input; a second transistor connected to the second node and the first clock terminal, and including a gate connected to the first node; and a third transistor connected to the second voltage input terminal and the second node, and including a gate connected to the first clock terminal.

5. The display device according to claim 4, wherein the first transistor includes a first-1 transistor and a first-2 transistor, the first-1 transistor is connected to the input terminal and the first-2 transistor, the first-2 transistor is connected to the first node and the first-1 transistor, and the gate of the first-1 transistor and the gate of the first-2 transistor are connected to the first clock terminal.

6. The display device according to claim 4, wherein each of the m output stages includes: a fourth transistor connected to the first voltage input terminal and the output terminal, and including a gate connected to the second node; a fifth transistor connected to the first node and the fourth transistor, and including a gate connected to the second node; and a sixth transistor connected to the second voltage input terminal and the fifth transistor, and including a gate connected to the second node. a fifth transistor connected to the output terminal and a second clock terminal to which another of the plurality of clock signals is input, and including a gate connected to a third node; and a sixth transistor connected to the first node and the third node, and including a gate connected to the second voltage input terminal.

7. The display device according to claim 6, wherein at least one of the m output stages further includes at least one of: a first capacitor connected to the first voltage input terminal and the second node; and a second capacitor connected to the output terminal and the third node.

8. The display device according to claim 2, wherein o / m is a natural number greater than or equal to 2, and one of the m output stages of one of the o / m first sub-drivers is connected to the control stage of another of the o / m first sub-drivers.

9. The display device according to claim 1, wherein the non-display region includes a corner region on a corner of the substrate, and the plurality of driver groups are arranged in the corner region.

10. The display device according to claim 1, wherein at least one of the m output lines connected to the first sub-driver and at least one of the n output lines connected to the second sub-driver are connected to the same pixel.

11. A display device comprising: a substrate including a display region and a non-display region surrounding the display region; a plurality of pixels arranged on the substrate in the display region; and a driver group arranged in the non-display region and connected to at least one of the plurality of pixels, wherein a first driver of the driver group includes: a control stage and m output stages sharing the control stage, and at least some of the m output stages being spaced apart from each other at regular intervals, wherein m is an integer greater than 0.

12. The display device according to claim 11, wherein the control stage is connected to an input terminal to which a start signal is input, a first voltage input terminal to which a first voltage is input, and a second voltage input terminal to which a second voltage is input, and controls a voltage of a first node and a voltage of a second node, and each of the m output stages is connected to an output terminal configured to output an output signal to a corresponding output line, and the m output stages are connected to the first node and the second node and share the control stage.

13. The display device according to claim 12, wherein the control stage includes: a first transistor connected to the input terminal and the first node, and including a gate connected to a first clock terminal to which one of a plurality of clock signals is input; a second transistor connected to the second node and the first clock terminal, and including a gate connected to the first node; and a third transistor connected to the first node and the second clock terminal, and including a gate connected to the second node. a third transistor connected to the second voltage input terminal and the second node, and including a gate connected to the first clock terminal.

14. The display device according to claim 13, wherein each of the m output stages includes: a fourth transistor connected to the first voltage input terminal and the output terminal, and including a gate connected to the second node; a fifth transistor connected to the output terminal and a second clock terminal to which another of the plurality of clock signals is input, and including a gate connected to a third node; and a sixth transistor connected to the first node and the third node, and including a gate connected to the second voltage input terminal.

15. The display device according to claim 14, wherein at least one of the m output stages further includes at least one of: a first capacitor connected to the first voltage input terminal and the second node; and a second capacitor connected to the output terminal and the third node.

16. The display device according to claim 12, wherein the driver group includes at least two first sub-drivers, and the output terminal of one of the m output stages of one of the at least two first sub-drivers is connected to the input terminal of the control stage of another of the at least two first sub-drivers.

17. The display device according to claim 11, wherein the non-display region includes a corner region on a corner of the substrate, and the driver group is arranged in the corner region.

18. The display device according to claim 11, wherein the driver group includes at least one second sub-driver, the at least one second sub-driver each being connected to n output lines connected to some of the plurality of pixels, where n is an integer greater than 0.

19. The display device according to claim 18, wherein when the least common multiple of m and n is o, the driver group includes: o / m first sub-drivers; and o / n second sub-drivers.

20. The display device according to claim 11, comprising: a plurality of driver groups including the driver group; and a dummy driver between adjacent two of the plurality of driver groups. ​ ​

Images