Pixel, display device including same, and electronic device including display device

Abstract

The invention discloses a pixel, a display device and an electronic device. The pixel includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, and including a gate electrode connected to the first scan line; a third transistor connected between a first power line supplied with the first driving power and the first node, and including a gate electrode connected to the emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line supplied with reference power; a third capacitor connected between the second node and a third node; and a light emitting element connected between the second node and a second power line supplied with the second driving power.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0075742 filed on June 11, 2024, as well as all benefits accruing therefrom, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] Various embodiments disclosed relate to a pixel, a display device including the same, and an electronic device including the same. BACKGROUND

[0003] With the development of information technology, the importance of display devices as a medium connecting users and information has been emphasized. Due to the importance of display devices, the use of various types of display devices such as liquid crystal display devices and organic light emitting display devices has increased.

[0004] Recently, a head-mounted display device ("HMD") has been developed. The HMD is a display device that allows a user to wear in the form of glasses or a helmet and is used to create a virtual reality ("VR") experience or an augmented reality ("AR") experience, in which a focal point is formed at a close distance in front of the user's eyes. The HMD employs a high-resolution panel, and thus requires a pixel that can be applied to the high-resolution panel. SUMMARY

[0005] Various embodiments disclosed relate to a pixel suitable for a high-resolution panel and a display device including the same.

[0006] Embodiments disclosed provide a pixel including a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node, a second transistor connected between a data line and the third node and including a gate electrode electrically connected to a first scan line, a third transistor connected between a first power line supplied with a first driving power and the first node and including a gate electrode electrically connected to an emission control line, a first capacitor connected between the first node and the third node, a second capacitor connected between the third node and a reference power line supplied with a reference power, a third capacitor connected between the second node and the third node, and a light emitting element connected between the second node and a second power line supplied with a second driving power.

[0007] In embodiments, the pixel can further include a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line supplied with an initialization power, and a gate electrode electrically connected to a second scan line.

[0008] In an embodiment, a voltage level of the reference power can be lower than a voltage level of the first driving power and higher than a voltage level of the initialization power.

[0009] In an embodiment, a voltage level of the reference power can be equal to a voltage level of the first driving power. The reference power line can be the first power line.

[0010] In an embodiment, the light emitting element can be turned off when a voltage of the initialization power is supplied to the second node.

[0011] In an embodiment, each of the first to fourth transistors can include a metal oxide semiconductor field effect transistor ("MOSFET") including a bulk electrode.

[0012] In an embodiment, a voltage of the first driving power can be supplied to the bulk electrode of each of the first to fourth transistors.

[0013] In an embodiment, the horizontal period can include a first period, a second period, and a third period. During the first period, the second transistor, the third transistor, and the fourth transistor can be set to an on state. During the second period, the second transistor and the fourth transistor can be set to an on state, and the third transistor can be set to an off state. During the third period, the third transistor and the fourth transistor can be set to an on state, and the second transistor can be set to an off state.

[0014] In an embodiment, a voltage of the data signal can be supplied to the data line during the first to third periods.

[0015] In an embodiment, each of the first to third capacitors can include a metal-oxide-metal ("MOM") capacitor or a metal-insulator-metal ("MIM") capacitor.

[0016] In an embodiment, each of the first and second capacitors can include a MOM capacitor or a MIM capacitor. The third capacitor can include a parasitic capacitor.

[0017] Disclosed embodiments provide a display device including a plurality of pixels connected to a write scan line, an initialization scan line, a data line, and an emission control line. Among the plurality of pixels, a pixel provided in an i-th pixel row (where i is a natural number greater than 0) and a j-th pixel column (where j is a natural number greater than 0) includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line among the data lines and the third node, and configured to be turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of a first driving power is supplied and the first node, and configured to be turned off when an emission control signal is supplied to a k-th emission control line (where k is a natural number greater than 0); a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line to which a reference power is supplied; a third capacitor connected between the second node and the third node; and a light emitting element connected between the second node and a second power line to which a second driving power is supplied.

[0018] In embodiments, the pixel provided in the i-th pixel row and the j-th pixel column can further include a fourth transistor including a first electrode connected to the second node and a second electrode electrically connected to a third power line to which an initialization power is supplied. The fourth transistor can be turned on when a second scan signal is supplied to a second scan line.

[0019] In embodiments, a voltage level of the reference power can be lower than a voltage level of the first driving power, and higher than a voltage level of the initialization power.

[0020] In embodiments, a voltage level of the reference power can be equal to a voltage level of the first driving power. The reference power line can be the first power line.

[0021] In embodiments, each of the first to fourth transistors can include a MOSFET including a bulk electrode, and a voltage of the first driving power can be supplied to the bulk electrode.

[0022] Disclosed embodiments provide an electronic device including a processor for providing input image data and a display device for displaying an image based on the input image data. The display device includes a plurality of pixels connected to a write scan line, an initialization scan line, a data line, and an emission control line. Among the plurality of pixels, a pixel provided at an i-th pixel row (where i is a natural number greater than 0) and a j-th pixel column (where j is a natural number greater than 0) includes a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line among the data lines and the third node and configured to be turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of a first driving power is supplied and the first node and configured to be turned off when an emission control signal is supplied to a k-th emission control line (where k is a natural number greater than 0); a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line to which a reference power is supplied; a third capacitor connected between the second node and the third node; and a light emitting element connected between the second node and a second power line to which a second driving power is supplied. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and other exemplary embodiments, advantages, and features of the present disclosure will become more apparent by describing in further detail exemplary embodiments thereof with reference to the attached drawings.

[0024] Figure 1 FIG. 1 is a diagram illustrating an embodiment of a transistor according to the disclosure.

[0025] Figure 2 FIG. 2 is a block diagram illustrating an embodiment of a display device in the disclosed embodiments.

[0026] Figure 3 FIG. 3 is a block diagram illustrating an embodiment of a scan driver, a data driver, and a power supply shown in FIG. 2. Figure 2

[0027] Figure 4 FIG. 4 is a circuit diagram illustrating an embodiment of a pixel shown in FIG. 2. Figure 2

[0028] FIG. 5 is a waveform diagram illustrating an embodiment of a method of driving the pixel shown in FIG. 4. Figure 5 Figure 4 FIG. 6 is a circuit diagram illustrating an operation process of the pixel in response to signals of FIG. 5.

[0029] Figures 6 to 9 Figure 5 FIG. 7 is a circuit diagram illustrating an operation process of the pixel in response to signals of FIG. 5.

[0030] Figure 10 ​​​This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0031] Figure 11 It is shown Figure 10 A schematic diagram illustrating an example of an electronic device implemented as a smartphone.

[0032] Figure 12 It is shown Figure 10 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0033] The disclosed embodiments will be described in detail below with reference to the accompanying drawings, enabling those skilled in the art to readily implement the disclosure. The disclosure may be implemented in various different forms, and is not limited to the embodiments described herein.

[0034] In the accompanying drawings, parts not related to the disclosure have been omitted to clarify the description of the disclosure, and the same reference numerals are used throughout the different drawings to denote the same or similar components.

[0035] It will be understood that when an element is referred to as “joined” or “connected” to another element, it may be directly joined or directly connected to said other element, or an intermediary element may be present between them. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In the specification, when an element is referred to as “comprising” or “including” a component, it does not exclude another component but may further include other components unless the context clearly states otherwise. “At least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term “and / or” can include any and all combinations of one or more of the associated listed items.

[0036] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0037] Figure 1 This is a diagram illustrating an embodiment of the disclosed transistor 10.

[0038] Reference Figure 1The transistor 10 in the disclosed embodiments may include a first electrode 12, a second electrode 14, a gate electrode 16, and a body electrode 18. In embodiments, the transistor 10 may be, for example, a metal-oxide-semiconductor field-effect transistor (“MOSFET”). The transistor 10 (e.g., a MOSFET) including the body electrode 18 is suitable for implementing high-resolution pixels due to its reduced mounting area.

[0039] Transistor 10 can be formed on a silicon wafer. In embodiments, the panel can be implemented by stacking layers such as transistor layers, emitter layers, and capping layers on the silicon wafer. However, the foregoing description is illustrative, and transistor 10 can be formed on various known substrates, such as glass substrates.

[0040] The first electrode 12 of transistor 10 can be configured as the source electrode (or drain electrode), and its second electrode 14 can be configured as the drain electrode (or source electrode). When transistor 10 includes a body electrode 18, the threshold voltage of transistor 10 can be changed by the body effect. The body effect refers to the change in the threshold voltage of transistor 10 due to the voltage difference between the body electrode 18 and the first electrode 12.

[0041] In the disclosed embodiments, threshold voltage compensation can be achieved while using the transistor 10, which includes the body electrode 18, as the driving transistor.

[0042] Figure 2 This is a diagram showing a display device 100 according to the disclosure. Figure 3 It is shown Figure 2 A block diagram of an embodiment of the scan driver 130, data driver 140, and power supply 150 shown.

[0043] Reference Figure 2 The display device 100 in the disclosed embodiments may include a pixel assembly 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, a power supply 150, and a transmit driver 160. The aforementioned components may be implemented as separate integrated circuits. Two or more of the aforementioned components may be implemented in a single integrated circuit. Furthermore, the scan driver 130 and / or the transmit driver 160 may be formed within the pixel assembly 110.

[0044] Pixel assembly 110 may include a pixel PX connected to write scan lines SL11 to SL1n, initialization scan lines SL21 to SL2n, data lines DL1 to DLm, transmit control lines EL1 to ELo, and power lines PL1, PL2, and PL3 (where n, m, and o are all natural numbers greater than 1).

[0045] In an embodiment, for example, pixel PXij is set on the j-th vertical line (or pixel column) of the i-th horizontal line (or pixel row) (refer to...). Figure 4 The i-th write scan line (also called the first scan line) SL1i, the i-th initialization scan line (also called the second scan line) SL2i, the k-th transmit control line ELk, and the j-th data line DLj (where i is a natural number greater than 0 and equal to or less than n, j is a natural number greater than 0 and equal to or less than m, and k is a natural number greater than 0 and equal to or less than 0). Here, k is a number equal to or less than i. In an embodiment, if each of the transmit control lines EL1 to ELo is connected to a pixel PX disposed on a single horizontal line, k is, for example, the same number as i. In an embodiment, if each of the transmit control lines EL1 to ELo is connected to a pixel PX disposed on two or more horizontal lines, k is, for example, a number less than i.

[0046] When a first scan signal is supplied to each of the write scan lines SL11 to SL1n, a pixel PX can be selected based on a horizontal line (e.g., pixels PX connected to the same scan line can be grouped into a horizontal line (or a row of pixels)). Each pixel PX selected by the first scan signal can receive a data signal from the corresponding data line (any one of DL1 to DLm) connected to it. The pixel PX receiving the data signal can generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0047] The timing controller 120 can receive input data Din and control signal CS from the host system via an interface. In an embodiment, for example, the timing controller 120 can receive input data Din and control signal CS from at least one of a graphics processing unit (“GPU”), a central processing unit (“CPU”), and an application processor (“AP”) included in the host system. The control signal CS can include various signals including a clock signal.

[0048] The timing controller 120 can generate a scan drive signal SCS, a data drive signal DCS, and a transmit drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the transmit drive signal ECS can be supplied to the scan driver 130, the data driver 140, and the transmit driver 160, respectively.

[0049] The timing controller 120 can rearrange the input data Din to match the specifications of the display device 100. Furthermore, the timing controller 120 can correct the input data Din to generate output data Dout and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 can correct the input data Din based on optical measurements obtained during the manufacturing process.

[0050] Scan driver 130 may receive scan drive signal SCS from timing controller 120. Scan drive signal SCS may include at least one scan start signal and a clock signal required to drive scan driver 130. Scan driver 130 may generate a first scan signal and a second scan signal in response to the clock signal, while shifting the scan start signal.

[0051] To achieve the aforementioned objectives, such as Figure 3 As shown, the scan driver 130 may include a first scan driver 132 and a second scan driver 134.

[0052] The first scan driver 132 can receive a first scan start signal FLM1 and shift the first scan start signal FLM1 while generating a first scan signal in response to a clock signal. The first scan driver 132 can sequentially supply the first scan signal to the write scan lines SL11 to SL1n.

[0053] The second scan driver 134 can receive the second scan start signal FLM2 and shift the second scan start signal FLM2 while generating the second scan signal in response to a clock signal. The second scan driver 134 can sequentially supply the second scan signal to the initialization scan lines SL21 to SL2n. Each of the first scan signal and the second scan signal can be set to a gate on-state voltage to allow the transistors included in the pixel PX to be turned on.

[0054] In an embodiment, for example, a relatively low-level first scan signal and a relatively high-level second scan signal can be supplied to a P-type transistor. The first scan signal and the second scan signal can be supplied to an N-type transistor. The transistor supplied with the first scan signal or the second scan signal can be turned on in response to the first scan signal or the second scan signal. Hereinafter, the supply of the first scan signal and the second scan signal can refer to a gate on-line voltage supplied to the write scan line SL1 and the initialization scan line SL2. The absence of the first scan signal and the second scan signal can refer to a gate off-line voltage supplied to the write scan line SL1 and the initialization scan line SL2.

[0055] although Figure 3 The illustration shows a first scan driver 132 and a second scan driver 134 connected to a write scan line SL1 and an initialization scan line SL2, respectively; however, the disclosed embodiments are not limited thereto. In embodiments, for example, the write scan line SL1 and the initialization scan line SL2 may be driven by a single scan driver.

[0056] The data driver 140 can receive output data Dout and data drive signal DCS from the timing controller 120. The data drive signal DCS may include sampling signals and / or timing signals required to drive the data driver 140.

[0057] The data driver 140 can generate a data signal based on the data drive signal DCS and the output data Dout. In an embodiment, for example, the data driver 140 can generate an analog data signal based on the grayscale value of the output data Dout.

[0058] The data driver 140 can apply a predetermined voltage to the data lines DL1 to DLm based on the generated analog data signal. In an embodiment, refer to... Figure 5 For example, data drive 140 can be in the first level time period 1H (refer to...) Figure 5 During this period, data signals DATA (refer to) are supplied to each of the data lines DL1 to DLm. Figure 5 The voltage Vdata (refer to) Figure 5 ).

[0059] The power supply 150 can generate various types of power required to drive the display device 100. In an embodiment, the power supply 150 can generate, for example, a first driving power VDD, a second driving power VSS, and an initialization power Vint.

[0060] A first driving power VDD can be provided to supply driving current to pixel PX. A second driving power VSS can be provided to receive driving current from pixel PX. During the period when pixel PX is set to the transmit state, the first driving power VDD can be set to a voltage higher than the voltage of the second driving power VSS.

[0061] Initial power Vint can be provided to enable the light-emitting element LD (see reference) included in each of the pixels PX. Figure 4 The initial voltage of the first electrode (or anode electrode) of the light-emitting element (LD). The initial power Vint can be a voltage value that causes the LD to turn off when supplied to the first electrode of the LD.

[0062] The first driving power VDD generated from power supply 150 can be supplied to the first power line PL1, the second driving power VSS generated from power supply 150 can be supplied to the second power line PL2, and the initialization power Vint generated from power supply 150 can be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 can be connected together to the pixel PX, but the disclosed embodiments are not limited thereto.

[0063] In an embodiment, the first power line PL1 can be configured as multiple power lines. Multiple first power lines PL1 can be connected to different pixels PX. In an embodiment, the second power line PL2 can be configured as multiple power lines. Multiple second power lines PL2 can be connected to different pixels PX. In an embodiment, the third power line PL3 can be configured as multiple power lines. Multiple third power lines PL3 can be connected to different pixels PX. In the disclosed embodiment, a pixel PX can be connected to any one of the first power lines PL1, any one of the second power lines PL2, and any one of the third power lines PL3.

[0064] In this embodiment, power supply 150 can generate a reference power VRF (reference). Figure 4 ), and will supply the reference power VRF to the fourth power line PL4 (reference) Figure 4 Pixel PX can be connected to the first power line PL1 through the fourth power line PL4.

[0065] The transmit driver 160 can receive a transmit drive signal ECS from the timing controller 120. The transmit drive signal ECS may include a transmit start signal EFLM and a clock signal required to drive the transmit driver 160. The transmit driver 160 can shift the transmit start signal EFLM while generating a transmit control signal in response to the clock signal. The transmit driver 160 can sequentially supply the transmit control signals to the transmit control lines EL1 to ELo. The transmit control signals can be set to a gate cutoff voltage, thus allowing the transistors included in the pixel PX to be turned off.

[0066] In an embodiment, for example, a relatively high-level emit control signal can be supplied to a P-type transistor, and a relatively low-level emit control signal can be supplied to an N-type transistor. The transistor supplied with the emit control signal can be turned off in response to the emit control signal. Subsequently, the supply of the emit control signal can refer to a gate cutoff voltage being supplied to the emit control line EL. The absence of the emit control signal can refer to a gate on-voltage being supplied to the emit control line EL.

[0067] Figure 4 It is shown Figure 2 A diagram illustrating an embodiment of the pixels shown. Figure 4 The image shows a pixel PXij positioned on the i-th horizontal line and the j-th vertical line.

[0068] Reference Figure 4In the disclosed embodiments, pixel PXij can be connected to corresponding signal lines SL1i, SL2i, ELk, and DLj. In the embodiments, pixel PXij can be connected to, for example, the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th transmit control line ELk, and the j-th data line DLj. In the embodiments, pixel PXij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4.

[0069] The pixel PXij in the disclosed embodiments may include a light-emitting element LD and a pixel circuit PC that controls the amount of current to be supplied to the light-emitting element LD.

[0070] The light-emitting element (LD) can be connected between a first electric power line PL1 and a second electric power line PL2. In an embodiment, for example, the first electrode (or anode electrode) of the light-emitting element LD can be electrically connected to the first electric power line PL1 via a second node N2, a first transistor M1, and a third transistor M3. The second electrode (or cathode electrode) of the light-emitting element LD can be electrically connected to the second electric power line PL2. The light-emitting element LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the first electric power line PL1 to the second electric power line PL2 via pixel circuitry.

[0071] Organic light-emitting diodes (OLEDs) can be selected as the light-emitting element (LD). Alternatively, inorganic light-emitting diodes such as micro-LEDs ("LEDs") or quantum dot LEDs can be selected as the light-emitting element (LD). The light-emitting element (LD) can be a combination of organic and inorganic materials or a combination of organic and inorganic materials. Although... Figure 4 The illustration shows a pixel PXij comprising a single light-emitting element (LD), but in this embodiment, pixel PXij may comprise multiple light-emitting elements (LDs). These multiple light-emitting elements (LDs) may be connected in series, in parallel, or in a series-parallel configuration.

[0072] The pixel circuit PC may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0073] Each of the first transistors M1 to the fourth transistor M4 may be a transistor including a body electrode. In an embodiment, each of the first transistors M1 to the fourth transistor M4 may include, for example, a metal-oxide-semiconductor field-effect transistor (“MOSFET”). In this case, the first transistors M1 to the fourth transistor M4 may be disposed (e.g., mounted) in a relatively small area, thus allowing pixel PXij to be applied to a high-resolution panel. The body electrode of the first transistors M1 to the fourth transistor M4 may be supplied with a first drive power VDD. In an embodiment, the body electrode of each of the first transistors M1 to the fourth transistor M4 may be electrically connected to, for example, a first power line PL1.

[0074] In the embodiments, each of the first transistor M1 to the fourth transistor M4 may include a P-type transistor. However, the foregoing example is illustrative, and at least one of the first transistor M1 to the fourth transistor M4 may be replaced by an N-type transistor.

[0075] The first transistor M1 may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2. Here, the term "connection" means electrical link or electrical connection. The gate electrode of the first transistor M1 may be connected to a third node N3. The first node N1 may refer to the node to which the second electrode of the third transistor M3 is connected. The second node N2 may refer to the node to which the first electrode of the light-emitting element LD is connected. The first transistor M1 may control the amount of current to be supplied from the first driving power VDD to the second driving power VSS via the light-emitting element LD in response to the voltage of the third node N3.

[0076] The second transistor M2 can be connected between the j-th data line DLj and the third node N3. The gate electrode of the second transistor M2 can be electrically connected to the i-th write scan line SL1i. When the first scan signal GW is supplied to the i-th write scan line SL1i, the second transistor M2 can be turned on to electrically connect the j-th data line DLj and the third node N3.

[0077] The first electrode of the third transistor M3 can be electrically connected to the first power line PL1, and its second electrode can be connected to the first node N1. The gate electrode of the third transistor M3 can be electrically connected to the k-th transmit control line ELk. The third transistor M3 can be turned off when a transmit control signal is supplied to the k-th transmit control line ELk, and can be turned on when no transmit control signal is supplied to it. When the third transistor M3 is turned off, the first power line PL1 and the first node N1 can be electrically disconnected.

[0078] The fourth transistor M4 may include a first electrode connected to the second node N2 and a second electrode electrically connected to the third power line PL3. The gate electrode of the fourth transistor M4 may be electrically connected to the i-th initialization scan line SL2i. When the second scan signal EB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 may be turned on to electrically connect the second node N2 to the third power line PL3.

[0079] A first capacitor C1 can be connected between the first node N1 and the third node N3. The first capacitor C1 can be driven as a coupling capacitor to transmit voltage changes from the first node N1 to the third node N3. Furthermore, the first capacitor C1 can store the voltage of the third node N3.

[0080] The second capacitor C2 can be connected between the third node N3 and the fourth power line PL4, which supplies reference power VRF. The voltage level of the reference power VRF can be set within a range not exceeding the maximum voltage of the second capacitor C2. In an embodiment, the voltage level of the reference power VRF can be lower than the voltage level of the first drive power VDD and higher than the voltage level of the initialization power Vint.

[0081] In other embodiments, the voltage level of the reference power VRF can be equal to the voltage level of the first drive power VDD. In this case, the second capacitor C2 can be connected between the third node N3 and the first power line PL1, which supplies the first drive power VDD.

[0082] The third capacitor C3 can be connected between the second node N2 and the third node N3. The third capacitor C3 can be driven as a coupling capacitor, thereby transmitting the voltage change of the second node N2 to the third node N3.

[0083] In an embodiment, each of the first capacitor C1 to the third capacitor C3 may include a metal-oxide-metal (“MOM”) capacitor or a metal-insulator-metal (“MIM”) capacitor.

[0084] In an embodiment, each of the first capacitor C1 and the second capacitor C2 may include a MOM capacitor or a MIM capacitor, and the third capacitor C3 may include a parasitic capacitor.

[0085] Figure 5 It shows the driver Figure 4 The waveform diagram shows an embodiment of the pixel method.

[0086] Reference Figure 2 , Figure 4 and Figure 5The data signal supplied to pixel PXij, located on the i-th horizontal line and j-th vertical line, during a horizontal time period 1H (or a predetermined horizontal time period), can be divided into a first time period T1, a second time period T2, and a third time period T3. The start time of the second time period T2 can be after the end time of the first time period T1. The start time of the third time period T3 can be after the end time of the second time period T2. After the horizontal time period 1H, a fourth time period T4, during which the light-emitting element LD emits light, can begin. The start time of the fourth time period T4 can be after the end time of the third time period T3.

[0087] The data driver 140 can supply the voltage Vdata of the data signal DATA to the j-th data line DLj during the first time period T1 to the third time period T3.

[0088] Scan driver 130 (or first scan driver 132) can supply a first scan signal GW to the i-th write scan line SL1i during the first time period T1 and the second time period T2.

[0089] Scan driver 130 (or second scan driver 134) can supply a second scan signal EB to the i-th initial scan line SL2i during the first time period T1 to the third time period T3.

[0090] Transmit driver 160 can supply transmit control signal EM to transmit control line ELk during the second time period T2.

[0091] The first time period T1 can be defined as the period during which the voltage of the first driving power VDD is applied to the first node N1, the voltage of the initialization power Vint is supplied to the second node N2, and the voltage of the data signal DATA Vdata is supplied to the third node N3. During the first time period T1, the light-emitting element LD can be initialized. During the first time period T1, the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be initialized, and simultaneously the voltage Vdata of the data signal DATA supplied to the third node N3 can be stored. The first time period T1 can also be referred to as the initialization period and the data signal writing period.

[0092] The second time period T2 can be the period during which the voltage of the initial power Vint is supplied to the second node N2, and the voltage Vdata of the data signal DATA is supplied to the third node N3. During the second time period T2, the voltage corresponding to the threshold voltage of the first transistor M1 can be stored in the first capacitor C1. The second time period T2 can also be referred to as the first threshold voltage compensation period.

[0093] During the third time period T3, the first transistor M1 can control the amount of current supplied from the first drive power VDD to the initialization power Vint in response to the voltage of the third node N3. In this case, unnecessary current can be prevented from being supplied to the light-emitting element LD after the second time period T2. The third time period T3 can also be referred to as the brightness control period.

[0094] During the fourth time period T4, the first transistor M1 can control the amount of current flowing from the first driving power VDD through the light-emitting element LD to the second driving power VSS in response to the voltage of the third node N3. During the fourth time period T4, the light-emitting element LD can emit light with a brightness corresponding to the amount of current supplied from the first transistor M1. The fourth time period T4 can also be referred to as the emission period.

[0095] Figures 6 to 9 This shows the pixel response to Figure 5 The circuit diagram of the signal operation process. Figures 6 to 9 The pixel circuit PC can correspond to Figure 4 The pixel circuit PC.

[0096] Reference Figure 6 During the first time period T1, the first scan signal GW is supplied to the i-th write scan line SL1i, and the second scan signal EB is supplied to the i-th initialization scan line SL2i. During the first time period T1, the transmit control signal EM is not supplied to the k-th transmit control line ELk. Therefore, the third transistor M3 can be set to the on state. When the third transistor M3 is on, the voltage of the first drive power VDD is supplied to the first node N1.

[0097] When the first scan signal GW is supplied to the i-th write scan line SL1i, the second transistor M2 is turned on. When the second transistor M2 is turned on, the voltage Vdata of the data signal DATA is supplied from the j-th data line DLj to the third node N3. Here, the first capacitor C1 can be initialized by the voltage Vdata of the data signal DATA and the voltage of the first drive power VDD. In an embodiment, for example, during the first time period T1, the first capacitor C1 can be charged with a voltage corresponding to the voltage Vdata of the data signal DATA and the first drive power VDD, regardless of the voltage charged in the previous time period (or the previous frame period).

[0098] When the second scan signal EB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the initialization power Vint is supplied to the second node N2. When the initialization power Vint is supplied to the second node N2, the light-emitting element LD can be initialized. In an embodiment, when the initialization power Vint is supplied, the parasitic capacitance of the light-emitting element LD can, for example, be discharged. Here, the initialization power Vint can be set to the voltage at which the light-emitting element LD is turned off (or does not emit light). As a result, the light-emitting element LD can be set to a non-emitting state.

[0099] The second capacitor C2 can be initialized by the voltage Vdata of the data signal DATA supplied through the j-th data line DLj. In an embodiment, for example, during the first time period T1, the second capacitor C2 can be charged with a voltage corresponding to the voltage Vdata of the data signal DATA and the reference power VRF, regardless of the voltage charged in the previous time period (or the previous frame period).

[0100] The third capacitor C3 can be initialized using the voltage Vdata of the data signal DATA supplied to the third node N3 and the voltage of the initialization power Vint supplied to the second node N2. In an embodiment, for example, during the first time period T1, the third capacitor C3 can be charged with the voltage corresponding to the voltage Vdata of the data signal DATA and the initialization power Vint, regardless of the voltage charged in the previous time period (or the previous frame period).

[0101] During the first time period T1, in response to the voltage of the third node N3, the current supplied from the first transistor M1 can be supplied to the initialization power Vint via the fourth transistor M4. Therefore, during the first time period T1, the light-emitting element LD can remain in a non-emitting state.

[0102] Reference Figure 7 During the second time period T2, the second transistor M2 can be kept in the on state by the first scan signal GW supplied to the i-th write scan line SL1i, and the fourth transistor M4 can be kept in the on state by the second scan signal EB supplied to the i-th initialization scan line SL2i.

[0103] During the second time period T2, the third transistor M3 can be turned off by the transmit control signal EM supplied to the k-th transmit control line ELk. When the third transistor M3 is turned off, the electrical connection between the first power line PL1 and the first node N1 can be interrupted.

[0104] Since the second transistor M2 is set to the on state during the second time period T2, the voltage Vdata of the data signal DATA is supplied from the j-th data line DLj to the third node N3. In this case, the voltage of the first node N1 can be reduced from the voltage of the first drive power VDD to the voltage obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal DATA (Vdata+|Vth(M1)|).

[0105] In other words, during the second time period T2, the third node N3 can be set to the voltage Vdata of the data signal DATA, and the first node N1 can be set to the voltage obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal DATA (Vdata+|Vth(M1)|). Therefore, during the second time period T2, the threshold voltage of the first transistor M1 can be stored in the first capacitor C1.

[0106] Since the fourth transistor M4 is set to the on state during the second time period T2, the current supplied from the first node N1 to the second node N2 via the first transistor M1 can be supplied to the initialization power Vint via the fourth transistor M4. Therefore, the light-emitting element LD can remain in a non-emitting state during the second time period T2.

[0107] Reference Figure 8 During the third time period T3, the supply of the transmit control signal EM to the k-th transmit control line ELk is interrupted, allowing the third transistor M3 to be turned on. Additionally, during the third time period T3, the supply of the first scan signal GW to the i-th write scan line SL1i can be interrupted, allowing the second transistor M2 to be turned off. During the third time period T3, the supply of the second scan signal EB to the i-th initialization scan line SL2i is maintained, keeping the fourth transistor M4 on.

[0108] During the third time period T3, because the third transistor M3 is set to the on state, the first drive power VDD is supplied to the first node N1. Because the second transistor M2 is set to the off state, the supply of the data signal DATA voltage Vdata from the j-th data line DLj to the third node N3 is interrupted. Therefore, the voltage of the third node N3 can be the sum of the data signal DATA voltage Vdata and the value reflecting the difference between the voltage of the first node N1 and the voltage of the first drive power VDD during the second time period T2 ((α(VDD-(Vdata+|Vth(M1)|))).

[0109] The first transistor M1 can control the amount of current supplied from the first drive power VDD to the second node N2 in response to the voltage applied to the third node N3.

[0110] Here, because the fourth transistor M4 is set to the on state, the current supplied to the second node N2 can be supplied to the initialization power Vint. Therefore, during the third time period T3, the light-emitting element LD can be set to a non-emitting state, thereby enabling accurate grayscale representation of the display device 100. In an embodiment, while the second time period T2 has passed, the voltage of the second node N2 can increase to, for example, a voltage higher than the desired voltage. Therefore, unexpected current may be supplied to the light-emitting element LD. In an embodiment, even when black grayscale is achieved in pixel PXij, the light-emitting element LD may emit light, for example, temporarily. In the disclosed embodiment, during the third time period T3, the current supplied from the first transistor M1 can be supplied to the initialization power Vint, thereby preventing unexpected emission of light from the light-emitting element LD.

[0111] Reference Figure 9 During the fourth time period T4, the supply of the second scan signal EB to the i-th initialization scan line SL2i is interrupted, causing the fourth transistor M4 to turn off. During the fourth time period T4, the first scan signal GW is not supplied to the i-th write scan line SL1i, causing the second transistor M2 to remain off. During the fourth time period T4, the transmit control signal EM is not supplied to the k-th transmit control line ELk. Therefore, the third transistor M3 remains on.

[0112] Here, the first transistor M1 can control the amount of current supplied from the first driving power VDD to the second driving power VSS via the light-emitting element LD in response to the voltage of the third node N3. During the fourth time period T4, the light-emitting element LD can generate light with a brightness corresponding to the amount of driving current supplied from the first transistor M1.

[0113] Reference Figures 6 to 9 The threshold voltage compensation process in the disclosed embodiments is described in detail.

[0114] Reference Figure 7The threshold voltage of the first transistor M1 can be determined by the voltage difference between its body electrode and source electrode (e.g., the first node N1). In an embodiment, for example, assuming the voltage of the first drive power VDD is set to 8 volts (V), the body electrode of the first transistor M1 can be set to 8V during the second time period T2, while its source electrode can be set to a voltage lower than the voltage of the body electrode. In an embodiment, for example, assuming the first node N1 is set to 4V, the voltage difference between the body electrode and source electrode of the first transistor M1 can be set to 4V (e.g., VBS = 4V). Here, the first transistor M1 can have a first threshold voltage corresponding to 4V as the voltage difference between the body electrode and the source electrode.

[0115] During the second time period T2, the first threshold voltage can be compensated. In an embodiment, during the second time period T2, the third node N3 is set to the voltage Vdata of the data signal DATA, and the first node N1 is set to a voltage obtained, for example, by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal DATA (Vdata + |Vth(M1)|). The threshold voltage of the first transistor M1 can be stored in the first capacitor C1. In the disclosed embodiment, during the second time period T2, the threshold voltage of the first transistor M1 can be primarily compensated. In an embodiment, after the second time period T2, the third transistor M3 can be turned on, thereby allowing, for example, the threshold voltage reflected in the first node N1 to be reflected in the voltage of the third node N3. Based on the voltage of the third node N3, the on and / or off state of the first transistor M1 can be controlled. Therefore, the first threshold voltage of the first transistor M1 can be compensated.

[0116] Reference Figure 8 During the third time period T3, the first node N1 can be set to the voltage of the first drive power VDD. Therefore, the source electrode of the first transistor M1 can have the same voltage as its body electrode. In an embodiment, the voltage difference between the source electrode and body electrode of the first transistor M1 can be, for example, approximately 0V. Based on the changing voltage difference between the body electrode and source electrode of the first transistor M1, the first transistor M1 can have a second threshold voltage different from the first threshold voltage.

[0117] During the third time period T3, when the voltage of the first driving power VDD is supplied to the first node N1, the voltage of the third node N3 can vary according to the voltage of the first node N1. In this embodiment, the voltage of the third node N3 can be set as shown in Equation 1.

[0118] [Equation 1]

[0119] Referring to Equation 1, VN3a can represent the voltage of the third node N3. Since the first driving power VDD is supplied to the first node N1 during the third time period T3, the voltage of the first node N1 during the third time period T3 can be changed from the voltage obtained by adding the voltage Vdata of the data signal DATA to the absolute threshold voltage (|Vth(M1)|) of the first transistor M1 (Vdata+|Vth(M1)|) to the voltage of the first driving power VDD. Therefore, VDD-(Vdata+|Vth(M1)|) can represent the voltage change of the first node N1.

[0120] The voltage of the third node N3 can also be changed through the coupling of the first capacitor C1. The amount of voltage change of the third node N3 can be determined based on the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3. In an embodiment, as shown in Equation 1, for example, the amount of voltage change of the third node N3 due to the amount of voltage change of the first node N1 can be a value obtained by multiplying the amount of voltage change of the first node N1 by C1 / (C1+C2+C3). When the amount of voltage change of the third node N3 is controlled by the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, the voltage range of the data signal can be sufficiently widened. In an embodiment, for example, the voltage range of the data signal can be determined based on the components included in the pixel PXij. In the disclosed embodiment, the voltage of the third node N3 can be changed according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, thereby allowing an increase in the range of the voltage Vdata of the data signal DATA. In an embodiment, for example, due to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, the voltage change of the third node N3 can be relatively reduced, thereby reducing the voltage of the third node N3. Therefore, even when the voltage range of the data signal is designed to be relatively wide, the voltage applied to the third node N3 can fall within the desired voltage range. In an embodiment, the data driver 140 can use, for example, a relatively wide voltage range of approximately 3.29V to implement 255 gray levels. As a result, a fine grayscale representation of pixel PXij in the disclosed embodiment is achieved.

[0121] The second capacitor C2 can adjust the rate at which the voltage change at the first node N1 reflects the voltage change at the second node N2. In an embodiment, for example, as the second capacitor C2 increases, the voltage change at the third node N3 relative to the voltage change at the first node N1 can decrease. In this case, the voltage range of the data signal can be selected to be more suitable for the display device 100.

[0122] After setting the voltage of the third node N3 as shown in Equation 1, the amount of current supplied to the second node N2 through the first transistor M1 can vary in response to the voltage of the third node N3. Therefore, the voltage of the anode electrode (e.g., the second node N2) of the light-emitting element LD can be changed.

[0123] The second node N2 and the third node N3 are connected to each other via a third capacitor C3. The voltage of the third node N3 can be further changed according to the voltage change of the second node N2. In an embodiment, for example, the voltage of the third node N3 can be changed through the coupling of the third capacitor C3.

[0124] [Equation 2]

[0125] Referring to Equation 2, ΔVN2 represents the voltage change at the second node N2, and VN3b represents the voltage at the third node N3 corresponding to the voltage change (ΔVN2). As shown in Equation 2, the voltage at the third node N3 can be determined by the sum of VN3a from Equation 1 and the value obtained by multiplying the voltage change (ΔVN2) at the second node N2 by C3 / (C1+C2+C3).

[0126] In the disclosed embodiment, the threshold voltage of the first transistor M1 can be compensated a second time by reflecting the voltage change (ΔVN2) of the second node N2 in the voltage of the third node N3 via the third capacitor C3.

[0127] The voltage change (ΔVN2) of the second node N2 can be set in response to a change in the threshold voltage of the first transistor M1. In an embodiment, for example, the voltage change (ΔVN2) of the second node N2 can be set to a different value in response to a change in the threshold voltage of the first transistor M1 from a first threshold voltage to a second threshold voltage. In an embodiment, for example, the voltage change (ΔVN2) of the second node N2 can reflect the second threshold voltage of the first transistor M1. In response to the voltage change (ΔVN2) of the second node N2, the voltage of the third node N3 can be further changed, causing the first transistor M1 to turn on and / or off, thereby compensating for the second threshold voltage of the first transistor M1.

[0128] In the disclosed embodiments, it is possible to include... Figure 2 The first transistor M1 in each of the pixels PX independently performs threshold voltage compensation. In the embodiment, it includes... Figure 2Each of the pixels PX in the pixel assembly 110 may include, for example, a first transistor. Here, during the driving process of the display device 100, each first transistor of the pixel PX may have a different threshold voltage. Here, the voltage variation of the first node N1 and the second node N2 of the pixel PX may also be set to different values ​​in response to the respective threshold voltage of the corresponding first transistor. Since the voltage variation of the first node N1 and the second node N2 is reflected in the third node N3, the threshold voltage of the first transistor included in each of the pixels PX can be compensated. In the disclosed embodiments, the display device 100 may have improved grayscale representation performance.

[0129] Figure 10 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Figure 11 It is shown Figure 10 The diagram shows an example of an electronic device 1000, which is a smartphone. Figure 12 It is shown Figure 10 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0130] Reference Figures 10 to 12 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 2 The display device. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as... Figure 11 As shown, the electronic device 1000 can be implemented as a smartphone. In an embodiment, as... Figure 12 As shown, the electronic device 1000 can be implemented as a tablet computer. However, the foregoing example is illustrative, and the electronic device 1000 is not limited to the foregoing example. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, head-mounted display device, etc.

[0131] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, etc. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0132] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory of the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0133] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0134] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0135] Power supply 1050 can supply the power required to operate electronic device 1000. For example, power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, power supply 1050 can supply power to display device 1060.

[0136] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0137] According to the pixels in the disclosed embodiments and the display device including the pixels, the pixels can be implemented using transistors (e.g., MOSFETs) to suit relatively high resolutions.

[0138] However, the effects of disclosure are not limited to those described above, and various modifications can be made without departing from the spirit and scope of disclosure.

[0139] The scope of the disclosure is not limited to the detailed description in the specification, but should be defined by the appended claims. Furthermore, all changes or modifications to the disclosure derived from the meaning and scope of the claims, and their equivalents, should be construed as being included within the scope of the disclosure.

Claims

1. A pixel, the pixel comprising: The first transistor includes a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; A second transistor is connected between the data line and the third node, and the second transistor includes a gate electrode electrically connected to the first scan line; A third transistor is connected between a first power line supplied with a first driving power and the first node, the third transistor including a gate electrode electrically connected to an emitter control line; A first capacitor is connected between the first node and the third node; The second capacitor is connected between the third node and the reference power line supplied with reference power; A third capacitor is connected between the second node and the third node; as well as A light-emitting element is connected between the second node and a second power line supplied with second driving power.

2. The pixel of claim 1, further comprising a fourth transistor, the fourth transistor comprising a first electrode connected to the second node, a second electrode electrically connected to a third power line supplied with initialization power, and a gate electrode electrically connected to a second scan line.

3. The pixel as described in claim 2, wherein, The voltage level of the reference power is lower than the voltage level of the first driving power, but higher than the voltage level of the initialization power.

4. The pixel as described in claim 2, in, The voltage level of the reference power is equal to the voltage level of the first drive power, and The reference power line is the first power line.

5. The pixel as described in claim 2, wherein, When the voltage of the initial power is supplied to the second node, the light-emitting element is turned off.

6. The pixel as claimed in claim 2, wherein, Each of the first to the fourth transistors includes a metal-oxide-semiconductor field-effect transistor containing a body electrode.

7. The pixel as claimed in claim 6, wherein, The voltage of the first driving power is supplied to the body electrode of each of the first to fourth transistors.

8. The pixel as described in claim 2, in, The horizontal time period includes the first time period, the second time period, and the third time period. During the first time period, the second transistor, the third transistor, and the fourth transistor are set to the on state. During the second time period, the second transistor and the fourth transistor are set to the on state, and the third transistor is set to the off state. During the third time period, the third transistor and the fourth transistor are set to the on state, and the second transistor is set to the off state.

9. The pixel as claimed in claim 8, wherein, During the first time period to the third time period, the voltage of the data signal is supplied to the data line.

10. The pixel as claimed in claim 1, wherein, Each of the first to the third capacitors comprises a metal-oxide-metal capacitor or a metal-insulator-metal capacitor.

11. The pixel as described in claim 1, in, Each of the first capacitor and the second capacitor comprises a metal-oxide-metal capacitor or a metal-insulator-metal capacitor, and The third capacitor includes a parasitic capacitor.

12. A display device, the display device comprising: Multiple pixels are connected to a write scan line, an initialization scan line, a data line, and an emit control line. These multiple pixels include a pixel located in the i-th pixel row and j-th pixel column, where i and j are both natural numbers greater than zero. The pixel located in the i-th pixel row and j-th pixel column includes: The first transistor includes a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; The second transistor is connected between the j-th data line and the third node in the data lines, and is configured to turn on when the first scan signal is supplied to the first scan line in the write scan line. The third transistor is connected between the first power line supplied with the voltage of the first drive power and the first node, and is configured to be cut off when the transmit control signal is supplied to the kth transmit control line, where k is a natural number greater than zero. A first capacitor is connected between the first node and the third node; The second capacitor is connected between the third node and the reference power line supplied with reference power; A third capacitor is connected between the second node and the third node; and A light-emitting element is connected between the second node and a second power line supplied with second driving power.

13. The display device as claimed in claim 12, wherein, The pixel located in the i-th pixel row and j-th pixel column further includes a fourth transistor, the fourth transistor including a first electrode connected to the second node and a second electrode electrically connected to a third power line supplied with initialization power, the fourth transistor being configured to turn on when a second scan signal is supplied to the second scan line in the initialization scan line.

14. The display device as claimed in claim 13, wherein, The voltage level of the reference power is lower than the voltage level of the first driving power, but higher than the voltage level of the initialization power.

15. The display device as claimed in claim 13, in, The voltage level of the reference power is equal to the voltage level of the first drive power, and The reference power line is the first power line.

16. The display device as claimed in claim 15, wherein, Each of the first to fourth transistors includes a metal-oxide-semiconductor field-effect transistor containing a body electrode, and the voltage of the first drive power is supplied to the body electrode.

17. An electronic device, the electronic device comprising: A processor used to provide input image data; as well as A display device for displaying an image based on the input image. The display device includes a plurality of pixels connected to a write scan line, an initialization scan line, a data line, and an emission control line. The plurality of pixels includes a pixel located in the i-th pixel row and j-th pixel column, where i and j are both natural numbers greater than zero. The pixel located in the i-th pixel row and j-th pixel column includes: The first transistor includes a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; The second transistor is connected between the j-th data line and the third node in the data lines, and is configured to turn on when the first scan signal is supplied to the first scan line in the write scan line. The third transistor is connected between the first power line supplied with the voltage of the first drive power and the first node, and is configured to be cut off when the transmit control signal is supplied to the kth transmit control line, where k is a natural number greater than zero. A first capacitor is connected between the first node and the third node; The second capacitor is connected between the third node and the reference power line supplied with reference power; A third capacitor is connected between the second node and the third node; and A light-emitting element is connected between the second node and a second power line supplied with second driving power.

Images