Display panel and display device

Abstract

The invention discloses a display panel and a display device, a first control module and a second control module can be added on the basis of a shift register, the potential of a second node is adjusted through the first control module, and the potential of a first node is adjusted through the second control module; under the condition of abnormal power failure of a display panel, the potentials of a first node and a second node are changed through a first control module and a second control module, so that an output signal is a cut-off voltage signal, a data signal input to a pixel circuit can be controlled to be a cut-off signal, and black is written to a transistor in the pixel circuit; a transistor in the pixel circuit is ensured to be disconnected, input of a power supply signal to a driving transistor is blocked, then the state of the driving transistor is directly controlled according to a limited data signal, and black writing operation is achieved. According to the embodiment of the invention, the leakage current is prevented from being transmitted to the light-emitting element through black writing or disconnection operation, and the splash screen problem caused by abnormal power-off of the display panel is solved.

Description

Technical Field

[0001] This application belongs to the field of display control technology, and in particular relates to a display panel and display device. Background Technology

[0002] Typically, when a display panel is powered on or off, the drive control signal needs to quickly provide or cut off power to ensure rapid illumination upon startup and rapid shutdown upon power failure. However, due to delays in some circuits or components during rapid power-down, residual current can remain, leading to screen flickering during abnormal power-down.

[0003] Therefore, how to solve the screen flickering problem during abnormal power-off has become an urgent technical problem to be solved. Summary of the Invention

[0004] This application provides a display panel and display device that can solve the screen flickering problem caused by the inability of the driver chip to operate when the display panel is abnormally powered off, thereby improving the control effect of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift registers, each shift register including: an input module, a first control module, a second control module, a gating module, a first output module, and a second output module.

[0006] The potentials of the first and second nodes are adjusted by the input module; the potential of the second node is adjusted by the first control module; the potential of the third node is adjusted by the second control module; and the first and second nodes are connected by the gating module. In the event of an abnormal power failure, the output signals of the first and second output modules are changed by adjusting the potentials of the first and second nodes.

[0007] Secondly, embodiments of this application provide a display device, including the display panel of the first aspect.

[0008] The display panel and display device provided in this application embodiment can add a first control module and a second control module to the shift register. The first control module adjusts the potential of the second node, and the second control module adjusts the potential of the first node. In the event of an abnormal power failure of the display panel, the first and second control modules change the potentials of the first and second nodes, making the output signal a cutoff voltage signal. This controls the data signal input to the pixel circuit to be a cutoff signal, writing black to the internal transistor of the pixel circuit, ensuring that the internal transistor of the pixel circuit is disconnected, blocking the power signal input to the driving transistor, and then directly controlling the state of the driving transistor according to the defined data signal to realize the black-writing operation. By writing black or disconnecting, leakage current is prevented from being transmitted to the light-emitting element, solving the screen flickering problem caused by abnormal power failure of the display panel. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a shift register structure provided by related technologies;

[0011] Figure 2 This is a schematic diagram of the structure of a shift register in a display panel provided in an embodiment of this application;

[0012] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0013] Figure 4 This is a timing diagram of a pixel circuit provided in an embodiment of this application;

[0014] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0015] Figure 6 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0016] Figure 7 This is a timing diagram of a display panel provided in an embodiment of this application;

[0017] Figure 8 This is a schematic diagram of the structure of a first control module provided in an embodiment of this application;

[0018] Figure 9 This is a schematic diagram of the structure of a second control module provided in an embodiment of this application;

[0019] Figure 10 This is a schematic diagram of the structure of a gating module provided in an embodiment of this application;

[0020] Figure 11 This is a schematic diagram of the structure of an input module provided in an embodiment of this application;

[0021] Figure 12 This is a schematic diagram of the structure of a first output module provided in an embodiment of this application;

[0022] Figure 13 This is a schematic diagram of the structure of a second output module provided in an embodiment of this application;

[0023] Figure 14 This is a schematic diagram of another shift register structure in a display panel provided in an embodiment of this application;

[0024] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0025] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0027] Full-screen black mode sets all pixels on the display panel to black, typically used for screen savers, power-saving modes, or special display needs. This operation forces all pixels to turn off or display a pure black screen. The full-black state usually recovers automatically after user operation or system timeout.

[0028] Display panel flickering refers to irregular changes in brightness or flickering on the screen, typically manifesting as image jitter, brightness fluctuations, or abnormal colors. When the monitor's refresh rate is below 75Hz, image tearing and jittering are more likely to occur, especially at 4K resolution when the graphics card is under heavy load.

[0029] Figure 1 This is a schematic diagram of a shift register structure provided by related technologies. According to... Figure 1 The provided diagram shows that, under the control of the CK, IN, and XCK signals, the gate voltages of transistors M9 and M10 are periodically changed, causing the output signal to alternate between high and low levels, providing gate drive signals for the subsequent pixel circuit. However, when the display panel experiences an abnormal power failure, residual charge in the data lines can cause abnormal illumination, flickering, or inability to perform black-filling operations. Alternatively, after black-filling operations, the cutoff level signal VGH drops to 0, but the power supply voltage PVDD does not drop to 0V. This results in incomplete black-filling operations by the transistors in the pixel circuit during abnormal power-off, with the power supply voltage PVDD still flowing into the light-emitting element through the driving transistor, causing screen flickering.

[0030] To address the screen flickering problem caused by abnormal power-down of display panels, this application provides a display panel and display device. By improving the structure of the shift register and adding a first control module and a second control module, the first control module adjusts the potential of the second node, and the second control module adjusts the potential of the first node. In the event of an abnormal power-down, the first and second control modules change the potentials of the first and second nodes, making the output signal a conduction voltage signal. This inputs a conduction signal to the pixel circuit, causing the internal compensation transistor of the pixel circuit to conduct and write the driving transistor black, ensuring that the internal driving transistor of the pixel circuit is disconnected and blocking the power signal input to the driving transistor, thus achieving the write-black operation. By using the write-black or disconnect operation, leakage current is prevented from flowing into the light-emitting element, solving the screen flickering problem caused by abnormal power-down of the display panel. The display panel provided in this application embodiment is described below.

[0031] Figure 2 This is a schematic diagram of the structure of a shift register in a display panel provided in an embodiment of this application. According to... Figure 2The provided diagram shows that the display panel includes a gate driving circuit, which includes multiple cascaded shift registers. The shift registers include: an input module 10, a first control module 20, a second control module 30, a gating module 40, a first output module 50, and a second output module 60.

[0032] The input module 10 is electrically connected to multiple input signal terminals, a first node N1, and a second node N2, and adjusts the potential of the first node N1 and the second node N2 based on the signals from the multiple input signal terminals.

[0033] The multiple input signal terminals mentioned here can be understood as signal terminals that control the shift register, such as clock signal terminals, synchronous clock signal terminals, signal writing terminals, etc., which provide signals to the input module.

[0034] The first node is set between the input module and the gating module, the second node is set between the input module and the first output module, and the third node is set between the gating module and the second output module.

[0035] The input module 10 receives multiple externally provided input signals and controls the input module 10 to adjust the potential of the first node N1. When the gating module 40 is turned on, the signal of the first node N1 is output to the third node N3 through the gating module 40. The second output module 60 determines the output signal based on the potential of the third node N3. Simultaneously, the input module 10 adjusts the potential of the second node N2, and the first output module 50 determines the output signal based on the potential of the second node N2.

[0036] according to Figure 2 The provided diagram shows that the first control module 20 is electrically connected to the cutoff level signal terminal, the first control line RST1, and the second node N2. Based on the signals from the cutoff level signal terminal and the first control line RST1, the potential of the second node N2 is adjusted.

[0037] The second control module 30 is electrically connected to the on-level signal terminal, the second control line RST2, and the third node N3. Based on the signals of the on-level signal terminal and the second control line RST2, it adjusts the potential of the third node N3.

[0038] The on-level mentioned here refers to the level that controls the corresponding module to be turned on, and the off-level refers to the level that controls the corresponding module to be turned off or disconnected. In this embodiment, the on-level is low and the off-level is high.

[0039] The first and second control lines mentioned here can be understood as the external control signals of the shift register.

[0040] During the normal display phase of the display panel, the first control module 20 and the second control module 30 are not activated. Low-level signals are output through the first control line RST1 and the second control line RST2, so that the cutoff level signal terminal is kept disconnected from the second node N2, and the conduction level signal terminal is kept disconnected from the third node N3. At this time, the shift register of the display panel operates normally and is not affected by the first control module 20 and the second control module 30.

[0041] During the abnormal power-down phase of the display panel, in order to completely turn off the driving transistors in the pixel circuit, a shift register outputs a control signal to keep the compensation transistors in the pixel circuit on, writing data signals (e.g., black state voltage) into the driving transistors, thus turning off the driving transistors in the pixel circuit. For example, when the display panel abnormally powers down, the first control line RST1 controls the first control module 20 to conduct, causing the potential of the second node N2 to rise. At the same time, the second control line RST2 controls the second control module 30 to conduct, causing the potential of the third node N3 to fall. The first output module 50 and the second output module 60 output low-level signals based on the potentials of the second node N2 and the third node N3, thereby controlling the compensation transistors in the pixel circuit to conduct, writing data signals into the driving transistors, causing the driving transistors to turn off, blocking the driving current generated by the driving transistors to light up the light-emitting elements, thus achieving the purpose of writing the entire screen to black.

[0042] The gating module 40 is electrically connected to the first node N1, the third node N3, and the third control line RST3, and controls the connection state between the first node N1 and the third node N3 based on the signal of the third control line RST3.

[0043] The gating module 40 is controlled by the third control line RST3. During the normal display phase of the display panel, the third control line RST3 inputs a low-level signal, controlling the gating module 40 to conduct, thereby connecting the first node N1 and the third node N3, facilitating the transmission of the signal from the input module 10 to the second output module 60 through the first node N1 and the third node N3. During the abnormal power-off period of the display panel, the third control line RST3 inputs a high-level signal, controlling the gating module 40 to deactivate, thereby disconnecting the first node N1 and the third node N3, facilitating the blocking of further input signals to the third node N3.

[0044] according to Figure 2 The provided diagram shows that the first output module 50 is electrically connected to the cutoff level signal terminal, the second node N2, and the gate drive circuit output terminal OUT. Based on the potential of the second node N2, the connection state between the cutoff level signal terminal and the gate drive circuit output terminal OUT is controlled.

[0045] The second output module 60 is electrically connected to the input signal terminal, the third node N3, and the gate drive circuit output terminal OUT. Based on the potential of the third node N3, it controls the connection state between the input signal terminal and the gate drive circuit output terminal OUT.

[0046] The first output module 50 and the second output module 60 are used to transmit the signal to the output terminal OUT of the gate drive circuit of the shift register.

[0047] During the abnormal power-down phase of the display panel, the first output module 50 is disconnected under the control of the high-level signal of the second node N2, blocking the output of the cutoff level signal VGH to the gate drive circuit output terminal OUT. At this time, the second output module 60 is turned on according to the low-level signal of the third node N3, and then outputs the turn-on level signal VGL to the gate drive circuit output terminal OUT, so that the gate drive circuit output terminal OUT provides a low-level signal to the pixel circuit. The low-level signal controls the internal compensation transistor of the pixel circuit to turn on, thereby writing the data signal to the drive transistor, controlling the drive transistor to turn off, blocking the drive transistor from generating drive current to light up the light-emitting element, thereby achieving the purpose of writing the entire screen to black. By setting the first transistor and the second transistor, and using the first control line RST1 and the second control line RST2, the output terminals of each stage shift register are the same. When the display panel experiences an abnormal power-down, by controlling the output of the gate drive circuit output terminal OUT to output a turn-on level, the transistor in the pixel circuit that performs data writing is turned on. This controls the drive transistor in the pixel circuit to be written with a black state voltage, thereby achieving the effect of turning off the drive transistor and solving the screen flickering problem.

[0048] pass Figure 2 The provided shift register output control signal provides gate control signals for the currently connected pixel circuit. According to... Figure 2 The provided diagram illustrates how the first control module 20 and the second control module 30 control the states of the first output module 50 and the second output module 60, thereby ensuring that the output terminals of each shift register output the same signal at the same time. For example, if the first control module 20 controls the first output module 50 to be off and the second control module 30 controls the second output module 60 to be on, then the output terminals of each shift register will output the XCK signal.

[0049] according to Figure 2The provided diagram illustrates that during normal display periods on the display panel, multiple input terminals output input signals to control input module 10 to input write data to gating module 40. The third control line RST3 controls gating module 40 to periodically conduct, inputting the data write signal to the second output module 60. The first output module 50 and the second output module 60 then input periodic data signals to the pixel circuit, causing the transistors in the pixel circuit to periodically turn on and off, enabling normal display of the OLED light-emitting element. During periods of abnormal power-off on the display panel, to ensure that the driving transistors in the pixel circuit are completely disconnected and to prevent the power supply voltage PVDD from continuing to power the light-emitting element, a shift register needs to input a scanning signal to the pixel circuit to activate the compensation transistors. At this time, the first control module 20 and the second control module 30 are turned on by the first control line RST1 and the second control line RST2, which raises the potential of the second node N2 and lowers the potential of the third node N3. The first output module 50 and the second output module 60 output low-level signals (signals that turn on the transistors in the pixel circuit) to control the compensation transistors in the pixel circuit to turn on, write the data signal DATA into the driving transistor, turn off the driving transistor, and block the driving transistor from generating driving current to light up the light-emitting element, thereby achieving the purpose of writing the entire screen to black and avoiding the screen flickering problem during abnormal power-off periods.

[0050] The display panel structure provided in this application embodiment can add a first control module and a second control module to the shift register. The first control module adjusts the potential of the second node, and the second control module adjusts the potential of the third node. In the event of an abnormal power failure of the display panel, the first and second control modules change the potentials of the third node and the second node, making the output signal a conduction level signal. This inputs a conduction signal to the pixel circuit, and after the internal transistor of the pixel circuit is turned on, it writes the data signal (such as black state voltage) into the driving transistor, controlling the driving transistor to turn off. This achieves writing black to the driving transistor, ensuring that the internal driving transistor of the pixel circuit is turned off, blocking the driving transistor from generating driving current to light up the light-emitting element, thereby achieving the purpose of writing black to the entire screen. By writing black or turning off the operation, leakage current is prevented from entering the light-emitting element, solving the screen flickering problem caused by abnormal power failure of the display panel.

[0051] according to Figure 2 The provided diagram shows multiple input signal terminals, including a first input signal terminal XCK, a second input signal terminal CK, and a third input signal terminal IN.

[0052] The first input terminal of the input module 10 is electrically connected to the first input signal terminal XCK, the second input terminal of the input module 10 is electrically connected to the second input signal terminal CK, the third input terminal of the input module 10 is electrically connected to the third input signal terminal IN, the fourth input terminal of the input module 10 is electrically connected to the cutoff level signal terminal, the fifth input terminal of the input module 10 is electrically connected to the on level signal terminal, the first output terminal of the input module 10 is electrically connected to the second node N2, and the second output terminal of the input module 10 is electrically connected to the first node N1.

[0053] The first input signal terminal XCK and the second input signal terminal CK are used to ensure that the waveform at the output of the shift register is the same as the waveform output from the first input signal terminal XCK. Simultaneously, the first and second input signal terminals are complementary clock signals. The third input signal terminal is used to write the trigger signal.

[0054] In the first operating condition, the first control line RST1 and the second control line RST2 provide a cutoff level, and the third control line RST3 provides a conduction level.

[0055] In the second operating condition, at least the second control line RST2 provides an on level.

[0056] The first operating condition mentioned here can be understood as the period when the display panel is displaying normally. The second operating condition mentioned here can be understood as the period when the display panel is not displaying normally, such as during an abnormal power-off.

[0057] according to Figure 2 The provided diagram illustrates that during the normal display period of the display panel, a cutoff level signal VGH is provided through the first control line RST1 and the second control line RST2, keeping the first control module 20 and the second control module 30 in a disconnected state. The third control line RST3 provides a conduction level signal VGL to the gating module 40, enabling the gating module 40 to conduct internally, thereby outputting the written data from the first node N1 to the second output module 60 connected to the third node N3. During the second operating condition period when the display panel is abnormally powered down, the second control line RST2 provides a conduction level signal VGL, controlling the second control module 30 to conduct internally, causing the potential of the third node N3 to decrease, controlling the second output module 60 to output a conduction level signal VGL to the pixel circuit. After receiving the conduction level signal VGL, the pixel circuit controls the corresponding transistor to conduct, directly writing the data signal into the driving transistor, controlling the driving transistor to disconnect, thereby turning off the driving transistor, realizing the write-to-black operation, blocking the driving transistor from generating driving current to light up the light-emitting element, thus achieving the purpose of writing the entire screen to black and avoiding screen flickering.

[0058] according to Figure 2 The structure of the provided display panel, Figure 3 This is a schematic diagram of the structure of a first pixel circuit provided in an embodiment of this application. Figure 4 This is a timing diagram of a pixel circuit provided in an embodiment of this application. According to... Figure 3 The provided diagram shows that the gate driving circuit includes a first gate driving circuit, and the control signal S2 output from the output terminal of the first gate driving circuit is used to control whether the data signal DATA is written into the pixel circuit.

[0059] In the second operating condition where the display panel experiences an abnormal power-off, the first control line RST1 and the second control line RST2 both provide a conduction level signal VGL, the first input signal terminal XCK and the second input signal terminal CK both provide a conduction level signal VGL, the third control line RST3 provides a cutoff level signal VGH, and the data signal DATA is a black state voltage.

[0060] according to Figure 3 and Figure 4 The provided diagram shows that during the abnormal power-off period of the display panel, a conduction level signal VGL is provided through both the first control line RST1 and the second control line RST2 to control the conduction inside the first control module 20 and the second control module 30. A conduction level signal VGL is provided through both the first input signal terminal XCK and the second input signal terminal CK to control the output control signal S2 to be output to the transistor in the pixel circuit. The output control signal S2 controls the pixel circuit transistor to conduct, outputting the data signal DATA as a black state voltage, and writing the black state voltage into the driving transistor M3, causing the driving transistor M3 to disconnect, blocking the connection between the power supply voltage PVDD and the light-emitting element OLED, realizing the black writing operation and avoiding screen flickering.

[0061] according to Figure 3 and Figure 4 The provided diagram shows that the gate driving circuit includes a second gate driving circuit. The control signal S1 output from the output terminal of the second gate driving circuit is used to control whether the reset signal VREF is written into the pixel circuit.

[0062] In the second operating condition where the display panel experiences an abnormal power-off, the second control line RST2 provides a conduction level signal VGL, the first input signal terminal XCK and the second input signal terminal CK both provide a cutoff level signal VGH, and the third control line RST3 provides a cutoff level signal VGH.

[0063] according to Figure 3 and Figure 4The provided diagram shows that during the abnormal power-off period of the display panel, a conduction level signal VGL is provided through the second control line RST2 to control the internal conduction of the second control module 30. A cutoff level signal VGH is provided through both the first input signal terminal XCK and the second input signal terminal CK, and a cutoff level signal VGH is provided through the third control line RST3, cutting off the conduction state of the gating module 40, thereby disconnecting the first node from the third node. Simultaneously, the output control signal S1 is the signal from the first input signal terminal XCK, meaning the output control signal S1 is the cutoff level signal VGH. This controls the reset transistor M5 in the pixel circuit to disconnect, thus blocking the reset signal VREF from being written to the driving transistor, ensuring that all reset transistors M5 are turned off throughout the screen, and ensuring that all reset transistors M5 are in the off state when writing black. According to... Figure 4 As can be seen from the provided timing information, the timing of control signals S2 and S1 output by different shift registers is different.

[0064] In one possible example scenario, Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. Figure 6 This is a timing diagram of another pixel circuit provided in an embodiment of this application. According to... Figure 5 The provided illustration Figure 5 Is Figure 3 Based on this, for complex pixel circuits, the number of control signals is increased, thereby increasing the number of shift registers corresponding to each control signal. That is, control signal S1 is used as the reset control signal (i.e., Figure 3 In S1), the control signal S2 is used as the data control signal (i.e. Figure 3 The control signal S2 is used as the control signal for the output of the third shift register, and the control signal S3 is used as the control signal for the output of the third shift register. When S2 is enabled, the control transistor M8 is turned on, writing the DVH voltage to node N2 of the driving transistor M3, thus writing the driving transistor black; at the same time, when S2 is enabled, the control transistor M7 is turned on, and the reset signal VREF is used to reset node N4 corresponding to the positive input terminal of the light-emitting element OLED, thereby improving the characteristics of the driving transistor M3. According to Figure 6 The provided timing diagram is used for control. When the display panel experiences an abnormal power-down period, the signals from the first control line RST1, the second control line RST2, the third control line RST3, and multiple input signal terminals in the shift register cause the output signal of the shift register to control the transistor in the pixel circuit to conduct. This writes the black state voltage to the driving transistor, controls the driving transistor in the pixel circuit to turn off, and ensures that the driving transistor is blocked from generating driving current to light up the light-emitting element, thereby achieving the purpose of writing the entire screen to black and avoiding the screen flickering problem.

[0065] To further illustrate the differences in the output signals corresponding to shift registers Figure 7This is a timing diagram of a display panel provided in an embodiment of this application. According to... Figure 7 The provided diagram illustrates the control of the shift register by the first control line RST1, the second control line RST2, and the third control line RST3. When the display panel experiences abnormal power-down, screen flickering occurs. By changing the structure and timing of the shift register, other timing parameters of the display panel are also altered. Furthermore, different shift registers have different timing parameters. That is, the circuit structures of the control signals S2 and S1 output by different shift registers are the same, but their timing differs during abnormal power-down.

[0066] The timing sequence for abnormal power-down of the display panel includes:

[0067] 1. Timing of the output control signal S2: The first control line RST1 and the second control line RST2 are both on-level signals VGL, the first input signal terminal XCK and the second input signal terminal CK are both set to on-level signals VGL, and the third control line RST3 is set to off-level signal VGH, so that the output control signal S2 is the same as the signal of the first input signal terminal XCK, that is, the output control signal S2 is the on-level signal VGL, which in turn makes the gate control signal S2 of the transistor in the pixel circuit the on-level signal VGL.

[0068] 2. Timing of the output control signal S1: The second control line RST2 is set to the on level signal VGL, the first input signal terminal XCK and the second input signal terminal CK are simultaneously set to the off level signal VGH, and the third control line RST3 is set to the off level signal VGH. At this time, the control signal S1 output by the shift register is the same as the signal of the first input signal terminal XCK, that is, the output control signal S1 is the off level signal VGH, and thus the control signal S1 corresponding to the full-screen reset transistor in the pixel circuit is the invalid off level signal VGH.

[0069] The display panel provided in this application embodiment exhibits flickering when the display panel is abnormally powered off. By changing the structure and timing of the shift register, other timing parameters of the display panel are also altered, with different shift registers corresponding to different timing parameters. Specifically, the control signals S2 and S1 output by different shift registers have the same circuit structure, but their timing parameters differ during abnormal power-off. This causes the transistors inside the pixel circuit to conduct when receiving control signal S2, writing a write voltage to the driving transistor to deactivate it, and to turn off the reset transistor upon receiving control signal S1, blocking the transmission of the reset signal to the driving transistor, thus resolving the flickering problem.

[0070] against Figure 2 The structure of the shift registers provided in the document is explained in detail for each module. Figure 8This is a schematic diagram of the structure of a first control module provided in an embodiment of this application. Figure 8 Is Figure 2 This explanation is based on [the above]. Figure 8 The provided diagram shows that the structure of the first control module 20 specifically includes:

[0071] The first transistor is T10.

[0072] The gate of the first transistor T10 is electrically connected to the first control line RST1, the first terminal of the first transistor T10 is electrically connected to the cutoff level signal terminal, and the second terminal of the first transistor T10 is electrically connected to the second node N2.

[0073] according to Figure 8 The provided diagram shows that the first transistor T10 is controlled by the first control line RST1. During the normal display period of the display panel, the first control line RST1 outputs a cutoff level signal VGH to control the first transistor T10 to turn off, keeping the second node N2 at a low level. Then, the potential of the second node N2 controls the first output module 50 to output a conduction level. Under the combined action of the first output module 50 and the second output module 60, the conduction level signal VGL controls the transistors inside the pixel circuit to conduct, controlling the light-emitting element to light up normally. During the abnormal power-off period of the display panel, the first control line RST1 outputs a conduction level signal VGL, which turns on the first transistor T10, thereby raising the potential of the second node N2. When the second node N2 is at a high potential, the first output module 50 internally disconnects. The gating module 40 controls the potential of the third node N3, causing the second output module 60 to output a conduction level. When the signal output by the shift register is the cutoff level signal VGH, the compensation transistor in the pixel circuit is turned on, and the data signal with black state voltage is written to the driving transistor. The driving transistor is then turned off, thus solving the screen flickering problem.

[0074] By configuring the first transistor T10, it is not activated during normal display periods. During periods of abnormal power-down on the display panel, the first transistor T10 is turned on, increasing the potential of the second node N2 and thus affecting the output signal of the shift register. This makes the output signal a conduction level, controlling the compensation transistor in the pixel circuit to turn on, writing black to the driving transistor, thereby disconnecting the driving transistor and ensuring that the driving transistor is blocked from generating driving current to light up the light-emitting elements. This achieves the goal of writing black across the entire screen and improves the flickering problem.

[0075] Figure 9 This is a schematic diagram of the structure of a second control module provided in an embodiment of this application. Figure 9 Is Figure 2 This explanation is based on [the above]. Figure 9The provided diagram shows that the structure of the second control module 30 specifically includes:

[0076] The second transistor is T9.

[0077] The gate of the second transistor T9 is electrically connected to the second control line RST2, the first terminal of the second transistor T9 is electrically connected to the on-level signal terminal, and the second terminal of the second transistor T9 is electrically connected to the third node N3.

[0078] according to Figure 9 The provided diagram shows that the conduction state of the second transistor T9 is controlled by the second control line RST2. During the normal display period of the display panel, the cutoff level signal VGH is output through the second control line RST2 to control the second transistor T9 to turn off. At the same time, under the control of the selection module 40, the data write signal is transmitted from the first node N1 to the third node N3. The third node N3 is kept at a low level. The potential of the third node N3 controls the second output module 60 to output a conduction level signal VGL or a cutoff level signal VGH. The conduction level signal VGL controls the transistor inside the pixel circuit to conduct, thereby controlling the light-emitting element to light up normally. Alternatively, the cutoff level signal VGH controls the transistor inside the pixel circuit to turn off, thereby controlling the light-emitting element to turn off normally. During the abnormal power-down period of the display panel, the second control line RST2 outputs a conduction level signal VGL, which turns on the second transistor T9. This raises the potential of the third node N3 to the cutoff level signal VGH. When the third node N3 is at a high potential, the second output module 60 controls the internal disconnection of the second output module. At this time, the gating module 40 is disconnected, and the first output module outputs a conduction level signal VGL, making the output signal of the shift register a conduction level signal VGL. This controls the driving transistor in the pixel circuit to turn on, writing the black state voltage into the driving transistor. By dynamically adjusting the gate voltage, source voltage, and drain voltage of the driving transistor, the driving transistor is turned off, thereby blocking the driving transistor from generating driving current and lighting up the light-emitting element, thus solving the screen flickering problem.

[0079] By configuring the second transistor T9, it is not activated during normal display periods. During periods of abnormal power-down of the display panel, the second transistor T9 is turned on. Under the combined action of the first output module 50 and the second output module 60, the potential of the third node N3 is increased, thereby changing the output signal of the shift register. This makes the output signal a conduction level signal VGL, controlling the transistors in the pixel circuit to conduct, writing black to the driving transistor, ensuring that the driving transistor is blocked from generating driving current to light up the light-emitting element, thus achieving the purpose of writing black across the entire screen and improving the flickering problem.

[0080] Figure 10 This is a schematic diagram of the structure of a gating module provided in an embodiment of this application. Figure 10 Is Figure 2 This explanation is based on [the above]. Figure 10 The provided diagram shows that the structure of the gating module 40 specifically includes:

[0081] The third transistor is M66.

[0082] The gate of the third transistor M66 is electrically connected to the third control line RST3, the first terminal of the third transistor M66 is electrically connected to the first node N1, and the second terminal of the third transistor M66 is electrically connected to the third node N3.

[0083] The switching state of the third transistor M66 is controlled by the third control line RST3. During normal display of the display panel, the input module 10 outputs a data write signal to the first output module 50 and the gating module 40. The third transistor M66 in the gating module 40 is turned on, connecting the first node N1 and the third node N3. The data write signal is then output to the second output module 60. The first output module 50 and the second output module 60 periodically and alternately output a turn-on level signal VGL and a cut-off level signal VGH. The turn-on level signal VGL controls the transistors in the pixel circuit to turn on, ensuring normal display of the light-emitting element. The cut-off level signal VGH controls the transistors in the pixel circuit to turn off, ensuring normal shutdown of the light-emitting element. During the abnormal power-down process of the display panel, the input module 10 inputs a data write signal to the first output module 50 and the third transistor M66. The third transistor M66 is turned off, blocking the data write signal output to the second output module 60. Then, under the control of the first output module 50 and the second output module 60, a conduction level signal VGL is output. The conduction level signal VGL controls the driving transistor in the pixel circuit to conduct. Then, the black state voltage is used to write black to the driving transistor to ensure that the driving transistor is turned off, avoiding the screen flickering problem caused by residual current.

[0084] Figure 11 This is a schematic diagram of the structure of an input module provided in an embodiment of this application. Figure 11 Is Figure 2 This explanation is based on [the above]. Figure 11 The provided diagram shows that the structure of the input module 10 specifically includes:

[0085] The fourth transistor is M11, the fifth transistor is M22, the sixth transistor is M33, the seventh transistor is M44, the eighth transistor is M55, and the ninth transistor is T11. The seventh transistor, M44, is a dual-gate transistor.

[0086] The gate of the fourth transistor M11 is electrically connected to the first input signal terminal XCK, the first terminal of the fourth transistor M11 is electrically connected to the second terminal of the sixth transistor M33, and the second terminal of the fourth transistor M1 is electrically connected to the gate of the fifth transistor M22, the first terminal of the seventh transistor M44, and the first node N1.

[0087] The first terminal of the fifth transistor M22 is electrically connected to the first terminal of the eighth transistor M55 and the second terminal of the ninth transistor T11. The second terminal of the fifth transistor M22 is electrically connected to the first and second gates of the seventh transistor M44, the first terminal of the eighth transistor M55, and the second input signal terminal CK.

[0088] The gate of the sixth transistor M33 is electrically connected to the second node and the first terminal of the ninth transistor T11, and the first terminal of the sixth transistor M33 is electrically connected to the cutoff level signal terminal.

[0089] The second terminal of the seventh transistor M44 is electrically connected to the third input signal terminal.

[0090] The second terminal of the eighth transistor M55 is electrically connected to the on-level signal terminal.

[0091] The gate of the ninth transistor T11 is electrically connected to the third control line RST3.

[0092] The signals output from the first and second input signal terminals are clock signals. The IN signal output from the third input signal terminal is the data write signal.

[0093] During normal display periods on the display panel, the first input signal terminal XCK controls the switching state of the fourth transistor M11, the second input signal terminal CK controls the switching states of the fifth transistor M22, the seventh transistor M44, and the eighth transistor M55, and the third input signal terminal IN outputs a data write signal to the fifth transistor M22 when the seventh transistor M44 is on, controlling the switching state of the fifth transistor M22. Simultaneously, the seventh transistor M44 transmits the data write signal to the first node N1. The third control line RST3 provides a conduction level signal VGL, causing the ninth transistor T11 to turn on and output the conduction level signal VGL through the eighth transistor M55 to the sixth transistor M33, thus enabling the second node N2 to provide a conduction level signal VGL. The first output module 50 outputs the conduction level VGL according to the potential of the second node N2.

[0094] When the display panel experiences an abnormal power failure, the third control line RST3 outputs a cutoff level signal VGH, controlling the ninth transistor T11 to disconnect, thereby raising the potential of the second node N2. Simultaneously, the gating module 40 internally disconnects, blocking the data write signal from being input to the third node N3, thus stopping the data write operation.

[0095] By setting up an input module, during normal display panel operation, the write data signal is output to the first output module 50 and the second output module 60 under the control of the clock signal and the data write signal, thereby driving the light-emitting elements. In the event of an abnormal power failure of the display panel, the input module is shut off, blocking the data write signal from being supplied to the third node N3. Then, the signal output from the shift register controls the transistors in the pixel circuit to conduct, writing the black state voltage to the driving transistors, thus writing the driving transistors across the entire screen black and resolving the screen flickering problem.

[0096] Figure 12 This is a schematic diagram of the structure of a first output module provided in an embodiment of this application. Figure 12 yes Figure 2 This explanation is based on [the above]. Figure 12 The provided diagram shows that the structure of the first output module 50 specifically includes:

[0097] The tenth transistor M77 and the first capacitor C1.

[0098] The gate of the tenth transistor M77 is electrically connected to the second node N2 and one end of the first capacitor C1. The first terminal of the tenth transistor M77 is electrically connected to the cutoff level signal terminal and the other end of the first capacitor C1. The second terminal of the tenth transistor M77 serves as the output terminal of the gate drive circuit.

[0099] The first capacitor here is the filter capacitor.

[0100] according to Figure 12 The provided diagram shows that during normal display on the display panel, a low-level signal is input to the second node through the input module 10. Under the action of the low-level signal, the tenth transistor M77 uses the cutoff level signal VGH as the output terminal of the gate drive circuit. At this time, the input module 10 inputs the data write signal to the gating module 40. When the gating module 40 is turned on, the data write signal is input to the third node N3, controlling the second output module 60 to turn off, thereby obtaining the cutoff level signal output by the shift register. During the abnormal power-down phase of the display panel, the first control module 20 and the second control module 30 are turned on through the first control line RST1 and the second control line RST2, thereby setting the potential of the second node N2 to the cutoff level signal VGH, controlling the internal disconnection of the first output module 50. At the same time, the potential of the third node N3 is set to the on level signal. Under the action of the on level signal of the third node N3, the second output module 60 makes the gate drive circuit output signal OUT a on level signal, thereby controlling the transistor in the pixel circuit to turn on, writing the black state voltage into the drive transistor, and controlling the drive transistor to turn off, thereby blocking the drive transistor from generating drive current to light up the light-emitting element, thus achieving the purpose of writing black to the whole screen and solving the screen flickering problem.

[0101] Figure 13 This is a schematic diagram of the structure of a second output module provided in an embodiment of this application. Figure 13 Is Figure 2 This explanation is based on [the above]. Figure 13 The provided diagram shows that the structure of the second output module specifically includes:

[0102] The eleventh transistor M88 and the second capacitor C2.

[0103] The gate of the eleventh transistor M88 is electrically connected to the third node N3 and one end of the second capacitor C2. The first terminal of the eleventh transistor M88 serves as the output terminal OUT of the gate drive circuit, and the second terminal of the eleventh transistor M88 is electrically connected to multiple input signal terminals.

[0104] The second capacitor here is a voltage regulator and filter capacitor.

[0105] according to Figure 13 The provided diagram illustrates that during normal display on the display panel, a low-level signal is input to the second node N2 via input module 10. This signal is then output as a cutoff level signal VGH via the first output module. Simultaneously, the first node N1 and the third node N3 are connected via the gating module 40, controlling the third node N3 to be a high-level signal. The eleventh transistor M88 is deactivated under the control of the high-level signal, thus using the cutoff level output by the first output module as the output signal. Alternatively, the eleventh transistor M88 can be turned on when the third node is a low-level signal, using the first input signal XCK as the output signal of the shift register; this controls the transistors in the pixel circuit to conduct, thereby controlling the display of the light-emitting elements. During the abnormal power-down phase of the display panel, the first control module 20 and the second control module 30 are turned on through the first control line RST1 and the second control line RST2. This sets the potential of the third node N3 to the voltage of the conduction level signal VGL, controls the eleventh transistor M88 to turn on and outputs the conduction level signal. The conduction level signal is used to control the conduction of the transistors in the pixel circuit, writes the black state voltage to the driving transistor, controls the transistor to turn off, blocks the driving transistor from generating driving current and lighting up the light-emitting element, thereby achieving the purpose of writing black to the whole screen and reducing screen flicker.

[0106] By selectively outputting a conduction level through the tenth transistor M77 and the eleventh transistor M88 during normal operation of the display panel, the output terminal OUT of the gate drive circuit outputs a conduction level signal, which in turn provides a conduction level to the pixel circuit, causing the transistors in the pixel circuit to conduct. The data signal with black state voltage is then written into the drive transistor, controlling the drive transistor to turn off and blocking the drive transistor from generating drive current to light up the light-emitting element, thereby achieving the purpose of writing black to the whole screen and solving the screen flickering problem.

[0107] In one possible example scenario, Figure 14This is a schematic diagram of another shift register structure in a display panel provided in an embodiment of this application. According to... Figure 14 The provided diagram shows that during the normal display period of the display panel, under the control of the XCK signal, CK signal, IN signal and RST3, the potential of node N2 is low and the third node N3 is high. Under the control of the low potential, M7 outputs a cutoff level signal to the output terminal OUT of the gate drive circuit. At the same time, M88 is disconnected under the potential of node N3, which makes the output terminal of the gate drive circuit high. When the third node is low, M88 is turned on and provides a low level signal to the output terminal OUT of the gate drive circuit. The control signal of the pixel circuit is a low level signal, which makes the transistor turn on and the light-emitting element emits light normally. When the display panel is abnormally powered down, RST1 and RST2 provide low-level signals to control the first transistor T10 and the ninth transistor T11 to conduct, thereby controlling node N2 to be at the cutoff level signal VGH and node N3 to be at the conduction level signal. M77 is internally disconnected when node N2 is at the high level, and M8 is turned on when node N3 is at the low level. Then, the XCK signal is used as the OUT signal of the gate drive circuit to be input to the pixel circuit, so that the transistors in the pixel circuit are turned on, writing the black state voltage to the drive transistor, controlling the drive transistor to turn off, realizing full-screen black writing and solving the screen flickering problem.

[0108] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. An embodiment of this application also provides a display device 1000; please refer to [link / reference]. Figure 15 The display device 1000 can be a PC, television, monitor, mobile terminal, tablet computer, and wearable device, etc. The display device 1000 may include the display panel 200 provided in the embodiments of this application.

[0109] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0110] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0111] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A display panel, characterized by, The gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises an input module, a first control module, a second control module, a gating module, a first output module and a second output module. The input module is electrically connected with a plurality of input signal terminals, a first node and a second node, and adjusts the potentials of the first node and the second node based on signals of the plurality of input signal terminals. The first control module is electrically connected with an off-level signal terminal, a first control line and the second node, and adjusts the potential of the second node based on signals of the off-level signal terminal and the first control line. The second control module is electrically connected with an on-level signal terminal, a second control line and a third node, and adjusts the potential of the third node based on signals of the on-level signal terminal and the second control line. The gating module is electrically connected with the first node, the third node and a third control line, and controls the communication state between the first node and the third node based on a signal of the third control line. The first output module is electrically connected with the off-level signal terminal, the second node and a gate drive circuit output terminal, and controls the communication state between the off-level signal terminal and the gate drive circuit output terminal based on the potential of the second node. The second output module is electrically connected with the input signal terminals, the third node and the gate drive circuit output terminal, and controls the communication state between the input signal terminals and the gate drive circuit output terminal based on the potential of the third node.

2. The display panel of claim 1, wherein, The plurality of input signal terminals comprise a first input signal terminal, a second input signal terminal and a third input signal terminal. A first input end of the input module is electrically connected with the first input signal terminal, a second input end of the input module is electrically connected with the second input signal terminal, a third input end of the input module is electrically connected with the third input signal terminal, a fourth input end of the input module is electrically connected with the off-level signal terminal, a fifth input end of the input module is electrically connected with the on-level signal terminal, a first output end of the input module is electrically connected with the second node, and a second output end of the input module is electrically connected with the first node.

3. The display panel of claim 1 or 2, wherein, In a first working condition, the first control line and the second control line provide an off level, and the third control line provides an on level. In a second working condition, at least the second control line provides the on level.

4. The display panel of claim 2, wherein, The gate drive circuit comprises a first gate drive circuit, and a signal output by an output end of the first gate drive circuit is used to control whether a data signal is written into a pixel circuit. In the second working condition, the first control line and the second control line both provide the on level, the first input signal terminal and the second input signal terminal both provide the on level, the third control line provides the off level, and the data signal is a black state voltage.

5. The display panel of claim 2, wherein, The gate drive circuit comprises a second gate drive circuit, and a signal output by an output end of the second gate drive circuit is used to control whether a reset signal is written into the pixel circuit. In the second working condition, the second control line provides a turn-on level, the first input signal terminal and the second input signal terminal both provide a turn-off level, and the third control line provides the turn-off level.

6. The display panel of claim 1, wherein, The first control module comprises a first transistor; a gate of the first transistor is electrically connected with the first control line, a first pole of the first transistor is electrically connected with the turn-off level signal terminal, and a second pole of the first transistor is electrically connected with the second node.

7. The display panel of claim 1, wherein, The second control module comprises a second transistor; a gate of the second transistor is electrically connected with the second control line, a first pole of the second transistor is electrically connected with the turn-on level signal terminal, and a second pole of the second transistor is electrically connected with the third node.

8. The display panel of claim 1, wherein, The gating module comprises a third transistor; a gate of the third transistor is electrically connected with the third control line, a first pole of the third transistor is electrically connected with the first node, and a second pole of the third transistor is electrically connected with the third node.

9. The display panel of claim 2, wherein, The input module comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and the seventh transistor is a double-gate transistor; a gate of the fourth transistor is electrically connected with the first input signal terminal, a first pole of the fourth transistor is electrically connected with a second pole of the sixth transistor, and a second pole of the fourth transistor is electrically connected with a gate of the fifth transistor, a first pole of the seventh transistor, and the first node; a first pole of the fifth transistor is electrically connected with a first pole of the eighth transistor and a second pole of the ninth transistor, and a second pole of the fifth transistor is electrically connected with a first gate and a second gate of the seventh transistor, a first pole of the eighth transistor, and the second input signal terminal; a gate of the sixth transistor is electrically connected with the second node and a first pole of the ninth transistor, and a first pole of the sixth transistor is electrically connected with the turn-off level signal terminal; a second pole of the seventh transistor is electrically connected with the third input signal terminal; a second pole of the eighth transistor is electrically connected with the turn-on level signal terminal; a gate of the ninth transistor is electrically connected with the third control line.

10. The display panel of claim 1, wherein, The first output module comprises a tenth transistor and a first capacitor; a gate of the tenth transistor is electrically connected with the second node and one end of the first capacitor, a first pole of the tenth transistor is electrically connected with the turn-off level signal terminal and the other end of the first capacitor, and a second pole of the tenth transistor serves as an output terminal of the gate drive circuit.

11. The display panel of claim 1, wherein, The second output module comprises an eleventh transistor and a second capacitor; a gate of the eleventh transistor is electrically connected with the third node and one end of the second capacitor, a first pole of the eleventh transistor serves as an output terminal of the gate drive circuit, and a second pole of the eleventh transistor is electrically connected with the plurality of input signal terminals.

12. A display device comprising: The display panel comprises any one of the display panels in claims 1-11.

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