Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a gate drive circuit, the gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises a node control module, a first output module and a second output module; the node control module is used for adjusting potentials of the first node and the second node; the first output module is used for outputting a first gate driving signal under the control of the potentials of the first node and the second node; the second output module is used for outputting a second gate driving signal under the control of the potentials of the first node and the second node; the effective level of the first gate drive signal and the effective level of the second gate drive signal are opposite in polarity. The frame of the display panel can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Compared to display panels with conventional bezel technology, narrow bezel display panels can achieve a higher screen-to-body ratio, allowing the display panel to incorporate a larger display area within a smaller body size, thus bringing a more perfect visual experience.

[0003] Therefore, how to reduce the bezel of the display panel is a technical problem that those skilled in the art are dedicated to solving. Summary of the Invention

[0004] This application provides a display panel and display device that can reduce the bezel of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift registers, each shift register including a node control module, a first output module, and a second output module. The node control module is used to adjust the potentials of the first node and the second node. The first output module is used to output a first gate driving signal under the control of the potentials of the first node and the second node. The second output module is used to output a second gate driving signal under the control of the potentials of the first node and the second node. The effective level of the first gate driving signal and the effective level of the second gate driving signal have opposite polarities.

[0006] Secondly, embodiments of this application provide a display device, including a display panel as described in the first aspect embodiment.

[0007] According to the display panel provided in the embodiments of this application, the gate driving circuit includes multiple cascaded shift registers (VSRs). The shift registers (VSRs) include a first output module and a second output module. Different gate driving signals output by the first output module and the second output module can be used to control different switching transistors in the pixel circuit. Compared with the requirement to set different gate driving circuits for different switching transistors in the pixel circuit, the gate driving circuit in this embodiment supports the simultaneous output of two types of gate driving signals, which can reduce the number of gate driving circuits required and achieve the purpose of saving bezels. In addition, the effective level of the first gate driving signal output by the gate driving circuit has opposite polarities to the effective level of the second gate driving signal, which can support multiple switching transistors in the pixel circuit, including N-type transistors and P-type transistors. This can combine the advantages of N-type transistors and P-type transistors respectively, so that the pixel circuit has more optimized performance. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application; Figure 2 This illustration shows a schematic diagram of a shift register in a display panel provided in an embodiment of this application; Figure 3 This illustration shows another structural diagram of the shift register in the display panel provided in an embodiment of this application; Figure 4 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application; Figure 5 This illustration shows a schematic diagram of a gate driving circuit in a display panel provided in an embodiment of this application; Figure 6 This illustration shows another structural schematic diagram of the gate driving circuit in the display panel provided in an embodiment of this application; Figure 7 This diagram illustrates the timing of an output signal of a shift register in a display panel according to an embodiment of this application. Figure 8 This illustration shows another structural diagram of the shift register in the display panel provided in an embodiment of this application; Figure 9 Show Figure 8 A timing diagram; Figure 10 Show Figure 8 A corresponding diagram illustrating a continuous relationship; Figure 11 Show Figure 10 A timing diagram; Figure 12 This illustration shows another structural diagram of the shift register in the display panel provided in an embodiment of this application; Figure 13 This illustration shows another structural diagram of the shift register in the display panel provided in an embodiment of this application; Figure 14 Show Figure 12 A timing diagram; Figure 15 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 16 Show Figure 12 A corresponding connection diagram; Figure 17 Show Figure 13 A timing diagram; Figure 18 Show Figure 13 A corresponding connection diagram; Figure 19 Show Figure 4 A corresponding timing diagram; Figure 20 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0010] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0011] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0012] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0013] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0014] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components. The display panel can be a display device or a module / part of a display device.

[0015] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0016] Display panels typically include pixel circuitry, which includes driving transistors and switching transistors. The switching transistors are used to write signals to the driving transistors, and the driving transistors are used to generate driving current to drive the light-emitting elements to emit light.

[0017] With the development of driving technology, pixel circuits can include multiple switching transistors, and multiple switching transistors require multiple different gate drive signals to drive them.

[0018] In related technologies, different gate drive circuits are typically placed in the non-display area of ​​the display panel to generate different gate drive signals, thereby driving multiple switching transistors in the pixel circuit. However, the more gate drive circuits there are, the larger the area of ​​the display panel's bezel (non-display area) required, making it impossible to achieve a narrow bezel design.

[0019] To address the aforementioned technical problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0020] Please refer to the reference. Figures 1 to 2 The display panel 100 provided in this application embodiment includes a gate driving circuit 10, which includes a plurality of cascaded shift registers (VSRs). The shift registers (VSRs) include a node control module 11, a first output module 12, and a second output module 13.

[0021] Node control module 11 is electrically connected to the first node N1 and the second node N2. First output module 12 is electrically connected to the first node N1 and the second node N2. Second output module 13 is electrically connected to the first node N1 and the second node N2.

[0022] Node control module 11 is used to adjust the potentials of the first node N1 and the second node N2. First output module 12 is used to output a first gate drive signal under the control of the potentials of the first node N1 and the second node N2. Second output module 13 is used to output a second gate drive signal under the control of the potentials of the first node N1 and the second node N2. The effective level of the first gate drive signal and the effective level of the second gate drive signal have opposite polarities.

[0023] For example, the output terminal of the first output module 12 is labeled as the first output terminal out1, and the output terminal of the second output module 13 is labeled as the second output terminal out2. The first output terminal out1 outputs the first gate drive signal, and the second output terminal out2 outputs the second gate drive signal.

[0024] The display panel also includes a pixel circuit 20, which includes a driving transistor and a plurality of switching transistors. A first gate driving signal and a second gate driving signal are used to drive different switching transistors in the pixel circuit. In other words, the first output terminal out1 and the second output terminal out are electrically connected to the gates of different switching transistors in the pixel circuit 20.

[0025] The effective levels of the first gate drive signal and the second gate drive signal are the levels at which the corresponding switching transistors in the pixel circuit are turned on. The effective levels of the first and second gate drive signals have opposite polarities, meaning one of them is high and the other is low.

[0026] Understandably, one of the switching transistors controlled by the first gate drive signal and the second gate drive signal is an N-type transistor, and the other is a P-type transistor. For an N-type transistor, the effective gate access level is high; for a P-type transistor, the effective gate access level is low. In this embodiment, the multiple switching transistors in the pixel circuit include both N-type and P-type transistors. N-type transistors have lower leakage current, while P-type transistors have higher mobility. This combines the advantages of both N-type and P-type transistors, resulting in optimized performance for the pixel circuit.

[0027] The display panel 100 includes a display area AA and a non-display area NA, where the non-display area NA can be understood as the border of the display panel. The display area AA includes a plurality of pixel circuits 20 arranged in a first direction X and a second direction Y, where the first direction X and the second direction Y intersect. The non-display area NA includes a gate driving circuit 10, in which a plurality of shift registers VSRs are arranged in the second direction Y.

[0028] For example, in the first direction X, gate driving circuits 20 can be provided on both sides of the display area AA, so as to realize bilateral driving of the pixel circuit 20 and improve the display unevenness caused by signal delay.

[0029] According to the display panel provided in the embodiments of this application, the gate driving circuit 10 includes multiple cascaded shift registers (VSRs). The shift registers (VSRs) include a first output module 12 and a second output module 13. Different gate driving signals output by the first output module 12 and the second output module 13 can be used to control different switching transistors in the pixel circuit 20. Compared with the requirement to set different gate driving circuits for different switching transistors in the pixel circuit, the gate driving circuit 10 in this embodiment supports the simultaneous output of two types of gate driving signals, which can reduce the number of gate driving circuits required and achieve the purpose of saving bezels. In addition, the effective level of the first gate driving signal output by the gate driving circuit 10 has opposite polarities to the effective level of the second gate driving signal, which can support multiple switching transistors in the pixel circuit, including N-type transistors and P-type transistors. This can combine the advantages of N-type transistors and P-type transistors respectively, so that the pixel circuit has more optimized performance.

[0030] In some embodiments, such as Figure 3 As shown, the shift register VSR also includes a gating module 14, which is electrically connected to the first node N1 and the second node N2. The gating module 14 is used to output a fourth gate drive signal under the control of the potentials of the first node N1 and the second node N2, and the gating signal terminal CTRL. The gating signal terminal CTRL is used to control whether the fourth gate drive signal includes a valid level. For example, the output terminal of the gating module 14 is labeled as the fourth output terminal out4, and the fourth output terminal out4 outputs the fourth gate drive signal.

[0031] The first output terminal ou1 of the first output module 12 in the m-th shift register VSR(m) is electrically connected to the input signal terminal IN of the node control module 11 in the (m+1)-th shift register VSR(m+1), where m is an integer greater than or equal to 1.

[0032] For the same shift register, the second output terminal out2 of the second output module 13 and the fourth output terminal out4 of the gating module 14 in the shift register are electrically connected to the gates of different switching transistors in the same pixel circuit.

[0033] When the shift register includes the gating module 14, the first gate drive signal output by the first output terminal ou1 of the first output module 12 in the previous stage shift register is used as the next signal. The first gate drive signal output by the first output terminal ou1 of the first output module 12 in the previous stage shift register is used to drive the operation of the next stage shift register.

[0034] The two types of gate drive signals output by the second output module 13 and the gating module 14 in the shift register are used to drive different switching transistors in the pixel circuit.

[0035] The effective level of the fourth gate drive signal output by the gating module 14 has the same polarity as the effective level of the first gate drive signal output by the first output module 12. The effective level of the fourth gate drive signal output by the gating module 14 has the opposite polarity to the effective level of the second gate drive signal output by the second output module 13.

[0036] For example, when the strobe signal terminal CTRL is low, the fourth gate drive signal output by the strobe module 14 does not include a valid level; when the strobe signal terminal CTRL is high, the fourth gate drive signal output by the strobe module 14 includes a valid level. Alternatively, when the strobe signal terminal CTRL is low, the fourth gate drive signal output by the strobe module 14 includes a valid level; when the strobe signal terminal CTRL is high, the fourth gate drive signal output by the strobe module 14 does not include a valid level.

[0037] In this embodiment, the signal output by the gating module 14 is used to drive the transistors in the pixel circuit. The gating signal terminal CTRL can control the refresh frequency of the fourth gate drive signal output by the gating module 14, and can support the refresh function of the display panel divided into zones and frequencies.

[0038] As an example, such as Figure 4 As shown, the pixel circuit 20 is electrically connected to the light-emitting element 30. The pixel circuit 20 includes a driving transistor T3 and multiple switching transistors. The multiple switching transistors include a data writing transistor T2, a threshold compensation transistor T4, a gate reset transistor T5, an anode reset transistor T7, a first light-emitting control transistor T1, a second light-emitting control transistor T6, and a bias adjustment transistor T8. SP, SPX, S1N, S2N, and EM represent the gate drive signals connected to the gates of each switching transistor.

[0039] For example, please refer to the reference. Figure 3 and Figure 4 When the shift register includes the gating module 14, the second output terminal out2 of the second output module 13 is electrically connected to the gate of the data write transistor T2, and the fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the threshold compensation transistor T4; alternatively, the fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the gate reset transistor T5. In other words, the second output terminal out2 of the second output module 13 outputs the gate drive signal SP, and the fourth output terminal out4 of the gating module 14 outputs the gate drive signal S1N or S2N.

[0040] In some embodiments, such as Figure 5 or Figure 6 As shown, the shift register also includes a third output module 15, which is electrically connected to the first node N1 and the second node N2.

[0041] The third output module 15 is used to output a third gate drive signal under the control of the potentials of the first node N1 and the second node N2. For example, the output terminal of the third output module 15 is marked as the third output terminal out3, and the third output terminal out3 outputs the third gate drive signal.

[0042] like Figure 7 As shown, taking the effective level of the first gate drive signal output by the first output terminal out1 as high, the effective level of the second gate drive signal output by the second output terminal out2 as low, and the effective level of the third gate drive signal output by the third output terminal out3 as low as an example, the effective level of the third gate drive signal output by the third output terminal out3 has the same polarity as the effective level of the second gate drive signal output by the second output terminal out2, and the effective levels of the third gate drive signal are misaligned with the effective levels of the second gate drive signal. The effective levels of the first gate drive signal output by the first output terminal out1, the second gate drive signal output by the second output terminal out2, and the third gate drive signal output by the third output terminal out3 all overlap in time.

[0043] For example, the transistor in the pixel circuit connected to the first output terminal out1 can be an N-type transistor, while the transistors in the pixel circuits connected to the second output terminal out2 and the third output terminal out3 can be P-type transistors. Because the effective levels of the signals output from the second output terminal out2 and the third output terminal out3 are misaligned, and the effective levels of the signals output from the first output terminal out1 overlap with the effective levels of the signals output from the second output terminal out2 and the third output terminal out3 in time, this allows for driving two rows of pixel circuits with a single shift register, saving the number of shift registers and further reducing the border area occupied by the gate drive circuit.

[0044] In some embodiments, please refer to the reference Figure 1 , Figure 4 and Figure 5 or Figure 6 The display panel includes a pixel circuit 20 and a light-emitting element 30. The pixel circuit 20 is electrically connected to the light-emitting element 30. For the same shift register, the second output terminal out2 of the second output module 13 and the third output terminal out3 of the third output module 15 in the same shift register are electrically connected to the pixel circuits in different rows. The second gate drive signal output by the second output terminal out2 and the third gate drive signal output by the second output terminal out2 are used to control the writing of data signals.

[0045] For example, the second output terminal out2 of the second output module 13 and the third output terminal out3 of the third output module 15 in the same level shift register are electrically connected to the pixel circuit of the adjacent row.

[0046] The data writing transistor T2 is used to write the data signal data, and the gate of the data writing transistor T2 is connected to the gate drive signal SP. The second output terminal out2 of the second output module 13 and the third output terminal out3 of the third output module 15 in the same stage shift register are electrically connected to the gate of the data writing transistor T2 in the adjacent row pixel circuit.

[0047] For example, the second output terminal out2 of the second output module 13 in the nth-level shift register is electrically connected to the gate of the data writing transistor T2 in the i-th row pixel circuit, and the third output terminal out3 of the third output module 15 in the nth-level shift register is electrically connected to the gate of the data writing transistor T2 in the (i+1)-th row pixel circuit; the second output terminal out2 of the second output module 13 in the (n+1)-th level shift register is electrically connected to the gate of the data writing transistor T2 in the (i+2)-th row pixel circuit, and the third output terminal out3 of the third output module 15 in the (n+1)-th level shift register is electrically connected to the gate of the data writing transistor T2 in the (i+3)-th row pixel circuit; and so on. Here, n and i are integers greater than or equal to 1.

[0048] In this embodiment, the first-level shift register can control the writing of data signals of the two rows of pixel circuits, which can reduce the number of shift registers and achieve a narrow bezel design.

[0049] In some embodiments, such as Figure 5 or Figure 6As shown, regardless of whether the shift register in the gate drive circuit includes a gating module, the cascading method of multiple shift registers can be: the first output terminal ou1 of the first output module 12 in the m-th shift register VSR(m) is electrically connected to the input signal terminal IN of the node control module 11 in the (m+1)-th shift register VSR(m+1), where m is an integer greater than or equal to 1.

[0050] As an example, such as Figure 5 As shown, the shift register does not include a gating module. The connection between the shift register and the pixel circuit can be as follows: the first output terminal out1 of the first output module 12 and the second output terminal out2 of the second output module 13 in the shift register are electrically connected to the gates of different transistors in the same pixel circuit.

[0051] For example, the first output terminal out1 of the first output module 12 is electrically connected to the gate of the threshold compensation transistor T4 in the pixel circuit, and the second output terminal out2 of the second output module 13 is electrically connected to the gate of the data writing transistor T2 in the pixel circuit.

[0052] In this embodiment, the first output terminal out1 of the first output module 12 serves as both a transmission signal terminal and a signal terminal that provides gate drive signals to the pixel circuit, thereby realizing the transmission of signals and the driving of the pixel circuit.

[0053] As another example, such as Figure 6 As shown, the shift register also includes a gating module 14, which is electrically connected to the first node N1 and the second node N2. The gating module 14 is used to output a fourth gate drive signal under the control of the potentials of the first node N1 and the second node N2 and the gating signal terminal CTRL. The gating signal terminal CTRL is used to control whether the fourth gate drive signal includes an active level.

[0054] When the shift register also includes a gating module 14, the connection between the shift register and the pixel circuit can be as follows: the second output terminal out2 of the second output module 13 in the shift register and the fourth output terminal out4 of the gating module 14 are electrically connected to the gates of different transistors in the same pixel circuit.

[0055] For example, the fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the threshold compensation transistor T4 in the pixel circuit, and the second output terminal out2 of the second output module 13 is electrically connected to the gate of the data writing transistor T2 in the pixel circuit.

[0056] In this embodiment, the first output terminal out1 of the first output module 12 serves as the stage transmission signal terminal, and the fourth output terminal out4 of the gating module 14 serves as the signal terminal that provides gate driving signals to the pixel circuit, thereby realizing the segmented frequency driving of the display panel.

[0057] In some embodiments, please refer to the reference Figure 5 and Figure 4 The shift register does not include the gating module. The connection between the shift register and the pixel circuit can be as follows: the first output terminal out1 of the first output module 12 is electrically connected to the gate of the transistor with the same function in the two rows of pixel circuits.

[0058] For example, the first output terminal out1 of the first output module 12 is electrically connected to the gate of the transistor with the same function in the two adjacent rows of pixel circuits.

[0059] For example, the first output terminal out1 of the first output module 12 in the nth-level shift register is electrically connected to the gate of the threshold compensation transistor T4 in the pixel circuit of the i-th row and the (i+1)-th row; the first output terminal out1 of the first output module 12 in the (n+1)-th level shift register is electrically connected to the gate of the threshold compensation transistor T4 in the pixel circuit of the (i+2)-th row and the (i+3)-th row; and so on. Here, n and i are integers greater than or equal to 1.

[0060] In this embodiment, the first output module of the first-level shift register can drive two rows of pixel circuits, which can reduce the number of shift registers to achieve a narrow bezel.

[0061] Alternatively, please refer to the following: Figure 6 and Figure 4 The shift register does not include the gating module 14. The connection between the shift register and the pixel circuit can be: the fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the transistor with the same function in the two rows of pixel circuits.

[0062] For example, the fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the transistor with the same function in the two adjacent rows of pixel circuits.

[0063] For example, the fourth output terminal out4 of the gating module 14 in the nth-level shift register is electrically connected to the gate of the threshold compensation transistor T4 in the pixel circuit of the i-th and i+1-th rows; the fourth output terminal out4 of the gating module 14 in the n+1-th-level shift register is electrically connected to the gate of the threshold compensation transistor T4 in the pixel circuit of the i+2-th and i+3-th rows; and so on. Here, n and i are integers greater than or equal to 1.

[0064] In this embodiment, the gating module of the first-level shift register can drive two rows of pixel circuits, which can reduce the number of shift registers to achieve a narrow bezel.

[0065] As an example, please refer to the reference. Figure 4 and Figure 5 The first output terminal out1 of the first output module 12 is electrically connected to the gate of the transistor with the same function in the two adjacent rows of pixel circuits, and the second output terminal out2 of the second output module 13 and the third output terminal out3 of the third output module 15 in the same level shift register are electrically connected to the pixel circuits in the adjacent rows.

[0066] For example, the second output terminal out2 of the second output module 13 in the nth-level shift register is electrically connected to the gate of the data writing transistor T2 in the i-th row pixel circuit, and the third output terminal out3 of the third output module 15 in the nth-level shift register is electrically connected to the gate of the data writing transistor T2 in the (i+1)-th row pixel circuit; the first output terminal out1 of the first output module 12 in the nth-level shift register is electrically connected to the gate of the threshold compensation transistor T4 in the i-th and (i+1)-th row pixel circuits.

[0067] The second output terminal out2 of the second output module 13 in the (n+1)th stage shift register is electrically connected to the gate of the data writing transistor T2 in the (i+2)th row pixel circuit, and the third output terminal out3 of the third output module 15 in the (n+1)th stage shift register is electrically connected to the gate of the data writing transistor T2 in the (i+3)th row pixel circuit; the first output terminal out1 of the first output module 12 in the (n+1)th stage shift register is electrically connected to the gate of the threshold compensation transistor T4 in the (i+2)th and (i+3)th row pixel circuits.

[0068] And so on. Here, n and i are integers greater than or equal to 1.

[0069] As another example, please refer to the reference. Figure 4 and Figure 6 The shift register also includes a gating module 14. The fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the transistor with the same function in the two adjacent rows of pixel circuits. Furthermore, the second output terminal out2 of the second output module 13 and the third output terminal out3 of the third output module 15 in the same level shift register are electrically connected to the pixel circuits in the adjacent rows.

[0070] For example, the second output terminal out2 of the second output module 13 in the nth-level shift register is electrically connected to the gate of the data writing transistor T2 in the i-th row pixel circuit, and the third output terminal out3 of the third output module 15 in the nth-level shift register is electrically connected to the gate of the data writing transistor T2 in the (i+1)-th row pixel circuit; the fourth output terminal out4 of the gating module 14 is electrically connected to the gate of the threshold compensation transistor T4 in the i-th and (i+1)-th row pixel circuits.

[0071] The second output terminal out2 of the second output module 13 in the (n+1)th stage shift register is electrically connected to the gate of the data writing transistor T2 in the (i+2)th row pixel circuit, and the third output terminal out3 of the third output module 15 in the (n+1)th stage shift register is electrically connected to the gate of the data writing transistor T2 in the (i+3)th row pixel circuit; the fourth output terminal out4 of the gating module 14 in the (n+1)th stage shift register is electrically connected to the gate of the threshold compensation transistor T4 in the (i+2)th and (i+3)th row pixel circuits.

[0072] And so on. Here, n and i are integers greater than or equal to 1.

[0073] The following describes some specific structures of the various modules in the shift register. It should be noted that the overall technical concept provided in this application is universal. That is to say, the overall technical concept provided in this application is not only applicable to the specific structures of the various functional modules described in the following examples, but also applicable to the specific structures of the various functional modules in other examples.

[0074] In some implementations, such as Figure 8 As shown, the node control module 11 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1. The first terminal of the first transistor M1 is electrically connected to the input signal terminal IN, the second terminal of the first transistor M1 is electrically connected to the first node N1, and the gate of the first transistor M1 is electrically connected to the first clock signal terminal CK. The first terminal of the second transistor M2 is electrically connected to the high-voltage signal terminal VGH, the second terminal of the second transistor M2 is electrically connected to the second node N2, and the gate of the second transistor M2 is electrically connected to the first node N1. The first terminal of the third transistor M3 is electrically connected to the high-voltage signal terminal VGH, the second terminal of the third transistor M3 is electrically connected to the third node N3, and the gate of the third transistor M3 is electrically connected to the input signal terminal IN. The first terminal of the fourth transistor M4 is electrically connected to the first clock signal terminal CK, the second terminal of the fourth transistor M4 is electrically connected to the second node N2, and the gate of the fourth transistor M4 is electrically connected to the third node N3. The first terminal of the first capacitor C1 is electrically connected to the first clock signal terminal CK, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0075] For example, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can all be P-type transistors. The first capacitor C1 serves as a coupling capacitor.

[0076] In this embodiment, the node control module 11 is electrically connected to the input signal terminal IN, the first clock signal terminal CK, the high voltage signal terminal VGH, and the first node N1 and the second node N2. The node control module 11 adjusts the potential of the first node N1 and the second node N2 based on the signals of the input signal terminal IN, the first clock signal terminal CK, and the high voltage signal terminal VGH.

[0077] In some embodiments, the shift register further includes a fifth transistor M5, and the node control module 11 is electrically connected to the first node N1 through the fifth transistor M5. The gate of the fifth transistor M5 is electrically connected to the low voltage signal terminal VGL.

[0078] Specifically, the second terminal of the first transistor M1 and the gate of the second transistor M2 are connected to the fourth node N4. The first terminal of the fifth transistor M5 is electrically connected to the fourth node N4, the second terminal of the fifth transistor M5 is electrically connected to the first node N1, and the fifth transistor M5 is electrically connected to the low-voltage signal terminal VGL. The fifth transistor M5 is a P-type transistor.

[0079] In this embodiment, the fifth transistor M5 can isolate the first node N1 and the fourth node N4, so that the voltage of the fourth node N4 can be maintained relatively stably. For example, the voltage of the fourth node N4 will not drop below the voltage of the low voltage signal terminal VGL, thereby reducing the bias stress applied to the transistor connected to the fourth node N4.

[0080] In some embodiments, such as Figure 8 As shown, the first output module 12 includes a sixth transistor M6 and a seventh transistor M7; the first terminal of the sixth transistor M6 is electrically connected to the low-voltage signal terminal VGL, the second terminal of the sixth transistor M6 is electrically connected to the first output terminal out1, and the gate of the sixth transistor M6 is electrically connected to the first node N1; the first terminal of the seventh transistor M7 is electrically connected to the high-voltage signal terminal VGH, the second terminal of the seventh transistor M7 is electrically connected to the first output terminal out1, and the gate of the seventh transistor M7 is electrically connected to the second node N2.

[0081] For example, the first output module 12 further includes a second capacitor C2 and a third capacitor C3. The second capacitor C2 is electrically connected between the first output terminal out1 and the first node N1, and the third capacitor C3 is electrically connected between the second node N2 and the high voltage signal terminal VGH.

[0082] For example, both the sixth transistor M6 and the seventh transistor M7 are P-type transistors. During the same time period, the potentials of the first node N1 and the second node N2 are opposite to each other. When the first node N1 is at a low potential and the second node N2 is at a high potential, the sixth transistor M6 is turned on, and the low voltage of the low-voltage signal terminal VGL is transmitted to the first output terminal out1. When the first node N1 is at a high potential and the second node N2 is at a low potential, the seventh transistor M7 is turned on, and the high voltage of the high-voltage signal terminal VGH is transmitted to the first output terminal out1.

[0083] In some embodiments, such as Figure 8 As shown, the second output module 13 includes an eighth transistor M8 and a ninth transistor M9; the first terminal of the eighth transistor M8 is electrically connected to the high voltage signal terminal VGH, the second terminal of the eighth transistor M8 is electrically connected to the second output terminal out2, and the gate of the eighth transistor M8 is electrically connected to the first node N1; the first terminal of the ninth transistor M9 is connected to the second clock signal terminal NCK1, the second terminal of the ninth transistor M9 is electrically connected to the second output terminal out2, and the gate of the ninth transistor M9 is electrically connected to the second node N2.

[0084] like Figure 9 As shown, the effective level of the second clock signal terminal NCK1 and the effective level of the second node N2 at least partially overlap. For example, if both the effective level of the second clock signal terminal NCK1 and the effective level of the second node N2 are low, then during time period d1, both the second clock signal terminal NCK1 and the second node N2 are low.

[0085] For example, both the eighth transistor M8 and the ninth transistor M9 are P-type transistors. During the same time period, the potentials of the first node N1 and the second node N2 are opposite to each other. When the first node N1 is low and the second node N2 is high, the eighth transistor M8 is turned on, and the high voltage of the high-voltage signal terminal VGH is transmitted to the second output terminal out2. When the first node N1 is high and the second node N2 is low, the ninth transistor M9 is turned on, and the voltage of the second clock signal terminal NCK1 is transmitted to the second output terminal out2.

[0086] Taking the effective level of the second gate drive signal output from the second output terminal out2 as low as an example, when the eighth transistor M8 is turned on, it can only transmit the high voltage of the high voltage signal terminal VGH to the second output terminal out2. Therefore, the effective level (e.g., low level) output from the second output terminal out2 comes from the second clock signal terminal NCK1. In this embodiment, the effective level (e.g., low level) of the second clock signal terminal NCK1 at least partially overlaps with the effective level of the second node N2. Thus, when the ninth transistor M9 is turned on, the effective level of the second clock signal terminal NCK1 can be transmitted to the second output terminal out2, so that the second gate drive signal output from the second output terminal out2 includes an effective level, thereby ensuring the validity of the second gate drive signal.

[0087] In some embodiments, during the period when the clock signal at the first clock signal terminal CK is at an invalid level, the clock signal at the second clock signal terminal NCK1 includes a valid pulse.

[0088] The clock signals of the first clock signal terminal CK and the second clock signal terminal NCK1 are out of phase. The effective level (e.g., low level) of the first clock signal terminal CK and the effective level of the second clock signal terminal NCK1 are out of phase in time.

[0089] For example, the clock signals of the first clock signal terminal CK and the second clock signal terminal NCK1 can have the same period.

[0090] For example, the invalid level of the first clock signal terminal CK is high, and the valid pulse of the second clock signal terminal NCK1 is low. During the period when the first clock signal terminal CK is high, the second clock signal terminal NCK1 includes at least one low pulse.

[0091] For example, the signal output by the first output terminal out1 is used to control the threshold compensation transistor T4 in the pixel circuit, and the signal output by the second output terminal out2 is used to control the data writing transistor T2 in the pixel circuit. In this embodiment, it can be guaranteed that during the period when the first output terminal out1 outputs an effective level (such as a high level), the second output terminal out2 outputs at least one effective pulse (such as a low level pulse) so that the pixel circuit can realize the writing of data signals and the compensation of threshold voltage.

[0092] In some embodiments, such as Figure 8 As shown, the second output module 13 also includes a fourth capacitor C4; the first end of the fourth capacitor C4 is electrically connected to the second output terminal out2, and the second end of the fourth capacitor C4 is electrically connected to the gate of the ninth transistor M9.

[0093] like Figure 9As shown, in stage d1, the ninth transistor M9 is turned on, the second clock signal NCK1 changes from high level to low level, and the second output terminal out2 outputs a low level. Under the coupling effect of the fourth capacitor C4, the gate potential of the ninth transistor M9 can be further pulled down, so that the ninth transistor M9 is turned on more fully.

[0094] In some embodiments, such as Figure 8 As shown, the third output module 15 includes a tenth transistor M10 and an eleventh transistor M11; the first terminal of the tenth transistor M10 is electrically connected to the high voltage signal terminal VGH, the second terminal of the tenth transistor M10 is electrically connected to the third output terminal out3, and the gate of the tenth transistor M10 is electrically connected to the first node N1; the first terminal of the eleventh transistor M11 is electrically connected to the third clock signal terminal NCK2, the second terminal of the eleventh transistor M11 is electrically connected to the third output terminal out3, and the gate of the eleventh transistor M11 is electrically connected to the second node N2.

[0095] like Figure 9 As shown, the effective level of the third clock signal terminal NCK2 overlaps at least partially with the effective level of the second node N2, and the clock signal of the third clock signal terminal NCK2 is out of phase with the clock signal of the second clock signal terminal NCK1 of the second output module 13.

[0096] For example, the effective level of the third clock signal terminal NCK2 and the effective level of the second node N2 are both low. During time period d2, both the third clock signal terminal NCK2 and the second node N2 are low.

[0097] For example, both the tenth transistor M10 and the eleventh transistor M11 are P-type transistors. During the same time period, the potentials of the first node N1 and the second node N2 are opposite to each other. When the first node N1 is at a low potential and the second node N2 is at a high potential, the tenth transistor M10 is turned on, and the high voltage of the high-voltage signal terminal VGH is transmitted to the third output terminal out3. When the first node N1 is at a high potential and the second node N2 is at a low potential, the eleventh transistor M11 is turned on, and the voltage of the third clock signal terminal NCK2 is transmitted to the third output terminal out3.

[0098] Taking the effective level of the third gate drive signal output from the third output terminal out3 as low as an example, when the tenth transistor M10 is turned on, it can only transmit the high voltage of the high voltage signal terminal VGH to the third output terminal out3. Therefore, the effective level (e.g., low level) output from the third output terminal out3 comes from the third clock signal terminal NCK2. In this embodiment, the effective level (e.g., low level) of the third clock signal terminal NCK2 at least partially overlaps with the effective level of the second node N2. Thus, when the eleventh transistor M11 is turned on, the effective level of the third clock signal terminal NCK2 can be transmitted to the third output terminal out3, so that the third gate drive signal output from the third output terminal out3 includes an effective level, thereby ensuring the validity of the third gate drive signal.

[0099] In addition, the clock signal of the third clock signal terminal NCK2 is out of phase with the clock signal of the second clock signal terminal NCK1, which makes the effective levels of the third gate drive signal output by the third output terminal out3 and the second gate drive signal output by the second output terminal out2 out of time, so that the signals output by the third output terminal out3 and the second output terminal out2 can drive pixel circuits in different rows.

[0100] In some embodiments, the duty cycle of the clock signal at the third clock signal terminal NCK2 is the same as the duty cycle of the clock signal at the second clock signal terminal NCK1 of the second output module 13.

[0101] The effective level (e.g., low level) output by the third output terminal out3 originates from the third clock signal terminal NCK2, and the effective level (e.g., low level) output by the second output terminal out2 originates from the second clock signal terminal NCK1. When the duty cycles of the clock signals of the third clock signal terminal NCK2 and the second clock signal terminal NCK1 are the same, the width of the effective level output by the third output terminal out3 is the same as the width of the effective level output by the second output terminal out2. For example, the signals output by the third output terminal out3 and the second output terminal out2 are used to control the writing of data signals for different row pixel circuits. When the width of the effective level output by the third output terminal out3 is the same as the width of the effective level output by the second output terminal out2, the writing duration of the data signals for different row pixel circuits is the same, thereby improving the consistency of data signal writing and thus improving display uniformity.

[0102] In some embodiments, such as Figure 9 As shown, during the period when the clock signal of the first clock signal terminal CK of the node control module 11 is at an invalid level, the clock signal of the third clock signal terminal NCK2 includes a valid pulse.

[0103] The clock signals of the first clock signal terminal CK and the third clock signal terminal NCK2 are out of phase. The effective level (e.g., low level) of the first clock signal terminal CK and the effective level of the third clock signal terminal NCK2 are out of phase in time.

[0104] For example, the clock signals of the first clock signal terminal CK and the third clock signal terminal NCK2 may have the same period.

[0105] For example, the invalid level of the first clock signal terminal CK is high, and the valid pulse of the third clock signal terminal NCK2 is low. During the period when the first clock signal terminal CK is high, the third clock signal terminal NCK2 includes at least one low pulse.

[0106] For example, the signal output by the first output terminal out1 is used to control the threshold compensation transistor T4 in the pixel circuit, and the signal output by the third output terminal out3 is used to control the data writing transistor T2 in the pixel circuit. In this embodiment, it can be guaranteed that during the period when the first output terminal out1 outputs an effective level (such as a high level), the third output terminal out3 outputs at least one effective pulse (such as a low level pulse) so that the pixel circuit can realize the writing of data signals and the compensation of threshold voltage.

[0107] In some embodiments, such as Figure 8 As shown, the third output module 15 also includes a fifth capacitor C5; the first end of the fifth capacitor C5 is electrically connected to the third output terminal out3, and the second end of the fifth capacitor C5 is electrically connected to the gate of the eleventh transistor M11.

[0108] like Figure 9 As shown, in stage d2, the eleventh transistor M11 is turned on, the third clock signal NCK2 changes from high level to low level, and the third output terminal out3 outputs a low level. Under the coupling effect of the fifth capacitor C5, the gate potential of the eleventh transistor M11 can be further pulled down, so that the ninth transistor M9 is turned on more fully.

[0109] In some embodiments, such as Figure 8 As shown, the shift register also includes a twelfth transistor M12; the second output module 13 and the third output module 15 are electrically connected to the second node N2 through the twelfth transistor M12, and the gate of the twelfth transistor M12 is electrically connected to the low voltage signal terminal VGL.

[0110] Specifically, the first terminal of the twelfth transistor M12 is electrically connected to the second node N2, the second terminal of the twelfth transistor M12 is electrically connected to the fifth node N5, and the gate of the twelfth transistor M12 is electrically connected to the low-voltage signal terminal VGL. The twelfth transistor M12 is a P-type transistor. The gates of the ninth transistor M9 and the eleventh transistor M11 are electrically connected to the fifth node N5.

[0111] In this embodiment, the twelfth transistor M12 can isolate the second node N2 and the fifth node N5, so that the voltage of the fifth node N5 can be maintained relatively stably. For example, the voltage of the fifth node N5 will not drop below the voltage of the low voltage signal terminal VGL, thereby reducing the bias stress applied to the transistor connected to the fifth node N5.

[0112] For example, please refer to the reference. Figure 4 , Figure 8 and Figure 10 For example, if the first direction X is the row direction, and the shift register includes a first output module 12, a second output module 13, and a third output module 15, one shift register VSR can drive two rows of pixel circuits 20. For example, the first output terminal out1 is electrically connected to the gate of the threshold compensation transistor T4 in the two rows of pixel circuits 20, and the second output terminal out2 and the third output terminal out3 are respectively electrically connected to the gate of the data writing transistor T2 in the two rows of pixel circuits 20.

[0113] The display panel also includes multiple clock signal lines 41, 42, and 51-54. The first clock signal terminal CK in the odd-level shift register is electrically connected to clock signal line 41, the first clock signal terminal CK in the even-level shift register is electrically connected to clock signal line 42, the second clock signal terminal NCK1 in the odd-level shift register is electrically connected to clock signal line 51, the third clock signal terminal NCK2 in the odd-level shift register is electrically connected to clock signal line 52, the second clock signal terminal NCK1 in the even-level shift register is electrically connected to clock signal line 53, and the third clock signal terminal NCK2 in the even-level shift register is electrically connected to clock signal line 54.

[0114] For example, such as Figure 11 As shown, the clock signals on clock signal lines 41 and 42 are shifted by 2H, and the clock signals on clock signal lines 51 to 54 are shifted by 1H, where H is the scan duration corresponding to one row of pixel circuits.

[0115] In some embodiments, such as Figure 12 or Figure 13As shown, the gating module 14 includes a first submodule 141 and a second submodule 142; the first submodule 141 is used to output an invalid level under the control of the potential of the first node N1; the second submodule 142 is used to output an effective level under the control of the potential of the second node N2 and the gating signal terminal CTRL.

[0116] The gate drive signal output by the gating module 14 is used to drive the corresponding transistor in the pixel circuit. When the gating module 14 outputs an invalid level, the transistor controlled by the gating module 14 is turned off; when the gating module 14 outputs an valid level, the transistor controlled by the gating module 14 is turned on.

[0117] In this embodiment, the gating module 14 is divided into two sub-modules, one for outputting an invalid level and the other for outputting an effective level, which makes the structure simpler.

[0118] In some embodiments, such as Figure 12 or Figure 13 As shown, the first submodule 141 includes a thirteenth transistor M13. The first terminal of the thirteenth transistor M13 is electrically connected to the low voltage signal terminal VGL, the second terminal of the thirteenth transistor M13 is electrically connected to the fourth output terminal out4 of the gating module 14, and the gate of the thirteenth transistor M13 is electrically connected to the first node N1.

[0119] In some embodiments, such as Figure 12 As shown, the second submodule 142 includes a fourteenth transistor M14. The first terminal of the fourteenth transistor M14 is electrically connected to the gating signal terminal CTRL, the second terminal of the fourteenth transistor M14 is electrically connected to the fourth output terminal out4 of the gating module 14, and the gate of the fourteenth transistor M14 is electrically connected to the second node N2.

[0120] Please refer to the reference. Figure 12 and Figure 14 When the strobe signal CTRL is high, the fourth output terminal out4 of the strobe module 14 can output a valid level (high level). When the strobe signal CTRL is low, the fourth output terminal out4 of the strobe module 14 can only output an invalid level (low level). The refresh rate can be switched by controlling the strobe signal CTRL.

[0121] For example, please refer to the reference. Figure 14 and Figure 15The display panel can be divided into display area A1, display area A2, and display area A3. The strobe signal terminal CTRL used to drive the shift register of display area A1 and display area A3 is at a low level, while the strobe signal terminal CTRL used to drive the shift register of display area A2 is at a high level. This makes the refresh rate of display area A2 greater than that of display area A1 and display area A3, thus realizing the function of segmented frequency display.

[0122] For example, please refer to the reference. Figure 12 and Figure 16 For example, if the first direction X is the row direction, and the shift register includes a first output module 12, a second output module 13, a third output module 15, and a gating module 14, one shift register VSR can drive two rows of pixel circuits 20. For example, the fourth output terminal out4 is electrically connected to the gate of the threshold compensation transistor T4 in the two rows of pixel circuits 20, and the second output terminal out2 and the third output terminal out3 are electrically connected to the gate of the data writing transistor T2 in the two rows of pixel circuits 20, respectively. In addition, the first output terminal out1 is no longer electrically connected to the pixel circuit, and its output signal is used as a stage transmission signal.

[0123] Figure 16 The connection method of the clock signal lines 41, 42, 51~54 and the shift register shown is the same. Figure 10 As shown, this will not be repeated here. See also Figure 16 The display panel also includes at least two gating control signal lines 61 and 62, which can be alternately electrically connected to shift registers corresponding to different display areas. The gating control signal line 61 or the gating control signal line 62 is electrically connected to at least 10 shift registers corresponding to one display area.

[0124] like Figure 12 As shown, the strobe signal terminal CTRL is electrically connected to the first pole of the fourteenth transistor M14. Setting at least two strobe control signal lines can prevent the effective level of the fourth output terminal out4 of part of the shift register from being cut off by the signal of the strobe signal terminal CTRL, resulting in incomplete output.

[0125] In other embodiments, such as Figure 13 As shown, the second submodule 142 includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19.

[0126] The first terminal of the fifteenth transistor M15 is electrically connected to the strobe signal terminal CTRL, the second terminal of the fifteenth transistor M15 is electrically connected to the gate of the sixteenth transistor M16, and the gate of the fifteenth transistor M15 is electrically connected to the first output terminal out1 of the first output module 12.

[0127] The first terminal of the sixteenth transistor M16 is electrically connected to the second node N2, and the second terminal of the sixteenth transistor M16 is electrically connected to the gate of the eighteenth transistor M18.

[0128] The first terminal of the seventeenth transistor M17 is electrically connected to the high-level signal terminal VGH, the second terminal of the seventeenth transistor M17 is electrically connected to the gate of the eighteenth transistor M18, and the gate of the seventeenth transistor M17 is electrically connected to the first node N1. The first node N1 and the fourth node N4 are electrically connected via the fifth transistor M5. Specifically, the gate of the seventeenth transistor M17 can be directly electrically connected to the fourth node N4 via a connecting wire, and the gate of the seventeenth transistor M17 is electrically connected to the first node N1 via the fifth transistor M5.

[0129] The first terminal of the eighteenth transistor M18 is electrically connected to the high-level signal terminal VGH, and the second terminal of the eighteenth transistor M18 is electrically connected to the fourth output terminal out4 of the gating module 14.

[0130] Please refer to the reference. Figure 13 and Figure 17 When the strobe signal CTRL is low, the fourth output terminal out4 of the strobe module 14 can output a valid level (high level). When the strobe signal CTRL is high, the fourth output terminal out4 of the strobe module 14 can only output an invalid level (low level). The refresh rate can be switched by controlling the strobe signal CTRL.

[0131] For example, please refer to the reference. Figure 17 and Figure 15 The display panel can be divided into display area A1, display area A2, and display area A3. The strobe signal terminal CTRL used to drive the shift register of display area A1 and display area A3 is high, and the strobe signal terminal CTRL used to drive the shift register of display area A2 is low, so that the refresh frequency of display area A2 is greater than that of display area A1 and display area A3, thus realizing the function of segmented frequency display.

[0132] For example, please refer to the reference. Figure 13 and Figure 18For example, if the first direction X is the row direction, and the shift register includes a first output module 12, a second output module 13, a third output module 15, and a gating module 14, one shift register VSR can drive two rows of pixel circuits 20. For example, the fourth output terminal out4 is electrically connected to the gate of the threshold compensation transistor T4 in the two rows of pixel circuits 20, and the second output terminal out2 and the third output terminal out3 are electrically connected to the gate of the data writing transistor T2 in the two rows of pixel circuits 20, respectively. In addition, the first output terminal out1 is no longer electrically connected to the pixel circuit, and its output signal is used as a stage transmission signal.

[0133] Figure 18 The connection method of the clock signal lines 41, 42, 51~54 and the shift register shown is the same. Figure 16 As shown, this will not be repeated here. See also Figure 18 The display panel may include only one gating control signal line 63, which is electrically connected to the gating signal terminal CTRL of each shift register.

[0134] like Figure 13 As shown, the signal of the strobe signal terminal CTRL is not used as the output signal of the fourth output terminal out4. Therefore, the signal of the strobe signal terminal CTRL will not destroy the integrity of the output signal of the fourth output terminal out4 of the shift registers of other stages. In this embodiment, only one strobe control signal line 63 is set, which can reduce the number of signal lines at the border and is beneficial to achieving a narrow border.

[0135] In some embodiments, such as Figure 13 As shown, the gating module 14 also includes a sixth capacitor C6 and / or a seventh capacitor C7; the first end of the sixth capacitor C6 is electrically connected to the low-level signal terminal VGL, and the second end of the sixth capacitor C6 is electrically connected to the gate of the sixteenth transistor M16; the first end of the seventh capacitor C7 is electrically connected to the high-level signal terminal VGH, and the second end of the seventh capacitor C7 is electrically connected to the fourth output terminal out4 of the gating module 14.

[0136] In this embodiment, by setting the sixth capacitor C6, the gate potential stability of the sixteenth transistor M16 can be maintained; similarly, by setting the seventh capacitor C7, the gate potential stability of the eighteenth transistor M18 can be maintained.

[0137] It should be noted that the first output module 12 is not controlled by the strobe signal terminal CTRL. Therefore, the first output terminal out1 can output a signal normally. The signal output by the first output terminal out1 is used as the transmission signal. In this way, even if the refresh rate of some display areas decreases, it will not affect the normal transmission.

[0138] For example, please refer to the reference. Figure 4 and Figure 19 , Figure 19 The diagram shows the gate drive signals connected to the pixel circuits in rows i and i+1. In the pixel circuits in rows i and i+1, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are connected to the same light-emitting control signal EM(i&i+1). In the pixel circuits in rows i and i+1, the gate reset transistor T5 is connected to the same gate drive signal S1N(i&i+1). In the pixel circuits in rows i and i+1, the threshold compensation transistor T4 is connected to the same gate drive signal S2N(i&i+1). In the pixel circuits in rows i and i+1, the anode reset transistor T7 and the bias adjustment transistor T8 are connected to the same gate drive signal SPX(i&i+1). In the pixel circuit in row i, the data writing transistor T2 is connected to the gate drive signal SP(i). In the pixel circuit in row i, the data writing transistor T2 is connected to the gate drive signal SP(i).

[0139] The gate drive signals S1N(i&i+1) and S2N(i&i+1) can be provided by shift registers of different stages in the above embodiments. For example, the k-th stage shift register provides the gate drive signal S1N(i&i+1), and the (k+p)-th stage shift register provides the gate drive signal S2N(i&i+1), where k is an integer greater than or equal to 1, and p is an integer greater than or equal to 1. For example, p=4. Of course, the value of p can be designed according to actual needs.

[0140] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 20 , Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 20 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 20 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0141] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, It includes a gate driving circuit, which includes multiple cascaded shift registers, each of which includes a node control module, a first output module, and a second output module. The node control module is used to adjust the potential of the first node and the second node; The first output module is used to output a first gate drive signal under the control of the potentials of the first node and the second node; The second output module is used to output a second gate drive signal under the control of the potentials of the first node and the second node; The effective level of the first gate drive signal has the opposite polarity to the effective level of the second gate drive signal.

2. The display panel according to claim 1, characterized in that, The shift register further includes a gating module, which is used to output a fourth gate drive signal under the control of the potentials of the first node and the second node and the gating signal. The gating signal is used to control whether the fourth gate drive signal includes an active level. The display panel includes pixel circuitry and light-emitting elements, wherein the pixel circuitry is electrically connected to the light-emitting elements. The output terminal of the first output module in the m-th level shift register is electrically connected to the input signal terminal of the node control module in the (m+1)-th level shift register, where m is an integer greater than or equal to 1. The output terminals of the second output module and the gating module in the shift register are electrically connected to the gates of different transistors in the same pixel circuit.

3. The display panel according to claim 1, characterized in that, The shift register further includes a third output module, which is used to output a third gate drive signal under the control of the potentials of the first node and the second node; The effective level of the third gate drive signal has the same polarity as the effective level of the second gate drive signal, the effective level of the third gate drive signal is misaligned with the effective level of the second gate drive signal, and the effective level of the first gate drive signal overlaps with the effective level of the second gate drive signal and the effective level of the third gate drive signal in time.

4. The display panel according to claim 3, characterized in that, The display panel includes pixel circuitry and light-emitting elements, wherein the pixel circuitry is electrically connected to the light-emitting elements. The output terminals of the second output module and the third output module in the same level shift register are electrically connected to the pixel circuits in different rows. The second gate drive signal and the third gate drive signal are used to control the writing of data signals.

5. The display panel according to claim 4, characterized in that, The output terminal of the first output module in the m-th level shift register is electrically connected to the input signal terminal of the node control module in the (m+1)-th level shift register, where m is an integer greater than or equal to 1. The output terminals of the first output module and the second output module in the shift register are electrically connected to the gates of different transistors in the same pixel circuit. Alternatively, the shift register may further include a gating module, which is used to output a fourth gate drive signal under the control of the potentials of the first node and the second node and the gating signal. The gating signal is used to control whether the fourth gate drive signal includes an effective level. The output terminal of the second output module in the shift register and the output terminal of the gating module are electrically connected to the gates of different transistors in the same pixel circuit.

6. The display panel according to claim 5, characterized in that, The output terminal of the first output module is electrically connected to the gate of the transistor with the same function in the two rows of pixel circuits; Alternatively, the output of the gating module is electrically connected to the gate of a transistor that performs the same function in both rows of the pixel circuit.

7. The display panel according to claim 1, characterized in that, The node control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor; The first terminal of the first transistor is electrically connected to the input signal terminal, the second terminal of the first transistor is electrically connected to the first node, and the gate of the first transistor is electrically connected to the first clock signal terminal. The first terminal of the second transistor is electrically connected to the high-voltage signal terminal, the second terminal of the second transistor is electrically connected to the second node, and the gate of the second transistor is electrically connected to the first node. The first terminal of the third transistor is electrically connected to the high-voltage signal terminal, the second terminal of the third transistor is electrically connected to the third node, and the gate of the third transistor is electrically connected to the input signal terminal. The first terminal of the fourth transistor is electrically connected to the first clock signal terminal, the second terminal of the fourth transistor is electrically connected to the second node, and the gate of the fourth transistor is electrically connected to the third node. The first terminal of the first capacitor is electrically connected to the first clock signal terminal, and the second terminal of the first capacitor is electrically connected to the third node.

8. The display panel according to claim 7, characterized in that, The shift register also includes a fifth transistor, and the node control module is electrically connected to the first node through the fifth transistor. The gate of the fifth transistor is electrically connected to a low-voltage signal terminal.

9. The display panel according to claim 7, characterized in that, The first output module includes a sixth transistor and a seventh transistor; The first terminal of the sixth transistor is electrically connected to the low-voltage signal terminal, the second terminal of the sixth transistor is electrically connected to the first output terminal, and the gate of the sixth transistor is electrically connected to the first node. The first terminal of the seventh transistor is electrically connected to the high-voltage signal terminal, the second terminal of the seventh transistor is electrically connected to the first output terminal, and the gate of the seventh transistor is electrically connected to the second node.

10. The display panel according to claim 8, characterized in that, The second output module includes an eighth transistor and a ninth transistor; The first terminal of the eighth transistor is electrically connected to the high-voltage signal terminal, the second terminal of the eighth transistor is electrically connected to the second output terminal, and the gate of the eighth transistor is electrically connected to the first node. The first terminal of the ninth transistor is electrically connected to the second clock signal terminal, the second terminal of the ninth transistor is electrically connected to the second output terminal, the gate of the ninth transistor is electrically connected to the second node, and the effective level of the second clock signal terminal and the effective level of the second node at least partially overlap.

11. The display panel according to claim 10, characterized in that, During the period when the clock signal at the first clock signal terminal is at an invalid level, the clock signal at the second clock signal terminal includes a valid pulse.

12. The display panel according to claim 9, characterized in that, The second output module also includes a fourth capacitor; The first terminal of the fourth capacitor is electrically connected to the second output terminal, and the second terminal of the fourth capacitor is electrically connected to the gate of the ninth transistor.

13. The display panel according to claim 3, characterized in that, The third output module includes a tenth transistor and an eleventh transistor; The first terminal of the tenth transistor is electrically connected to the high-voltage signal terminal, the second terminal of the tenth transistor is electrically connected to the third output terminal, and the gate of the tenth transistor is electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the third clock signal terminal, the second terminal of the eleventh transistor is electrically connected to the third output terminal, the gate of the eleventh transistor is electrically connected to the second node, the effective level of the third clock signal terminal and the effective level of the second node overlap at least partially, and the clock signal of the third clock signal terminal is out of phase with the clock signal of the second clock signal terminal of the second output module.

14. The display panel according to claim 13, characterized in that, The duty cycle of the clock signal at the third clock signal terminal is the same as the duty cycle of the clock signal at the second clock signal terminal of the second output module.

15. The display panel according to claim 13, characterized in that, During the period when the clock signal at the first clock signal terminal of the node control module is at an active level, the clock signal at the third clock signal terminal includes a valid pulse.

16. The display panel according to claim 13, characterized in that, The third output module also includes a fifth capacitor; The first terminal of the fifth capacitor is electrically connected to the third output terminal, and the second terminal of the fifth capacitor is electrically connected to the gate of the eleventh transistor.

17. The display panel according to claim 3, characterized in that, The shift register also includes a twelfth transistor; The second output module and the third output module are electrically connected to the second node through the twelfth transistor, and the gate of the twelfth transistor is electrically connected to the low-voltage signal terminal.

18. The display panel according to claim 2, characterized in that, The gating module includes a first sub-module and a second sub-module; The first submodule is used to output an invalid level under the control of the potential of the first node; The second submodule is used to output an effective level under the control of the potential of the second node and the strobe signal terminal.

19. The display panel according to claim 18, characterized in that, The first submodule includes a thirteenth transistor, the first terminal of which is electrically connected to a low-voltage signal terminal, the second terminal of which is electrically connected to the output terminal of the gating module, and the gate of which is electrically connected to the first node.

20. The display panel according to claim 18, characterized in that, The second submodule includes a fourteenth transistor, the first terminal of which is electrically connected to the gating signal terminal, the second terminal of which is electrically connected to the output terminal of the gating module, and the gate of which is electrically connected to the second node.

21. The display panel according to claim 18, characterized in that, The second submodule includes the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the nineteenth transistor; The first terminal of the fifteenth transistor is electrically connected to the gating signal terminal, the second terminal of the fifteenth transistor is electrically connected to the gate of the sixteenth transistor, and the gate of the fifteenth transistor is electrically connected to the output terminal of the first output module. The first terminal of the sixteenth transistor is electrically connected to the second node, and the second terminal of the sixteenth transistor is electrically connected to the gate of the eighteenth transistor. The first terminal of the seventeenth transistor is electrically connected to the high-level signal terminal, the second terminal of the seventeenth transistor is electrically connected to the gate of the eighteenth transistor, and the gate of the seventeenth transistor is electrically connected to the first node; The first terminal of the eighteenth transistor is electrically connected to the high-level signal terminal, and the second terminal of the eighteenth transistor is electrically connected to the output terminal of the gating module.

22. The display panel according to claim 21, characterized in that, The gating module also includes a sixth capacitor and / or a seventh capacitor; The first terminal of the sixth capacitor is electrically connected to the low-level signal terminal, and the second terminal of the sixth capacitor is electrically connected to the gate of the sixteenth transistor. The first terminal of the seventh capacitor is electrically connected to the high-level signal terminal, and the second terminal of the seventh capacitor is electrically connected to the output terminal of the gating module.

23. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 22.

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