Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and aims to improve the performance of the semiconductor device. The semiconductor device comprises a first semiconductor structure, a third bonding layer and a second semiconductor structure, the first semiconductor structure comprises a first bonding layer and a first bonding pad extending into the first bonding layer; the second semiconductor structure comprises a second bonding layer and a second bonding pad extending into the second bonding layer; the third bonding layer is located between the first bonding layer and the second bonding layer, and one of the first bonding pad and the second bonding pad penetrates through the third bonding layer to be bonded with the other one; the bonding energy of the third bonding layer is greater than that of the first bonding layer; the diffusion coefficient of the material of the first bonding pad in the first bonding layer is smaller than the diffusion coefficient of the material of the first bonding pad in the third bonding layer; the diffusion coefficient of the material of the second bonding pad in the second bonding layer is smaller than the diffusion coefficient of the material of the second bonding pad in the third bonding layer. The semiconductor device is used for image display.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] With the development of semiconductor technology, the manufacturing process of semiconductor devices is constantly improving.

[0003] In the fabrication of semiconductor devices, it is generally necessary to bond two semiconductor structures together. The bonding strength between the bonding layers in the two semiconductor structures, as well as the degree of diffusion of the bonding pad material during the bonding process, affects the bonding strength and performance of the semiconductor device. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, as well as an electronic device, with the aim of improving the bonding strength and performance of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] Some embodiments of this disclosure provide a semiconductor device, including: a first semiconductor structure, a third bonding layer, and a second semiconductor structure stacked together. The first semiconductor structure includes a first bonding pad and a first substrate and a first bonding layer stacked together. The first bonding pad extends at least into the interior of the first bonding layer along a direction from the first bonding layer to the first substrate. The second semiconductor structure includes a second bonding pad and a second substrate and a second bonding layer stacked together. The second bonding pad extends at least into the interior of the second bonding layer along a direction from the second bonding layer to the second substrate. The orthographic projection of the first bonding pad onto the first substrate at least partially overlaps with the orthographic projection of the second bonding pad onto the first substrate. The third bonding layer is located between the first bonding layer and the second bonding layer. One of the first bonding pad and the second bonding pad passes through at least a portion of the third bonding layer and is bonded to the other of the first bonding pad and the second bonding pad. The bonding energy of the third bonding layer is greater than the bonding energy of the first bonding layer and greater than the bonding energy of the second bonding layer. The diffusion coefficient of the material of the first bonding pad in the first bonding layer is less than the diffusion coefficient of the material of the first bonding pad in the third bonding layer. And / or, the diffusion coefficient of the material of the second bonding pad in the second bonding layer is less than the diffusion coefficient of the material of the second bonding pad in the third bonding layer.

[0007] The semiconductor device provided by the embodiments of this disclosure, by providing a third bonding layer between a first bonding layer of a first semiconductor structure and a second bonding layer of a second semiconductor structure, and by providing one of a first bonding pad and a second bonding pad through at least a portion of the third bonding layer to bond with the other, and further providing that the bonding energy of the third bonding layer is greater than that of the first bonding layer and greater than that of the second bonding layer, thereby ensuring the bonding stability between the first and second semiconductor structures and improving the performance of the semiconductor device. Simultaneously, the diffusion coefficient of the material of the first bonding pad in the first bonding layer is relatively small, making it difficult for the material of the first bonding pad to diffuse in the first bonding layer, and the diffusion coefficient of the material of the second bonding pad in the second bonding layer is relatively small, making it difficult for the material of the second bonding pad to diffuse in the second bonding layer, thereby protecting the morphology of the first and second bonding pads, which is beneficial to improving the performance of the semiconductor device, preventing short circuits between adjacent first bonding pads due to material diffusion of the first bonding pad, and preventing short circuits between adjacent second bonding pads due to material diffusion of the second bonding pad.

[0008] In some embodiments, the third bonding layer includes a first sublayer and a second sublayer stacked together. The first sublayer is located between the second sublayer and the first bonding layer, the first sublayer surrounding the first bonding pad, and the second sublayer surrounding the second bonding pad.

[0009] In some embodiments, the thickness of the first sublayer is less than the thickness of the first bonding layer, and the thickness of the second sublayer is less than the thickness of the second bonding layer.

[0010] In some embodiments, the thickness range of the first sublayer includes The thickness range of the second sublayer includes

[0011] In some embodiments, the material of the first sublayer includes silicon oxide, and the material of the second sublayer includes silicon oxide or silicon oxynitride.

[0012] In some embodiments, the first bonding pad includes a first conductive pattern and a first bonding pattern stacked along the thickness direction of the first bonding layer, and the second bonding pad includes a second conductive pattern and a second bonding pattern stacked along the thickness direction of the second bonding layer. The first bonding pattern and the second bonding pattern are bonded to each other.

[0013] In some embodiments, the first bonding pad penetrates the third bonding layer, and the first bonding pad includes a first conductive pattern and a first bonding pattern stacked along the thickness direction of the first bonding layer. The first bonding pattern is located between the first conductive pattern and the second bonding pad, and is bonded to the second bonding pad. Alternatively, the second bonding pad penetrates the third bonding layer, and the second bonding pad includes a second conductive pattern and a second bonding pattern stacked along the thickness direction of the second bonding layer. The second bonding pattern is bonded to the first bonding pad.

[0014] In some embodiments, the material of the first bonding layer includes silicon oxynitride, and the material of the second bonding layer includes silicon nitride.

[0015] Some embodiments of this disclosure also provide a method for fabricating a semiconductor device, the method comprising: providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding pad and a first substrate and a first bonding layer stacked thereon. Along the direction from the first bonding layer to the first substrate, the first bonding pad extends at least into the interior of the first bonding layer. The second semiconductor structure includes a second bonding pad and a second substrate and a second bonding layer stacked thereon. Along the direction from the second bonding layer to the second substrate, the second bonding pad extends at least into the interior of the second bonding layer. A third bonding layer is formed. The third bonding layer is located on the first bonding layer and / or the second bonding layer. The bonding energy of the third bonding layer is greater than the bonding energy of the first bonding layer and greater than the bonding energy of the second bonding layer. The first semiconductor structure and the second semiconductor structure are bonded together. The third bonding layer is located between the first bonding layer and the second bonding layer, and the orthographic projection of the first bonding pad onto the first substrate at least partially overlaps with the orthographic projection of the second bonding pad onto the first substrate. One of the first and second bonding pads extends through at least a portion of the third bonding layer and is bonded to the other of the first and second bonding pads. The diffusion coefficient of the material of the first bonding pad in the first bonding layer is less than the diffusion coefficient of the material of the first bonding pad in the third bonding layer. And / or, the diffusion coefficient of the material of the second bonding pad in the second bonding layer is less than the diffusion coefficient of the material of the second bonding pad in the third bonding layer.

[0016] The beneficial effects that can be achieved by the semiconductor device fabrication methods provided in some embodiments of this disclosure are the same as those that can be achieved by the semiconductor devices provided in some of the above embodiments, and will not be repeated here.

[0017] In some embodiments, the third bonding layer is located on the first bonding layer. Forming the third bonding layer includes: using a first target gas to process the surface of the first bonding layer away from the first substrate to form the third bonding layer, and simultaneously processing the surface of the first bonding pad away from the first substrate to form a first bonding pattern. Alternatively, the third bonding layer is located on the second bonding layer. Forming the third bonding layer includes: using a first target gas to process the surface of the second bonding layer away from the second substrate to form the third bonding layer, and simultaneously processing the surface of the second bonding pad away from the second substrate to form a second bonding pattern.

[0018] In some embodiments, the third bonding layer is located on the first bonding layer, and before bonding the first semiconductor structure to the second semiconductor structure, the fabrication method further includes:

[0019] The first bonding pattern is reduced using a second target gas. Alternatively, the third bonding layer is located on the second bonding layer, and before bonding the first semiconductor structure to the second semiconductor structure, the fabrication method further includes: reducing the second bonding pattern using a second target gas.

[0020] In some embodiments, the third bonding layer includes a first sublayer and a second sublayer, the first sublayer being located on the first bonding layer and the second sublayer being located on the second bonding layer. Forming the third bonding layer includes: using a first target gas to process the surface of the first bonding layer away from the first substrate to form the first sublayer; simultaneously processing the surface of the first bonding pad away from the first substrate to form the first bonding pattern. The first sublayer surrounds the first bonding pattern. Using the first target gas, the surface of the second bonding layer away from the second substrate is processed to form the second sublayer; simultaneously processing the surface of the second bonding pad away from the second substrate to form the second bonding pattern. The second sublayer surrounds the second bonding pattern.

[0021] In some embodiments, before bonding the first semiconductor structure to the second semiconductor structure, the fabrication method further includes: using a second target gas to reduce the first bonding pattern and / or the second bonding pattern.

[0022] In some embodiments, the first target gas includes nitrous oxide.

[0023] In some embodiments, the second target gas includes ammonia or hydrogen.

[0024] Some embodiments of this disclosure also provide an electronic device comprising: a semiconductor device as described in any of the above embodiments, and a circuit board connected to the semiconductor device.

[0025] The beneficial effects that the electronic devices provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the semiconductor devices provided in some embodiments above can achieve, and will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0028] Figure 2 This is a structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0029] Figure 3 This is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 4 This is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 5 This is a structural diagram of a semiconductor device according to related technologies;

[0032] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

[0033] Figures 7-18 The diagram shows the structure of a semiconductor device in different fabrication steps according to some embodiments of this disclosure. Detailed Implementation

[0034] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0037] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0038] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0039] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0040] As used herein, “approximately” includes the values ​​stated and the average value within an acceptable range of deviation from the given values, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0041] As used herein, “equal” includes the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity could also be, for example, a deviation within 5°. “Equal” includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality could be, for example, a difference between the two equalities less than or equal to 5% of either one.

[0042] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0043] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0044] This disclosure provides an electronic device. This electronic device can be a camera, mobile phone, tablet computer, desktop computer, laptop computer, handheld computer, laptop computer, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch), in-vehicle device, smart home device, and / or smart city device, etc., that requires image acquisition. This disclosure does not impose any special limitations on the specific type of this electronic device.

[0045] like Figure 1 As shown, the above-mentioned electronic device 1000 includes a semiconductor device 100 and a circuit board 200.

[0046] For example, the semiconductor device 100 is connected to the circuit board 200 and receives control signals provided by the circuit board 200, enabling the electronic device 1000 to perform functions such as display and storage.

[0047] Specifically, such as Figure 2 As shown, the semiconductor device 100 includes a first semiconductor structure 101 and a second semiconductor structure 102 stacked together.

[0048] For example, the first semiconductor structure 101 can be a logic semiconductor structure, etc. The second semiconductor structure 102 can be a sensor semiconductor structure, such as an image sensor semiconductor structure, etc. Of course, both the first semiconductor structure 101 and the second semiconductor structure 102 can be logic semiconductor structures.

[0049] The first semiconductor structure 101 includes a first substrate 10 and a first bonding layer 20 stacked together. For example, the first substrate 10 may include a first substrate, a first circuit structure layer, etc., stacked together. The first circuit structure layer may include at least one conductive layer, at least one dielectric layer, etc.

[0050] The first semiconductor structure 101 further includes a first bonding pad 50. The first bonding pad 50 extends at least into the interior of the first bonding layer 20 in the direction from the first bonding layer 20 to the first substrate 10.

[0051] It is understood that the portion of the first bonding pad 50 near the second semiconductor structure 102 is used to achieve bonding between the first semiconductor structure 101 and the second semiconductor structure 102, and the portion of the first bonding pad 50 extending into the first bonding layer 20 is used to electrically connect with the first circuit structure layer in the first substrate 10 to achieve signal transmission.

[0052] Along the direction from the first bonding layer 20 to the first substrate 10, the size of the first bonding pad 50 can be selected and set according to actual conditions, and the embodiments of this disclosure do not limit this. For example, the first bonding pad 50 penetrates a portion of the first bonding layer 20. Or, the first bonding pad 50 penetrates the first bonding layer 20 and stops at the interface between the first substrate 10 and the first bonding layer 20. Or, as... Figure 2 As shown, the first bonding pad 50 penetrates the first bonding layer 20 and extends into the first substrate 10.

[0053] The second semiconductor structure 102 includes a second substrate 40 and a second bonding layer 30 stacked together.

[0054] For example, the second substrate 40 may include a second substrate, a second circuit structure layer, etc., stacked together. The second circuit structure layer may include at least one conductive layer, at least one dielectric layer, etc.

[0055] The second semiconductor structure 102 also includes a second bonding pad 60. The second bonding pad 60 extends at least into the interior of the second bonding layer 30 in the direction from the second bonding layer 30 to the second substrate 40.

[0056] Understandably, the portion of the second bonding pad 60 near the first semiconductor structure 101 is used to achieve bonding between the first semiconductor structure 101 and the second semiconductor structure 102, and the portion of the second bonding pad 60 extending into the second bonding layer 30 is used to electrically connect with the second circuit structure layer in the second substrate 40 to achieve signal transmission.

[0057] Along the direction from the second bonding layer 30 to the second substrate 40, the size of the second bonding pad 60 can be selected and set according to actual conditions, and the embodiments of this disclosure do not limit this. For example, the second bonding pad 60 may penetrate a portion of the second bonding layer 30. Or, the second bonding pad 60 may penetrate the second bonding layer 30 and stop at the interface between the second substrate 40 and the second bonding layer 30. Or, as... Figure 2 As shown, the second bonding pad 60 penetrates the second bonding layer 30 and extends into the second substrate 40.

[0058] The orthographic projection of the first bonding pad 50 onto the first substrate 10 and the orthographic projection of the second bonding pad 60 onto the first substrate 10 at least partially overlap. The first bonding pad 50 and the second bonding pad 60 are bonded to each other.

[0059] For example, the boundary line of the orthographic projection of the first bonding pad 50 onto the first substrate 10 intersects the boundary line of the orthographic projection of the second bonding pad 60 onto the first substrate 10.

[0060] For example, the area of ​​the orthographic projection of the first bonding pad 50 on the first substrate 10 is smaller than the area of ​​the orthographic projection of the second bonding pad 60 on the first substrate 10, and the boundary line of the orthographic projection of the first bonding pad 50 on the first substrate 10 is located inside the boundary line of the orthographic projection of the second bonding pad 60 on the first substrate 10.

[0061] For example, the area of ​​the orthographic projection of the second bonding pad 60 on the first substrate 10 is smaller than the area of ​​the orthographic projection of the first bonding pad 50 on the first substrate 10, and the boundary line of the orthographic projection of the second bonding pad 60 on the first substrate 10 is located inside the boundary line of the orthographic projection of the first bonding pad 50 on the first substrate 10.

[0062] For example, the area of ​​the orthographic projection of the second bonding pad 60 on the first substrate 10 is equal to or approximately equal to the area of ​​the orthographic projection of the first bonding pad 50 on the first substrate 10, and the orthographic projection of the first bonding pad 50 on the first substrate 10 coincides with or approximately coincides with the orthographic projection of the second bonding pad 60 on the first substrate 10.

[0063] Thus, along the thickness direction of the first substrate 10, the first bonding pad 50 and the second bonding pad 60 are at least partially aligned, thereby facilitating the bonding and connection of the first bonding pad 50 and the second bonding pad 60.

[0064] In related technologies, such as Figure 5 As shown, in the first semiconductor structure, the first bonding layer 20 is made of silicon oxide, and in the second semiconductor structure, the second bonding layer 30' is made of silicon nitride. The first bonding pad 50 and the second bonding pad 60 are made of copper. The first bonding layer 20 and the second bonding layer 30' are bonded to each other, and the first bonding pad 50 and the second bonding pad 60 are bonded to each other. However, the bonding energy of the second bonding layer 30' is relatively small, resulting in a low bonding strength between the first and second semiconductor structures, which affects the performance of the semiconductor device. Furthermore, the material of the first bonding pad has a large diffusion coefficient in the first bonding layer, making it easy for the material of the first bonding pad to diffuse along the bonding interface between the first and second bonding layers into the first bonding layer, affecting the morphology of the first bonding pad and potentially causing short circuits between adjacent first bonding pads, thereby affecting the performance of the semiconductor device.

[0065] Based on this, such as Figures 2-4 As shown, the semiconductor device 100 provided in the embodiments of this disclosure further includes a third bonding layer 90. The third bonding layer 90 is located between the first bonding layer 20 and the second bonding layer 30.

[0066] For example, one of the first bonding pad 50 and the second bonding pad 60 passes through at least a portion of the third bonding layer 90 and is bonded to the other of the first bonding pad 50 and the second bonding pad 60.

[0067] For example, the first bonding pad 50 extends into the interior of the third bonding layer 90 and bonds with the second bonding pad 60. Or, as... Figure 4 As shown, the first bonding pad 50 penetrates the third bonding layer 90 and is bonded to the second bonding pad 60.

[0068] For example, the second bonding pad 60 extends into the interior of the third bonding layer 90 and bonds with the first bonding pad 50. Or, as... Figure 3 As shown, the second bonding pad 60 penetrates the third bonding layer 90 and is bonded to the first bonding pad 50.

[0069] For example, such as Figure 2 As shown, the first bonding pad 50 extends into the interior of the third bonding layer 90, and the second bonding pad 60 extends into the interior of the third bonding layer 90. The first bonding pad 50 and the second bonding pad 60 are bonded together.

[0070] The bonding energy of the third bonding layer 90 is greater than that of the first bonding layer 20 and also greater than that of the second bonding layer 30.

[0071] Therefore, the first semiconductor structure 101 and the second semiconductor structure 102 can be bonded using the third bonding layer 90, thereby improving the bonding energy between the first semiconductor structure 101 and the second semiconductor structure 102 and improving the performance of the semiconductor device 100.

[0072] For example, the diffusion coefficient of the material of the first bonding pad 50 in the first bonding layer 20 is less than the diffusion coefficient of the material of the first bonding pad 50 in the third bonding layer 90. The diffusion coefficient of the material of the second bonding pad 60 in the second bonding layer 30 is less than the diffusion coefficient of the material of the second bonding pad 60 in the third bonding layer 90.

[0073] Therefore, the material of the first bonding pad 50 has a small diffusion coefficient in the first bonding layer 20, and the material of the first bonding pad 50 is not easily diffused in the first bonding layer 20. Similarly, the material of the second bonding pad 60 has a small diffusion coefficient in the second bonding layer 30, and the material of the second bonding pad 60 is not easily diffused in the second bonding layer 30. This can protect the morphology of the first bonding pad 50, which is beneficial to improving the performance of the semiconductor device 100. It also prevents the diffusion of the material of the first bonding pad 50 from causing short circuits between adjacent first bonding pads 50, and prevents the diffusion of the material of the second bonding pad 60 from causing short circuits between adjacent second bonding pads 60.

[0074] The semiconductor device 100 provided in the embodiments of this disclosure provides a third bonding layer 90 between the first bonding layer 20 of the first semiconductor structure 101 and the second bonding layer 30 of the second semiconductor structure 102. One of the first bonding pad 50 and the second bonding pad 60 passes through at least a portion of the third bonding layer 90 and bonds with the other. Furthermore, the bonding energy of the third bonding layer 90 is greater than the bonding energy of the first bonding layer 20 and greater than the bonding energy of the second bonding layer 30. This ensures the bonding stability between the first semiconductor structure 101 and the second semiconductor structure 102 and improves the performance of the semiconductor device 100. Meanwhile, the material of the first bonding pad 50 has a relatively small diffusion coefficient in the first bonding layer 20, making it difficult for the material of the first bonding pad 50 to diffuse in the first bonding layer 20. The material of the second bonding pad 60 has a relatively small diffusion coefficient in the second bonding layer 30, making it difficult for the material of the second bonding pad 60 to diffuse in the second bonding layer 30. This can protect the morphology of the first bonding pad 50 and the second bonding pad 60, which is beneficial to improving the performance of the semiconductor device 100, avoiding short circuits between adjacent first bonding pads 50 due to the diffusion of the material of the first bonding pad 50, and avoiding short circuits between adjacent second bonding pads 60 due to the diffusion of the material of the second bonding pad 60.

[0075] For example, such as Figure 3 As shown, the thickness of the third bonding layer 90 is less than the thickness of the first bonding layer 20 and less than the thickness of the second bonding layer 30.

[0076] This allows for a smaller thickness of the third bonding layer 90, which is beneficial for achieving a thinner and lighter design of the semiconductor device 100.

[0077] It is understood that there are various structures for the third bonding layer 90, which can be configured as needed, and the embodiments disclosed herein do not limit this.

[0078] In some embodiments, such as Figure 2 As shown, the third bonding layer 90 includes a first sublayer 91 and a second sublayer 92 stacked together. The first sublayer 91 is located between the second sublayer 92 and the first bonding layer 20, and the first sublayer 91 surrounds the first bonding pad 50, while the second sublayer 92 surrounds the second bonding pad 60.

[0079] Therefore, the bonding of the first sublayer 91 and the second sublayer 92 can be used to achieve the bonding of the first semiconductor structure 101 and the second semiconductor structure 102. Since the bonding energy of the third bonding layer 90 is high, the bonding energy of the first sublayer 91 and the second sublayer 92 is also high, thereby improving the bonding strength of the first semiconductor structure 101 and the second semiconductor structure 102 and improving the performance of the semiconductor device 100.

[0080] For example, such as Figure 2 As shown, the thickness of the first sublayer 91 is less than the thickness of the first bonding layer 20, and the thickness of the second sublayer 92 is less than the thickness of the second bonding layer 30.

[0081] For example, the thickness of the first sublayer 91 can be much smaller than the thickness of the first bonding layer 20, and the thickness ratio between the two can be approximately 1:100.

[0082] Therefore, the thickness of the first sublayer 91 can be reduced, resulting in less space for the diffusion of the material of the first bonding pad 50 within the first sublayer 91. This reduces the adverse effects of the diffusion of the material of the first bonding pad 50 within the first sublayer 91 on the morphology of the first bonding pad 50, thereby protecting the morphology of the first bonding pad 50. Similarly, the reduced thickness of the second sublayer 92 can also reduce the adverse effects of the diffusion of the material of the second bonding pad 60 within the second sublayer 92 on the morphology of the second bonding pad 60, thereby protecting the morphology of the second bonding pad 60.

[0083] In some examples, the thickness range of the first sublayer 91 includes The thickness range of the second sublayer 92 includes

[0084] For example, the thickness range of the first sublayer 91 can be... or

[0085] For example, the thickness of the first sublayer 91 can be or

[0086] For example, the thickness range of the second sublayer 92 can be... or

[0087] For example, the thickness of the first sublayer 91 can be or

[0088] For example, the thickness of the first sublayer 91 may be equal to or unequal to the thickness of the second sublayer 92.

[0089] In some examples, the material of the first sublayer 91 includes silicon oxide, and the material of the second sublayer 92 includes silicon oxide or silicon oxynitride.

[0090] This allows for a larger bonding energy between the first sublayer 91 and the second sublayer 92, which is beneficial for improving the bonding strength between the first semiconductor structure 101 and the second semiconductor structure 102, thereby enhancing the performance of the semiconductor device 100.

[0091] In some examples, such as Figure 2 As shown, the first bonding pad 50 includes a first conductive pattern 51 and a first bonding pattern 52 stacked along the thickness direction of the first bonding layer 20, and the second bonding pad 60 includes a second conductive pattern 61 and a second bonding pattern 62 stacked along the thickness direction of the first bonding layer 20.

[0092] The first bonding pattern 52 and the second bonding pattern 62 are located between the first conductive pattern 51 and the second conductive pattern 61, and are bonded to each other. Thus, the bonding between the first bonding pad 50 and the second bonding pad 60 is achieved.

[0093] For example, the first conductive pattern 51 extends at least into the interior of the first bonding layer 20. At least a portion of the first bonding pattern 52 extends into the first sublayer 91.

[0094] For example, the second conductive pattern 61 extends at least into the interior of the second bonding layer 30. At least a portion of the second bonding pattern 62 extends into the second sublayer 92.

[0095] In other examples, such as Figure 15 As shown, a portion of the first bonding pad 50 is located within the first sublayer 91, and a portion of the second bonding pattern 62 is located within the second sublayer 92. The first bonding pad 50 and the second bonding pad 60 are bonded within the third bonding layer 90.

[0096] In some other examples, such as Figure 16As shown, the first bonding pad 50 includes a first conductive pattern 51 and a first bonding pattern 52 stacked along the thickness direction of the first bonding layer 20. A portion of the first bonding pattern 52 is located within the first sub-layer 91, and a portion of the second bonding pad 60 is located within the second sub-layer 92. The first bonding pattern 52 and the second bonding pad 60 are bonded together.

[0097] In some other examples, such as Figure 17 As shown, the second bonding pad 60 includes a second conductive pattern 61 and a second bonding pattern 62 stacked along the thickness direction of the first bonding layer 20. A portion of the second bonding pattern 62 is located within the second sub-layer 92, and a portion of the first bonding pad 50 is located within the first sub-layer 91. The second bonding pattern 62 and the first bonding pad 50 are bonded together.

[0098] In another embodiment, such as Figure 3 and Figure 4 As shown, the third bonding layer 90 is a single-layer structure. The material of the third bonding layer 90 includes silicon oxide or silicon oxynitride.

[0099] For example, the thickness range of the third bonding layer 90 includes

[0100] For example, the thickness of the third bonding layer 90 can be or

[0101] In some examples, such as Figure 4 As shown, the first bonding pad 50 penetrates the third bonding layer 90. The first bonding pad 50 includes a first conductive pattern 51 and a first bonding pattern 52 stacked along the thickness direction of the first bonding layer 20. The first bonding pattern 52 is located between the first conductive pattern 51 and the second bonding pad 60, and is bonded to the second bonding pad 60.

[0102] The setting of the first bonding pattern 52 facilitates the bonding of the first bonding pad 50 and the second bonding pad 60.

[0103] In other examples, such as Figure 3 As shown, the second bonding pad 60 penetrates the third bonding layer 90. The second bonding pad 60 includes a second conductive pattern 61 and a second bonding pattern 62 stacked along the thickness direction of the first bonding layer 20. The second bonding pattern 62 is located between the second conductive pattern 61 and the first bonding pad 50, and is bonded to the first bonding pad 50.

[0104] The setting of the second bonding pattern 62 facilitates the bonding of the first bonding pad 50 and the second bonding pad 60.

[0105] In some examples, the material of the first bonding layer 20 includes silicon oxynitride, and the material of the second bonding layer 30 includes silicon nitride.

[0106] Therefore, it can be ensured that the diffusion coefficient of the first bonding pad 50 in the first bonding layer 20 is relatively small, mitigating or even avoiding the diffusion of the material of the first bonding pad 50 in the first bonding layer 20, thus not affecting the morphology of the first bonding pad 50. It can also be ensured that the diffusion coefficient of the second bonding pad 60 in the second bonding layer 30 is relatively small, mitigating or even avoiding the diffusion of the material of the second bonding pad 60 in the second bonding layer 30, thus not affecting the morphology of the second bonding pad 60, thereby improving the performance of the semiconductor device 100.

[0107] For example, the materials of the first bonding pad 50 and the second bonding pad 60 can be conductive materials, such as metal materials.

[0108] For example, the material of the first bonding pad 50 and the material of the second bonding pad 60 can be the same, for example, both of them are copper.

[0109] For example, when the material of the first bonding pad 50 includes a first conductive pattern 51 and a first bonding pattern 52, the material of the first conductive pattern 51 can be copper, and the material of the first bonding pattern 52 can be copper oxide. When the material of the second bonding pad 60 includes a second conductive pattern 61 and a second bonding pattern 62, the material of the second conductive pattern 61 can be copper, and the material of the second bonding pattern 62 can be copper oxide.

[0110] In some examples, such as Figures 2-5 As shown, the first semiconductor structure 101 further includes a first barrier layer 70, which covers the side of the first bonding pad 50.

[0111] The first barrier layer 70 does not cover the surface of the first bonding pad 50 away from the second substrate 40. The surface of the first bonding pad 50 away from the second substrate 40 can be connected to the circuit structure layer or the like within the first substrate 10 to enable signal transmission.

[0112] The second semiconductor structure 102 also includes a second barrier layer 80 that covers the side of the second bonding pad 60.

[0113] The second barrier layer 80 does not cover the surface of the second bonding pad 60 away from the first substrate 10. The surface of the second bonding pad 60 away from the first substrate 10 can be connected to the circuit structure layer, etc., within the second substrate 40 to achieve signal transmission.

[0114] Therefore, during the bonding process of the first semiconductor structure 101 and the second semiconductor structure 102, the first barrier layer 70 can be used to block the diffusion of material from the first bonding pad 50, thereby protecting the morphology of the side surface of the first bonding pad 50, improving the yield of the semiconductor device 100, and preventing the material of the first bonding pad 50 from diffusing into the first bonding layer 20 and the first substrate 10 through the first barrier layer 70, thus preventing short circuits between the first bonding pad 50 and another adjacent first bonding pad 50. Similarly, the second barrier layer 80 can be used to block the diffusion of material from the second bonding pad 60, thereby protecting the morphology of the side surface of the second bonding pad 60 and improving the yield of the semiconductor device 100.

[0115] For example, the materials of the first barrier layer 70 and the second barrier layer 80 may be the same or different.

[0116] For example, if the materials of the first barrier layer 70 and the second barrier layer 80 are the same, the material of the first barrier layer 70 may include tantalum nitride and tantalum, and the material of the second barrier layer 80 may also include tantalum nitride and tantalum.

[0117] Some embodiments of this disclosure also provide a method for fabricating a semiconductor device 100, which is used to fabricate the semiconductor device 100 described in any of the above embodiments. Specifically, as Figure 6 As shown, the preparation method includes: A100 to A300.

[0118] A100, such as Figure 12 As shown, a first semiconductor structure 101 and a second semiconductor structure 102 are provided. The first semiconductor structure 101 includes a first bonding pad 50 and a first substrate 10 and a first bonding layer 20 stacked thereon. Along the direction from the first bonding layer 20 to the first substrate 10, the first bonding pad 50 extends at least into the interior of the first bonding layer 20. The second semiconductor structure 102 includes a second bonding pad 60 and a second substrate 40 and a second bonding layer 30 stacked thereon. Along the direction from the second bonding layer 30 to the second substrate 40, the second bonding pad 60 extends at least into the interior of the second bonding layer 30.

[0119] For a description of the first semiconductor structure 101 and the second semiconductor structure 102, please refer to the description in some of the embodiments of this disclosure above, which will not be repeated here.

[0120] A200, such as Figure 13 As shown, a third bonding layer 90 is formed. The third bonding layer 90 is located on the first bonding layer 20 and / or the second bonding layer 30. The bonding energy of the third bonding layer 90 is greater than the bonding energy of the first bonding layer 20 and greater than the bonding energy of the second bonding layer 30.

[0121] For example, a plasma vapor deposition process can be used to form the third bonding layer 90. The material of the third bonding layer 90 can be silicon oxide and / or silicon oxynitride.

[0122] For example, the third bonding layer 90 has a layered structure.

[0123] For example, the third bonding layer 90 is located on the first bonding layer 20. Or, the third bonding layer 90 is located on the second bonding layer 30. Or, as... Figure 13 As shown, the third bonding layer 90 includes a first sublayer 91 and a second sublayer 92, wherein the first sublayer 91 is located on the first bonding layer 20 and the second sublayer 92 is located on the second bonding layer 30.

[0124] A300, such as Figure 15 As shown, a first semiconductor structure 101 and a second semiconductor structure 102 are bonded together. A third bonding layer 90 is located between the first bonding layer 20 and the second bonding layer 30. The orthographic projection of the first bonding pad 50 onto the first substrate 10 at least partially overlaps with the orthographic projection of the second bonding pad 60 onto the first substrate 10. One of the first bonding pad 50 and the second bonding pad 60 passes through at least a portion of the third bonding layer 90 and is bonded to the other of the first bonding pad 50 and the second bonding pad 60. The diffusion coefficient of the material of the first bonding pad 50 in the first bonding layer 20 is less than the diffusion coefficient of the material of the first bonding pad 50 in the third bonding layer 90. And / or, the diffusion coefficient of the material of the second bonding pad 60 in the second bonding layer 30 is less than the diffusion coefficient of the material of the second bonding pad 60 in the third bonding layer 90.

[0125] The bonded first semiconductor structure 101 and second semiconductor structure 102 constitute the aforementioned semiconductor device 100.

[0126] Taking the third bonding layer 90 located on the first bonding layer 20 as an example, during the bonding process of the first semiconductor structure 101 and the second semiconductor structure 102, the third bonding layer 90 is bonded to the second bonding layer 30, and the first bonding pad 50 and the second bonding pad 60 are bonded to each other. Since the bonding energy of the third bonding layer 90 is greater than that of the first bonding layer 20, the bonding between the first semiconductor structure 101 and the second semiconductor structure 102 is achieved by using the bonding between the third bonding layer 90 and the second bonding layer 30, rather than the bonding between the first bonding layer 20 and the second bonding layer 30. This improves the bonding strength between the first semiconductor structure 101 and the second semiconductor structure 102, thereby enhancing the performance of the semiconductor device 100.

[0127] The method for fabricating a semiconductor device 100 provided in the embodiments of this disclosure involves forming a third bonding layer 90 on the first bonding layer 20 and / or the second bonding layer 30, setting the bonding energy of the third bonding layer 90 to be greater than the bonding energy of the first bonding layer 20 and the second bonding layer 30, and using the third bonding layer 90 to achieve bonding between the first semiconductor structure 101 and the second semiconductor structure 102, thereby improving the bonding strength between the first semiconductor structure 101 and the second semiconductor structure 102 and improving the performance of the semiconductor device 100. Furthermore, one of the first bonding pad 50 and the second bonding pad 60 is configured to pass through at least a portion of the third bonding layer 90 and bond to the other. The diffusion coefficient of the material of the first bonding pad 50 in the first bonding layer 20 is less than its diffusion coefficient in the third bonding layer 90, and the diffusion coefficient of the material of the second bonding pad 60 in the second bonding layer 30 is less than its diffusion coefficient in the third bonding layer 90. This makes the first bonding layer 20 more effective at blocking the diffusion of the material of the first bonding pad 50, and the second bonding layer 30 more effective at blocking the diffusion of the material of the second bonding pad 60. This protects the morphology of the first bonding pad 50 and the second bonding pad 60, avoids short circuits caused by the diffusion of material between adjacent first bonding pads 50 (or second bonding pads 60), and thus improves the yield of the semiconductor device 100.

[0128] For example, the fabrication process of the first semiconductor structure 101 may include: as follows Figure 7 As shown in (a), a first substrate 10 is provided; a first bonding layer 20 is formed on the first substrate 10 using a deposition process; as shown in (a), a first bonding layer 20 is formed on the first substrate 10. Figure 8 As shown in (a), a first via 93 is formed by dry etching, extending at least into the interior of the first bonding layer 20; as Figure 9 As shown in (a), a first barrier film 71 is formed within the first via 93 and on the first bonding layer 20 using physical vapor deposition (PVD). Figure 10 As shown in (a), the portion of the first barrier film 71 located on the bottom wall of the first via 93 is removed using photolithography; as shown in (a). Figure 11 As shown in (a), an electroplating process is used to form a first conductive film 53 on the first barrier film 71 and on the bottom wall of the first via 93; as shown in (a), a first conductive film 53 is formed on the first barrier film 71 and on the bottom wall of the first via 93; Figure 12 As shown in (a), a chemical mechanical polishing (CMP) process is used to remove the portion of the first conductive film 53 located on the first bonding layer 20, while retaining the portion of the first conductive film 53 located within the first via 93, forming the first bonding pad 50. Simultaneously, the portion of the first barrier film 71 located on the first bonding layer 20 is removed, while retaining the portion of the first barrier film 71 located within the first via 93, forming the first barrier layer 70.

[0129] The fabrication process of the second semiconductor structure 102 is similar to the fabrication process of the first semiconductor structure 101 described above. Specifically, as follows: Figure 7 As shown in (b), a second substrate 40 is provided; a second bonding layer 30 is formed on the second substrate 40 using a deposition process; as shown in (b). Figure 8 As shown in (b), a dry etching process is used to form a second via 94 that extends at least into the interior of the second bonding layer 30; as Figure 9 As shown in (b), a second barrier film 81 is formed within the second via 94 and on the second bonding layer 30 using physical vapor deposition (PVD). Figure 10 As shown in (b), the portion of the second barrier film 81 located on the bottom wall of the second via 94 is removed using photolithography; as shown Figure 11 As shown in (b), an electroplating process is used to form a second conductive film 63 on the second barrier film 81 and on the bottom wall of the second via 94; Figure 12 As shown in (b), a chemical mechanical polishing (CMP) process is used to remove the portion of the second conductive film 63 located on the second bonding layer 30, while retaining the portion of the second conductive film 63 located within the second via 94, forming the second bonding pad 60. Simultaneously, the portion of the second barrier film 81 located on the second bonding layer 30 is removed, while retaining the portion of the second barrier film 81 located within the second via 94, forming the second barrier layer 80.

[0130] Understandable, Figure 7 (a) Figure 8 (a) Figure 9 (a) Figure 10 (a) Figure 11 (a) Figure 12 Figure (a) shows the structure of the first semiconductor structure 101 in different fabrication processes. Figure 7 (b) Figure 8 (b) Figure 9 (b) Figure 10 (b) Figure 11 (b) Figure 12 Figure (b) shows the structure of the second semiconductor structure 102 in different fabrication processes.

[0131] In some examples, such as Figure 13In (a), the third bonding layer 90 is located on the first bonding layer 20. In the above A200, forming the third bonding layer 90 includes: using a first target gas to process the surface of the first bonding layer 20 away from the first substrate 10 to form the third bonding layer 90, and simultaneously processing the surface of the first bonding pad 50 away from the first substrate 10 to form the first bonding pattern 52.

[0132] For example, a plasma vapor deposition process is used to form a third bonding layer 90 and a first bonding pattern 52.

[0133] For example, the surface of the first bonding pad 50 away from the first substrate 10 can be treated with an oxidation process. Taking copper as an example, after the above oxidation process, copper oxide is formed, which is the first bonding pattern 52.

[0134] The surface of the first bonding pattern 52 away from the first substrate 10 and the surface of the third bonding layer 90 away from the first substrate 10 may be flush or not flush.

[0135] For example, after forming the first bonding pattern 52, the first bonding pattern 52 can be bonded to the second bonding pad 60 (see reference). Figure 4 The third bonding layer 90 and the second bonding layer 30 are bonded together to realize the bonding between the first semiconductor structure 101 and the second semiconductor structure 102.

[0136] It should be noted that, because the thickness of the third bonding layer 90 and the thickness of the first bonding pattern 52 are relatively small, the overall thickness of the first bonding pad 50 increases. However, during the formation of the third bonding layer 90, the dimensions of the first barrier layer 70 along the thickness direction of the first substrate 10 remain almost unchanged. Therefore, in Figure 13 In the schematic diagram, some sides of the first bonding pattern 52 are not covered by the first barrier layer 70, and similarly, some sides of the second bonding pattern 62 are not covered by the second barrier layer 80.

[0137] It is understandable that after the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, the signal delay phenomenon between the first bonding pad 50 and the second bonding pad 60 in the semiconductor device 100 can be detected to see if it is within an acceptable range.

[0138] When the signal delay between the first bonding pad 50 and the second bonding pad 60 is severe and within an unacceptable range, in the aforementioned A300, before bonding the first semiconductor structure 101 and the second semiconductor structure 102, as follows... Figure 14 As shown in (a), the preparation method further includes: using a second target gas to reduce the first bonding pattern 52.

[0139] For example, the material of the first bonding pattern 52 is copper oxide. After being reduced by the second target gas, the copper oxide is reduced to copper. The first bonding pad 50 contains only the first conductive pattern 51 made of copper.

[0140] This results in lower resistance in the first bonding pad 50, less signal transmission loss between the first bonding pad 50 and the second bonding pad 60, which helps improve the accuracy of signal transmission between the first bonding pad 50 and the second bonding pad 60, and also reduces signal delay between the first bonding pad 50 and the second bonding pad 60, thereby improving the yield and performance of the semiconductor device 100.

[0141] It should be noted that, because the thickness of the first bonding pattern 52 is relatively small, after its restoration, the overall thickness of the first bonding pad 50 is reduced, causing the top surface of the first bonding pad 50 to be slightly lower than the top surface of the first bonding layer 20. Therefore, in Figure 14 In the schematic diagram, the top surface of the first bonding pad 50 is not flush with the top surface of the first bonding layer 20, and correspondingly, the top surface of the second bonding pad 60 is not flush with the top surface of the second bonding layer 30.

[0142] In other examples, such as Figure 13 In (b), the third bonding layer 90 is located on the second bonding layer 30. In the above A200, forming the third bonding layer 90 includes: using a first target gas to process the surface of the second bonding layer 30 on the side away from the second substrate 40 to form the third bonding layer 90, and simultaneously processing the surface of the second bonding pad 60 on the side away from the second substrate 40 to form the second bonding pattern 62.

[0143] For example, a third bonding layer 90 and a second bonding pattern 62 are formed using a plasma vapor deposition process.

[0144] For example, the surface of the second bonding pad 60 on the side away from the second substrate 40 can be treated with an oxidation process. Taking copper as an example, after oxidation treatment, copper oxide is formed, which is the second bonding pattern 62.

[0145] The surface of the second bonding pattern 62 away from the second substrate 40 and the surface of the third bonding layer 90 away from the second substrate 40 may be flush or not flush.

[0146] For example, after forming the second bonding pattern 62, the second bonding pattern 62 can be bonded to the first bonding pad 50 (see reference). Figure 3 The third bonding layer 90 and the first bonding layer 20 are bonded together to achieve the bonding of the first semiconductor structure 101 and the second semiconductor structure 102.

[0147] For example, in the above A300, the third bonding layer 90 is located on the second bonding layer 30, before the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, as... Figure 14 As shown in (b), the preparation method further includes: reducing the second bonding pattern 62 using a second target gas.

[0148] For example, the material of the second bonding pattern 62 is copper oxide. After being reduced by the second target gas, the copper oxide is reduced to copper. The second bonding pad 60 contains only the second conductive pattern 61 made of copper.

[0149] This results in lower resistance in the second bonding pad 60, reducing signal transmission loss between the first bonding pad 50 and the second bonding pad 60. This improves the accuracy of signal transmission between the first bonding pad 50 and the second bonding pad 60, and also reduces signal delay between the first bonding pad 50 and the second bonding pad 60, thereby improving the yield and performance of the semiconductor device 100.

[0150] In some examples, such as Figure 13 As shown, the third bonding layer 90 includes a first sublayer 91 and a second sublayer 92. The first sublayer 91 is located on the first bonding layer 20, and the second sublayer 92 is located on the second bonding layer 30.

[0151] In the aforementioned A200, the formation of the third bonding layer 90 includes:

[0152] Using a first target gas, the surface of the first bonding layer 20 away from the first substrate 10 is processed to form a first sublayer 91. Simultaneously, the surface of the first bonding pad 50 away from the first substrate 10 is processed to form a first bonding pattern 52. The first sublayer 91 surrounds the first bonding pattern 52.

[0153] Using a first target gas, the surface of the second bonding layer 30 away from the second substrate 40 is treated to form a second sublayer 92. Simultaneously, the surface of the second bonding pad 60 away from the second substrate 40 is treated to form a second bonding pattern 62. The second sublayer 92 surrounds the second bonding pattern 62.

[0154] For example, plasma vapor deposition is used to form the first sublayer 91, the second sublayer 92, the first bonding pattern 52, and the second bonding pattern 62.

[0155] For example, after forming the first bonding pattern 52 and the second bonding pattern 62, the second bonding pattern 62 can be bonded to the first bonding pattern 52 (see reference). Figure 18 and Figure 2 The first sublayer 91 and the second sublayer 92 are bonded together to achieve the bonding of the first semiconductor structure 101 and the second semiconductor structure 102.

[0156] For example, before bonding the first semiconductor structure 101 to the second semiconductor structure 102, such as Figure 14 As shown, the preparation method of the above A300 further includes: using a second target gas to reduce the first bonding pattern 52 and / or the second bonding pattern 62.

[0157] For example, only the first bonding pattern 52 (or the second bonding pattern 62) can be restored (see reference). Figure 16 or Figure 17 For example, both the first bonding pattern 52 and the second bonding pattern 62 can be restored (see reference). Figure 15 ).

[0158] After bonding the first semiconductor structure 101 and the second semiconductor structure 102, an annealing process can be used to anneal the semiconductor device 100.

[0159] In some examples, the first target gas mentioned above includes oxidizing gases, such as nitrous oxide.

[0160] Nitric oxide, also known as laughing gas, has strong oxidizing properties. Therefore, the third bonding layer 90 formed using the first target gas can be ensured to have a high bonding energy, thereby improving the bonding strength between the first semiconductor structure 101 and the second semiconductor structure 102, and enhancing the performance of the semiconductor device 100.

[0161] In some examples, the second target gas includes reducing gases, such as ammonia or hydrogen.

[0162] This allows for the restoration of the first bonding pattern 52 or the second bonding pattern 62, resulting in a lower resistance in the first bonding pad 50 or the second bonding pad 60, which in turn helps improve the performance of the semiconductor device 100.

[0163] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a first semiconductor structure, a third bonding layer, and a second semiconductor structure stacked together; The first semiconductor structure includes a first bonding pad and a first substrate and a first bonding layer stacked thereon; along the direction from the first bonding layer to the first substrate, the first bonding pad extends at least into the interior of the first bonding layer; The second semiconductor structure includes a second bonding pad and a second substrate and a second bonding layer stacked together; the second bonding pad extends at least into the interior of the second bonding layer along the direction from the second bonding layer to the second substrate; the orthographic projection of the first bonding pad on the first substrate and the orthographic projection of the second bonding pad on the first substrate at least partially overlap; The third bonding layer is located between the first bonding layer and the second bonding layer; one of the first bonding pad and the second bonding pad passes through at least a portion of the third bonding layer and is bonded to the other of the first bonding pad and the second bonding pad; Wherein, the bonding energy of the third bonding layer is greater than the bonding energy of the first bonding layer and greater than the bonding energy of the second bonding layer; the diffusion coefficient of the material of the first bonding pad in the first bonding layer is less than the diffusion coefficient of the material of the first bonding pad in the third bonding layer; and / or, the diffusion coefficient of the material of the second bonding pad in the second bonding layer is less than the diffusion coefficient of the material of the second bonding pad in the third bonding layer.

2. The semiconductor device according to claim 1, characterized in that, The third bonding layer includes a first sub-layer and a second sub-layer stacked together; The first sublayer is located between the second sublayer and the first bonding layer, the first sublayer surrounds the first bonding pad, and the second sublayer surrounds the second bonding pad.

3. The semiconductor device according to claim 2, characterized in that, The thickness of the first sublayer is less than the thickness of the first bonding layer, and the thickness of the second sublayer is less than the thickness of the second bonding layer.

4. The semiconductor device according to claim 3, characterized in that, The thickness range of the first sublayer includes The thickness range of the second sublayer includes 5. The semiconductor device according to claim 2, characterized in that, The material of the first sublayer includes silicon oxide, and the material of the second sublayer includes silicon oxide or silicon oxynitride.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that, The first bonding pad includes a first conductive pattern and a first bonding pattern stacked along the thickness direction of the first bonding layer, and the second bonding pad includes a second conductive pattern and a second bonding pattern stacked along the thickness direction of the second bonding layer, wherein the first bonding pattern and the second bonding pattern are bonded to each other.

7. The semiconductor device according to claim 1, characterized in that, The first bonding pad penetrates the third bonding layer. The first bonding pad includes a first conductive pattern and a first bonding pattern stacked along the thickness direction of the first bonding layer. The first bonding pattern is bonded to the second bonding pad. Alternatively, the second bonding pad penetrates the third bonding layer, and the second bonding pad includes a second conductive pattern and a second bonding pattern stacked along the thickness direction of the second bonding layer, wherein the second bonding pattern is bonded to the first bonding pad.

8. The semiconductor device according to claim 1, characterized in that, The material of the first bonding layer includes silicon oxynitride, and the material of the second bonding layer includes silicon nitride.

9. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A first semiconductor structure and a second semiconductor structure are provided; the first semiconductor structure includes a first bonding pad and a first substrate and a first bonding layer stacked thereon; the first bonding pad extends at least into the interior of the first bonding layer along the direction from the first bonding layer to the first substrate; the second semiconductor structure includes a second bonding pad and a second substrate and a second bonding layer stacked thereon; the second bonding pad extends at least into the interior of the second bonding layer along the direction from the second bonding layer to the second substrate. A third bonding layer is formed; the third bonding layer is located on the first bonding layer and / or the second bonding layer; the bonding energy of the third bonding layer is greater than the bonding energy of the first bonding layer and greater than the bonding energy of the second bonding layer; The first semiconductor structure is bonded to the second semiconductor structure; the third bonding layer is located between the first bonding layer and the second bonding layer, and the orthographic projection of the first bonding pad on the first substrate and the orthographic projection of the second bonding pad on the first substrate at least partially overlap; one of the first bonding pad and the second bonding pad passes through at least a portion of the third bonding layer and is bonded to the other of the first bonding pad and the second bonding pad; the diffusion coefficient of the material of the first bonding pad in the first bonding layer is less than the diffusion coefficient of the material of the first bonding pad in the third bonding layer; and / or, the diffusion coefficient of the material of the second bonding pad in the second bonding layer is less than the diffusion coefficient of the material of the second bonding pad in the third bonding layer.

10. The preparation method according to claim 9, characterized in that, The third bonding layer is located on the first bonding layer; forming the third bonding layer includes: Using a first target gas, the surface of the first bonding layer away from the first substrate is processed to form the third bonding layer, and simultaneously the surface of the first bonding pad away from the first substrate is processed to form the first bonding pattern. or, The third bonding layer is located on the second bonding layer; forming the third bonding layer includes: Using a first target gas, the surface of the second bonding layer away from the second substrate is processed to form the third bonding layer, and simultaneously the surface of the second bonding pad away from the second substrate is processed to form the second bonding pattern.

11. The preparation method according to claim 10, characterized in that, The third bonding layer is located on the first bonding layer. Before bonding the first semiconductor structure to the second semiconductor structure, the preparation method further includes: using a second target gas to reduce the first bonding pattern. Alternatively, the third bonding layer is located on the second bonding layer. Before bonding the first semiconductor structure to the second semiconductor structure, the preparation method further includes: using a second target gas to reduce the second bonding pattern.

12. The preparation method according to claim 10, characterized in that, The third bonding layer includes a first sub-layer and a second sub-layer, wherein the first sub-layer is located on the first bonding layer and the second sub-layer is located on the second bonding layer; The formation of the third bonding layer includes: Using a first target gas, the surface of the first bonding layer away from the first substrate is treated to form the first sublayer; simultaneously, the surface of the first bonding pad away from the first substrate is treated to form the first bonding pattern; the first sublayer surrounds the first bonding pattern. Using the first target gas, the surface of the second bonding layer away from the second substrate is processed to form the second sublayer, and the surface of the second bonding pad away from the second substrate is processed simultaneously to form the second bonding pattern; the second sublayer surrounds the second bonding pattern.

13. The preparation method according to claim 12, characterized in that, Before bonding the first semiconductor structure to the second semiconductor structure, the preparation method further includes: using a second target gas to reduce the first bonding pattern and / or the second bonding pattern.

14. The preparation method according to any one of claims 10-13, characterized in that, The first target gas includes nitrous oxide.

15. The preparation method according to claim 11 or 13, characterized in that, The second target gas includes ammonia or hydrogen.

16. An electronic device, characterized in that, include: The semiconductor device as claimed in any one of claims 1 to 8, and the circuit board connected to the semiconductor device.

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