Photonic crystal surface emitting laser array and preparation method thereof

Abstract

The invention relates to a photonic crystal surface emitting laser array (PCSEL-array) and a preparation method thereof. The PCSEL-array is composed of a driving substrate and a plurality of laser units arranged on one side of the driving substrate in an array mode. Each laser unit comprises a bottom end electrode layer, a buffer layer, a first conducting layer, a light emitting layer, a second conducting layer, a photonic crystal layer and a top end electrode layer which are sequentially stacked from bottom to top, and the first conducting layer and the second conducting layer are respectively a p-conducting layer and an n-conducting layer. Wherein the light emitting layer at least comprises a first quantum dot active layer and a second quantum dot active layer, and the two quantum dot active layers are connected through a tunnel junction to form a multi-junction cascade structure. Besides, in the preparation method of the PCSEL-array, the processing of the whole epitaxial wafer with the multi-junction cascade structure can be completed only through one-time epitaxial growth, the process is more simplified, and the PCSEL-array can effectively improve the output power of the PCSEL device and expand the application field of the PCSEL device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor optoelectronic technology, in particular to a photonic crystal surface emitting laser array and a preparation method thereof. BACKGROUND

[0002] The photonic crystal surface emitting laser is different from the edge emitting laser and the vertical surface emitting laser, and has the advantages of high power, high reliability, small size, small beam divergence angle, high quality factor, etc., and is suitable for key fields such as high-definition display, medical treatment, and communication. The multi-junction cascade photonic crystal surface emitting laser refers to a photonic crystal laser containing multiple quantum dot active layers in the epitaxial structure design of the laser, and adjacent quantum dot active layers are separated by a tunnel junction. The multi-junction cascade technology can help realize high power and high internal quantum efficiency. However, for the quantum well active layer type laser, the weak carrier confinement capability and low injection efficiency in the active layer will significantly affect the output power and electro-optical conversion efficiency of the laser. In addition, the radiation recombination rate in the quantum well is low, so the non-radiation efficiency is usually high, which leads to high optoelectronic loss. SUMMARY

[0003] The present application provides a photonic surface emitting laser array and a preparation method thereof to solve the technical problems of weak carrier confinement capability and low injection efficiency in the quantum well active layer, and low radiation recombination rate in the quantum well in the surface laser emitter.

[0004] First aspect

[0005] The present application discloses a photonic crystal surface emitting laser array, comprising:

[0006] A driving substrate comprising a substrate and a metal bonding layer arranged on one side of the substrate;

[0007] A plurality of laser units are arranged on one side of the substrate in an array, and each laser unit comprises, in the light emitting direction, a bottom electrode layer, a buffer layer, a first conductive layer, a light emitting layer, a second conductive layer, a photonic crystal layer and a top electrode layer arranged in sequence, the bottom electrode layer is bonded to the metal bonding layer, and the first conductive layer and the second conductive layer are p-conductive layer and n-conductive layer respectively;

[0008] The light emitting layer comprises at least a first quantum dot active layer and a second quantum dot active layer, and the first quantum dot active layer and the second quantum dot active layer are connected by a tunnel junction layer to form a multi-junction cascade structure.

[0009] In one of the embodiments, the light emitting layer comprises two groups of p-cladding layers and n-cladding layers, and in the light emitting direction, one group of the p-cladding layers and the n-cladding layers are respectively stacked on opposite sides of the first quantum dot active layer, and the other group of the p-cladding layers and the n-cladding layers are respectively stacked on opposite sides of the second quantum dot active layer.

[0010] In one of the embodiments, the light emitting layer further comprises a p-doped layer and an n-doped layer, and in the light emitting direction, the p-doped layer and the n-doped layer are respectively stacked on opposite sides of the tunnel junction layer; wherein the p-doped layer is stacked with the p-cladding layer, and the n-doped layer is stacked with the n-cladding layer.

[0011] In one of the embodiments, the p-doped layer is embedded with a first oxidation limiting layer, and the first oxidation limiting layer extends radially inward from the side wall of the p-doped layer to form an annular state; and / or, the n-doped layer is embedded with a second oxidation limiting layer, and the second oxidation limiting layer extends radially inward from the side wall of the n-doped layer to form an annular state.

[0012] In one of the embodiments, the gap between any adjacent laser units forms an array channel, and the inner side wall and the bottom wall of the array channel are covered with an insulating layer, so that the current between any adjacent laser units is blocked by the insulating layer.

[0013] In one of the embodiments, each laser unit comprises an anti-reflection layer, and the anti-reflection layer is stacked with the top electrode layer on the upper surface of the second conductive layer, and the top electrode layer is arranged around the anti-reflection layer.

[0014] In one of the embodiments, the laser unit comprises a high reflection layer, and the high reflection layer is stacked between the buffer layer and the bottom electrode layer.

[0015] In one of the embodiments, the upper surface of the second conductive layer is recessed to form a plurality of spaced-apart crystal holes to form a cylindrical hole array, and the crystal holes are filled with air or silicon oxide medium to form the photonic crystal layer, and in the light emitting direction, the crystal holes are spaced apart from the upper surface of the light emitting layer; and the photonic crystal layer is embedded in the second conductive layer from top to bottom.

[0016] In one of the embodiments, the substrate is a conductive substrate, and the metal bonding layer is integrally formed on one side of the substrate.

[0017] Second aspect

[0018] The present application provides a preparation method of a photonic crystal surface emitting laser array, comprising the following steps:

[0019] S10, providing an epitaxial wafer with a multi-junction cascade structure, sequentially epitaxially growing a buffer layer, a first conductive layer, a light-emitting layer, a second conductive layer and a photonic crystal layer on a growth substrate; wherein the first conductive layer and the second conductive layer are respectively a p-conductive layer and an n-conductive layer;

[0020] S20, providing a driving substrate, the driving substrate comprising a substrate and a metal bonding layer provided on one side of the substrate;

[0021] S30, bonding the epitaxial wafer and the driving substrate, polishing the back surface of the epitaxial wafer to the buffer layer, depositing a bottom electrode layer on the thinned back surface of the epitaxial wafer to obtain a first processed body, bonding the first processed body to the substrate by using a metal bonding technology, bonding the bottom electrode layer to the metal bonding layer to obtain a second processed body of a photonic crystal laser;

[0022] S40, processing an array structure, etching a plurality of spaced array channels from top to bottom on the second processed body, the array channels extending from the upper surface of the second processed body to the upper surface of the metal bonding layer to obtain a third processed body;

[0023] S50, processing a top electrode layer, depositing a top electrode layer on the top layer of each unit of the third processed body, i.e. on the photonic crystal layer, to obtain a photonic crystal surface-emitting laser array,

[0024] wherein the light-emitting layer comprises at least a first quantum dot active layer and a second quantum dot active layer, and the first quantum dot active layer and the second quantum dot active layer are connected by a tunnel junction layer to form a multi-junction cascade structure, so that the prepared photonic crystal surface-emitting laser array is arranged by a plurality of laser unit arrays with the multi-junction cascade structure

[0025] In one embodiment, in step S10, a p-cladding layer and an n-cladding layer are respectively deposited on opposite sides of the first quantum dot active layer and opposite sides of the second quantum dot active layer; a p-doped layer and an n-doped layer are respectively deposited on opposite sides of the tunnel junction layer; wherein the p-doped layer and the p-cladding layer are deposited in a stack, and the n-doped layer and the n-cladding layer are deposited in a stack.

[0026] In one embodiment, in step S40, the corresponding p-doped layer sidewall in the array channel is subjected to oxidation etching, so that the p-doped layer forms a ring-shaped first oxidation limiting layer radially inward from the side; and / or, in step S40, the corresponding n-doped layer sidewall in the array channel is subjected to oxidation etching, so that the n-doped layer forms a ring-shaped second oxidation limiting layer radially inward from the side.

[0027] In one of the embodiments, a high reflection layer is grown on the back surface of the thinned epitaxial wafer before the bottom electrode layer is deposited in step S30, and the high reflection layer is stacked between the buffer layer and the bottom electrode layer.

[0028] In one of the embodiments, an epitaxial growth technique is used to grow an insulating layer on the inner sidewall and bottom wall of the array channel.

[0029] In one of the embodiments, the top electrode layer is processed into a ring shape, and an oxidation-resistant layer is deposited in the middle of the ring of the top electrode layer.

[0030] From the above technical solutions, the embodiments of the present application have at least the following advantages and positive effects:

[0031] The embodiment of the present application provides a photonic crystal surface emitting laser array (PCSEL-array) and a preparation method thereof. First, for the laser unit, the introduction of the quantum dot active region (first quantum dot active layer and second quantum dot active layer) effectively improves the quantum efficiency inside the active region. The tunnel junction layer as a connecting layer in the multi-junction cascade structure improves the output power and conversion efficiency of the laser unit. Further, the plurality of laser units are arranged in an array to form a PCSEL-array. Since the plurality of laser units simultaneously lase, the output power of the entire PCSEL-array can be greatly improved, which can improve or offset the negative effects of the weak carrier confinement ability, low injection efficiency, and high radiation recombination rate in the quantum well active layer of the laser unit, thereby reducing photoelectric loss and improving photoelectric efficiency. The PCSEL-array also helps to expand the application market of the PCSEL device in the industrial and consumer markets. In addition, in the preparation method of the PCSEL-array, the entire epitaxial wafer with a multi-junction cascade structure can be processed only once by epitaxial growth, and the process is more simplified and the processing cost is lower. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained from the structures shown in the drawings without creative labor.

[0033] Figure 1 It is a whole structure schematic diagram of the photonic crystal surface emitting laser array of an embodiment of the present application.

[0034] Figure 2 It is a whole structure schematic diagram of the photonic crystal surface emitting laser array of an embodiment of the present application. Figure 1Structure diagram of laser unit in the photonic crystal surface emitting laser array shown;

[0035] Figure 3 For Figure 1 Top view structure diagram of the photonic crystal surface emitting laser array shown;

[0036] Figure 4 For Figure 1 Preparation flow chart of the photonic crystal surface emitting laser array shown;

[0037] Figures 5-9 For Figure 1 Preparation step diagram of the photonic crystal surface emitting laser array shown.

[0038] The reference signs are explained as follows:

[0039] 1. Photonic crystal surface emitting laser array;

[0040] 10. Driving substrate; 11. Substrate; 12. Metal bonding layer;

[0041] 20. Laser unit; 21. Bottom electrode layer; 22. Buffer layer; 23. First conductive layer; 231. n-conductive layer; 24. Light emitting layer; 241. First quantum dot active layer; 242. Second quantum dot active layer; 243. Tunnel junction layer; 244. p-cladding layer; 245. n-cladding layer; 246. p-doped layer; 247. n-doped layer; 248. First oxidation confinement layer; 249. Second oxidation confinement layer; 25. Second conductive layer; 251. p-conductive layer; 26. Photonic crystal layer; 26a. Cylindrical hole array; 261. Crystal hole; 27. Top electrode layer; 27a. Circular electrode; 28. Anti-reflection layer; 29. High reflection layer; 291. Distributed Bragg reflector;

[0042] 30. Multi-junction cascade structure; 31. Two-junction cascade structure; 40. Array channel; 41. Insulating layer; 50. Epitaxial wafer; 51. Growth substrate; 61. First processing body; 62. Second processing body; 63. Third processing body. DETAILED DESCRIPTION

[0043] The typical embodiments embodying the features and advantages of the present application are specifically set forth in the following description. It should be understood, however, that the present application can be practiced in a variety of embodiments other than those specifically described, without departing from the scope of the present application. The following description and drawings are illustrative of the present application and are not to be construed as limiting the present application.

[0044] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as implying or suggesting relative importance or an indicated number of technical features. Thus, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0045] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "setting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0046] In combination with reference Figure 1 and Figure 2 The present application provides a photonic crystal surface emitting laser array 1 (PCSEL-array for short), which comprises a driving substrate 10 and a laser unit 20, the driving substrate 10 is provided with a driving circuit, the driving substrate 10 provides power supply and support function for the device, and the laser unit 20 serves as the light emitting main body, the number of the laser unit 20 is multiple and the array is arranged on one side of the driving substrate 10 to form an array light emitting structure. Here, the PCSEL-array 1 can be driven by the same pair of electrodes, and all the laser units 20 in the array are in parallel connection mode; of course, in other embodiments, different laser units 20 can also be driven by different electrode pairs.

[0047] The driving substrate 10 comprises a substrate 11 and a metal bonding layer 12 arranged on one side of the substrate 11, and the number of the laser units 20 is multiple and arranged in an array on one side of the substrate 11. In the light emitting direction, each laser unit 20 comprises, from bottom to top, a bottom electrode layer 21, a buffer layer 22, a first conductive layer 23, a light emitting layer 24, a second conductive layer 25, a photonic crystal layer 26 and a top electrode layer 27 arranged in sequence, the bottom electrode layer 21 is bonded to the metal bonding layer 12, and the first conductive layer 23 and the second conductive layer 25 are respectively p-conductive layer and n-conductive layer. It can be understood that the first conductive layer 23 is a p-conductive layer, and the second conductive layer 25 is an n-conductive layer; or the first conductive layer 23 is an n-conductive layer, and the second conductive layer 25 is a p-conductive layer.

[0048] The light-emitting layer 24 includes at least a first quantum dot active layer 241 and a second quantum dot active layer 242, and the first quantum dot active layer 241 and the second quantum dot active layer 242 are connected by a tunnel junction layer 243 to form a multi-junction cascade structure 30. Here, the introduction of the quantum dot active region effectively improves the quantum efficiency inside the active region, and the tunnel junction layer 243 as the connecting layer of the multi-junction cascade structure 30 improves the output power and conversion efficiency of the single laser unit 20. The first quantum dot active layer 241 and the second quantum dot active layer 242 contain quantum well or quantum dot structures and are the source of laser gain, and are usually located below the photonic crystal layer 26. It can be understood that the number of quantum dot active layers in the light-emitting layer 24 of the present application is at least two, and any two adjacent quantum dot active layers (i.e., the first quantum dot active layer 241 and the second quantum dot active layer 242) are connected by a tunnel junction layer 243. The adjacent two quantum dot active layers and the tunnel junction layer 243 therebetween serve as a cycle unit of the multi-junction cascade, so the present application takes the two-junction cascade structure 31 as a specific embodiment for description and explanation, and the remaining multi-junction cascade structure 30 can be clearly described. In addition, it should be understood that the number of cycle units in each laser unit 20 can be the same or different, for example, the laser unit 20 with the two-junction cascade structure 31 can also be arranged with the laser unit 20 with the multi-junction cascade structure 30 with 3 / 4 / 5 junctions on one side of the substrate 11 to form a PCSEL-array 1.

[0049] Optionally, referring to Figure 2 In an embodiment, in the two-junction cascade structure 31, the light-emitting layer 24 includes two groups of p-cladding layers 244 and n-cladding layers 245, and in the light-emitting direction, one group of p-cladding layers 244 and n-cladding layers 245 are respectively arranged on the opposite sides of the first quantum dot active layer 241, i.e., they are symmetric above and below the first quantum dot active layer 241, providing conductive and optical confinement functions. The other group of p-cladding layers 244 and n-cladding layers 245 are respectively arranged on the opposite sides of the second quantum dot active layer 242, i.e., they are symmetric above and below the second quantum dot active layer 242, providing conductive and optical confinement functions.

[0050] Optionally, referring to Figure 2In an embodiment, in the two-junction cascade structure 31, the light-out layer 24 further comprises a set of p-doped layers 246 and n-doped layers 247, which are stacked on opposite sides of the tunnel junction layer 243 in the light-out direction, respectively. The p-doped layers 246 are stacked with the p-cladding layer 244, and the n-doped layers 247 are stacked with the n-cladding layer 245. The p-doped layers 246 and the n-doped layers 247 are both high-concentration heavily doped layers, and are very thin, which provide power and energy for the tunnel junction layer 243. That is, the tunnel junction layer 243 is provided with sufficient field-assisted tunneling current with the thinnest thickness, the lowest absorption and the smallest voltage drop, while the polarity of the carriers is reversed, so that the P-type layer is moved to the back surface, and the front surface is provided with N-type transparent material for light-out.

[0051] Reference Figure 2 In a specific embodiment, the light-out layer 24 comprises, from bottom to top, the n-cladding layer 245, the first quantum dot active layer 241, the p-cladding layer 244, the p-doped layer 246, the tunnel junction layer 243, the n-doped layer 247, the n-cladding layer 245, the second quantum dot active layer 242, and the p-cladding layer 244, which are stacked in sequence. At this time, the second conductive layer 25 is the p-conductive layer 251, the top electrode layer 27 is the P-type metal electrode layer, the first conductive layer 23 is the n-conductive layer 231. It should be understood that, in the semiconductor device, the n-conductive layer 231, the n-cladding layer 245, and the n-doped layer 247 are all N-type doped layers, and their dopant concentrations can be the same or different. Therefore, in the present application, at least one of the n-cladding layer 245 and the n-doped layer 247 can be provided. Similarly, in the semiconductor device, the p-conductive layer 251, the p-cladding layer 244, and the p-doped layer 246 are all P-type doped layers, and their dopant concentrations can be the same or different. Therefore, in the present application, at least one of the p-cladding layer 244 and the p-doped layer 246 can be provided.

[0052] Preferably, continuing to refer to Figure 2In an embodiment, the p-doped layer 246 is embedded with a first oxidation confinement layer 248, which extends radially inward from the side wall of the p-doped layer 246 to form a ring shape, so as to form a circular current injection confinement layer in the middle of the p-doped layer 246, to provide the current localization capability, to achieve low threshold, single mode, and high power output. The n-doped layer 247 is embedded with a second oxidation confinement layer 249, which extends radially inward from the side wall of the n-doped layer 247 to form a ring shape, so as to form a circular current injection confinement layer in the middle of the n-doped layer 247, to provide the current localization capability, to achieve low threshold, single mode, and high power output. Of course, in other embodiments, the first oxidation confinement layer 248 or the second oxidation confinement layer 249 is not necessarily provided, and the tunnel junction layer 243 itself can improve the output power and conversion efficiency of the device.

[0053] Optionally, referring to Figure 1 In an embodiment, the gap between any two adjacent laser units 20 forms an array channel 40, and the inner side wall and the bottom wall of the array channel 40 are covered with an insulating layer 41, so that the current between any two adjacent laser units 20 is blocked by the insulating layer 41. The insulating layer 41 herein is a high-resistance, low-leakage, high-breakdown, and low-interface-state dielectric film, including but not limited to silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, and other passivation layers. In this embodiment, aluminum nitride is preferred, which can prevent the adjacent laser units 20 from leaking current between the array channels 40, and the high-thermal-conductivity insulating layer 41 can help to alleviate the heat accumulation in the light-emitting layer 24 of the laser unit 20, achieving the dual functions of insulation and heat dissipation. It should be understood that in other embodiments, the substrate 11 is made of a passivation or insulating material, and the metal bonding layer 12 is designed properly, so that the insulating layer 41 can not be provided.

[0054] Preferably, in combination with reference 1-3, in an embodiment, the laser unit 20 includes an anti-reflection layer 28, which is stacked together with the top electrode layer 27 on the upper surface of the second conductive layer 25, Figure 3 It is shown that the top electrode layer 27 is arranged around the anti-reflection layer 28 to form a circular electrode 27a. Here, the anti-reflection layer 28 is made of a material with low absorption and high transmission in the laser emission wavelength band, including but not limited to silicon oxide, aluminum oxide, and other materials, to reduce light reflection and improve transmission. Of course, in other embodiments, not every laser unit 20 needs to be provided with an anti-reflection layer 28.

[0055] Preferably, in combination with Figure 1 and Figure 2In an embodiment, the laser unit 20 comprises a high-reflection layer 29 stacked between the buffer layer 22 and the bottom electrode layer 21, which can enhance the vertical light feedback and improve the light efficiency of the whole laser unit 20. In addition, a high-reflection layer 29 can also be stacked on the top of the laser unit 20, and the two high-reflection layers 29 form a resonant cavity or microcavity structure to further improve the light efficiency through the microcavity effect. It should be understood that in other embodiments, the high-reflection layer 29 can also not be provided.

[0056] Optionally, in an embodiment, the high-reflection layer 29 comprises a distributed Bragg reflector 291 (DBR) composed of two different refractive index dielectric films stacked alternately, wherein the thickness of each dielectric film is 1 / 4 of the central wavelength, and the dielectric film combination preferably uses SiO2 / TiO2. According to the principle of thin film optics, the reflected light at the thin film interface of the target wavelength has the same phase and interferes with each other to enhance, thereby producing a higher reflectivity. Therefore, the design of the thickness of each dielectric film being 1 / 4 of the central wavelength can reduce the reflection loss of light on the distributed Bragg reflector 291 and improve the performance of the device. According to the principle of optical propagation, the optical thickness of a single dielectric film must be 1 / 4 of the central wavelength to reduce the loss to the maximum extent to improve the reflectivity and the quality of the resonant cavity. The reason why the dielectric film combination uses SiO2 / TiO2 is that the refractive index difference between SiO2 and TiO2 is large, which can easily obtain a higher reflectivity; both have small absorption to visible light, which helps to improve the light output power of the laser unit 20; the preparation process of the SiO2 / TiO2 dielectric film combination is mature, easy to obtain, and low in cost. Optionally, in other embodiments of the present application, the dielectric film combination can use SiO2 / TiO2 or SiO 2 / Ti2O5, or any of the dielectric film combinations of SiO2 / Ti3O5. In addition, optionally, in the present application, the high-reflection layer 29 can also use a metal mirror with high reflectivity.

[0057] Optionally, referring to Figure 2In an embodiment, the upper surface of the second conductive layer 25 is recessed to form a plurality of spaced-apart crystal holes 261 to form a cylindrical hole array 26a, and the crystal holes 261 are filled with air or silicon oxide medium to form a photonic crystal layer 26. In the light emission direction, the bottoms of the crystal holes 261 are spaced apart from the upper surface of the light emission layer 24. Here, the photonic crystal layer 26 is embedded in the second conductive layer 25 in the form of the cylindrical hole array 26a from top to bottom. Here, the cylindrical hole array 26a is a common and easy-to-process two-dimensional photonic crystal form in the art, and is the most intuitive and easy-to-implement way of the photonic crystal layer 26. Of course, in other embodiments, the photonic crystal layer 26 can also exist in the form of a dielectric column / dielectric rod array, a high-low refractive index film alternation (one-dimensional photonic crystal), a reverse column / opal structure, a solid-solid photonic crystal, and the like.

[0058] Optionally, in an embodiment, the substrate 11 is an electrically conductive plate, which can not only serve as a support layer of the PCSEL array 1, but also as a bottom electrode, which is conducive to current spreading. In this case, the metal bonding layer 12 can be integrally formed on one side of the substrate 11. Of course, in other embodiments, the substrate 10 can also be an insulating plate, and the metal bonding layer 12 needs to be additionally sputtered and deposited.

[0059] In a second aspect, in combination with reference to Figures 1-9 , the application also provides a preparation method of the PCSEL array 1. Taking the preparation of the PCSEL array 1 with a two-junction cascade structure 31 as an example, the method includes the following steps, as shown in Figure 4 :

[0060] S10, providing an epitaxial wafer 50 with a multi-junction cascade structure 30, and epitaxially growing a buffer layer 22, a first conductive layer 23, a light emission layer 24, a second conductive layer 25, and a photonic crystal layer 26 on a growth substrate 51 in sequence; wherein the first conductive layer 23 and the second conductive layer 25 are respectively a p-conductive layer and an n-conductive layer, and here, taking the first conductive layer 23 as an n-conductive layer and the second conductive layer 25 as a p-conductive layer as an example for further processing (as shown in Figure 5 ) ;

[0061] S20, providing a driving substrate 10, which includes a substrate 11 and a metal bonding layer 12 provided on one side of the substrate 11 (as shown in Figure 7 ) ;

[0062] S30, bonding the epitaxial wafer 50 and the driving substrate 10, polishing and thinning the back surface of the epitaxial wafer 50 to the buffer layer 22 (i.e., removing the growth substrate 51), depositing a bottom electrode layer 21 on the thinned back surface of the epitaxial wafer 50 to obtain a first processed body 61, and bonding the first processed body 61 to the substrate 11 by using a metal bonding technology to obtain a second processed body 62 (in combination with Figures 5-7 ) ;

[0063] S40, processing array structure, using dry etching technology, etching multiple spaced array channels 40 from the top of the second processed body 62 to the upper surface of the metal bonding layer 12, obtaining the third processed body 63 in array structure (combined with Figures 7-8 );

[0064] S50, processing top electrode layer 27, depositing top electrode layer 27 on the top layer of each unit structure in the third processed body 63, i.e. the photonic crystal layer 26, to obtain the PCSEL-array 1 (combined with Figure 9 );

[0065] Note that the first processed body 61, the second processed body 62 and the third processed body above are collectively referred to as the intermediate processed body.

[0066] Among them, the light-emitting layer 24 at least includes a first quantum dot active layer 241 and a second quantum dot active layer 242, and the two quantum dot active layers are connected by a tunnel junction layer 243 to form a multi-junction cascade structure 30, so that the prepared PCSEL-array 1 is arranged by a plurality of laser units 20 with a multi-junction cascade structure 30.

[0067] Optionally, referring to Figure 5 In step S10, electron beam lithography (EBL) is used to prepare for subsequent etching of the crystal holes 261 of the GaN photonic crystal layer 26 on the surface of the epitaxial wafer using photoresist as a mask. The thickness of the photoresist varies depending on the type of photoresist. In this example, the thickness of the EBL special photoresist is 200 nm. Then, using dry etching technology, the photoresist with a pattern formed in the previous step is used as a mask for GaN layer etching. The size of the crystal hole 261 is between 40 nm and 80 nm, and the bottom of the crystal hole 261 is spaced apart from the upper surface of the light-emitting layer 24 and the distance between the uppermost quantum dot active layer is about 100 nm-200 nm. It can be understood that the photonic crystal layer 26 is in the form of a cylindrical hole array 26a arranged in the form of multiple spaced crystal holes 261, and the silicon oxide can be deposited in the crystal holes 261 by plasma enhanced chemical vapor deposition (PECVD) method. Of course, in other embodiments, air can also be directly filled in the crystal holes 261. In addition, the GaN layer here is the second conductive layer 25 described above, which can be p-GaN or n-GaN, and the photonic crystal layer 26 is embedded in the second conductive layer 25 from top to bottom.

[0068] Optionally, in combination with reference to Figure 2 and Figure 5In step S10, p-cladding layer 244 and n-cladding layer 245 are deposited on opposite sides of first quantum dot active layer 241 and on opposite sides of second quantum dot active layer 242 respectively; p-doped layer 246 and n-doped layer 247 are deposited on opposite sides of tunnel junction layer 243 respectively. Here, p-doped layer 246 is deposited on p-cladding layer 244, and n-doped layer 247 is deposited on n-cladding layer 245. Here, p-cladding layer 244 and n-cladding layer 245 are of general doping concentration, and p-doped layer 246 and n-doped layer 247 are of heavy doping concentration and are thin.

[0069] Optionally, in combination with reference to Figure 2 and Figure 9 In step S40, the sidewall of p-doped layer 246 in the etched array channel 40 is subjected to oxidation process, so that p-doped layer 246 forms a ring-shaped first oxidation confinement layer 248 radially inward from the side, thereby forming a circular current injection confinement layer of a certain size in the middle of p-doped layer 246. And / or, in step S40, the sidewall of n-doped layer 247 in the etched array channel 40 is subjected to oxidation process, so that n-doped layer 247 forms a ring-shaped second oxidation confinement layer 249 radially inward from the side, thereby forming a circular current injection confinement layer of a certain size in the middle of n-doped layer 247. Note that here and / or means that at least one of the two cases exists.

[0070] Optionally, in combination with reference to Figure 6 In step S30, before depositing bottom electrode layer 21, a high-reflectivity layer 29 is grown on the back of the thinned epitaxial wafer (i.e. the back of buffer layer 22) by epitaxial technology or magnetron sputtering technology, and the high-reflectivity layer 29 is stacked between buffer layer 22 and bottom electrode layer 21. Here, the high-reflectivity layer 29 can be selected as DBR mirror 291 or metal mirror.

[0071] Optionally, in combination with reference to Figure 7 In steps S20 and S30, sputtering bonding metal is performed on the back of the epitaxial wafer and the surface of substrate 11 respectively to form bottom electrode layer 21 and metal bonding layer 12 respectively, and then the back of the epitaxial wafer and the front of substrate 11 are bonded under certain temperature and pressure, i.e. metal bonding layer 12 and bottom electrode layer 21 are bonded to achieve electrical connection.

[0072] Optionally, in combination with Figure 7 and Figure 8In one embodiment, in step S40, a photolithography technique is used to form the pattern of the arrayed channels 40 on the upper surface of the second processed body 62 by using a designed device array pattern mask, and then a dry etching technique is used to etch the arrayed channels 40 by using the photoresist formed in the previous step as a mask, so that the arrayed channels 40 extend from the upper surface of the second processed body 62 to the upper surface of the metal bonding layer 12.

[0073] Optionally, referring to Figure 1 In step S40, an epitaxial technique is used to grow an insulating layer 41 on the inner sidewall and bottom wall of the arrayed channels 40, so that the insulating layer 41 covers the sidewall of all functional layers of the laser unit 20. On one hand, this prevents leakage between adjacent laser units 20 in the arrayed channels 40, and on the other hand, the high thermal conductivity of the insulating layer 41 can help to alleviate the heat accumulation in the light emitting layer 24 of the laser unit 20, thereby providing a heat dissipation function.

[0074] Optionally, in combination with Figure 3 and Figure 9 In one embodiment, in step S50, a photolithography technique is used to form a top electrode layer 27 on the top of each unit device in the third processed body 63 by using a designed top electrode pattern mask, and then photoresist is used to cover the middle region of the top of each device, and a sputtering technique is used to form the top electrode layer 27 on the surface, and then after the photoresist is removed, a circular ring metal electrode 27a with a certain size is formed. A photolithography technique is used to form an anti-reflection layer 28 on the top of each unit device in the third processed body 63 by using a designed top anti-reflection layer 28 pattern mask, and then photoresist is used to cover the middle part of the circular ring electrode 27a, and a sputtering technique is used to form the anti-reflection layer 28 on the surface, which is usually a SiO2 layer, i.e. the anti-reflection layer 28 is deposited in the middle of the ring of the top electrode layer 27.

[0075] The present application provides a photonic crystal surface emitting laser array 1 (PCSEL-array 1) and a preparation method thereof. Firstly, for the laser unit 20, the introduction of the quantum dot active region (the first quantum dot active layer 241 and the second quantum dot active layer 242) effectively improves the quantum efficiency inside the active region. The tunnel junction layer 243 serves as a connecting layer in the multi-junction cascade structure 30, thereby improving the output power and conversion efficiency of the laser unit 20. Further, the plurality of laser units 20 are arranged in an array to form the PCSEL-array 1. Since the plurality of laser units 20 can simultaneously lase, the output power of the entire PCSEL-array 1 device can be greatly improved. To some extent, the negative effects of the weak carrier confinement ability, low injection efficiency and radiation recombination rate in the quantum well active layer of the laser unit 20 can be improved or offset, thereby reducing the photoelectric loss and improving the photoelectric efficiency. The PCSEL-array 1 also helps to expand the application market of the PCSEL device in the industrial and consumer markets. In addition, in the preparation method of the PCSEL-array 1, the entire epitaxial wafer with the multi-junction cascade structure 30 can be processed by only one epitaxial growth, and the process is more simplified and the processing cost is lower.

[0076] Although the present application has been described with reference to several exemplary embodiments, it is understood that the terms used are illustrative and not restrictive ones. Since the present application can be embodied in many different forms without departing from the spirit or essential characteristic thereof, it is understood that the above described embodiments are not limited to any of the described details but are susceptible to modifications or equivalents of their own. Accordingly, all changes and modifications that come within the spirit and scope of the claims are to be embraced by the appended claims.

Claims

1. A photonic crystal surface emitting laser array, characterized by, The application relates to a laser array substrate. The laser array substrate comprises a driving substrate, a plurality of laser units and an array channel. The driving substrate comprises a substrate and a metal bonding layer arranged on one side of the substrate. Each of the laser units comprises, in the light emitting direction, a bottom electrode layer, a buffer layer, a first conductive layer, a light emitting layer, a second conductive layer, a photonic crystal layer and a top electrode layer which are sequentially stacked.

2. The photonic crystal surface emitting laser array according to claim 1, wherein The bottom electrode layer is bonded to the metal bonding layer.

3. The photonic crystal surface emitting laser array according to claim 2, wherein The first conductive layer and the second conductive layer are respectively a p-conductive layer and an n-conductive layer.

4. The photonic crystal surface emitting laser array according to claim 3, wherein The light emitting layer comprises a first quantum dot active layer and a second quantum dot active layer.

5. The photonic crystal surface emitting laser array according to claim 1, wherein The first quantum dot active layer and the second quantum dot active layer are connected by a tunnel junction layer to form a multi-junction cascade structure.

6. The photonic crystal surface emitting laser array according to claim 1, wherein The light emitting layer comprises two groups of p-cladding layers and n-cladding layers. In the light emitting direction, one group of the p-cladding layers and the n-cladding layers are respectively stacked on opposite sides of the first quantum dot active layer. The other group of the p-cladding layers and the n-cladding layers are respectively stacked on opposite sides of the second quantum dot active layer. The light emitting layer further comprises a p-doped layer and an n-doped layer.

7. A method of fabricating a photonic crystal surface emitting laser array, characterized by, In the light emitting direction, the p-doped layer and the n-doped layer are respectively stacked on opposite sides of the tunnel junction layer. The p-doped layer is embedded with a first oxidation limiting layer which extends radially inward from the side wall of the p-doped layer to form an annular state. The n-doped layer is embedded with a second oxidation limiting layer which extends radially inward from the side wall of the n-doped layer to form an annular state. The gap between any adjacent laser units forms an array channel. The inner side wall and the bottom wall of the array channel are covered with an insulating layer so that the current between any adjacent laser units is blocked by the insulating layer. Each of the laser units comprises an anti-reflection layer which is stacked together with the top electrode layer on the upper surface of the second conductive layer. The top electrode layer surrounds the anti-reflection layer. The laser units further comprise a high-reflection layer which is stacked between the buffer layer and the bottom electrode layer. The upper surface of the second conductive layer is recessed to form a plurality of spaced-apart crystal holes to form a cylindrical hole array. The crystal holes are filled with air or silicon oxide medium to form the photonic crystal layer. The photonic crystal layer is embedded in the second conductive layer from top to bottom. The substrate is a conductive substrate. The metal bonding layer is integrally formed on one side of the substrate. The application further provides a method for manufacturing the laser array substrate. The method comprises the following steps. S10: providing an epitaxial wafer with a multi-junction cascade structure. The buffer layer, the first conductive layer, the light emitting layer, the second conductive layer and the photonic crystal layer are sequentially epitaxially grown on a growth substrate. The first conductive layer and the second conductive layer are respectively a p-conductive layer and an n-conductive layer. The light emitting layer comprises a first quantum dot active layer and a second quantum dot active layer. The first quantum dot active layer and the second quantum dot active layer are connected by a tunnel junction layer to form a multi-junction cascade structure. The light emitting layer comprises two groups of p-cladding layers and n-cladding layers. In the light emitting direction, one group of the p-cladding layers and the n-cladding layers are respectively stacked on opposite sides of the first quantum dot active layer. The other group of the p-cladding layers and the n-cladding layers are respectively stacked on opposite sides of the second quantum dot active layer. The light emitting layer further comprises a p-doped layer and an n-doped layer. In the light emitting direction, the p-doped layer and the n-doped layer are respectively stacked on opposite sides of the tunnel junction layer. The p-doped layer is embedded with a first oxidation limiting layer which extends radially inward from the side wall of the p-doped layer to form an annular state. The n-doped layer is embedded with a second oxidation limiting layer which extends radially inward from the side wall of the n-doped layer to form an annular state. The gap between any adjacent laser units forms an array channel. The inner side wall and the bottom wall of the array channel are covered with an insulating layer so that the current between any adjacent laser units is blocked by the insulating layer. Each of the laser units comprises an anti-reflection layer which is stacked together with the top electrode layer on the upper surface of the second conductive layer. The top electrode layer surrounds the anti-reflection layer. The laser units further comprise a high-reflection layer which is stacked between the buffer layer and the bottom electrode layer. The upper surface of the second conductive layer is recessed to form a plurality of spaced-apart crystal holes to form a cylindrical hole array. The crystal holes are filled with air or silicon oxide medium to form the photonic crystal layer. The photonic crystal layer is embedded in the second conductive layer from top to bottom. The substrate is a conductive substrate. The metal bonding layer is integrally formed on one side of the substrate. S20, providing a driving substrate, the driving substrate comprising a substrate and a metal bonding layer arranged on one side of the substrate; S30, bonding the epitaxial wafer and the driving substrate, polishing the back surface of the epitaxial wafer to the buffer layer, depositing a bottom electrode layer on the thinned back surface of the epitaxial wafer to obtain a first processed body, bonding the first processed body to the substrate by metal bonding technology, bonding the bottom electrode layer to the metal bonding layer to obtain a second processed body of the photonic crystal laser; S40, processing an array structure, etching a plurality of spaced array channels from top to bottom on the second processed body, the array channels extending from the upper surface of the second processed body to the upper surface of the metal bonding layer to obtain a third processed body; S50, processing a top electrode layer, depositing a top electrode layer on the top layer of each unit of the third processed body, i.e. on the photonic crystal layer, to obtain a photonic crystal surface emitting laser array, Wherein, the light emitting layer at least comprises a first quantum dot active layer and a second quantum dot active layer, the first quantum dot active layer and the second quantum dot active layer are connected by a tunnel junction layer to form a multi-junction cascade structure, so that the prepared photonic crystal surface emitting laser array is arranged by a plurality of laser unit arrays with the multi-junction cascade structure.

8. The method of claim 7, wherein the method further comprises: In step S10, p-cladding layer and n-cladding layer are respectively deposited on the opposite sides of the first quantum dot active layer and the opposite sides of the second quantum dot active layer; p-doped layer and n-doped layer are respectively deposited on the opposite sides of the tunnel junction layer; wherein the p-doped layer and the p-cladding layer are deposited in stack, and the n-doped layer and the n-cladding layer are deposited in stack.

9. The method of claim 8, wherein the method further comprises: In step S40, the corresponding p-doped layer sidewall in the array channel is subjected to oxidation etching, so that the p-doped layer forms a ring-shaped first oxidation limiting layer radially inward from the side; and / or, in step S40, the corresponding n-doped layer sidewall in the array channel is subjected to oxidation etching, so that the n-doped layer forms a ring-shaped second oxidation limiting layer radially inward from the side.

10. The method for fabricating a surface-emitting laser array of a photonic crystal according to claim 7, characterized in that, In step S30, before depositing the bottom electrode layer, a high reflection layer is grown and deposited on the back surface of the thinned epitaxial wafer, the high reflection layer is stacked between the buffer layer and the bottom electrode layer; And / or, in step S40, an insulating layer is grown on the inner sidewall and bottom wall of the array channel by epitaxial growth technology; And / or, in step S50, the top electrode layer is processed into a ring shape, and an oxidation-resistant layer is deposited in the middle of the ring of the top electrode layer.

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