Addressable VCSEL array chip, driving circuit and driving method

Abstract

The invention discloses an addressable VCSEL array chip for laser radar and 3D sensing, a driving circuit and a driving method, all light-emitting units on a substrate are divided into two light-emitting areas, a sharing area is arranged between every two adjacent light-emitting areas, when the chip is in a first scanning time period T1, the light-emitting areas are divided into two light-emitting areas through a multiplexer, the light-emitting areas are divided into two light-emitting areas, and the light-emitting areas are divided into two light-emitting areas; simultaneously activating a first driving electrode group and a shared electrode group, and lightening a first light-emitting area and a shared area; when the chip is in a second scanning period T2, activating a second driving electrode group and a shared electrode group at the same time through the multiplexer, and lightening a second light-emitting area and a shared area; according to the invention, through the innovative design of the shared electrode group, the light-emitting units at the junction can be multiplexed by adjacent areas in a time-sharing manner, so that seamless connection of illumination light spots in the scanning process is ensured, and a blind area is thoroughly eliminated; the scheme can be directly integrated in a driving framework of an existing pure solid-state laser radar, a core partition scanning working mode does not need to be changed, and the implementation cost is low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device manufacturing and driving technology, and in particular to an addressable VCSEL array chip, driving circuit and driving method for lidar and 3D sensing. Background Technology

[0002] In lidar, especially in pure solid-state lidar systems for applications such as autonomous driving, advanced driver assistance systems, and robot navigation, the use of two-dimensional addressable vertical-cavity surface-emitting laser (VCSEL) arrays as the core light source has become one of the mainstream technologies for achieving reliable and fast beam scanning without mechanical parts. Compared with traditional edge-emitting laser arrays, VCSEL arrays are easier to integrate on a large scale in two dimensions and possess superior beam quality and reliability.

[0003] The core of this type of solid-state lidar's scanning principle lies in the partitioning and electronic addressing of the VCSEL array. Through precise driving circuitry, the control system illuminates different sub-regions within the array sequentially or in a specific pattern within extremely short time intervals. This time-division multiplexing electronic scanning mechanism is the key technological foundation for achieving a purely solid-state architecture and eliminating mechanical components. It not only effectively reduces peak power consumption and heat accumulation, but more importantly, by controlling the illumination sequence of different partitions, it enables flexible electronic scanning of the detection field, thereby acquiring three-dimensional spatial information.

[0004] However, this inherent time-division multiplexing-based operating mode also brings an unavoidable technical problem: at any given brief emission moment, only one or a limited number of sub-regions within the entire illumination field of view are activated to emit light. Since the light intensity of the emitting unit decreases with distance, there are physical gaps where the unit is not activated during the switching between sub-regions, i.e., "illumination blind spots." The spatial locations corresponding to these blind spots cannot be detected by lidar at this moment.

[0005] Existing technologies attempt to mitigate this problem from different levels, including: 1) Optical diffusion method: using optical diffusers to blur the emitted light spot, but this sacrifices the system's angular resolution and causes energy loss, contradicting the high-precision and high-efficiency detection requirements of lidar; 2) Increasing scanning frequency and density: by optimizing the driver chip to increase the partition switching speed and thus the scanning frame rate per unit time. However, this cannot fundamentally eliminate the inherent blind zone within a single frame period and places extremely high demands on the driver circuit, increasing system complexity and cost; 3) Algorithm interpolation method: at the data processing end, point cloud interpolation algorithms are used to predict and fill in the blind zone information. This method is a "post-hoc remedy," as the filled data is not the actual measured value, which may introduce misjudgment risks in critical scenarios, raising questions about its reliability.

[0006] Therefore, although zoned illumination is the core operating method of solid-state LiDAR, the accompanying illumination blind zone problem severely restricts the density, uniformity, and detection integrity of the final point cloud data, becoming one of the key technical bottlenecks limiting the further improvement of the system's performance and its large-scale commercial application. There is an urgent need for an innovative solution that can effectively eliminate the illumination blind zone from the source of VCSEL chip design and manufacturing, without sacrificing the scanning mechanism or significantly increasing system complexity. Summary of the Invention

[0007] Based on existing VCSEL arrays used in pure solid-state lidar, when performing electronic scanning using regional illumination, there are illumination blind spots between adjacent illumination areas, leading to insufficient lidar point cloud density and poor detection integrity. This invention provides a VCSEL structure and method that seamlessly connects illumination spots during scanning, completely eliminating blind spots. The specific solution is as follows:

[0008] An addressable VCSEL array chip includes a substrate and a plurality of light-emitting units closely arranged on the substrate, characterized in that: all the light-emitting units on the substrate are divided into at least two light-emitting regions, and a shared region is provided between each two adjacent light-emitting regions, and at least one light-emitting unit is also arranged in the shared region.

[0009] By adopting the above scheme, a bidirectional addressable shared area is set between adjacent light-emitting areas. The light-emitting units in the shared area can be alternately addressed and lit by the two adjacent light-emitting areas during scanning switching, thereby realizing the overlapping transition of light spots in adjacent lighting areas and eliminating the lighting blind spots in traditional partition scanning.

[0010] Furthermore, all the light-emitting units are arranged in a one-dimensional linear array or a two-dimensional addressable array.

[0011] Furthermore, when all the light-emitting units are arranged in a two-dimensional addressable array, all the light-emitting units are arranged in a hexagonal close-packed configuration. Compared with the traditional row and column matrix arrangement, the hexagonal arrangement of light-emitting units not only eliminates the dark areas and blind spots caused by the gaps between light spots, but also makes the light spot coverage between adjacent light-emitting areas and their shared areas more uniform, effectively improving the overall lighting continuity and energy utilization rate.

[0012] Furthermore, the shared area has multiple light-emitting units, and the shared area presents a sawtooth or wave shape.

[0013] A driving circuit for an addressable VCSEL array chip includes a driving chip, the key feature of which is that: each light-emitting region is provided with a driving electrode group, the first driving electrode group drives the light-emitting unit of the first light-emitting region, the second driving electrode group drives the light-emitting unit of the second light-emitting region, the Nth driving electrode group drives the Nth light-emitting region, and each shared region is also provided with a shared electrode group to drive its light-emitting unit; all the driving electrode groups are connected in parallel with the driving chip through a multiplexer, and the shared electrode group is directly or indirectly connected to the driving chip through adjacent driving electrode groups.

[0014] Furthermore, the shared electrode group and the adjacent driving electrode group are each connected to the driving chip indirectly via unidirectional diodes. The diodes can only conduct in the direction from the shared electrode group to the driving electrode group.

[0015] Using the above-mentioned driving circuit design, the driving chip independently controls the on / off state and lighting sequence of each light-emitting area and the shared area through a multiplexer, realizing seamless switching and coordinated light emission of the light-emitting units in the shared area when adjacent light-emitting areas are connected during the scanning process.

[0016] A driving method for an addressable VCSEL array chip driving circuit, the key of which includes the following steps:

[0017] Step S1: When the chip is in the first scanning period T1, the first driving electrode group and the first shared electrode group are activated simultaneously through the multiplexer to light up the first light-emitting area and the first shared area.

[0018] Step S2: When the chip is in the second scanning period T2, the second driving electrode group and the first shared electrode group are activated simultaneously through the multiplexer to light up the second light-emitting area and the first shared area. ......

[0020] Step Sn: When the chip is in the Nth scan period Tn, the Nth driving electrode group and the (N-1)th shared electrode group are activated simultaneously through the multiplexer, and the Nth light-emitting area and the (N-1)th shared area are lit up.

[0021] By employing the above method, adjacent luminous areas and their shared areas are alternately activated, allowing the illumination spots to overlap and cover each other spatially, thus eliminating the gaps in traditional segmented scanning. This method does not require changes to the external optical system; it achieves continuous, blind-spot-free linear or two-dimensional scanning solely through internal electrode layout optimization and drive timing control. This significantly improves the point cloud resolution and detection reliability of LiDAR, making it particularly suitable for high-precision perception scenarios in autonomous driving.

[0022] Beneficial effects: (1) The present invention achieves the effect of no blind zone in two ways. First, the traditional arrangement of light-emitting unit array is changed to hexagonal close-knit array, which initially eliminates the basic blind zone. Second, through the innovative design of shared electrode group, the light-emitting unit at the junction can be reused by the adjacent area in time division, which ensures the seamless connection of the illumination spot during the scanning process. There is no scanning point with too weak light intensity, and the blind zone at the junction is completely eliminated when the time zone is switched. (2) At the same time, compared with the traditional rectangular grid, the hexagonal close-knit array arrangement can supplement the weak light intensity of each light-emitting unit by the light-emitting unit around it, thus having a higher fill factor and better light field uniformity. (3) This scheme can be directly integrated into the driving architecture of the existing pure solid-state lidar without changing its core partition scanning working mode. Its system compatibility is very good and the implementation cost is low. Attached Figure Description

[0023] Figure 1 This is a comparison of the light spots of the hexagonal array and the traditional grid array of the addressable VCSEL array chip of this invention;

[0024] Figure 2 This is a schematic diagram of the electrode region division in Embodiment 1 of the present invention;

[0025] Figure 3 This is a schematic diagram of the light spot of the light-emitting unit array in time-division multiplexing according to Embodiment 1 of the present invention;

[0026] Figure 4 This is a driving circuit diagram of Embodiment 1 of the present invention;

[0027] Figure 5 This is a driving circuit diagram of Embodiment 2 of the present invention;

[0028] 1-First light-emitting area, 2-Second light-emitting area, 3-Shared area, 4-Light-emitting unit, 5-Multiple choice. Detailed Implementation

[0029] The present application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that similar or identical parts are referred to by the same reference numerals in the drawings or description. Implementations not shown or described in the drawings are forms known to those skilled in the art. In the description of this application, terms such as "first" and "second" are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Example 1:

[0031] This embodiment provides an addressable VCSEL array chip for LiDAR and 3D face recognition, such as... Figure 1 , Figure 2As shown, it includes a substrate and a two-dimensional 6×6 array of light-emitting units 4 closely arranged on the substrate. All light-emitting units 4 are arranged in hexagonal close arrangement. All the light-emitting units 4 on the substrate are divided into two light-emitting areas. The first light-emitting area 1 and the second light-emitting area 2 are arranged adjacent to each other. A shared area 3 is located between the two. Multiple light-emitting units 4 are also arranged in the shared area 3. The shared area 3 has a sawtooth shape or a wave shape.

[0032] A driving circuit for an addressable VCSEL array chip includes a driving chip. The key feature is that each light-emitting region is provided with a driving electrode group; the first driving electrode group drives the light-emitting unit 4 of the first light-emitting region 1; the second driving electrode group drives the light-emitting unit 4 of the second light-emitting region 2; and the shared region 3 is also provided with a shared electrode group to drive its light-emitting unit 4. Figure 3 As shown, the first driving electrode group, the second driving electrode group, and the shared electrode group are connected in parallel to the driving chip via a multiplexer 5. Through the control of the multiplexer, the light-emitting units of the first light-emitting area and the shared area can be addressed independently in a time-division multiplexing manner. The above describes three sets of independent electrodes formed through a metallization process.

[0033] A driving method for an addressable VCSEL array chip driving circuit, the key of which is: Figure 3 As shown: Includes the following steps:

[0034] Step S1: When the chip is in the first scanning period T1, the first driving electrode group and the shared electrode group are activated simultaneously through the multiplexer 5 to light up the first light-emitting area 1 and the shared area 3; at this time, the second light-emitting area 2 is in the off state, forming the first light spot distribution.

[0035] In step S2, when the chip is in the second scanning period T2, the second driving electrode group and the shared electrode group are activated simultaneously through the multiplexer 5, illuminating the second light-emitting area 2 and the shared area 3. At this time, the first light-emitting area 1 is in the off state, forming the second light spot distribution; by alternately scanning the T1 and T2 periods, time-division addressing control of the entire array is achieved.

[0036] Example 2:

[0037] In the driving circuit of the addressable VCSEL array chip, the shared electrode group and the adjacent driving electrode group are indirectly connected to the multiplexer 5 through unidirectional diodes, thereby indirectly connecting to the driving chip; the diode conduction direction is from the shared electrode group to the driving electrode group. The driving method of the driving circuit is the same as in Embodiment 1.

[0038] Example 3:

[0039] The light-emitting units 4 on the substrate are arranged in a one-dimensional addressable array. The one-dimensional array is closely arranged along a straight line. The first light-emitting region 1 and the second light-emitting region 2 are located at both ends of the array. The shared region 3 is located between the two. There can be one or two light-emitting units 4 in the shared region to achieve a smooth transition of the light field. The driving circuit structure and driving method are the same as in Embodiment 1.

[0040] Example 4:

[0041] The light-emitting unit 4 on the substrate is divided into three light-emitting regions: a first light-emitting region, a second light-emitting region, and a third light-emitting region. These three regions are arranged adjacent to each other in sequence. Two shared regions are located between the first and second light-emitting regions, and between the second and third light-emitting regions, respectively. Each shared region has an independent shared electrode group. The driving circuit controls the time-division co-operation of each light-emitting region and its corresponding shared region through a multiplexer 5, realizing independent addressing of multiple regions and continuous control of the light field. By controlling the on / off state of each electrode group in a time-division manner, a natural transition of light intensity between adjacent light-emitting regions is ensured. The driving method includes the following steps: Step S1, when the chip is in the first scanning period T1, the first driving electrode group and the first shared electrode group are activated simultaneously through the multiplexer 5 to light up the first light-emitting area 1 and the first shared area; Step S2, when the chip is in the second scanning period T2, the second driving electrode group, the first shared electrode group and the second shared electrode group are activated simultaneously through the multiplexer 5 to light up the second light-emitting area 2 and the first shared area and the second shared area; Step S3: when the chip is in the third scanning period T3, the third driving electrode group and the second shared electrode group are activated simultaneously through the multiplexer 5 to light up the third light-emitting area and the second shared area.

[0042] The driving methods for multiple light-emitting zones follow the same principle.

[0043] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An addressable VCSEL array chip, comprising a substrate and a plurality of light-emitting units closely arranged on the substrate, characterized in that: All the light-emitting units on the substrate are divided into at least two light-emitting regions, and a shared region is provided between each two adjacent light-emitting regions. At least one light-emitting unit is also arranged in the shared region.

2. The addressable VCSEL array chip according to claim 1, characterized in that: All the light-emitting units are arranged in a one-dimensional linear array or a two-dimensional addressable array.

3. The addressable VCSEL array chip according to claim 2, characterized in that: When all the light-emitting units are arranged in a two-dimensional addressable array, all the light-emitting units are arranged in a hexagonal close arrangement.

4. The addressable VCSEL array chip according to claim 3, characterized in that: The shared area has multiple light-emitting units, and the shared area is serrated or wavy.

5. The driving circuit for any one of the addressable VCSEL array chips according to claims 1-4, comprising a driving chip, characterized in that: Each of the light-emitting areas is provided with a driving electrode group. The first driving electrode group drives the light-emitting unit of the first light-emitting area, the second driving electrode group drives the light-emitting unit of the second light-emitting area, and the Nth driving electrode group drives the Nth light-emitting area. Each of the shared areas is also provided with a shared electrode group to drive its light-emitting unit. All of the drive electrode groups are connected in parallel to the drive chip via a multiplexer, and the shared electrode group is directly or indirectly connected to the drive chip via adjacent drive electrode groups.

6. The driving circuit for an addressable VCSEL array chip according to claim 5, characterized in that: The shared electrode group and the adjacent driving electrode group are connected to each other via unidirectional diodes, thereby indirectly connecting to the driving chip.

7. The driving method for an addressable VCSEL array chip driving circuit according to claim 5, characterized in that: Includes the following steps: Step S1: When the chip is in the first scanning period T1, the first driving electrode group and the first shared electrode group are activated simultaneously through the multiplexer to light up the first light-emitting area and the first shared area. Step S2: When the chip is in the second scanning period T2, the second driving electrode group and the first shared electrode group are activated simultaneously through the multiplexer to light up the second light-emitting area and the first shared area. In step Sn, when the chip is in the Nth scan period Tn, the Nth driving electrode group and the (N-1)th shared electrode group are activated simultaneously through the multiplexer, illuminating the Nth light-emitting area and the (N-1)th shared area.

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