3D and LiDAR sensing module

Abstract

Systems and methods disclosed herein include an illumination module for 3D sensing applications. The illumination module can include a vertical cavity surface emitting laser (VCSEL) array that emits light, a driver configured to provide current to the VCSEL array, and an optical element configured to receive the light emitted by the VCSEL array and output a light pattern from the illumination module.

Description

[0001] Cross Reference to Related Applications

[0002] This application is an international application of, and claims priority to, U.S. Application No. 16 / 801,231, filed February 26, 2020, entitled “3D and LiDAR Sensing Modules,” which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to illumination modules that include modules that generate light for applications such as 3D sensing, including structured light or time-of-flight sensing, and Light Detection and Ranging (LiDAR). More specifically, the present disclosure relates to various features of optoelectronic emitters, and the integration of these emitters with drivers, optoelectronic detectors, and optics on compact modules. BACKGROUND

[0004] Vertical Cavity Surface Emitting Lasers (VCSELs) and VCSEL arrays, as well as other surface emitting devices such as Light Emitting Diodes (LEDs) and Resonant Cavity LEDs (RCLEDs), are important technologies for applications in various markets, including but not limited to the consumer, industrial, automotive, and medical industries. VCSEL arrays have been applied to optical communications and optical sensing. Many optical communications applications use arrays of VCSELs on integrated chips. Figure 1 An example of a one-dimensional VCSEL array 102 is shown, where each VCSEL has its own pad so that it can be individually modulated. Example sensor applications include, but are not limited to, illumination for security cameras, illumination for sensors such as three-dimensional (3D) cameras or gesture recognition systems, medical imaging systems, light therapy systems, medical sensing systems such as medical sensing systems that require deep tissue penetration, or industrial sensors. Often in cases where high optical power is required, it is set up as a VCSEL array where all of the VCSELs are tied together with a common anode and a common cathode. Figure 1 VCSEL array 104 in FIG. 1 is an example of such an array. In this case, the cathode contact is fabricated through the substrate, and the single anode tie pad is connected to the metal that contacts all of the VCSELs in the array, so that the entire array is turned on and off together. These optical emitters and emitter arrays provide some benefits in such optical sensing and illumination applications, as well as other applications, as will be described in further detail herein, including but not limited to power efficiency, narrow spectral width, narrow beam divergence, high speed, and packaging flexibility.

[0005] For VCSELs and VCSEL arrays, power conversion efficiency (PCE) of 30-60% can be achieved in the 660 nanometer - 1000 nanometer (nm) wavelength range. PCE can be defined as the ratio of optical power emitted from one or more lasers, such as a VCSEL or VCSEL array, divided by the electrical power used to drive the laser(s). While VCSEL PCE alone is comparable to some of the most efficient light emitting diodes (LEDs) currently available, VCSELs have a significant efficiency advantage over LEDs when considering spectral width and beam divergence.

[0006] For example, a VCSEL array has a spectral width of approximately 1 nm. This allows for the use of filters for photodetectors or cameras to reduce noise associated with background radiation. In contrast, LEDs typically have a spectral linewidth of 20-50 nm, resulting in rejection of a large portion of the light by such filters, thereby reducing the effective PCE of the LED. Additionally, the wavelength of a VCSEL is less sensitive to temperature, with the wavelength increasing by only about 0.06 nm for every 1 °C increase in temperature. The rate of change of VCSEL wavelength with temperature is one fourth that of an LED.

[0007] The angular beam divergence of a VCSEL is typically 10-30 degrees over a full width of 1 / e2, while the output beam of an LED is a Lambertian beam that fills the entire hemisphere. This means that essentially all, if not all, of the light of a VCSEL can be collected using various optical elements, such as lenses for collimating or focusing the beam profile, diffusers for wide beam (40-90 degrees or more) profiles, or diffractive optical elements for generating spot or line patterns. Due to the wide beam angle of an LED, it can be difficult to collect all or nearly all of the light, resulting in further degradation of the effective PCE, and also difficult to direct the light as precisely as possible as is possible with a VCSEL.

[0008] The vertical emission characteristics of a VCSEL also give it greater packaging flexibility than conventional lasers and open the door for use of a wide range of packaging that can be used for LEDs or semiconductor integrated circuits (ICs). In addition to integrating multiple VCSELs on the same chip, a photodetector or optical element can be utilized to package a VCSEL or VCSEL array. Plastic or ceramic surface mount packaging or chip-on-board options are also available for VCSELs.

[0009] The amount of power emitted from a single VCSEL aperture can range from microwatts to tens of milliwatts, while VCSEL arrays are used to generate power in the hundreds of milliwatts to watts or even kilowatts range. For sensors operating over longer distances, such as 3D sensors based on time-of-flight or structured light methods, higher power VCSEL arrays can be preferred. For medical sensors, diagnostic devices, or therapeutic lasers, higher power can also be required to penetrate tissue more deeply. Chemical sensors or environmental sensors can also require higher power.

[0010] An additional requirement for light sources in time-of-flight applications is the ability to generate short pulses with a fast rise time. The rise time determines the distance resolution that can be achieved. There is typically a maximum voltage that can be supplied to drive the VCSEL, which is in the range of 3-5 volts and determines the maximum current that can be driven into the VCSEL. The rise time of the light source determines the resolution of the distance measured in the third dimension.

[0011] LiDAR is typically used for time-of-flight in automotive, industrial, or military applications. This is also based on the time-of-flight physical effect, but is typically an application for sensing over larger distances and requiring larger amounts of power. For these applications, the restrictions on size and allowable voltage are slightly lower than for consumer applications. However, higher power is typically required, and it is desirable to generate this optical power while minimizing the current and / or electrical power. As mentioned above, the rise time is critical for the distance resolution, and this becomes more challenging at high current drive. Many LIDAR systems use a scanning beam to cover the field of view, but flash LIDAR systems are also used that illuminate the field of view simultaneously.

[0012] Figure 2 Some prior art solutions for time-of-flight illumination modules are shown. Package 202 includes submounts, spacers, and diffuser elements on the package surface. Package 204 shows the interior of package 202. It can be seen that the bottom spacers are patterned with metal pads, and both the VCSEL array chip and the photodiode are located inside package 204. Package 206 is an alternative method using a plastic package. The size of package 202 and package 204 is approximately 2.8 mm x 3.5 mm.

[0013] Figure 3Another prior art solution for a time-of-flight illumination module is shown. Package 300 includes a substrate, a spacer, a VCSEL array, and a photodiode. In this case, an IC has been added to package 300. On the top surface of package 300 there is still a diffuser, and a metal link has been added to the surface of the diffuser. Adding the driver into package 300 reduces the inductance between the VCSEL and the driver, and thus improves the rise time of the VCSEL pulse when used for time-of-flight measurements. The metal link has been added to the diffuser to enable detection of cracks in the diffuser.

[0014] However, for future generations of VCSEL packages for time-of-flight applications, it is desirable to continue to improve the rise time of the VCSEL array, which means further reducing the inductance or inductance effects between the VCSEL and the driver chip. In addition, since many applications are space-constrained, it is desirable to reduce the overall size of the package.

[0015] In addition, illumination modules often include optics for controlling the beam profile. For structured light methods, diffractive optical elements and lenses have been used to produce an array of points. For 3D sensing using time-of-flight methods, diffusers have been used to convert a narrow circular beam into a wider circular or rectangular field of view. The distribution of light over multiple spots or a wider field of view also helps to maintain eye safety by reducing the amount of light that can be focused into the eye. Photodiodes can also be included in the package to help control the driver circuit, as well as monitor the output power and provide measures to ensure eye safety, as described below.

[0016] The greater the output power of the VCSEL, the more important it is to monitor the output power. The output power of the optical device can be affected by temperature, aging, and other factors. In many applications, it is desirable to maintain sufficient output power from the VCSEL die to achieve good signal or high signal-to-noise ratio. On the other hand, VCSELs are often operated in environments that humans can access, and it is necessary to ensure that people are not exposed to emission levels that can cause damage to the eye or skin. These requirements set a lower and upper limit on the optical output power, and it is desirable to have a mechanism to ensure that the power remains within this range over a range of temperatures and time periods.

[0017] In addition to controlling power variations with temperature or performance variations over time, demonstrating that an optical device is eye-safe also requires that it survive a single failure mode. For example, many high-power VCSEL arrays are used in consumer devices. VCSEL arrays are not inherently eye-safe, but they are made eye-safe by pulsed devices with low duty cycles and / or by adding a diffuser above the VCSEL to extend the beam over a wide angle, thus limiting the amount of light that can enter the eye. However, failure mechanisms can include the diffuser removing from its package, liquid condensing on the diffuser surface (which would eliminate the diffuser effect and render the diffuser transparent and ineffective), the diffuser surface melting, or electronic malfunctions that would cause the VCSEL to remain continuously on instead of pulsed.

[0018] Currently, at least several methods exist for monitoring and controlling the output power of VCSELs. Some of these methods are also applicable to other optoelectronic devices, such as edge-emitting lasers. Characterizing the VCSEL's performance at temperature is crucial. A thermistor or temperature sensor can then be included in the system, and the measured temperature can be used to adjust the current to achieve the desired output power based on the previously described temperature-dependent characteristics. This... Figure 4 The diagram shows that, in Figure 4 The diagram illustrates the output power versus current of a VCSEL array over a temperature range from 25°C to 85°C. In this diagram, at 25°C-40°C, the current required to achieve 2W output power is approximately 3A. As the ambient temperature rises to 70°C, the current required to achieve 2W increases to approximately 3.2A, and at 85°C, the current required to achieve 2W is approximately 4A. This information can be incorporated into a lookup table, and the current can be adjusted based on temperature measurements taken by a thermistor. The limitation of this method is that variations exist between devices, and these variations may occur over time due to the aging effects of device lifespan. Variations between devices can be compensated for by individually calibrating each device, but this is both expensive and time-consuming. Variations over time are even more difficult to compensate for.

[0019] The second method is to directly monitor the output power and adjust the drive current of the laser or LED to keep the output power within the desired range. This is often done for devices packaged in transistor outline (TO) headers and transistor outline cans, especially in the fiber optic data communication market. Figure 5An example of a prior art TO is shown in FIG. 1. A VCSEL with a smaller active area than the photodiode can be used to create a stack using a photodiode mounted on a metal TO header and a metal pad on the photodetector. To isolate the photodiode from the header, it can optionally be mounted on a ceramic submount that is patterned with metal between the header and the photodiode. Various VCSEL and photodiode (PD) contacts are wire bonded to the header or package pins for electrical contact. A cap is provided on the top of the package. In the case of a TO header, this is typically a tall metal can with a window in the top surface. The window preferably has no AR coating, or a controlled coating to determine the amount of light that will be reflected at both surfaces of the window. Since the beam of light emitted by the VCSEL has a non-zero angular divergence range, some of the light rays are reflected downward at an angle. Light reflected at a high enough angle will reach areas of the photodetector not covered by the VCSEL chip and can be used to monitor the output power.

[0020] Figure 6 The method is shown in a top view 602 of a prior art TO header. In the top view 602, the VCSEL diode is on top of the metal pad on the photodiode (which in turn is on the header), and wire bonds to the individual anode and cathode contacts of the two diodes are shown. Figure 6 An enlarged view of the photodiode 604, including the pad that houses the VCSEL, is also included. Alternatively, the VCSEL and photodiode can be placed side by side on a submount or header, and the photodiode will capture light emitted from the VCSEL that is reflected to one side by the window. This will typically increase the distance from the active emission area of the VCSEL to the active portion of the photodiode, and thus require an increase in the height of the window above the VCSEL.

[0021] These methods have been used effectively, but there are some limitations. In order to capture enough light on the photodiode, the cover of the TO package is relatively high, which limits the compactness of the package. For example, if the distance from the VCSEL emitting area to the target portion of the photodiode is 0.5 millimeters (mm) (which is a fairly small distance) and the VCSEL half angle is 11 degrees, then the bottom side of the window must be about 1.28 mm above the top of the VCSEL. If the VCSEL to photodiode distance is increased to 1 mm, the height doubles to 2.56 mm. The total package height also includes the package or submount thickness, the window thickness, and the VCSEL thickness, and so can easily reach 3-4 mm high. Since VCSELs are used in consumer electronics where miniaturization is key, this can be problematic. In addition, the beam divergence of the VCSEL can be affected by both temperature and current, so the relationship needs to be understood again and potentially compensated for. The precise geometry of the VCSEL placement relative to the photodiode can also be important. For higher output power arrays, good heat sinking is needed, and the TO as a package is not typically good enough at heat sinking.

[0022] Another version of monitoring the output power in a plastic or ceramic surface mount package using a separate photodiode is shown in Figure 7 There is a plastic or ceramic submount and a side wall to the package, the VCSEL and photodiode dies are side by side on the plastic or ceramic submount, and a glass window or plastic window can be placed on the top of the package. If relying on reflection from this window, the dimensions must be considered to allow an effective signal to reach the photodiode from the VCSEL. Assuming the available angular emission from the VCSEL, the height of the cover needs to be raised to a higher position above the VCSEL, which can prevent the package from achieving the desired low profile.

[0023] A second version of a package with the VCSEL and photodiode monitor placed side by side is shown in Figure 8 In this case, the flat window is replaced by a diffuser. The diffuser creates a certain angular field of view for most of the light that exits the package, but a small portion of the light is scattered parallel to the diffuser glass and gradually scatters the return light down to the photodetector. Due to the lateral scattering, the distance between the VCSEL and the monitor diode can be greater, and the signal received by the photodiode is less sensitive to the spacing between the VCSEL and the monitor diode. However, this monitor photodiode takes up more space in the package, and this method is only effective when it is necessary or desirable to include a diffuser.

[0024] Another method of monitoring the output power of an array is to monolithically integrate the photodiode onto the VCSEL chip, while minimizing the height of the reflective or scattering window above. By reducing the lateral distance from the VCSEL to the monitor, the reflective surface or scattering surface can be lower.

[0025] Another aspect of miniaturization for many applications, especially consumer applications, is the development of flip-chip bonded VCSELs. Figure 9 Such a method is shown schematically. Both the cathode and anode contacts are made from the top surface of the chip. The chip can then be flipped, for example using solder, to attach it to a circuit board or submount, and allow light emission through the original substrate. In this case, optical devices can be attached or fabricated into the substrate. The flip-chip method can enable miniaturization by eliminating the bond pads, increasing the required footprint area. Incorporating optical devices into the wafer backside can help miniaturize the package and / or reduce cost by replacing the need for external optical devices attached to the lid of the package.

[0026] Based on the desired characteristics for optical emitters for illumination and sensing, it would be beneficial if the illumination source had a high slope efficiency. In other words, the illumination source would generate more optical power per unit of current. Advantages of high slope efficiency include the ability to reduce the footprint area of the chip for a desired level of optical power, or alternatively, to increase the output power if the footprint area remains the same. Another key benefit of higher slope efficiency is the ability to achieve shorter rise times when modulating or pulsing the VCSEL device. This is particularly useful for 3D sensing or imaging using time-of-flight mechanisms.

[0027] For 3D sensing, in order to achieve the necessary power to image over a field of view, VCSEL arrays have been used to generate sufficient optical power. However, in the simplest 3D sensing implementation, the array of VCSELs can share both a common anode and a common cathode, and all individual VCSELs are turned on and off together, as shown by VCSEL array 104 in Figure 1 .

[0028] However, instead, the VCSEL chip can be segmented into individual regions, with the VCSELs in a given region modulated together, while the other segments are modulated independently. Figure 10 Several illustrations of this method are shown in FIGS. 10A-10C. VCSEL chip 1002 is a single chip, divided into four segments of similar size. This can be to control the total optical output power and electrical power consumption, as depending on how much optical power is needed, 1, 2, 3, or 4 segments can be activated. Alternatively, by combining the chip with one or more lenses, light from different segments can be steered to different regions of interest. On the other hand, in VCSEL array 1004, one segment is very small, while the other segment is significantly larger. An example of an application of such a chip can be to use the small segment as a narrow beam for a point sensor, while the rest of the chip provides more power for illumination of the region to be imaged.

[0029] However, to individually modulate VCSELs or segments monolithically integrated on the same conductive substrate, one has to choose between driving segments arranged with a common anode or segments arranged with a common cathode. For VCSELs, the common cathode arrangement is much more common, as the most mature substrate with the lowest defect density is doped n-type and thus VCSELs share a common cathode. There are p-doped substrates that allow for a common anode, but are typically smaller and / or have a higher defect density. Smaller substrates lead to higher production costs, while substrate defects can lead to defects in the device, reducing reliability. Insulating substrates also exist, but typically also have a higher defect density and also complicate the manufacturing process of the device, as they still need to be contacted on both sides of the junction and one connection can no longer pass through the substrate.

[0030] Figure 11 A circuit diagram comparison of a common cathode diode design of a multi-segment VCSEL array with a common anode design of a multi-segment VCSEL array is shown. In general, the common anode configuration is preferred, as it allows for smaller and lower power drivers. For bipolar junction transistors (BJTs) and metal oxide semiconductor field effect transistors (MOSFETs), n-type devices have lower resistance and thus higher current handling capability than p-type devices. N-channel FETs (or npn BJTs) are optimally configured as low-side drivers to be placed in a circuit between a load and a ground plane. In this type of driving scheme, the transistor becomes a current sink for the laser, not a current source. Therefore, multiple lasers can only be addressed individually if each channel has an isolated cathode contact. On the other hand, the laser anode contacts can have a common node tied to the power supply (Vcc).

[0031] Assuming a VCSEL array that can be contacted individually or divided into segments, there is now a need for a method to drive the VCSELs or VCSEL segments to turn them on quickly, especially for time-of-flight or 3D sensing applications. Providing a separate tie pad for each VCSEL or each segment can result in a dramatic increase in chip size. Furthermore, as the array size grows, more interconnect metal links are needed to reach additional VCSELs, and the pitch between VCSELs will necessarily increase. A driver chip can be needed for each VCSEL or segment, and as the number grows, the overall package size also grows, as does the distance from the circuit to the VCSEL segments, increasing the inductance of the interconnects. What is needed in the art is a matrix addressable method for 2D VCSEL arrays.

[0032] In summary, illumination modules for sensing applications need to have the following features: compact design that minimizes footprint of the VCSEL chip, optics and potential photodiode incorporated therein, high efficiency, minimization of current and driver inductance for fast pulse rise time, ability to independently drive segments of the VCSEL chip, preferably with a common anode driver design, and ability to switch individual VCSELs or individual VCSEL segments independently of other segments. SUMMARY

[0033] Various implementations disclosed herein include an illumination module comprising a vertical cavity surface emitting laser (VCSEL) array that emits light, a driver configured to provide current to the VCSEL array, and an optical element configured to receive the light emitted by the VCSEL array and output a light pattern from the illumination module.

[0034] In some implementations, at least one VCSEL of the VCSEL array comprises a multi-junction VCSEL. In some implementations, the at least one VCSEL comprises an integrated heterojunction bipolar transistor (HBT).

[0035] In some implementations, the VCSEL array shares a common anode. In some implementations, at least one VCSEL of the VCSEL array comprises a multi-junction VCSEL. In some implementations, the VCSEL array is a bottom emitting VCSEL.

[0036] In some implementations, at least one VCSEL of the VCSEL array comprises an integrated HBT. In some implementations, the at least one VCSEL is a bottom emitting VCSEL. In some implementations, the at least one VCSEL shares a common anode with at least one other VCSEL of the VCSEL array.

[0037] In some implementations, each VCSEL of the VCSEL array comprises an integrated HBT and the VCSEL array comprises a plurality of rows and a plurality of columns. In some implementations, each VCSEL in each row shares a common emitter of the integrated HBT and each VCSEL in each column shares a common base of the integrated HBT, such that each VCSEL of the VCSEL array is individually addressable. In some implementations, at least one VCSEL of the VCSEL array is a multi-junction VCSEL. In some implementations, at least two VCSELs of the VCSEL array share a common anode.

[0038] In some embodiments, the VCSEL array is segmented into a first VCSEL segment and a second VCSEL segment, the first VCSEL segment is configured to emit light, and the second VCSEL segment is configured to detect light emitted by the first VCSEL segment. In some embodiments, the first VCSEL segment is forward biased and the second VCSEL segment is reverse biased. In some embodiments, at least one VCSEL in the first VCSEL segment is a multi-junction VCSEL. In some embodiments, at least one VCSEL in the first VCSEL segment includes an integrated HBT.

[0039] In some embodiments, the optical element is integrated into the VCSEL array. In some embodiments, the optical element is deposited onto a substrate of the VCSEL array. In some embodiments, the module further includes a photodetector located proximate to the VCSEL array. In some embodiments, the module further includes a photodetector located on top of the optical element. In some embodiments, the VCSEL array is segmented into a first VCSEL segment and a second VCSEL segment, the first VCSEL segment is configured to emit light, and the second VCSEL segment is configured to detect light emitted by the first VCSEL segment. In some embodiments, at least one VCSEL in the VCSEL array is a multi-junction VCSEL. In some embodiments, at least two VCSELs in the VCSEL array share a common anode. In some embodiments, at least one VCSEL in the VCSEL array includes an integrated HBT. In some embodiments, the VCSEL array is flip-chip bonded on a substrate that includes the driver and photodetector. In some embodiments, the VCSEL array is flip-chip bonded on a silicon interposer that is connected to the driver, where the silicon interposer includes the photodetector. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 An example of a prior art VCSEL array is shown.

[0041] Figure 2 An example of a prior art time-of-flight illumination module is shown.

[0042] Figure 3 Another prior art solution for a time-of-flight illumination module is shown.

[0043] Figure 4 A plot of current versus output power for a VCSEL array over an operating temperature range is shown.

[0044] Figure 5 An example of a prior art transistor outline.

[0045] Figure 6 is another example of a prior art transistor footprint.

[0046] Figure 7 shows a prior art method of incorporating a photodiode into a lighting module.

[0047] Figure 8 shows another prior art method of incorporating a photodiode into a lighting module.

[0048] Figure 9 shows a prior art method of bonding flip chip VCSELs.

[0049] Figure 10 shows a prior art segmented VCSEL array.

[0050] Figure 11 shows a prior art solution of a VCSEL array with a common cathode.

[0051] Figure 12 is a cross-sectional structure diagram of a VCSEL according to various embodiments.

[0052] Figure 13 is a representation of an active region of a two-junction VCSEL according to various embodiments.

[0053] Figure 14 shows conduction and valence band structures of a quantum well according to various embodiments.

[0054] Figure 15 shows a plot comparing performance between single-junction and double-junction VCSELs according to various embodiments.

[0055] Figure 16 is a block diagram illustrating a lighting module with a VCSEL and integrated driver according to various embodiments.

[0056] Figure 17 shows equivalent circuit estimates of single-junction and double-junction VCSELs according to various embodiments.

[0057] Figure 18 illustrates current response times of single-junction and multi-junction VCSELs according to various embodiments.

[0058] Figure 19 shows a plot comparing rise times of single-junction and double-junction VCSELs according to various embodiments.

[0059] Figure 20 shows a circuit diagram of three VCSELs connected in series according to various embodiments.

[0060] Figure 21 A prior art common cathode VCSEL is shown.

[0061] Figure 22 A common anode VCSEL according to various embodiments is shown.

[0062] Figure 23 Another common anode VCSEL according to various embodiments is shown.

[0063] Figure 24 Another common anode VCSEL according to various embodiments is shown.

[0064] Figure 25 A bottom emitting common anode VCSEL according to various embodiments is shown.

[0065] Figure 26 Another bottom emitting common anode VCSEL according to various embodiments is shown.

[0066] Figure 27 A common anode VCSEL array according to various embodiments is shown.

[0067] Figure 28 A bottom emitting common anode VCSEL array according to various embodiments is shown.

[0068] Figure 29 A VCSEL with an n-doped top layer according to various embodiments is shown.

[0069] Figure 30 A bottom emitting VCSEL with an n-doped top layer according to various embodiments is shown.

[0070] Figure 31 A common anode VCSEL with an integrated HBT according to various embodiments is shown.

[0071] Figure 32 A bottom emitting VCSEL with an integrated HBT according to various embodiments is shown.

[0072] Figure 33 A common cathode VCSEL with an integrated HBT according to various embodiments is shown.

[0073] Figure 34 A VCSEL array with an integrated HBT according to various embodiments is shown.

[0074] Figure 35 A circuit diagram and cross-sectional view of a VCSEL array with an integrated HBT according to various embodiments is shown.

[0075] Figure 36 A mask layout for a VCSEL array with integrated HBTs is shown in accordance with various embodiments.

[0076] Figure 37 An example fabrication of a VCSEL array with integrated HBTs is shown in accordance with various embodiments.

[0077] Figure 38 A conventional VCSEL array and a VCSEL array with integrated photodetectors is shown in accordance with various embodiments.

[0078] Figure 39 A circuit diagram for a VCSEL array with integrated photodetectors connected to a power supply is shown in accordance with various embodiments.

[0079] Figure 40 Another VCSEL array with integrated photodetectors is shown in accordance with various embodiments.

[0080] Figure 41 Another VCSEL array with integrated photodetectors is shown in accordance with various embodiments.

[0081] Figure 42 Another VCSEL array with integrated photodetectors is shown in accordance with various embodiments.

[0082] Figure 43 A plot showing the reflectance spectrum of a semiconductor layer of a substrate forming a VCSEL is shown in accordance with various embodiments.

[0083] Figure 44 A standard VCSEL and a VCSEL with reduced wavelength sensitivity and integrated photodetectors is shown in accordance with various embodiments.

[0084] Figure 45 Another VCSEL with reduced wavelength sensitivity and integrated photodetectors is shown in accordance with various embodiments.

[0085] Figure 46 Another VCSEL with a channel and integrated photodetectors is shown in accordance with various embodiments.

[0086] Figure 47 A VCSEL die with integrated optics is shown in accordance with various embodiments.

[0087] Figure 48 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0088] Figure 49Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0089] Figure 50 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0090] Figure 51 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0091] Figure 52 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0092] Figure 53 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0093] Figure 54 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0094] Figure 55 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0095] Figure 56 A VCSEL die with integrated optics combined with a photodetector is shown in accordance with various embodiments.

[0096] Figure 57 Another VCSEL die with integrated optics combined with a photodetector is shown in accordance with various embodiments.

[0097] Figure 58 Another VCSEL die with integrated optics combined with a photodetector is shown in accordance with various embodiments.

[0098] Figure 59 A VCSEL die with integrated optics combined with a photodetector and driver circuit is shown in accordance with various embodiments.

[0099] Figure 60 Another VCSEL die with integrated optics combined with a photodetector and driver circuit is shown in accordance with various embodiments.

[0100] Figure 61 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0101] Figure 62A VCSEL die with integrated optics combined with a photodetector and driver circuit is shown in accordance with various embodiments.

[0102] Figure 63 Another VCSEL die with integrated optics combined with a photodetector is shown in accordance with various embodiments.

[0103] Figure 64 Another VCSEL die with integrated optics combined with a photodetector is shown in accordance with various embodiments.

[0104] Figure 65 Another VCSEL die with integrated optics is shown in accordance with various embodiments.

[0105] These and other features of the present embodiments can be better understood with respect to the drawings described below, when considered in light of the description provided herein. The accompanying drawings are not intended to be drawn to scale. In order to clearly illustrate the implementation, not every component is labeled in every drawing. DETAILED DESCRIPTION

[0106] The present disclosure describes methods for addressing performance optimization and miniaturization of components for 3D sensing and other applications. Multi-junction VCSELs allow for improved output power as a function of input current. Incorporating multi-junction VCSELs into modules that include driver integrated circuits, photodetectors, beam shaping elements, or other features provides very compact, high performance sensing illumination sources. Further functionality can be achieved by subdividing the VCSEL chip into multiple segments and implementing a structure that allows individual segments to be driven separately with a common anode driver array. Additional improvements in modulation can include incorporating heterojunction bipolar transistors (HBTs) in the VCSEL array to facilitate high speed switching of the VCSEL segments. Further enhancements in miniaturization can include integrating monitoring diodes onto the VCSEL chip for monitoring the output power of the VCSEL or VCSEL array in a manner that allows for compact packaging. Other miniaturization methods include incorporating optics into the wafer backside.

[0107] Multi-junction VCSEL module

[0108] Figure 12are cross-sectional diagrams of two different VCSEL designs according to various embodiments. VCSEL 1202 is the most commonly produced type. VCSEL 1201 includes a bottom substrate, which is typically GaAs for VCSEL wavelengths in the range from about 630 nm to 1060 nm. However, the substrate can be other materials, such as GaN for shorter wavelength VCSELs or sapphire, or InP for longer wavelength VCSELs. On top of this substrate is grown a distributed Bragg reflector (DBR) composed of alternating layers with different refractive indices, where each layer is a fraction of the emission wavelength in thickness . These layers are typically n-doped. Following is an active region with a p-n junction, where injected carriers recombine at the active region of the p-n junction to emit light. In the center of the active region is a quantum well, typically GaAs for 850 nm emission, GaInP for red VCSEL emission, or InGaAs for emission wavelengths longer than 870 nm. The quantum well is separated by a barrier layer, and the quantum well / barrier structure is sandwiched by a confinement layer, which is doped n-type on the substrate side and p-type on the top side. For example, for 850 nm emission, the quantum well would be GaAs, the barrier layer can be Al x Ga 1-x As, where x = 0.25, and the confinement layer can be Al x Ga 1-x A, where x = 0.50. On top of the p-doped confinement layer is deposited a second DBR composed of a stack of quarter- wavelength thick layers, which are also doped p-type. The total thickness of the active region (quantum well, barrier layer, and confinement layer) can be one optical wavelength, but can be any integer multiple of half a wavelength. An alternative to this structure is to invert the doped layers, with p-type doping on the bottom of the structure and n-type doping on the top.

[0109] VCSEL 1204 is a two-junction VCSEL. The structure is similar to the single-junction VCSEL 1202, except for the active region. In this case, the active region contains two p-n junctions centered on two sets of quantum wells. Each set of quantum wells can include one or more wells, although the typical number is between 1 and 4 quantum wells separated by a barrier well. In this case, each set of quantum wells can be separated by a confinement layer. Between the two quantum well p-n junctions is a tunnel junction. The p-doping and n-doping on each side of the tunnel junction are very high to lower the breakdown voltage and allow current to flow through the junction. The doping is typically chosen so that the transport through the junction has a near ohmic character.

[0110] Figure 13is a representation of the active region of a two-junction VCSEL according to various embodiments. After the bottom n-type mirror is deposited, an n-type confinement layer is grown. This is followed by a set of nominally undoped 1-4 quantum wells separated by a barrier layer. Growth then begins a p-doped confinement layer. In the middle of the confinement layer, a tunnel junction is placed, the p-type doping is increased to 10e 19 / cm 3 or higher, then abruptly switches to high n-type doping (10e 19 / cm 3 or higher). The rest of the middle confinement layer is grown with lower concentration n-type doping, followed by a nominally undoped quantum well active region, followed by a p-type confinement layer and a p-type DBR. Thus, the active region has two quantum well active regions centered around a p-n junction and separated by a tunnel junction. The purpose of the tunnel junction is to allow current to flow through the reverse biased junction without excessive loss due to the voltage required to transport current through the reverse biased junction. The two p-n junctions allow holes and electrons to recombine at both junctions to generate light.

[0111] For high efficiency, the quantum well layers should be located at the peak of the electric field, while the tunnel junction should be located at the minimum of the electric field. This is shown in Figure 13 The top and bottom mirrors sandwich the active layer in between. The two sets of quantum wells are located at the peak of the electric field, with a forward biased p-n junction centered on each set of quantum wells, while a reverse biased tunnel junction is located between the two quantum well active regions and at the minimum of the electric field. This helps to minimize the absorption caused by the high doping in the tunnel junction.

[0112] Figure 14 The conduction and valence band structures of various quantum wells are shown according to various embodiments. Figure 1402 represents a conventional quantum well device with no bias, while Figure 1404 shows the band structure of a multi-junction active region, in this case, there are 3 separate quantum well p-n junctions separated by a tunnel junction and placed under bias. If a sufficient bias is applied, the tunnel junction is easily passed through by current under reverse bias conditions, while the p-n junctions at the quantum wells are forward biased.

[0113] Figure 15A plot comparing performance between a single-junction 940 nm VCSEL and a double-junction 940 nm VCSEL is shown. In plot 1502, the output power versus current for both designs is compared, in plot 1504, the voltage versus current is compared, and in plot 1506, the efficiency versus output power is compared. As can be seen in plot 1502, the slope efficiency (i.e., the output power divided by the input current) is significantly higher for the double-junction VCSEL. The slope efficiency for the single-junction is about 1 W / A, while the slope coefficient for the double-junction VCSEL is about twice or 2 W / A. On the other hand, plot 1504 shows the voltage versus current for both designs. For example, the voltage required to drive a 10 mA current through the single-junction VCSEL is 2 V, while the voltage required to drive 10 mA through the double-junction VCSEL is 3.5 V. Finally, in plot 1506, it is seen that the peak electro-optical power conversion efficiency for the single-junction VCSEL is about 52%, with an electrical power dissipation of 9 mW, while the peak efficiency for the double-junction VCSEL is about 59%, with an electrical power loss of about 15 mW. The efficiency improvement can be explained by the fact that the threshold current is very similar for both designs, and the slope efficiency for the double-junction device is essentially double that of the single-junction design, but the voltage increase is less than a factor of 2. The voltage is a function of the junction voltage plus the resistance times the current through the mirror. While the junction voltage is doubled due to the presence of two junctions, the series resistance is still approximately the same.

[0114] For applications such as time-of-flight based 3D sensing, the VCSEL array can be integrated with a driver integrated circuit (IC) that can provide short pulses, typically in the range of 1 to 10 nanoseconds, although the pulses can be shorter or longer. Importantly, the rise time of the pulse should be as short as possible in order to have the best time, and thus the best distance resolution, in 3D time-of-flight applications. Figure 16 is a block diagram showing an illumination module with a VCSEL and integrated driver according to various embodiments. In some embodiments, the illumination module includes an optical element that produces a particular light pattern or field of view. In Figure 16 In the modules shown, the optical element is a diffuser that converts a generally circular beam to a rectangular field of view. Another function is to incorporate a photodetector (PD) that can monitor the output of the VCSEL and also detect if the optical element is somehow lost or damaged. Light can be reflected or scattered down from the diffuser or window onto the photodetector. Illumination module 1602 shows the photodetector adjacent to the VCSEL and both the VCSEL and photodetector are separate from the driver, while illumination module 1604 shows the photodetector incorporated in the driver and the VCSEL chip mounted on top of the driver.

[0115] Other passive components such as capacitors and resistors can be incorporated into the module to improve performance. All of these components can be incorporated into a housing with a transparent glass or optical element incorporated as a window to allow light to exit the module. The base of the module can be a printed circuit board, a lead frame, a ceramic submount, or any other substrate that provides mechanical support and electrical signal routing. Electrical connections to the semiconductor chips (VCSEL, photodetector, driver integrated circuit) and passive electrical components can be by wire bonds, bump bonds, or direct wire bonds or bump bonds between the substrate or device.

[0116] The VCSEL die can be electrically connected to a driver IC that provides nanosecond range pulses to the VCSEL. Several laser driver structures are available including structures based on silicon CMOS or high power GaN FETs. The respective switching speeds of the driver and laser can be greater than a few GHz in general, but the response of the system is limited by the interconnect between the two components. The response time of the VCSEL (i.e. the rise time of the optical light pulse) is affected by the rise time of the electrical pulse, the parasitics (capacitance and resistance) of the VCSEL chip, and the inductance due to the method of connection between the driver and the VCSEL. In particular at high currents, the inductance of the connection method can dominate. For example, the inductance can be due to one or more wire bonds, traces running through a submount, or bump bonds to the driver or submount. SPICE simulations have been performed to estimate and compare the rise times of a single junction VCSEL versus a double junction VCSEL. Figure 17 Equivalent circuit estimates of a single junction VCSEL and a double junction VCSEL are shown in accordance with various embodiments. Circuit diagram 1702 shows the equivalent circuit estimate of a single junction VCSEL, while circuit diagram 1704 shows the equivalent circuit of a double junction VCSEL. The interconnect inductance is assumed to be 0.2 nanohenry, while the resistance of the VCSEL array is assumed to be 0.25 ohms. To make a comparison, the drive conditions of both designs are assumed to result in the same amount of optical output power. For the single junction VCSEL, the drive current is assumed to be 4A, while for the double junction VCSEL, the drive current is assumed to be 2A, since the slope efficiency is approximately 2 times higher.

[0117] The transient response of the current through the inductor and the VCSEL is defined as dI / dt = L s / V L where L s is the inductance, V L is the supply voltage. Thus, the switching speed can be optimized by minimizing the inductance or increasing the available supply voltage. However, a multi-junction VCSEL provides another method to increase the speed of the circuit. As Figure 18The total response of the system is shown to be characterized by dP / dt = dP / dI * dI / dt. If we consider bias conditions above the VCSEL threshold, dP / dI = η sl , the slope efficiency, so the response becomes dP / dt = η sl * L s / V L . For a single-junction VCSEL, the maximum slope efficiency is limited to a differential quantum efficiency of 100%, but for a multi-junction VCSEL, the differential quantum efficiency can greatly exceed 100%. The maximum slope efficiency for n-stages becomes: η sl = n / λ * 1.24 [A*um / W]. Then, the rise time can be proportionally reduced in a multi-junction VCSEL in the number of stages. Furthermore, if the total current required to operate the VCSEL is lower, the resistance losses due to other parasitic elements in the module are also proportionally reduced, resulting in a more efficient system.

[0118] Figure 19 Results of SPICE simulations using the equivalent circuit of Figure 17 are shown. The plot shows the rise time of the current flowing through each type of device, corresponding to the rise time of the light emission. For each type of design, the rise time is shown for the current to rise from 20% to 80% of the maximum value. For the single-junction VCSEL (upper curve), the 20 / 80 rise time is estimated to be 416 picoseconds, while for the dual-junction VCSEL (lower curve), the estimated rise time is 134 picoseconds. Thus, Figure 19 the benefits of using a dual-junction VCSEL for time-of-flight or LIDAR applications are shown. The reduction in the current required results in a faster rise time, improving the depth resolution.

[0119] For consumer applications where the voltage can be limited to a range less than 5 volts, a dual-junction VCSEL design would be suitable and would bring the advantage of a faster rise time to improve the distance resolution in 3D sensing, and would also provide the advantage of higher power per chip area, or alternatively, a smaller chip area to obtain a constant output power level. For LIDAR applications, three or even more junctions can further enhance the output power per area, while providing the same advantages of fast rise time and associated improved distance resolution. For LIDAR applications, several multi-junction VCSEL chips can be arrayed in a module with one or more driver circuits for providing the electrical pulses to the VCSEL dies.

[0120] For very high power systems, several VCSEL arrays can be connected in series or in parallel to tailor the voltage and current required to precisely match the optimal load of the driver. The interconnections can be made within a single VCSEL chip, or by tiling multiple chips on a circuit board, sub-mount, or directly on the driver itself.Figure 20 A circuit diagram 2000 of three VCSELs connected in series is shown, according to various embodiments. In the circuit diagram 2000, three groups of VCSELs are connected in series, but each group includes two three-junction VCSELs in parallel. In general, any combination of VCSELs in parallel and series is possible.

[0121] The multi-junction design can be developed in both top-emitting VCSELs or bottom-emitting VCSELs, and can also be implemented in any wavelength suitable for a VCSEL. This includes long wavelength (>1 micron) VCSELs based on InP systems, near infrared VCSELs (750 nm to 1100 nm) based on AlGaAs / GaAs / InGaAs material systems, red VCSELs based on AlGaAs / InGaP material systems, and blue and green VCSELs based on AlGaN / GaN / InGaN material systems.

[0122] While Figure 16 While the VCSELs are shown incorporated into a module including optics and a driver IC, the VCSELs can also be provided in a simple first-level package with or without optics and integrated with a driver IC on board. The optics can also be integrated directly onto the VCSEL chip itself.

[0123] Common anode VCSEL array

[0124] In addition to showing two VCSEL diodes, Figure 21 A prior art common cathode VCSEL 2102 is shown, previously shown in Figure 12 Starting from the bottom of the VCSEL 2101, there is an n-metal contact to the n-doped substrate. This substrate is most likely GaAs in the case of a VCSEL wavelength in the range from 650 nm to 1060 nm, but can also be InP or GaN for other wavelength ranges. On top of the substrate is an epitaxially deposited n-doped DBR mirror layer, composed of alternating layers of two different compositions with different refractive indices. For example, the two layers can be GaAs and AlAs or ternary AlGaAs of different compositions. This is followed by a quantum well based diode junction. On top of the mirror is an n-doped spacer layer, followed by nominally undoped multiple quantum wells, and then a p-doped spacer layer. On top of this active region is grown a p-doped DBR mirror similarly composed of GaAs, AlAs or ternary AlGaAs thereof. A metal contact to the p-doped layer is deposited and patterned on top of the structure. Figure 21Two diodes are shown, with a mesa etched around each diode that goes down to the bottom n-doped mirror, thus isolating the p-side of the diode. One layer with a higher aluminum composition than the other layers (AlAs or AlGaAs with very high aluminum content) is grown in this structure. After the mesa is etched around each diode, the structure is exposed to steam, which causes the high aluminum content layer to convert to Al203. The oxidation process is controlled to leave an opening in the center of the mesa. The oxide is insulating, thus providing a current aperture to limit the current flow to the center of the mesa. Diagram 2104 represents the circuit layout of the VCSEL 2102, showing that they share a common cathode but have separate anode contacts.

[0125] Figure 22 A common anode VCSEL 2202 is shown, according to various embodiments. The structure starts as before with a metal contact to the n-type material of the substrate. The n-doped DBR mirror stack follows as before. An n-doped spacer layer follows, but then a tunnel junction is grown. The tunnel junction includes a very highly doped n-type layer directly on top of the n-spacer layer, followed by a very highly doped p-type layer. A p-type spacer layer is grown next to the highly doped p-layer of the tunnel junction, followed by a nominally undoped multiple quantum well, and then an n-doped spacer layer. In contrast to the VCSEL 2102, where the light emitting junction is n-p (i.e., the bottom layer is n-doped and the top layer is p-doped), in the VCSEL 2202, the light emitting junction is reversed, now a p-n junction. An n-type DBR mirror is grown on top of the n-spacer layer, and a metal is deposited and patterned on the top surface to form ohmic contacts to these n-type layers. As before, a mesa is etched around each diode, and as before, current confinement is provided by oxidizing the high aluminum content layer to form a current aperture.

[0126] Diagram 2204 represents the circuit layout of the VCSEL 2202. In this structure, the junctions are reversed, so that the p-side of the junctions are tied together as a common anode. When the multiple quantum well junction is operated in forward bias to emit light, the tunnel junction will be reverse biased. Despite the fact that the tunnel junction will be reverse biased in operation, the very high doping levels result in a very low breakdown voltage of the junction, so that the transmission of current through the tunnel junction under reverse bias is essentially ohmic in nature. The function of the tunnel junction is to allow current to flow through the n-type substrate and n-type mirror to the p-side of the junction. This structure allows the design to remain built on an n-doped substrate, but the fabrication of the device is nearly identical to that of a conventional VCSEL. The n-doped top mirror also has the advantage that n-type doped carrier absorption is less than p-type doped carrier absorption, which can result in lower losses and higher efficiency.

[0127] Figure 23Another common anode VCSEL 2302 is shown, in accordance with various embodiments. In the VCSEL 2302, the tunnel junction is moved deeper into the bottom mirror. In this case, again starting from the bottom and going up, a metal contact is deposited on the substrate side of the structure, where the substrate is doped n-type. Again, the tunnel junction is created with a high n-type doping followed by a high p-type doping, partially through the bottom mirror. The rest of the bottom mirror is grown with p-type doping. Placing the tunnel junction into the bottom mirror results in a bottom DBR that is partially p-type and partially n-type. A p-doped spacer is grown, followed by a nominally undoped multi-quantum well active layer and an n-type spacer. As Figure 22 shown, the top mirror is now n-type doped, and a metal contact is deposited and patterned on the top surface of the structure. As before, a trench is etched around each diode, and a carrier confinement layer is created by oxidation. The corresponding equivalent circuit is shown in diagram 2304. In this case, the tunnel junction is shared by two diodes. This can further reduce the resistance and remove the high-doped layers from the active region that generates light, at the cost of the p-doped mirror layers close to the active region.

[0128] Figure 24 Yet another common anode VCSEL 2402 is shown, in accordance with various embodiments. In this case, the tunnel junction is moved to a buffer layer grown on top of the substrate. An optional n-type buffer layer can be grown on top of n-type GaAs, followed by a highly doped n-type layer and a highly doped p-type layer to form a tunnel junction, followed by a p-doped bottom DBR mirror. As before, the active region includes a p-spacer, a nominally undoped multi-quantum well active region, an n-type spacer, an n-doped top DBR mirror, and a top metal contact. The equivalent circuit diagram is shown in diagram 2404, which looks equivalent to diagram 2304, although the quantitative values of the resistor values can be different.

[0129] Figure 22- Figure 24 A VCSEL structure is shown that emits from the top (i.e., light is emitted from the top surface of the VCSEL). Figure 25 A structure for a "bottom emitting" VCSEL 2502 is shown, i.e., a device designed to emit through the bottom substrate, in accordance with various embodiments. In this case, the semiconductor layers and equivalent circuit are the same as Figure 22The VCSEL 2202 is similar to the VCSEL 2202 in FIG. 22. However, the epitaxial layers are chosen to favor light emission through the substrate. This means that the emission wavelength should be greater than 870 nm, and preferably 930 nm or greater to minimize light absorption in the GaAs substrate. This means that the multiple quantum wells can be an InGaAs composition designed to emit light at 870 nm or greater. In addition, the number of periods in the DBR mirrors will be chosen so that the top DBR mirror will be highly reflective, while the bottom mirror (closest to the substrate) will be less reflective, enhancing emission through the substrate side. Since the emission is through the substrate, the top metal contact can completely cover the VCSEL mesa, while the bottom metal contact will be patterned to leave an open window for light emission through the bottom. The graphic 2504 represents the circuit layout of the VCSEL 2502.

[0130] Figure 26 A schematic design of another bottom-emitting common anode VCSEL 2602 is shown, according to various embodiments. Since the n-doped substrate is relatively thick compared to the thickness of the VCSEL, the residual free carrier absorption of the doped substrate can significantly reduce the overall efficiency. In the VCSEL 2602, the structure is deposited on an undoped substrate. In this case, a doped buffer layer can be grown under or within the bottom mirror. This layer is thick enough and doped enough to allow a metal contact to be made to this layer. The rest of the bottom DBR n-doped mirror is grown, followed by a tunnel junction, a p-doped spacer, a multiple quantum well active region, an n-doped spacer, and a top n-doped DBR mirror. In this case, the mesa should be etched deep enough to reach this buffer layer so that a metal contact can be deposited at the bottom of the etched region to make a contact to the anode side of the junction. The top metal can completely cover the VCSEL mesa, since the light will be emitted through the bottom. The graphic 2604 represents the circuit layout of the VCSEL 2602.

[0131] In some embodiments, the VCSEL 2602 can be altered by growing a buffer layer on top of the substrate and under the bottom mirror, or placing a buffer layer on top of the bottom mirror just before growing the spacer layer and tunnel junction. In some embodiments, the buffer layer can be eliminated and the mesa etched down into the n-doped metal mirror, making electrical contacts directly to these layers.

[0132] The above-described methods for creating a common anode array can also be combined with a multi-junction VCSEL. As described above, a multi-junction VCSEL contains two or more p-n junctions for generating light and allows for current recycling by placing a tunnel junction between the active regions. An example of such a multi-junction VCSEL is the Figure 12VCSEL 1204 in FIG. 12. As before, the double junction VCSEL can start with a bottom metal contact, an n-doped substrate, and an n-doped DBR bottom mirror. Next is an n-doped spacer, followed by a tunnel junction with a highly doped p-type layer, followed by a highly doped n-type layer, where these two layers form the tunnel junction. Another n-doped spacer is followed by a second set of nominally undoped multiple quantum well active region and another p-doped spacer. A p-doped DBR top mirror is then grown, and a metal contact is deposited and patterned. In operation, the two multiple quantum well junctions are forward biased, and electrons and holes combine to emit light. The tunnel junction is reverse biased, and will have a low breakdown voltage due to the high doping, and thus allow current to pass with near ohmic characteristics. Carriers can thus be recycled. The performance of this structure is presented in FIG. 13. Figure 15 This structure can also improve the speed performance of an array for applications such as time-of-flight sensors. When high current is driven into a VCSEL array, the package inductance can limit the speed, but the reduction in current needed for a given output power can result in a faster rise time for the optical output power. Additional junctions can be added, separated by tunnel junctions, to further increase the output power versus current.

[0133] The multiple junction VCSEL just described can also be designed to produce a common anode array. Figure 27 A common anode VCSEL array 2702 is shown, according to various embodiments. The layers of the VCSEL array 2702 are described from the bottom up, starting with a metal contact on the substrate dimension. The substrate is doped n-type, and an n-doped DBR bottom mirror is deposited on the substrate. Next is an n-doped spacer, followed by a tunnel junction consisting of a highly doped n layer, followed by a highly doped p layer. Next is a p spacer, followed by a nominally undoped multiple quantum well active layer, followed by an n-doped spacer. Next is a second tunnel junction, followed by a p-doped spacer, a second nominally undoped multiple quantum well active region, and an n-doped spacer. The top DBR mirror is n-doped, and a metal contact is deposited and patterned on the top surface. The two tunnel junctions accommodate two multiple quantum well n-p junction active regions, allowing both the top DBR and the bottom DBR to be doped n-type, so that a segmented array can be driven in a common anode configuration. The graphic 2704 represents the circuit layout of the VCSEL array 2702.

[0134] Additional junctions (three or more) can be added to the VCSEL array 2702 by adding a tunnel junction and another p-n junction quantum well region to each junction. As shown in FIG. 14, a variation on the location of the tunnel junction closest to the substrate can be similarly applied to the multiple junction case. Figure 22- Figure 24

[0135] The multiple junction common anode segmented VCSEL array can also be fabricated in a bottom emitting format. Figure 28 ​A bottom-emitting common-anode VCSEL array 2802 according to various embodiments is shown. The VCSEL array 2802 can be deposited on a semi-insulating substrate. An n-doped buffer layer is shown as being grown inside the bottom mirror and doped to n-type. The mesa surrounding each diode can then be etched down into this layer and metal contacts deposited and patterned. As before, the buffer layer can be deposited below, inside, or on top of the bottom mirror. Figure 2804 shows the circuit layout of the VCSEL array 2802.

[0136] Conventional VCSELs end with a p-type material. Typically, the material at the top surface of the epitaxial layer structure is highly p-type, allowing current to easily tunnel through to the deposited metal layer. However, this approach is generally less effective for n-type GaAs or AlGaAs at the surface. Achieving the required high doping is more difficult. Metal stacks that diffuse at the surface or form intermetallic layers can be used to ensure ohmic behavior. However, these approaches can lead to reliability issues. Another approach is to reduce the potential between the GaAs surface and the metal by inserting a relatively highly n-type doped InGaAs layer at the top surface of the structure, which allows for good ohmic contact without the need for alloying processes. The InGaAs layer prevents n-metal diffusion into the top DBR. This... Figure 29 The VCSEL 2902 shown in the image depicts an InGaAs layer on the top surface beneath patterned metal contacts. However, to avoid light absorption in this layer, the InGaAs layer is etched away from the emitting surface of the VCSEL.

[0137] Figure 30 A bottom-emitting VCSEL 3002 with an n-doped top layer is shown according to various embodiments. Similar to the VCSEL 2902, the top layer of the VCSEL 3002 can be an InGaAs contact layer. In this case, because light emission passes through the substrate side, the top contact metal and the InGaAs contact layer cover the entire mesa. In this version, the substrate is non-conductive, and the anode-side contacts are fabricated by etching down into the doped buffer layer and depositing and patterning the contacts, as shown in the reference. Figure 26 As stated above.

[0138] VCSEL with integrated HBT

[0139] The diode structure described above, which has two n-type mirrors and a tunnel junction, can also be incorporated into a three-terminal device by integrating it with an npn HBT. Figure 31 A common anode VCSEL 3102 with integrated HBT is shown according to various embodiments. VCSEL 3102 is similar to the reference design. Figure 22The VCSEL 2202 is described. As previously described, the layers starting from the bottom may include a bottom metal contact, an n-doped GaAs substrate, an n-doped mirror, an n-spacer layer, a tunnel junction, a p-spacer containing oxide apertures, a nominally undoped multiple quantum well active region, an n-spacer, and an n-doped DBR top mirror. However, on top of this surface is an NPN HBT structure. If the VCSEL 3102 is designed to emit at wavelengths greater than approximately 900 nm, this structure may include an n-doped GaAs collector layer, a p-spacer layer, and a p-spacer layer. + A GaAs base layer, an n-doped InGaP emitter layer, a GaAs cap layer, and an n-doped InGaAs layer used as a non-alloy contact layer are constructed. Larger dimensions are etched around the VCSEL diode to allow for the formation of an oxide current-limiting layer. The structure includes an n-doped InGaP emitter layer, a GaAs cap layer, and an n-doped InGaAs layer. + The InGaAs contact layer is etched with smaller mesa surfaces. In p + A p-type metal contact is formed on top of the GaAs base layer, and emitter metal contacts are deposited and patterned on the InGaAs contact layer. The InGaAs contact layer is also etched away from the light-emitting region on the top surface of the chip so that light will not be absorbed by the layer.

[0140] Figure 3104 illustrates the circuit layout of a VCSEL array 3102 with an integrated HBT. By controlling the voltage to the base contact of the HBT, the HBT acts as a switch, turning on and off the current flowing through the VCSELs. In the array, this switching function allows VCSEL addressing within the array. This integration can also help improve the switching speed of the VCSELs by controlling the switching of higher currents through the VCSEL devices by applying a lower voltage to the HBT base.

[0141] The above Figure 22- Figure 30 The variations described can also be incorporated into structures integrated with HBTs. For example, Figure 32 A bottom-emitting VCSEL 3202 with an integrated HBT is shown according to various embodiments. This can be... Figure 31 The integrated HBT shown is Figure 26 The diagram shows a combination of bottom-emitting VCSEL designs. A buffer layer for contacts is included in the bottom n-type mirror, and the VCSEL diode mesa is etched down into this layer. Metal is deposited and patterned on this layer to serve as the VCSEL contacts and, effectively, the HBT collector contacts.

[0142] The multi-junction design can be developed in both top-emitting VCSELs or bottom-emitting VCSELs and in any wavelength suitable for a VCSEL. This includes long wavelength (>1 micron) VCSELs based on InP systems, near infrared VCSELs (750 nm to 1100 nm) based on AlGaAs / GaAs / InGaAs material systems, red VCSELs based on AlGaAs / InGaP material systems, and blue and green VCSELs based on AlGaN / GaN / InGaN material systems.

[0143] While Figure 31 While the integration of a VCSEL with a NPN heterojunction bipolar transistor (HBT) is shown for a common anode design, the HBT can also be integrated into a common cathode VCSEL. Figure 33 A common cathode VCSEL 3302 with integrated HBT is shown according to various embodiments. Starting from the bottom, there is a metal contact on the bottom surface, followed by a GaAs substrate that is typically n-type doped. On top of the substrate is an n-type DBR mirror, followed by a quantum well active region. The active region is composed of multiple layers, including quantum wells separated by barrier layers, and has spacer layers on either side of the quantum and barrier layers. On top of the active region is a p-doped DBR. Within this DBR is typically a layer containing a high percentage of Al, which is subsequently oxidized to convert it from (almost) AlAs to an insulating aluminum oxide layer that forms a current confinement layer. This layer is not fully converted, leaving a conductive region through which current can flow.

[0144] The layer on top of the top p-doped mirror is the collector layer of the HBT, and in one embodiment, is p-type doped. On top of the collector is an n-doped base layer, followed by a p-doped emitter layer. In this structure, a mesa is etched to expose the base layer, and metal contacts are deposited on both the base and emitter layers. In this embodiment, the light from the VCSEL passes through the layers on top of the structure and an emission window, which can be protected by a transparent dielectric layer. To achieve efficient emission from the structure, the sum of the thicknesses of the collector, base, and emitter layers should be an odd number of λ / 4 optical thickness layers. The composition of the emitter, base, and collector layers must be chosen so as not to cause absorption of the emitted light. For example, for a VCSEL emitting at 940 nm, the layers can include mostly GaAs / AlGaAs / AAlAs material systems. However, for a VCSEL emitting at 850 nm, GaAs layers cannot be used, and the emitter should be all AlGaAs with a high enough Al content to avoid absorption by GaAs. This typically means Al x Ga 1-xAs, where x is greater than or equal to 0.12. Alternatively, the GaAs layers can be thin enough, or placed at the nulls of the optical standing wave, to limit the absorption of the output light transmitted through these layers.

[0145] The pattern 3304 represents the circuit layout of the VCSEL 3302. With the bottom cathode grounded and a voltage applied to the top metal in contact with the emitter, the emitter, base, and collector layers form a PNP transistor in series with the VCSEL diode. With the voltage applied to the emitter, controlling the bias of the base layer of the transistor allows turning on and off the current through the VCSEL. For example, there is a string of VCSELs with a common cathode and metal contacts connecting all the emitters, but with separate contacts to the base of each VCSEL. If a bias is applied to one base, the corresponding VCSEL will turn on, while the rest of the VCSELs will remain off.

[0146] As shown in FIG. 3A, the HBT can be designed as an NPN, then naturally interfaced with a VCSEL structure designed as having two n mirrors, such that the structure can be driven with a common anode. If the VCSEL is inverted by growing on a p-type substrate with a bottom p mirror and a top n mirror, this is also a natural approach. If combined with a conventional VCSEL structure as shown in FIG. 3B, a high-doped np tunnel junction between the collector layer and the VCSEL active region is required to allow current flow through the VCSEL. This structure can be designed for a bottom-emitting VCSEL as shown in FIG. 3C. In this case, the metal contacting the emitter layer can cover the top mesa completely, and an opening can be created in the bottom metal to allow the emitted light. In this case, the top mirror will reflect almost 100%, then the composition and thickness of the HBT components will no longer need to be non-absorbing and specific thickness, since the light is no longer emitted through them. In a fourth variation, the HBT structure can also be placed within one or the other of the DBR structures. Depending on the location, careful control of the thickness, doping, and composition can be required to maintain the mirror reflectivity without creating an absorption source. Figure 31 Figure 31 Figure 33 Figure 31

[0147] Figure 34 ​​​​A VCSEL array 3400 with integrated HBTs is shown, according to various embodiments. The integration of HBT structures in the stack with the VCSELs can be used to create a method of addressability for a two-dimensional array of VCSELs. This layout assumes a common contact is formed to the bottom of the chip. On the top side, the emitter of all HBTs / VCSELs in a row (E1-E7) share the same emitter interconnect metal that contacts the emitter layer of all VCSELs in that row. The base layer of all HBTs in a column (b1-b8) are interconnected with a common base metal interconnect that contacts the base layer in each HBT / VCSEL in the column. If a single emitter row and a single base column are activated, the VCSEL at the intersection of the two will light up. A single base column and multiple emitter lines can be activated, then multiple VCSELs in the base column will emit light. Other patterns can be created by the combination of emitter and base lines activated.

[0148] Figure 35 A circuit diagram 3502 and a cross-sectional view 3504 of a VCSEL array with integrated HBTs is shown, according to various embodiments. Figure 35 More details are provided on how the connections are made for the 2D matrix implementation. Figure 35 Three VCSELs are shown in FIG. 3 to illustrate how the VCSELs in the common emitter row (V1 and V2) are connected and how the VCSELs in the common base column (V2 and V3) are connected. Each VCSEL can have the same set of layers: bottom metal, substrate, bottom mirror, active quantum well region, oxidation layer for carrier confinement, top mirror, collector, base, emitter, and top metallization. The area labeled BCB / polyethylene is an etched area that is created to allow the oxidation process of the carrier confinement layer to occur. It is then filled with a polymer material such as benzocyclobutene (BCB) or polyimide to re-planarize the wafer. An etch down to the top of the base layer is made, an ohmic contact is deposited, and then a metal ohmic contact is made to the top surface emitter layer. An interconnect metal that connects all the base layers in the column can be deposited. This interconnect can be covered by an additional BCB layer or polyimide so that the interconnect metal can connect all of the emitter layers in the vertical direction.

[0149] Figure 36 A mask layout for a VCSEL array with integrated HBTs is shown, according to various embodiments. The area labeled base mesa shows the etch down to the boundary of the oxidation layer so that the oxidation of the current confinement layer can occur. The emitter mesa shows where the etch is made to reach the semiconductor base, and where the base metal can be deposited. Both mesas are covered by a polymer planarization layer so that the emitter interconnect metal can be deposited across the base metal contacts.

[0150] VCSELs with integrated HBTs can be used in a variety of ways. For example, as described above, it can be used to create an array switch matrix to turn on selected modes of the VCSELs. In another example, the HBT can be used as an integrated driver to enable high speed switching. In another example, it can also be used as a distributed driver in an array. By positioning a driver at each VCSEL, the entire array can be switched at high speed.

[0151] Figure 37 An example VCSEL array 3700 with integrated HBTs is shown in accordance with various embodiments. An example fabrication process for the VCSEL array 3700 is described below, but fabrication of such an array is not limited to the parameters described below. Those of ordinary skill in the art will appreciate that variations in the fabrication process can be considered herein.

[0152] In this example, the epitaxial structure of the VCSEL array 3700 can be grown on an n-doped GaAs substrate for wavelengths in the range of 630 nm to 1060 nm. Next, an n-doped DBR is grown, followed by an n-i-p doped active region containing quantum wells for light emission, followed by a p-doped mirror, followed by layers that form the HBT. This includes first a p-doped collector, an n-doped base, and a p-doped emitter. In this wavelength range, the DBR layers and HBT layers can include various compositions of AlGaAs or InAlGaP. For emission of 630 nm to 700 nm, the quantum wells and other active region layers can be from the InAlGaP material system. For 700 nm to 860 nm, the active region layers can include AlGaAs material, while for 870 nm to 1060 nm, the quantum wells can include InGaAs and AlGaAs or GaAsP spacer layers. Wavelengths below 630 nm and above 1060 nm can also be implemented. For example, wavelengths below 630 nm can be implemented by structure growth in the InAlGaN material system, while wavelengths above 1060 nm can use the InP / InGaAsP material system. x Ga 1-x As or InAlGaP. For emission of 630 nm to 700 nm, the quantum wells and other active region layers can be from the InAlGaP material system. For 700 nm to 860 nm, the active region layers can include AlGaAs material, while for 870 nm to 1060 nm, the quantum wells can include InGaAs and AlGaAs or GaAsP spacer layers. Wavelengths below 630 nm and above 1060 nm can also be implemented. For example, wavelengths below 630 nm can be implemented by structure growth in the InAlGaN material system, while wavelengths above 1060 nm can use the InP / InGaAsP material system.

[0153] An etch can be performed to reach the base, leaving the emitter mesa. Then, metal contacts can be deposited on the base and emitter layers. Another etch can be performed that extends beyond the oxide layer and to or beyond the active layer region. After the oxide layer is exposed, a wet oxidation step can be used to partially oxidize the layer. However, timing is required to leave the region in the middle of the mesa unoxidized so that current can flow through this region. After oxidation, deposition of a protective nitride layer covering all of the mesas and metal is performed.

[0154] Next, a planarization layer can be deposited, which includes a material that fills the etched trenches (such as BCB or polyimide), followed by a second protective nitride. Next, the nitride material can be etched to open the metal pads, contact should be made between the contact metal and the subsequent interconnect metal layer. After that, interconnect metal can be deposited that connects the rows and columns of VCSELs to bond pads at the edge of the chip. The substrate can then be thinned to the desired chip thickness, followed by deposition of a metal cathode contact on the backside of the wafer. At this point, the wafer can be tested at the wafer level, and then diced into individual VCSEL chips.

[0155] Figure 37 A cross-sectional view of the final VCSEL array 3700 after the fabrication process described above is complete is shown. The VCSEL array 3700 includes two VCSELs that share a common emitter contact. The arrows at the top of the figure show where the laser light is emitted from the top surface of the chip.

[0156] VCSEL with integrated photodetector

[0157] As described previously, it is also important in an illumination module to be able to monitor and potentially control the output power of the VCSELs. This can be done with a photodetector, and integrating the detector with the VCSEL chip in the same chip can help with additional miniaturization of the VCSEL based illumination module. Methods for such integration are described below.

[0158] Figure 38 A conventional VCSEL array 3802 and a VCSEL array 3804 with integrated photodetector according to various embodiments are shown. The VCSEL array 3802 is a typical VCSEL array die design or layout. The die is depicted from the top surface of the VCSEL die, which includes 812 VCSEL apertures, shown as small circles. A common metal layer connects all of the VCSEL apertures together so that they turn on and off together. The VCSEL light is emitted from the top surface.

[0159] Figure 5- Figure 8 How a VCSEL die such as the VCSEL array 3802 can be combined in a package with a separate photodiode is shown. In these package examples, the VCSEL die is placed on top of or next to a photodetector die. Figure 5- Figure 8A side view or cross-section of the package is shown. The purpose of the package is to facilitate electrical and optical interfacing with the chip. VCSELs are diodes, therefore requiring contacts to the anode and to the cathode for operation. Since the substrate of a VCSEL is typically conductive, this is achieved by attaching the VCSEL to the package using conductive epoxy or solder between the VCSEL substrate and the package. Other contacts can be formed by wire connections to metal interconnect pads on the top side of the chip.

[0160] However, the illumination sub-assembly can be further miniaturized by integrating the optical power monitor onto the same chip as the VCSEL array, as this brings the monitor closer in physical proximity. The VCSEL array 3804 is an example of such a design. In this case, the VCSEL array 3804 is divided into two segments, 3806 and 3808. The larger segment (segment 3806) is an array of VCSEL emitters that generate optical power. The VCSELs in this array have a common cathode (on the back of the chip) and a common anode (all VCSELs share a common metal). These devices are forward biased to emit light. The smaller segment of the VCSELs (segment 3808) serves as a photodetector and shares the cathode (on the back of the chip) with the larger VCSEL array but has separate anode contacts. The smaller group of VCSELs shares an anode with each other but is separated from the anode of the larger array. To be used as a monitor of optical power, this segment will be reverse biased.

[0161] In the example VCSEL array 3804, larger segments 3806 may include hundreds of VCSELs (specifically, such as...). Figure 38 As shown, there are 427 VCSELs in the segment 3808, while the smaller segment 3808 may include 7 VCSELs, but the number and ratio of VCSELs in each segment can vary. The number of VCSELs in the smaller segment 3808 can be up to 25% of the VCSELs on the chip, but can be as small as a single VCSEL. Such smaller segments can be arranged in a variety of ways, including 2D arrays or 1D arrays.

[0162] Figure 39 A circuit diagram 3900 is shown of a VCSEL array having an integrated photodetector connected to a power supply, according to various embodiments. Circuit diagram 3900 shows a shared cathode connection to two segments of the VCSEL array (e.g., segments 3806 and 3808). The larger segment is forward biased to emit light, and the smaller segment is reverse biased to detect the light signal.

[0163] Figure 40Another VCSEL array with integrated photodetectors 4000 is shown, according to various embodiments. In this layout, the smaller segments 4004 are located in the middle of the array, surrounded by the larger segments 4002. This allows the smaller segments 4004 to more evenly sample the light emitted from the chip. In alternative embodiments, there can be multiple small VCSEL segments / photodetectors around the die (e.g., one segment on each corner).

[0164] One limitation of using a small standard VCSEL array as an optical power monitor is that the small aperture limits the area that accepts light, thereby limiting the overall responsivity of the monitor photodiode. A solution to this limitation is shown in Figure 41 Figure 41 Another VCSEL array with integrated photodetectors is shown, according to various embodiments. In this example, the smaller segments 4102 used as photodetectors can include one large aperture, rather than several small apertures as shown in Figure 38 and Figure 40 The aperture can be any shape, such as circular or rectangular. The segments 4102 can also be placed anywhere on the chip as described with respect to Figure 40 The metal contacts surround the open area to connect to the anode side of the device, but the total detection area can be an order of magnitude larger compared to using a standard individual VCSEL, thereby significantly increasing the size of the signal detected.

[0165] However, this approach in turn creates a limitation that can be minimized by changing the design. As the aperture size of the monitor diode gets larger, the carrier transit time increases. This is less of an issue if the average power is being measured, but if the rise time of a pulse or series of pulses is being measured, then a large area can slow down the response, making it more difficult. Figure 42 Another VCSEL array with integrated photodetectors is shown, according to various embodiments. The smaller segments 4202 in the VCSEL array can be divided into smaller areas with narrow metal contacts 4204 between the smaller areas. Figure 43 The example shown in

[0166] Another issue to address is the wavelength sensitivity of the monitor photodiode area, if it is based solely on the standard VCSEL epitaxial layers, in addition to the reverse bias. Figure 43 ​is a graph showing the reflectance spectrum of the semiconductor layers of a substrate forming a VCSEL according to various embodiments. The two mirrors with an air gap in between form a Fabry-Perot structure, which is highly reflective except at the resonant wavelength. In Figure 43 The graph of reflectivity versus wavelength shown in FIG. 3, taken from a 795 nm VCSEL wafer, the reflectivity is high (close to 100%) between 754 nm and 844 nm. The reflectivity drops at about 794 nm, which is the resonant wavelength of the cavity. This is the wavelength at which light can escape from the cavity and enter the cavity. Thus, this is nominally the wavelength at which the VCSEL array will emit laser light, but also the wavelength at which the diode will most efficiently detect light when reverse biased. When the incident light deviates from this wavelength, the responsivity of the detector drops sharply, as most of the light in the light will be reflected and not enter the cavity to be detected. If the light from the VCSEL on the same chip is monitored, this can not be considered a problem, as the wavelength should match. However, as the VCSEL is driven with more and more current, more energy is converted to heat and the junction temperature of the VCSEL rises. In turn, the resonant wavelength will shift slightly to longer wavelengths. On the other hand, the heat dissipated in the photodiode monitor is much less, so the shift in the peak responsivity wavelength of the reverse biased section is much less. In this way, the resonant wavelengths of the forward biased VCSEL and the reverse biased photodiode monitor can become misaligned. There are a few ways to address this effect. One way is to add a dielectric or other optically transparent layer on the surface, which can reduce the reflectivity of the resonant cavity and broaden the resonance. If a dielectric is added to the VCSEL, the desired wavelength is λ / 2. At this thickness, the dielectric is transparent and does not affect the finesse or wavelength of the cavity. However, if the dielectric on the photodiode is changed to λ / 4, this will reduce the reflectivity and broaden the resonance spectrum width. This is relatively easy to achieve by using a mask where material is selectively removed from the surface of the photodiode.

[0167] Figure 44A second method for reducing wavelength sensitivity and increasing responsivity is shown, which shows a standard VCSEL 4402 and a VCSEL 4404 with reduced wavelength sensitivity and integrated photodetector according to various embodiments. The VCSEL 4402 includes a bottom dielectric mirror, a top dielectric mirror, and a quantum well active region, which together form a Fabry-Perot cavity. Metal contacts are made to the top and bottom, and a partial oxide layer provides current confinement through the structure. A dielectric layer with an integer number of half- wavelength thickness can be deposited on the top surface. The VCSEL 4404 is a modification of the VCSEL 4402 in order to produce a monitor diode with less wavelength sensitivity. By etching down through the top mirror, an etched region 4406 is formed that reduces the mirror reflectivity and widens the transmission line width in the structure. The surface of the etched region 4406 can be somewhat rough, further reducing the reflectivity, while also allowing beams that are off normal incidence to more easily enter the cavity and be detected. This can also be accomplished by masking the VCSEL regions to protect them from this etch, and etching only the region that forms the photodiode monitor.

[0168] Figure 45 Another VCSEL 4500 with reduced wavelength sensitivity and integrated photodetector according to various embodiments is shown. In this case, additional layers are grown on top of the VCSEL epitaxial structure, including an upper doped (i) layer and an n-doped (n) layer. This forms a pin junction for the photodiode that shares the p-contact with the top of the VCSEL. This structure also requires the addition of a third metal that contacts the top n-doped layer in the epitaxial structure. As before, the VCSEL array is forward biased, and the photodiode monitor is reverse biased. In this method, the detection layer is outside of the VCSEL cavity, and therefore has reduced wavelength sensitivity. Additionally, the thickness of the i- and n-layers can be adjusted to optimize the responsivity. However, this method requires additional epitaxial growth and processing. The entire structure can be grown together, and then the additional “i-” and “n-” layers are etched away from the area of the VCSEL that is processed. It is also possible to only grow the standard VCSEL structure and then protect the VCSEL region with a dielectric, while separately growing the additional “i” and “n” layers, and removing any material deposited on the surface of the dielectric by selective etching. Either manufacturing method uses an additional lithography step to achieve the final structure.

[0169] An additional issue with integrating a VCSEL array and photodiode on the same chip is optical cross-talk. When laser light is emitted vertically from each VCSEL aperture, additional spontaneous emission can occur at the p-n junction. This emission is not directional, so it can travel through the epitaxial layers to an adjacent device. Thus, in addition to light that is emitted from the VCSEL and reflects or scatters from the external surface, the monitor diode can also detect light from an adjacent VCSEL. Since the spontaneous emission does not track the laser light emitted from the VCSEL well, cross-talk can lead to inaccurate results if the goal is to track the emitted laser light.

[0170] The solution to this problem is to optically isolate the monitor photodiode from the lateral light transport. This is shown in Figure 46 Figure 46 A VCSEL with metal-filled trenches 4602 and integrated photodetector is shown according to various embodiments. Figure 46 The cross-sectional view on the left shows the location of the trench 4602 within the epitaxial structure of the VCSEL. To provide optical isolation, a trench 4602 is etched between the two types of devices. This trench is filled with an optically absorbing material such as metal. The metal will typically be highly absorbing, and thus will prevent spontaneous emission from the VCSEL from reaching the photodiode. Figure 46 The top view of the VCSEL chip on the right shows the region with the VCSEL array and the photodiode region. This figure shows the boundary region between the two, where the metal is filled. The trench can be filled with other absorbing materials.

[0171] Incorporating a monitor photodiode into the same chip as a VCSEL or VCSEL array can simplify monitoring of the output power of a VCSEL array. This can help control the output power to maintain a desired signal-to-noise ratio, to keep the output power within eye safety levels, or to monitor the rise and fall times of the VCSEL pulses. Multiple approaches have been presented to integrate a monitor diode into the chip, as well as tradeoffs between photodiode design and performance and manufacturing simplicity.

[0172] VCSEL with integrated optics

[0173] Another design approach to miniaturize the size of the illumination module is to integrate optics such as lenses, diffractive optical elements, diffusers directly on the chip. This can be done on the top side of the chip, but it is typically preferred to add the optics to the back side of the chip, in combination with a back side emission design.

[0174] Figure 47 ​A VCSEL die 4700 with integrated optics is shown, according to various embodiments. The VCSEL die 4700 incorporates VCSEL illumination, beam shaping optics, and the function of driving the VCSELs to achieve fast pulse rise times, while reducing size and cost. The VCSEL die 4700 includes a VCSEL array designed to allow for VCSEL flip-chip bonding to a substrate, with emission from the substrate side of the chip. In this case, the GaAs substrate remains in place, so this approach will work for devices with emission wavelengths greater than 870 nm, but preferably greater than 920 nm. For shorter wavelengths, the GaAs substrate can be reduced or removed. However, the die 4700 will be suitable for mobile device or LiDAR applications, which typically specify wavelengths in the 940 nm range. The die 4700 is shown with the top side down, as it will be attached to a submount or package. Electrical contacts are made to the top surface of the chip, which is typically p-type doped, while the second connection is made by etching through the top mirror structure to the bottom n-mirror, or to the n-doped buffer layer below the n-mirror, or even to the GaAs substrate. As shown, metal contacts to this layer are brought to the surface by metal traces along the sidewalls to the top surface, or by plated metal contacts, or using a stud bumping process. Figure 47

[0175] The GaAs substrate shown can be several hundred microns thick. The wafer backside, on which the die 4700 is built, can be polished and / or an anti-reflective coating can be deposited on the wafer backside. To form the optics, a curable polymer material can be deposited on the wafer backside. This deposition can be performed by lamination, spin coating, spray coating, or various other deposition techniques. A tool that has been machined with the inverse image of the engineered diffuser pattern can be used to imprint this pattern into the polymer. The polymer is then cured. The polymer can be a material that withstands subsequent chip assembly procedures, such as solder reflow.

[0176] Figure 48 Another VCSEL die 4800 with integrated optics is shown, according to various embodiments. The VCSEL die 4800 is shown with the top side down, with the same chip design as the VCSEL die 4700 in Figure 47 Figure 48 ​​A one-to-one correspondence between VCSELs and lenses is shown, and this design can be used for calibration, focusing, or controlling the divergence of the VCSELs. However, other options exist. For example, the lens structure can be randomized with respect to the VCSEL structure, there can be a many-to-one or one-to-many relationship between lenses and VCSELs, or the lenses can be offset with respect to the VCSELs so as to beam-steer each VCSEL in a different direction. One or more diffractive gratings can also be patterned on the backside of the wafer.

[0177] Figure 49 Another VCSEL die 4900 with integrated optics is shown, according to various embodiments. The VCSEL die 4900 is shown with the top side facing down, with the same chip design and the same deposition of curable epoxy on the back surface as the VCSEL die 4700 in Figure 47 A via can be etched in the polymer material to allow metal contact to the substrate. Metal traces can be patterned on top of the substrate and / or the polymer material. The metal will include thin contact bars 4902 so that most of the polymer material is not covered by metal. The contacts 4902 can be used to detect any possible delamination of the polymer or the formation of cracks in the polymer from the back of the chip, thereby detecting any possible situation that can create an eye safety risk. This method works best if the GaAs substrate is not doped.

[0178] Figure 50 Another VCSEL die 5000 with integrated optics is shown, according to various embodiments. The VCSEL die 5000 is shown with the top side facing down, with the same chip design. As in the VCSEL die 4700 in Figure 47 the curable epoxy on the back of the VCSEL die 4700, and the etching or imprinting of a pattern into the polymer as shown in Figure 48- Figure 49 but this polymer now acts as a mask 5002 for transferring the pattern directly into the GaAs substrate. This can be achieved using dry etching, for example. The advantage of this method is that the pattern cannot now be removed from the substrate.

[0179] Figure 51 Another VCSEL die 5100 with integrated optics is shown, according to various embodiments. The VCSEL die 5100 is shown with the top side facing down, with the same chip design and the same deposition of curable epoxy on the back as the VCSEL die 4700 in Figure 47 In this structure, a dielectric layer 5102 is also deposited or bonded to the back of the wafer, followed by the deposition and imprinting or patterning of the polymer. This can be done for several reasons: to provide protection for the die, to provide some structural support if the GaAs substrate is very thin or is removed completely, and to provide insulation for the electrical circuit from the conductive substrate to detect if the diffuser layer has been peeled off the chip.Figure 51 A similar method of adding a continuous layer with metal contacts for detecting if the optical layer has been delaminated from the dielectric layer is also shown, as previously described with respect to Figure 49 .

[0180] Figure 52 Another VCSEL die 5200 with integrated optics is shown according to various embodiments. The VCSEL die 5200 is shown with the top side facing down, with the same chip design as Figure 47 The same deposition of curable epoxy resin on the back side as the VCSEL die 4700 in FIG. 4B can be implemented to serve as a transfer layer. The VCSEL die 5200 can also include a dielectric layer 5202 placed on top of the GaAs substrate (or in place of the GaAs substrate), where the pattern etched or imprinted into the polymer has been transferred into the dielectric by etching.

[0181] Figure 53 Another VCSEL die 5300 with integrated optics is shown according to various embodiments. The VCSEL die 5300 is shown with the top side facing down, with the same chip design as Figure 47 the VCSEL die 5000 in FIG. 5A. In this case, pockets 5302 have been etched into the GaAs substrate, with unetched posts 5304 between the pockets 5302. Each VCSEL can have one pocket, or one pocket for the entire VCSEL array or subset of the array. In this case, diffuser or lens structures 5306 have been created on another transparent substrate, which can be glass or other transparent dielectric, polymer, or a polymer layer on glass. This layer can be created by etching, imprinting, or any other technique. In this case, the structures 5306 are mounted with the optically patterned side facing down, facing the GaAs wafer. This substrate can be attached at wafer scale by wafer-to-wafer bonding using van der Waals forces, by using adhesive materials. While Figure 53 The lens structures 5306 are shown as a diffuser pattern distributed uniformly across the wafer, but the attachment strength can be enhanced by patterning the optical wafer to have unpatterned regions of unetched posts attached to the GaAs substrate.

[0182] Figure 54 Another VCSEL die 5400 with integrated optics is shown according to various embodiments. The VCSEL die 5400 is shown with the top side facing down, with the same chip design as Figure 53similar design to the VCSEL die 5300 in FIG. 53. In this case, a patterned conductive epoxy, solder layer, or metal sinter film attachment 5402 can also be used to attach the lens structure. The attachment 5402 can be achieved with metal contacts patterned on both or one or the other of the GaAs and the transparent optical wafer, with solder or epoxy adhered to the other side. This same method can be applied to the fabrication of a VCSEL die with integrated optics similar to the VCSEL die 5400 in FIG. 54. Figure 48 VCSEL structure aligned lens array.

[0183] Figure 55 Another VCSEL die with integrated optics 5500 is shown in accordance with various embodiments. The VCSEL die 5500 is shown with the top side facing down, with a similar design to the VCSEL die 5300 in FIG. 53. Figure 53 VCSEL die 5400 in FIG. 54. In this version, the pockets are etched first into the GaAs substrate. Then, a diffuser pattern 5502 can be etched into the bottom of each pocket using various methods including those already discussed. For example, a polymer or photoresist can be deposited with a pattern etched or imprinted into the polymer, or a pattern transferred into the photoresist using a gray scale mask. The pattern can then be transferred into the GaAs using dry etching. The photoresist mask can be used to protect the posts. This method allows the diffuser, lens, or grating pattern to be protected during subsequent processing of the wafer. A non-patterned, flat, transparent glass or polymer wafer can be attached to the back of the wafer in order to provide additional protection for the optics during testing, and also provide additional structural stability for the processing of the wafer.

[0184] Another consideration is how a VCSEL chip structure with integrated optics can be combined with monitor photodiodes and / or driver circuitry. Figure 56 A VCSEL die with integrated optics 5600 combined with a photodetector 5602 is shown in accordance with various embodiments. The VCSEL die 5600 is shown with the top side facing down, with a similar design to the VCSEL die 5400 in FIG. 54. Figure 54 VCSEL die 5400 in FIG. 54. The VCSEL die 5600 can be attached to a circuit board or submount with solder or bump bonds fabricated on the die, and a photodetector 5602 (e.g., a photodiode) placed on the same circuit board or submount in close proximity to the VCSEL die. The submount can be composed of ceramic, leadframe, semiconductor, or circuit board material. A percentage of the light can be transmitted through the optical layer used as a waveguide, and subsequently scattered back from the diffuser. The adjacent photodetector 5602 captures this scattered light, and the detected signal will track the size of the light emitted from the VCSEL die 5600.

[0185] Figure 57Another VCSEL die 5700 with integrated optics combined with photodetectors is shown in accordance with various embodiments. The VCSEL die 5700 is shown with the top side facing down, with a similar design to the VCSEL die 5400 in Figure 54

[0186] Figure 58 Another VCSEL die 5800 with integrated optics combined with photodetectors is shown in accordance with various embodiments. The VCSEL die 5800 is shown with the top side facing down, with a similar design to the VCSEL die 5400 in Figure 54

[0187] Figure 59 A VCSEL die 5902 with integrated optics combined with photodetectors 5904 and driver circuitry 5906 is shown in accordance with various embodiments. The VCSEL die 5902 is shown with the top side facing down, with the same chip design and deposition of curable epoxy on the backside as the VCSEL die 4700 in Figure 47

[0188] Figure 60 ​​​Another VCSEL die with integrated optics 6002 combined with photodetector 6004 and driver circuit 6006 is shown, according to various embodiments. The VCSEL die 6002 is shown top side down, with the same chip design and same deposition of curable epoxy on the back surface as the VCSEL die 4700 in Figure 47 The subassembly uses a silicon interposer 6008 to integrate and connect the Si driver IC 6006, the silicon-based photodetector 6004, and the VCSEL die 6002. In this case, the photodetector 6004 is fabricated in the silicon interposer, but the interconnects are also fabricated within the silicon. Both the driver IC 6006 and the integrated VCSEL array die 6002 are bump-bonded to the silicon interposer 6008, with the integrated VCSEL array die bump-bonded on top of the interposer. As in Figure 59 As in the case of 5400 in FIG. 5B, the anode metal on the VCSEL array has an opening over the emission aperture of the VCSELs, so that a small amount of light emitted in that direction will reach the photodiodes.

[0189] Figure 61 Another VCSEL die with integrated optics 6100 is shown, according to various embodiments. The VCSEL die 6100 is shown top side down, with a similar design as the VCSEL die 5400 in Figure 54 Figure 61 A variation of the method that allows many of the techniques described herein to be used for shorter wavelength VCSELs is shown. In this case, the etching of the recess 6102 into the GaAs substrate is carried out all the way to the backside mirror, with a frame of GaAs substrate left around the emission area of the VCSEL or VCSEL array. Subsequent attachment of a glass or polymer wafer containing the optics helps to provide mechanical stability to the structure for subsequent sawing and handling.

[0190] Figure 62 VCSEL dies with integrated optics combined with photodetectors and driver circuits are shown, according to various embodiments. Subassembly 6202 shows an integrated VCSEL die bump-bonded directly to a Si driver IC, while subassembly 6204 shows a VCSEL bump-bonded to a Si driver IC with an embedded photodetector. In this case, the photodetector is fabricated inside the silicon driver IC. As in Figure 59 As in the case of 5400 in FIG. 5B, the anode metal on the VCSEL array has an opening over the emission aperture of the VCSELs, so that a small amount of light emitted in that direction will reach the photodiodes. The attachment / bonding of the VCSEL to the Si driver IC can be performed at the die level or wafer level with direct bonding techniques using copper pillars or micro-bumps.

[0191] Figure 63 ​Another VCSEL die 6300 with integrated optics combined with photodetectors is shown in accordance with various embodiments. The VCSEL die 6300 is shown with the top side facing down, with the same chip design and deposition of curable epoxy on the back surface as the VCSEL die 4700 in Figure 47 In this case, a subset of the VCSEL structures in the array (e.g., the rightmost VCSEL in Figure 63 In this case, a subset of the VCSEL structures in the array (e.g., the rightmost VCSEL in

[0192] Figure 64 Another VCSEL die 6400 with integrated optics combined with photodetectors is shown in accordance with various embodiments. The VCSEL die 6400 is shown with the top side facing down, with a similar design as the VCSEL die 5000 in Figure 50 In this case, a subset of the VCSEL structures in the array (e.g., the rightmost VCSEL in Figure 64 In this case, a subset of the VCSEL structures in the array (e.g., the rightmost VCSEL in

[0193] Figure 65 Another VCSEL die 6500 with integrated optics is shown in accordance with various embodiments. The VCSEL die 6500 is shown with the top side facing down, with a similar design as the VCSEL die 5000 in Figure 54VCSEL die 5400 in FIG. 54. In this case, a silicon wafer is etched all the way through the wafer to form an open grid. This wafer is then attached to the substrate side of a GaAs wafer to form a spacer 6502 with a silicon frame around each die. The silicon wafer can be attached with van der Waals forces, adhesive, metal solder, or any other method. It can be attached to the original GaAs substrate, or the GaAs substrate can be thinned or removed before attachment. After the GaAs VCSEL wafer and silicon spacer frame are joined together, an optical wafer can be attached to the other side of the silicon frame. The optical devices can face the frame or face outward, but facing the frame will provide greater protection for the optical devices.

[0194] Unless otherwise stated, the use of the word "substantially" can be construed to include exact relationships, conditions, arrangements, orientations, and / or other characteristics that vary by only minor amounts from the recited relationship, condition, arrangement, orientation, and / or other characteristic, unless specifically stated otherwise.

[0195] Throughout the entirety of this disclosure, the use of the articles "a" and / or "an" and / or "the" to modify a noun can be understood to be convenient language and includes one or more of the modified noun unless otherwise indicated. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there can be additional elements other than the listed elements.

[0196] The foregoing description of implementations of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. An illumination module, comprising: an array of vertical cavity surface emitting lasers (VCSELs) that emit light; a driver configured to provide current to the array of VCSELs; and an optical element configured to receive the light emitted by the array of VCSELs and output a light pattern from the illumination module, the array of VCSELs is partitioned into a first VCSEL segment and a second VCSEL segment, the first VCSEL segment is configured to emit light, and the second VCSEL segment is configured to detect light emitted by the first VCSEL segment, wherein VCSELs in the first VCSEL segment share a first common anode and a first common cathode; and wherein VCSELs in the second VCSEL segment share the first common cathode with VCSELs in the first VCSEL segment, and further share a second common anode that is separate from the first common anode. At least one VCSEL in the array of VCSELs comprises a multiple-junction VCSEL.

2. The lighting module of claim 1, wherein, The at least one VCSEL comprises an integrated heterojunction bipolar transistor (HBT).

3. The lighting module of claim 2, wherein, The array of VCSELs is a bottom-emitting VCSEL.

4. The lighting module of claim 1, wherein, At least one VCSEL in the array of VCSELs comprises an integrated HBT.

5. The lighting module of claim 1, wherein, The at least one VCSEL is a bottom-emitting VCSEL.

6. The lighting module of claim 5, wherein, Each VCSEL in the array of VCSELs comprises an integrated HBT and the array of VCSELs comprises a plurality of rows and a plurality of columns.

7. The lighting module of claim 1, wherein, Each VCSEL in each row shares a common emitter of the integrated HBT, and each VCSEL in each column shares a common base of the integrated HBT, such that each VCSEL in the array of VCSELs is individually addressable.

8. The lighting module of claim 7, wherein, At least one VCSEL in the array of VCSELs is a multiple-junction VCSEL.

9. The lighting module of claim 8, wherein, The first VCSEL segment is forward biased, and the second VCSEL segment is reverse biased.

10. The lighting module of claim 1, wherein, At least one VCSEL in the first VCSEL segment is a multiple-junction VCSEL.

11. The lighting module of claim 1, wherein, At least one VCSEL in the first VCSEL segment comprises an integrated HBT.

12. The lighting module of claim 1, wherein, The optical element is integrated into the array of VCSELs.

13. The lighting module of claim 1, wherein, The optical element is deposited onto a substrate of the array of VCSELs.

14. The lighting module of claim 13, wherein, The illumination module further comprises a photodetector located proximate to the array of VCSELs.

15. The lighting module of claim 13, wherein, The illumination module further comprises a photodetector located on top of the optical element.

16. The lighting module of claim 13, wherein, At least one VCSEL in the array of VCSELs is a multiple-junction VCSEL.

17. The lighting module of claim 13, wherein, At least one VCSEL in the array of VCSELs comprises an integrated HBT.

18. The lighting module of claim 13, wherein, The array of VCSELs is flip-chip bonded on a substrate, the substrate comprising the driver and a photodetector.

19. The lighting module of claim 13, wherein, The array of VCSELs is flip-chip bonded on a silicon interposer, the silicon interposer connected to the driver, wherein the silicon interposer comprises a photodetector.

20. The lighting module of claim 13, wherein, ​

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