surface-emitting laser

Abstract

The enhanced vertical cavity surface emitting laser (VCSEL) includes an epitaxially laterally overgrown semiconductor portion comprised of a III-nitride active region between a hole-injection III-nitride layer and an electron-injection III-nitride layer, an angled p-type mirror on the hole-injection side, and a planar mirror angled relative to the III-nitride active region, the planar mirror including a nanoporous layer on the electron-injection side and a non-porous layer on the n-side.

Description

[Technical Field]

[0001] The present invention relates to a III-nitride vertical cavity surface emitting laser (VCSEL) with a nanoporous GaN DBR. [Background technology]

[0002] This application refers to a number of patent and non-patent publications by reference numbers in brackets, i.e., [ ], as set forth throughout this specification. A list of publications arranged according to these reference numbers can be found below in the sections entitled "Non-Patent Publications" or "Patent Publications." "Quote List" "Non-patent literature"

[0003] [NPL1] Appl.Phys.Lett.Volume 92, Page 141102 (2008) [NPL2] Appl.Phys.Express, Vol. 12, p. 044004 (2019) [NPL3] Sci.Rep., vol. 8, pp. 10350 (2018) [NPL4] Jpn.J.Appl.Phys.Vol.58, SC0806(2019) [NPL5] Appl.Phys.Express, Vol. 11, pp. 112101 (2018) [NPL6] Appl.Phys.Lett.Volume 101, Page 151113 (2012) [NPL7] ACS Photonics, vol. 2, pp. 980-986 (2015) [NPL8] Sci.Rep., vol. 7, pp. 45344 (2017) [NPL9] Appl.Phys.Lett.Volume 112, Page 041109 (2018) [NPL10] Scr. Mater, vol. 156, pp. 10-13 (2018) [NPL11] Appl.Phys.Express 2012, Vol. 5, pp. 092104 [NPL12] Optics Express, Volume 27, Page 24717 (2019) [NPL13] Appl.Phys.Express, Volume 13, Page 041003 (2020) [NPL14] Appl.Phys.Express, Volume 14, Page 031002 (2021) [NPL15] Applied Phys. Lett. Volume 119, Page 142103 (2021) [NPL16] Crystals, Vol. 11, No. 12, 1563, (2021) [NPL17] M.B. Stern and T.R. Jay, "Dry etching for coherent refractive microlens arrays," Opt. Eng. 33, 3547-3551 (1994)

[0004] Surface-emitting lasers are known as vertical-cavity surface-emitting lasers (VCSELs). VCSELs contain a semiconductor active region disposed between n-side and p-side semiconductor regions and two distributed Bragg reflectors (DBRs) that function as highly reflective mirrors. The semiconductor active region, also known as the gain medium, is disposed between the two DBRs to form an optical cavity. The n-side and p-side regions inject carriers, i.e., electrons and holes, into the active region, where they recombine to generate light. The light or electromagnetic radiation thus generated travels through the optical cavity, reflecting multiple times off the DBRs, resulting in lasing. One of the DBRs in a VCSEL is a less reflective mirror and is used to emit the laser beam.

[0005] Gallium nitride (GaN) VCSELs have recently attracted increasing research attention due to their ability to emit light in the visible and ultraviolet (UV) regions. This opens up a variety of new application spaces in displays, solid-state lighting including automotive and residential lighting, sensing, and communications. Due to VCSELs' lower energy consumption and faster modulation speeds, one of the most exciting applications is where blue-emitting GaN VCSELs coupled with phosphor devices collectively function as a spontaneous emission source and data transmission device. This application could reshape AR / VR applications, smartphones, and conventional displays by adding communications capabilities to each emitting pixel.

[0006] While GaAs-based infrared VCSELs have adopted mature fabrication techniques, III-nitride-based VCSELs are still not commercially viable. Continuous-wave (CW) lasing at 462 nm from electrically injected GaN VCSELs was first demonstrated at a temperature of 77 K in 2008 [NPL1]. Since then, considerable progress has been made in terms of output power, efficiency, threshold current, lasing wavelength, and room-temperature stability. However, industrial viability has not yet been achieved. One problem is the n-side DBR mirror, which is typically a dielectric DBR that causes thermal instability in device operation. Traditionally, a dielectric DBR is deposited on the n-side of the VCSEL after carefully polishing the host substrate. Alternative approaches, such as epitaxial DBRs and nanoporous GaN DBRs, have been grown on top of the host substrate, and long optical GaN cavity VCSELs have been proposed in the literature for better thermal stability.

[0007] While these approaches have been successful to some extent, even for long cavities and nanoporous GaN DBR cavities, issues must be addressed, such as expensive GaN substrates, increased growth times for epitaxial DBRs while maintaining the quality of the device layers, and expensive methods for delaminating the GaN substrates.

[0008] VCSELs with long optical cavities and curved lenses refocus the electric field into the gain medium, thereby reducing diffraction losses due to the long cavity length [NPL2–NPL4]. Until 2022, Sony's long cavity design held the performance record with 15.8 mW CW output power, a threshold current of 0.25 mA, and a wall-plug efficiency (WPE) of 9.5%. Long optical GaN cavity VCSEL designs achieve excellent results by utilizing a significant portion of the host substrate in the cavity design. The substrate is redesigned with curved mirrors after grinding away the unnecessary portions, a process that is also tedious, time-consuming, and expensive. Curved mirrors are necessary in long optical cavity designs because they prevent diffraction and scattering losses. Because the typical gain in the active region of a nitride VCSEL is ~1%, in long optical GaN cavities, diffraction losses can rapidly degrade device performance for cavities longer than 10 micrometers. Sony's curved mirror VCSEL cavity is ~28 micrometers. This will essentially result in the greatest amount of difficulty with polishing as the cavity approaches the active region.

[0009] Meanwhile, epitaxial designs using AlGaN / GaN or AlInN / GaN mirror pairs have also recently attracted attention [NPL5-NPL6], and the latter have shown excellent performance due to the lattice matching ability of AlInN to GaN. However, the need for more than 40 AlInN / GaN layers to achieve reasonable reflectivity (>99.5% on the emitting side) and maintaining uniform growth conditions for better quality and improved yields can make epitaxial DBR designs difficult to achieve.

[0010] More recently, nanoporous GaN DBR (NP-GaN DBR) designs [NPL7–NPL10] have also gained popularity due to their relative ease of fabrication, their lattice match to GaN, and their high achievable refractive index difference. This high index difference allows a 99.5% reflectivity to be achieved with only 17 periods at a realistic porosity of 36%. Since the first NP-GaN DBR was first demonstrated in 2015, several groups have successfully achieved lasing with NP-GaN DBR designs. NP-GaN DBR layers offer better thermal stability than dielectric DBR mirrors. However, the common challenge of thinning and grinding the expensive host GaN substrate after realizing the NP-GaN DBR layer on the substrate remains.

[0011] An ideal VCSEL should be able to address the following concerns in an effective manner: 1) Better crystalline quality of III-nitride layers Currently, most companies are focusing their attention on fabricating III-nitride VCSELs on bulk GaN substrates. The best available III-nitride bulk substrates are 10 6 Defects / cm 2 It has the following characteristics. The active volume of VCSELs is small, about 10 times smaller than that of conventional edge-emitting lasers. Therefore, better crystal quality than existing bulk substrate quality is desirable. Furthermore, bulk GaN substrates are very expensive even with the current existing quality. Therefore, the demand for better quality will increase prices and further delay the market entry of III-nitride VCSELs. 2) Larger wafers required for better yield. In general, VCSELs are almost a copy of LED manufacturing. Most of the LEDs are manufactured on substrates with a size of 6 inches or larger. It is also natural for manufacturers to choose large substrates to enable better yields and competitive prices. 3) Thermal stability by providing a heat-conducting DBR mirror Another technical problem that has kept VCSELs from the market is the placement of the n-side DBR mirror. VCSELs are surface-emitting lasers, so they are thinned along the substrate surface. Even if an expensive bulk III-nitride substrate is first used to form the thin VCSEL device layers, the expensive III-nitride substrate must be removed from the VCSEL device to place the n-side dielectric DBR mirror, or a DBR layer that does not damage the substrate material must be placed before forming the VCSEL device layers. There are several techniques to circumvent this VCSEL manufacturing problem. Long cavity VCSEL: To avoid the need to remove the substrate to yield-reducing levels, Sony devised a long cavity VCSEL that still retains a significant amount of substrate within the VCSEL's optical cavity. While this design offers better thermal stability due to the long cavity III-nitride materials, this design has some practical limitations on the cavity length and the number of cavity emission modes. Epitaxial DBRs: As mentioned above, InGaN / GaN or AlN / GaN epitaxial DBRs have been proposed in the literature. Due to the low refractive index contrast, such ∼40 pairs of InGaN / GaN DBRs are required to achieve reflectivity above 99%. 0.82 Ga 0.18 An N / GaN lattice-matched DBR mirror layer is required. Long growth times and difficult control of In and Al compositions remain concerns. Also, heat dissipation and vertical injection issues remain. Due to low reflectivity, the emitting side is the epitaxial DBR side, so the substrate area under the epitaxial DBR mirror requires some surface treatment and sometimes grinding to reduce absorption and scattering losses. Nanoporous (NP) DBRs: Nanoporous DBRs typically have high reflectivity >99% and are grown simply lattice-matched to GaN. They are applicable to all crystallographic orientations of GaN. Furthermore, the reflectivity of the layers can be tuned. However, because the NP layers are configured parallel to the active layer of the device, this is not the ideal configuration for heat extraction or vertical carrier injection. 4) Current spreading layer in the cavity on the p-side VCSEL devices typically face a problem on the p-side due to the higher activation energy required for p-type conductivity: increased resistance of the p-GaN layer. Researchers have minimized the thickness of the p-GaN layer in VCSEL devices to eliminate Joule heating and light absorption. Reducing the thickness of the p-GaN layer and incorporating current-spreading layers such as transparent conductive oxides (TCOs) like indium tin oxide or more tunnel junctions can aid the design, but light absorption remains an issue. Researchers have cleverly positioned the intracavity conductive layers at the device's minimum electromagnetic field, but such fine-grained requirements reduce yield and increase cost. Some, but not all, of the above problems can be addressed by substrate removal techniques such as photoelectrochemical (PEC) [NPL11] and epitaxial lateral overgrowth (ELO)-assisted thermal exfoliation [NPL12-NPL16]. Summary of the Invention [Problem to be solved by the invention]

[0012] Considering all these drawbacks, it is an object of the present invention to provide a III-nitride VCSEL with a nanoporous GaN DBR, making the nanoporous GaN DBR more functional to improve the device performance in terms of thermal and optical properties. [Means for solving the problem]

[0013] To overcome the limitations of the prior art mentioned above, the present invention discloses a III-nitride based VCSEL that includes a III-nitride active region between a p-type (hole-injecting) III-nitride layer and an n-type (electron-injecting) III-nitride layer, and a flat dielectric mirror designed on or above the angled p-type III-nitride layer.

[0014] ELO growth begins with the gradual formation of III-nitride crystal planes, which can be consistently maintained by applying an appropriate growth mode with optimized parameters. Then, by periodically adjusting the sources and then doping the layers as needed, the growth plane can be more precisely altered during epitaxial lateral overgrowth. Combining the ELO technique with a growth-tuned, tilted (semipolar) III-nitride layer with a designed doping level results in a high-crystal-quality crystal plane on a dielectric mask. These selectively doped layers subsequently form porous III-nitride layers, resulting in a tilted NP-GaN DBR mirror.

[0015] The optical cavity thickness, including the device layers, n-GaN layer, active region, p-AlGaN electron blocking layer and p-GaN layer (and possibly current-spreading tunnel junction (p++ / n++GaN)), can be controlled during epitaxial growth.

[0016] The VCSEL further includes one or more tunnel junction layers on the p-side III-nitride layer for current injection, and a dielectric DBR mirror is positioned at an angle away from the tunnel junction.

[0017] Instead of a tunnel junction, the VCSEL further includes one or more transparent conductive oxide (TCO) layers on the p-type III-nitride layer as intracavity contact layers, which may be composed of indium tin oxide, ZnO.

[0018] The VCSEL further includes a region for disposing a dielectric DBR mirror on or above the p-type III-nitride region, the p-type III-nitride layer being formed at an angle with the plane of the active layer.

[0019] The VCSEL further includes an angled p-type III-nitride layer, which is one of the semipolar planes of III-nitride material obtained by either physical or chemical etching. Preferably, a combination of physical and chemical etching is used to smooth the surface for placement of the dielectric DBR mirror layer. The surface morphology of the etched semipolar plane on the p-GaN layer can be controlled by using etchants such as H3PO4 or KOH. Alternatively, acidic or basic etching methods similar to c-plane Ga polar etching with 5M NaOH can be used. Alternatively, immersion in 98% H2SO4 can be used to prepare the semipolar plane for placement of the dielectric DBR mirror layer.

[0020] The VCSEL further includes periodic selectively doped III-nitride layers on or above the dielectric mask. The selectively doped III-nitride layers are subsequently formed as nanoporous layers, while the interposed undoped bulk III-nitride layers remain non-porous. The VCSEL further comprises alternating nanoporous layers that are highly doped n-type compared to the non-porous bulk III-nitride layers.

[0021] The VCSEL is further constructed from alternating nanoporous and non-porous III-nitride layers, the combination of which constitutes a tilted n-type DBR mirror, with the layers oriented in one of the III-nitride semipolar planes.

[0022] The VCSEL further comprises a periodically modulated layer growth in the formation of a selectively doped semipolar layer, where NH, Ga metal, and an n-type doping source are periodically changed / alternated to create a sharp interface at the boundary between the nanoporous III-nitride layer and the non-porous III-nitride layer.

[0023] The VCSEL, further composed of a non-porous bulk III-nitride layer and a nano-porous III-nitride layer, has an identical interface with the dielectric mask, which is later dissolved during the device fabrication process, which can provide a gateway for vertical current injection and heat evacuation.

[0024] The VCSEL is further designed to have a smooth (sub-nanometer) interface between the sloped III-nitride n-type DBR mirror and the dielectric mask. The dielectric mask material in the III-nitride layer growth is prepared using means such as sputtering, atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), or ion beam evaporation, using SiO2 or SiN, preferably a combination of both.

[0025] The VCSEL further includes a discrete III-nitride ELO base layer that is accessible to the chemicals used in the electrochemical etching, and pore formation is achieved in the selectively doped GaN layer by electrochemical etching.

[0026] The bulk non-porous III-nitride layers of the DBR mirror have better thermal and electrical conductivity compared to nanoporous III-nitride layers. Therefore, combining these layers in an alternating periodic arrangement makes the device best suited to function as a DBR mirror as well as a thermal heat sink and electrical injector. The crystal orientation of the host substrate for the preferred invention can be c-plane, semi-polar, or non-polar, but preferably c-plane. [Brief explanation of the drawings]

[0027] [Figure 1A] FIG. 1A is a schematic diagram showing a foreign substrate with a III-nitride template. [Figure 1B] FIG. 1B is a schematic diagram showing dielectric mask open area patterning into the III-nitride growth layer. [Figure 1C] FIG. 1C is a schematic diagram showing a stripe design, each housing a VCSEL device. [Figure 1D] FIG. 1D is a schematic diagram, and FIG. 1D is a triangular lattice pattern. [Figure 1E] FIG. 1E is a schematic diagram, and FIG. 1F is an alternative approach to growing an ELO base layer using a patterned III-nitride template. [Figure 1F] FIG. 1F is a schematic diagram, and FIG. 1G is an alternative approach to growing an ELO base layer using a patterned III-nitride template. [Figure 2A] FIG. 2A is a schematic diagram of the base ELO III-nitride layer after growth. [Figure 2B] FIG. 2B is a schematic diagram of the base ELO III-nitride layer after growth. [Figure 2C] FIG. 2C is a schematic diagram of the base ELO III-nitride layer after growth. [Figure 2D] FIG. 2D is a schematic diagram of the planarized ELO base. [Figure 3A] FIG. 3A illustrates various growth modes for ELO growth of III-nitride crystals. [Figure 3B] FIG. 3B illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3C] FIG. 3C illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3D] FIG. 3D illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3E] FIG. 3E illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3F] FIG. 3F illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3G] FIG. 3G illustrates various growth modes for ELO growth of III-nitride crystals. [Figure 3H] FIG. 3H illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3I] Figure 3I illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3J] FIG. 3J illustrates various growth modes of ELO growth of III-nitride crystals. [Figure 3K] FIG. 3K illustrates various growth modes for ELO growth of III-nitride crystals. [Figure 4A] FIG. 4A shows the planarized ELO base layer of bar-shaped and hexagonal structures, respectively, showing alternating doped III-nitride layers. [Figure 4B] FIG. 4B shows the planarized ELO base layer of bar-shaped and hexagonal structures, respectively, showing alternating doped III-nitride layers. [Figure 5A] FIG. 5A is a schematic diagram of the processed VCSEL design prior to removal from the host substrate. [Figure 5B] FIG. 5B is a VCSEL fabricated with vertical current injection. [Figure 5C] FIG. 5C is a VCSEL with a tunnel junction. [Figure 5D] FIG. 5D is a VCSEL fabricated with a tunnel junction and heat spreader. [Figure 6A] FIG. 6A is a schematic diagram of a processed VCSEL having two or more optical cavities in the form of an ELO bar prior to removal from the host substrate. [Figure 6B] FIG. 6B is a VCSEL processed for vertical current injection. [Figure 6C] FIG. 6C is a hexagonal patterned fabricated VCSEL with a different optical cavity. [Figure 6D] Figure 6D shows a VCSEL fabricated in a hexagonal pattern that emits a ring of light. [Figure 7A] Figure 7A shows typical chip dimensions for an ELO bar. [Figure 7B] Figure 7B shows the wafer-scale integration of ELO bar VCSELs and hexagonal VCSELs. DETAILED DESCRIPTION OF THE INVENTION

[0028] The teachings of the present invention can be readily understood by considering the following detailed description, taken in conjunction with the accompanying drawings, which are presented by way of example only, in which: With reference to the accompanying drawings, a general overview illustrating a vertical cavity surface emitting laser (VCSEL) and a method for manufacturing a VCSEL according to the present disclosure is set forth below: For ease of understanding, where possible, identical reference numerals are used to indicate identical elements common to the figures.

[0029] In the following embodiments, a description is provided with reference to the drawings. The use of non-porous and nano-porous tilted DBR mirrors on top of ELO base layers, as well as angled DBR mirrors on the p-side of III-nitride VCSELs, has been proposed as a viable method to improve device performance in terms of thermal, optical, and electrical aspects. Technical Disclosure:

[0030] The following disclosure is divided into four sections: the first describes the preparation of the ELO base layer; the second provides information on the growth of porous and non-porous layers; and the third presents VCSEL device fabrication procedures and advantages.

[0031] Section 1: Preparation of ELO base The ELO method for forming the III-nitride semiconductor islands may include growth by metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc. The III-nitride semiconductor layers are sized to form one or more of the III-nitride semiconductor islands. Alternatively, the ELO III-nitride layers may initially be coalesced so that they can be later separated into individual devices.

[0032] The ELO layer has two portions: an aperture region, which generally has more defects than its control region extending above the ELO mask. The control region extends bidirectionally from the aperture region onto the ELO mask and is called the ELO wing. The VCSEL light-emitting aperture is formed on the ELO wing. Furthermore, the present invention may use heterosubstrates to grow the III-nitride semiconductor island layers that form the bars. For example, the present invention may use GaN templates grown on heterosubstrates such as sapphire, Si, SiC, SiN, GaAs, Ga2O3, LiAlO2, and ScAlMgO4 (SAM).

[0033] Furthermore, the ELO method can significantly reduce dislocation and stacking fault densities, which are important issues when using heterosubstrates, when non-Basel GaN crystal planes are used. Therefore, the present invention can simultaneously solve many types of problems associated with the use of heterosubstrates. For example, in a laser device, the interface between the ELO mask and the III-nitride template layer may be smoothed to prevent light emission from the interface.

[0034] 1A, 1B, and 1C are schematic diagrams illustrating a method that includes providing a III-nitride-based substrate 10, such as GaN on Si, GaN on sapphire, or a bulk GaN substrate, such as GaN on ScAlMgO (SAM). In the case of a foreign substrate 10, a III-nitride template 11 may be deposited on the substrate 10. The III-nitride template 11 may be a uniform layer on the host foreign substrate 10, or the template 11 may be arranged in open area stripes 12. A III-nitride stripe design that includes the substrate 10 is such as the stripe shown in the schematic diagram of FIG. 1C. The open area stripes 12 can be designed as a single device by shortening their length or as multiple devices by increasing their length. Alternatively, as shown in FIG. 1D, a triangular lattice of circular openings can be designed on a dielectric mask 13, with the openings exposing the underlying III-nitride layer.

[0035] 1C and 1D, a dielectric mask 13 is formed on or above a III-nitride template 11 that includes a substrate 10. Specifically, the dielectric mask 13 is disposed directly on the substrate 10, or indirectly via a template layer grown by MOCVD or the like.

[0036] The dielectric mask 13 may be formed from an insulator film, such as a SiO2 film, deposited on the substrate 10 by, for example, plasma-enhanced chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc., and then the SiO2 film is patterned by photolithography and etching using a predetermined photomask to include open areas as shown in Figures 1B and 1C. The design of this dielectric film has profound effects on subsequent device processing and operation.

[0037] In an alternative approach, the III-nitride template layer 11 on the substrate is first designed as rectangular stripes or triangular circular spots, and then filled with the above-mentioned dielectric mask, leaving the top and sidewalls partially exposed. The exposed III-nitride regions in Figure 1F or the underlying growth-assisted III-nitride regions in Figure 1B form the ELO base layer, as shown in Figure 1A or 1E.

[0038] 2A-2D, an epitaxial III-nitride layer 14, such as a GaN-based layer, is grown by ELO on a GaN-based substrate and a dielectric mask 13. Growth of the ELO III-nitride layer 14 occurs first within the open areas on the GaN-based substrate and then laterally from the open areas onto the dielectric mask 13. The growth of the ELO III-nitride layer is stopped or interrupted before the ELO III-nitride layer from adjacent open areas 12 can coalesce on the dielectric mask 13.

[0039] Alternatively, the growth of the ELO III-nitride layer may continue and merge with adjacent ELO III-nitride layers. The wings 15 of the ELO III-nitride layer are regions of reduced defect density on either side of the opening area. In the ELO growth method, the fill factor, which is the ratio between the opening area and the dielectric mask, can significantly deviate from 1, as shown in FIG. 2C, resulting in a greater accumulation of III-nitride atoms at the edges of the III-nitride layer compared to the center of the layer. This, seen as edge growth, can be detrimental if allowed to continue during the growth of device layers. In FIG. 2D, the III-nitride ELO base layer deposited in this manner is polished to obtain a flat surface. Because the surfaces of these layers are achieved using epitaxial growth, a slight chemical-mechanical polishing or dry or wet etching should be sufficient to obtain a planarized layer.

[0040] Section 2: Growth of nanoporous and non-DBR layers as ELO bases The combination of nanoporous and nonporous layers as the n-side DBR mirror of VCSELs has been found to be a promising solution for GaN-based VCSELs because it can provide better thermal stability compared to dielectric DBRs, their lattice matching ability to GaN makes them desirable for growth and fabrication, and nano- and nonporous GaN DBRs offer high refractive index contrast. For example, a nanoporous DBR layer with a porosity ranging from 10% to 75% can provide a refractive index contrast of 0.1 to 0.9, while the contrast for dielectric DBRs is only about 0.7 and that for epitaxial DBRs is less than 0.2.

[0041] Furthermore, when nanoporous and nonporous layers are aligned in a plane parallel to the active region, they provide thermal conductivities of 10-1 W / (mK) at the stated porosities. It is not uncommon for thermal conductivity to decrease with increasing porosity when these layers are aligned parallel to the device active region plane. Similarly, electrical conductivity decreases by 1000 S / m to 100 S / m due to increased electrical resistance with increasing porosity. However, when nanoporous and nonporous layers are aligned at an angle such that thermal and electrical conductivities are primarily dependent on the bulk-interface of the nonporous layer, thermal and electrical conductivities can be significantly improved, resulting in significant improvements in VCSEL operation, yield, and lifetime. The formation of nanoporous III-nitride layers has been extensively studied, and the etching procedure is well understood [NPL7]. At a constant applied bias, the size and shape of the pores are controlled by the n-type doping and the crystallographic orientation of the layer upon exposure to an oxalic acid solution during electrochemical etching (EC). As etching progresses, first, the applied negative bias creates a hole inversion layer at the electrolyte / n-GaN interface; second, the n-GaN surface is oxidized due to the presence of holes at the inversion surface; and third, the oxidized GaN is converted into Ga 3+ and nitrogen gas, which eventually becomes free to migrate into the electrolyte, leaving behind voids called nanoporous. In the present invention, the formation of porosity occurs in later processing of the VCSEL device; however, initially, alternating nanoporous and non-porous layers were carefully grown in different growth steps during the growth of the ELO base layer.

[0042] Figure 3A shows the GaN crystal structure with all possible planes, simplifying the growth situation: Planes perpendicular to the c-plane, such as the (10-10) (m-plane) and (11-20) (a-plane), are nonpolar, while crystal planes oriented between the c-plane and the nonpolar planes, such as the (20-21) (r-plane), are semipolar.

[0043] In the initial stage of ELO growth, the base seed 30 having the r-plane and c-plane shown in Fig. 3B is formed from the open area 12 of the dielectric mask 13. Alternatively, the III-nitride template 11 on the substrate 10 is etched to expose the r-plane and c-plane.

[0044] After forming the base seed 30, the growth supply parameters, NH3-source, Ga-source, are optimized to grow the r-plane and c-plane crystal orientations at a better rate and in a more timely manner, suppressing the growth of undesired crystal orientations. Over time, dopants such as silicon (Si) can be added for a specific time interval to form interfaces between doped and undoped layers of these crystal orientations.

[0045] The doped crystal orientation is then transformed into a porous III-nitride layer to form a DBR mirror. As can be seen, crystal plane orientation control can be achieved in several ways. FIG. 3C shows uniform growth of the c-plane and r-plane, resulting in a bulky III-nitride ELO base layer. In another embodiment, FIG. 3D results in impure c-plane crystal growth while maintaining significant wing growth by maintaining r-plane growth laterally. The c-plane crystal plane growth can be suppressed by providing a small amount of nitrogen source, thus resulting in a low V / III ratio growth regime.

[0046] Similar to the edge growth described in the previous section, FIG. 3E shows a non-uniform ELO base layer, with coloration or impurities in the c-plane crystal orientation likely due to absorption of impurities such as carbon.

[0047] FIG. 3G is an illustration of a different base seed 30, where the r-plane is the complementary plane of FIG. 3B. The growth parameters were controlled so that the r-plane could grow laterally on the dielectric mask to form better ELO wings. The c-plane crystal orientation growth could be controlled and the impurities accommodated. Optimized ELO base layer conditions are important.

[0048] Figures 3B-3K show conventional and tailored ELO growth methods. The key difference lies in the V / III ratio: either varying the NH3 flow rate while keeping the TMGa flow rate the same, or keeping the V / III ratio as low as possible to promote one of the r-plane growths while equally suppressing the c-plane growth. High and low V / III ratios can tailor the growth anisotropy and promote lateral growth. Of course, planarization is the final step for surface preparation before placing the VCSEL device layers on the ELO base.

[0049] Figures 3F and 3K show the planarized base diagrams. The non-porous and nanoporous III-nitride layers of the R-plane semiconductor crystal plane orientation of the periodic superlattice are unintentionally doped (UID) GaN and n+-GaN ([Si] ~ 10 19 / cm 3 )

[0050] 4A and 4B show the r-plane views of the ELO bar structure after planarization and the ELO wing of the hexagonal close-packed (HCP) structure, respectively. The device layers then include III-nitride n-GaN layer 17, III-nitride active layer 18, III-nitride p-type electron blocking layer (EBL) 19, p-type III-nitride layer 20, and p++ GaN layer 21, as shown in FIG. 5A. The VCSEL design of the present invention can utilize several current injection methods to inject current. Growth can be simply stopped at p++ GaN layer 21, or indium tin oxide can be used as a current spreading layer, or an n++ GaN layer can be grown on p++ GaN layer 21 after some surface treatment to utilize a tunnel junction.

[0051] Although the present invention utilizes intracavity layers for current injection, the light emitted from the active region is directed away from the intracavity contact layers, so the inclusion of the intracavity contact layers may or may not be an option.

[0052] Section 3: VCSEL Manufacturing Procedure After growth of the device layers, including the ELO base with the NP DBR 16 superlattice, current injection is prepared. If a tunnel junction is used, the current injection aperture 31 is formally defined during the tunnel junction implantation process. Otherwise, the current injection region 31 is separated from the optical cavity region 32 by photolithographically defining a separate, preferably circular, pattern on the ELO wings. A protective layer is then deposited over the injection region 31 and the optical cavity region 32. Next, a slightly larger mesa is prepared over the area excluding the injection region 31 and the optical cavity region 32 for contact pad placement. To meet the polarization alignment requirements of the bottom nanoporous DBR mirror, angle etching is performed on the p-type layer of the VCSEL's optical cavity region 32. The etching angle is predetermined so that light deflected from the bottom nanoporous GaN DBR 16 properly impinges on the etched p-layer. The etched area exposed the r-plane surface, which was smoothed using a chemical etchant before the placement of the dielectric DBR mirror 24. A 16-period dielectric DBR 24 consisting of SiO2 / Ta2O5 periods was then deposited on this prepared surface.

[0053] Next, a SiO2 or protective film was deposited (not shown) to protect the device from nanoporous etching and provide electrical insulation 24. Next, EC etching was performed by immersing the sample in oxalic acid under a bias voltage, etching the doped n+ GaN layer in the bottom ELO base layer into a DBR. Next, p-contact pads 33 connecting the current injection regions 31 were selectively patterned using photolithography, followed by deposition of metal contacts of Ti / Au. The resulting device is shown in Figure 5A.

[0054] Next, the VCSEL device is separated from the host substrate by either peeling or laser lift-off or chemical lift-off, followed by blanket deposition of the n-contact metal 34, resulting in the overall image shown in Figure 5B. The nanoporous GaN DBR region can be either the light-emitting side or the angled p-type layer side. In the present invention, the interface between the n-contact pad 34 and the n-DBR 16 is prepared using ELO growth and is therefore crystallographically pure, with the interface surface roughness designed to be sub-nanometer (e.g., 2 nm) without the introduction of CMP or any polishing techniques. The dielectric mask 13 used is ~300 nm thick and is preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask 13 is designed to be less than sub-nanometer so that it can be replicated on the lift-off interface. As can be seen from the overall image, the n-side DBR mirror 16 appears flat, with the bulk non-porous III-nitride layer and the nanoporous GaN layer forming the interface with the n-contact pad 34. This suggests that the thermal evacuation of the device is primarily dominated by the bulk non-porous GaN layer, which has better thermal conductivity. Similarly, the electrical conduction resistance is primarily dominated by the bulk non-porous GaN layer, and thus the described configuration allows for vertical current injection.

[0055] FIG. 5C shows the tunnel junction configuration of the current injection region 31. Growth of the device layers continues until p++ GaN is grown, after which a circular section 35 is defined to define the current aperture. Optionally, ion implantation is added to enhance current injection into the active region 18. The cut-out region of the device at the tunnel junction implant is shown in FIG. 5C, with the shaded region 36 indicating the optical cavity region that does not directly overlap with the current injection region.

[0056] Figure 5D focuses on adding a thermally conductive layer to the tunnel junction device shown in Figure 5C described above. After preparing the angled p-GaN 24 for DBR mirror placement, and preparing the current injection region 31 and contact pad placement area, an AlN heat spreading layer 37 is sputtered. Next, the p-contact pad 33 and dielectric DBR mirror 24, a 16-period dielectric DBR consisting of SiO2 / Ta2O5 periods, are deposited on top of the device as previously described. The VCSEL device is then separated from the host substrate by either thermal lift-off or laser or chemical lift-off, followed by blanket deposition of n-contact metal 34, resulting in the overall image shown in Figure 5D.

[0057] Figures 6A-6D show a simple variation of the device mentioned in Figures 5A and 5B, where at least two or more ELO wings are used to position the current injection regions. In the case of an ELO bar, two emissions can be achieved by placing two current injection regions on either side of the aperture area 12. Similarly, in the case of a hexagonal pattern, six emissions 38, as seen in Figure 6C, or a continuous ring-like emission, as seen in Figure 6D, are possible. As seen in Figure 6C, the base ELO layer is an n-type DBR mirror, but redirects the light toward the aperture area. Similarly, in Figure 6D, the current injection can be positioned as a ring, where the emission appears as a ring but is slightly shifted inward toward the aperture area. The p-contact pad 33 is positioned on the outer circle as shown, and the n-contact pad 34 is positioned on the n-side after removing the VCSEL device from the host substrate.

[0058] FIG. 7A illustrates typical chip dimensions for a single ELO bar, and FIG. 7B shows several VCSEL devices integrated on the ELO bar and hexagonal close-packed VCSEL units on the wafer.

[0059] advantage: 1. The intracavity contact layer does not overlap the optical cavity. 2. Nanoporous DBR layer used for better heat sink. 3. The graded arrangement of the nanoporous DBR reduces the electrical resistance of the device. 4. Angular release is possible. 5. Better heat management. 6. Cheaper large template substrates such as GaN on sapphire can be used to advantage. 7. High-quality and larger-sized GaN substrates are very expensive. The present ELO technique can enable the use of foreign substrates in the fabrication of VCSELs. 8. The present invention is expected to provide significant improvements in performance and reduction in manufacturing costs, as well as elimination of complex procedures.

[0060] Purpose illumination: GaN-based LEDs have brought about a dramatic change in residential and automotive lighting. Lighting combined with communication services is highly desired for future smart cities and smart infrastructures. VCSELs are a better alternative to LEDs and edge-emitting laser diodes. However, the lack of suitable profitable mass-production technology has prevented GaN VCSELs from entering the market. The procedures developed in the above embodiments can be used to mass-produce VCSEL units applicable to lighting applications. Visible Light Communication:

[0061] Laser light for future potential data transfer and communication applications through Light Fidelity (LiFi). With the rapid increase in IoT devices, the demand for data transmission continues to expand. The RF spectrum is becoming saturated, and new frequencies are needed to keep up with the continuously increasing demand. Applying GaN VCSELs to existing LED configurations is easier than replacing them with edge-emitting lasers. Therefore, the devices described in the above embodiments can serve the purpose. Near-eye display:

[0062] Near-eye displays represent the next big wave of consumer electronics. They are a key component of virtual reality (VR) and augmented reality (AR) technologies. Currently, microLEDs are the primary display choice. However, progress in VCSEL research has been limited, but VCSELs will undoubtedly be introduced as miniature displays and near-eye displays. Relatively low optical power is beneficial for maintaining eye safety. Low divergence and circular symmetry reduce additional optical elements, thus resulting in compactness. VCSELs' two-dimensional array integration capabilities are less complex than edge-emitting lasers. Therefore, VCSEL products manufactured using the invention can be applied to these applications.

[0063] While the principles of this invention have been explained and illustrated in its preferred embodiments, it will be understood by those skilled in the art that the invention can be changed in arrangement and detail without departing from such principles. We therefore claim all modifications and variations that come within the spirit and scope of the following claims. [Explanation of symbols]

[0064] 10. Group III nitride substrates 11 Group III nitride templates 12 Opening area stripe 13 Dielectric Mask 14 Group III nitride layer 15 Wing 16 Nanoporous GaN DBR 17 n-GaN layer 18 Group III nitride active layer 19 Group III nitride p-type electron blocking layer (EBL) 20 p-type III-nitride layer 21 p ++ GaN layer 23 Insulating layer 24 Dielectric DBR 30 Base Seeds 31 Current injection region 32 Optical cavity region 33 p-contact pad 34 n-contact pads 35 circular plots 36 Shaded Area 37 Thermal diffusion layer 38 Luminous

Claims

1. an epitaxial lateral overgrown semiconductor portion comprising a Group III nitride active region between a hole-injecting Group III nitride layer and an electron-injecting Group III nitride layer; an angled p-type mirror on the hole injection side, and a flat mirror angled relative to the III-nitride active region, the flat mirror including a nanoporous layer on the electron injection side and a non-porous layer on the n-side; an enhanced vertical cavity surface emitting laser (VCSEL), including:

2. The VCSEL of claim 1 , wherein the flat mirror on the electron injection side comprises a nanoporous III-nitride based DBR.

3. 3. The VCSEL of claim 2, wherein the III-nitride based DBR has interfaces that sandwich alternating nanoporous and non-porous regions.

4. The VCSEL of claim 2 , wherein the III-nitride based DBR is used for vertical current injection of electrons.

5. The VCSEL of claim 2 , wherein the III-nitride based DBR is used for heat extraction.

6. The VCSEL of claim 2 , wherein an interface of the III-nitride based DBR contacts an n-contact pad.

7. The VCSEL of claim 2 , wherein the III-nitride based DBR is formed by epitaxial lateral overgrowth.

8. 3. The VCSEL of claim 2, wherein the roughness of the interface between the III-nitride based DBR and the dielectric mask is on the order of sub-nanometer.

9. 9. The VCSEL of claim 8, wherein no chemical mechanical polishing (CMP), etching, or grinding is used to smooth the surface of the III-nitride based DBR.

10. 10. The VCSEL of claim 1, wherein the angled mirror on the p-type layer is a dielectric mirror.

11. 11. The VCSEL of claim 10, wherein the angled p-type layer is a semipolar plane of a Group III nitride layer.

12. 12. The VCSEL of claim 11, wherein angled etching is used to obtain the semipolar p-type layer.

13. 13. The VCSEL of claim 12, wherein a chemical treatment is used to prepare a smooth surface for the angled p-type layer that is semipolar.

14. The VCSEL of claim 1 , wherein the current injection region is separated from the optical cavity region.

15. 15. The VCSEL of claim 14, wherein the current injection region comprises a tunnel junction.

16. The VCSEL of claim 1 , wherein a heat spreader is disposed on a p-side of the VCSEL.

17. The VCSEL of claim 2 , wherein the III-nitride based DBR directs light to the angled p-type layer side mirror.

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