Surface-emitting laser and method for manufacturing surface-emitting laser

Abstract

The extended vertical-cavity surface-emitting laser (VCSEL) includes an epitaxially laterally overgrown semiconductor portion, a III-nitride active region between a hole-injecting III-nitride layer and an electron-injecting III-nitride layer, and a nanoporous III-nitride layer on the electron-injecting III-nitride layer side.

Description

[Technical Field]

[0001] The present invention relates to III-nitride vertical cavity surface emitting lasers (VCSELs) with nanoporous GaN DBRs and methods for fabricating III-nitride VCSELs with nanoporous GaN DBRs. [Background technology]

[0002] This application refers to a number of patent and non-patent publications by reference numbers in brackets, i.e., [ ], as set forth throughout this specification. A list of publications arranged according to these reference numbers can be found below in the sections entitled "Non-Patent Publications" or "Patent Publications." "Quote List" "Non-patent literature"

[0003] [NPL1] Appl.Phys.Lett.Volume 92, Page 141102 (2008) [NPL2] Appl.Phys.Express, Vol. 12, p. 044004 (2019) [NPL3] Sci.Rep., vol. 8, pp. 10350 (2018) [NPL4] Jpn.J.Appl.Phys.Vol.58, SC0806(2019) [NPL5] Appl.Phys.Express, Vol. 11, pp. 112101 (2018) [NPL6] Appl.Phys.Lett.Volume 101, Page 151113 (2012) [NPL7] ACS Photonics, vol. 2, pp. 980-986 (2015) [NPL8] Sci.Rep., vol. 7, pp. 45344 (2017) [NPL9] Appl.Phys.Lett.Volume 112, Page 041109 (2018) [NPL10] Scr. Mater, vol. 156, pp. 10-13 (2018) [NPL11] Appl.Phys.Express 2012, Vol. 5, pp. 092104 [NPL12] Optics Express, Volume 27, Page 24717 (2019) [NPL13] Appl.Phys.Express, Volume 13, Page 041003 (2020) [NPL14] Appl.Phys.Express, Volume 14, Page 031002 (2021) [NPL15] Applied Phys. Lett. Volume 119, Page 142103 (2021) [NPL16] Crystals, Vol. 11, No. 12, 1563, (2021) [NPL17] M.B. Stern and T.R. Jay, "Dry etching for coherent refractive microlens arrays," Opt. Eng. 33, 3547-3551 (1994)

[0004] Surface-emitting lasers are known as vertical-cavity surface-emitting lasers (VCSELs). VCSELs contain a semiconductor active region located between n-side and p-side semiconductor regions and two distributed Bragg reflectors, called DBRs, which function as highly reflective mirrors. The semiconductor active region, also known as the gain medium, is located between the two DBRs so that the two DBRs and the semiconductor active region form an optical cavity. The n-side and p-side regions inject carriers, i.e., electrons and holes, respectively, into the active region, where they recombine to generate light. The light or electromagnetic radiation thus generated travels through the optical cavity, reflecting multiple times off the DBRs, resulting in laser oscillation. One of the DBRs in a VCSEL is a less reflective mirror and is used to emit the laser beam.

[0005] Gallium nitride (GaN) VCSELs have recently attracted increasing research attention due to their ability to emit light in the visible and ultraviolet (UV) regions. This opens up a variety of new application spaces in displays, solid-state lighting including automotive and residential lighting, transmission, and communications. One particularly exciting application is when a blue-emitting GaN VCSEL is coupled with a phosphor to simultaneously function as both a source of spontaneous emission and a data transmission device. This application could reshape all new AR / VR applications, smartphones, and regular displays by adding communication capabilities to each emitting pixel.

[0006] While GaAs-based infrared VCSELs have adopted mature fabrication techniques, III-nitride-based VCSELs are still not commercially viable due to technical challenges, such as the need for a conductive dielectric Bragg reflector (DBR). Continuous-wave (CW) lasing at 462 nm from an electrically injected GaN VCSEL was first demonstrated at a temperature of 77 K in 2008 [NPL1]. Since then, considerable progress has been made in terms of output power, efficiency, threshold current, lasing wavelength, and room-temperature stability. However, industrial adoption has yet to be achieved. As mentioned above, one of the issues is the n-side DBR mirror, which is typically a dielectric DBR that causes thermal instability in device operation. Traditionally, a dielectric DBR is deposited on the n-side of the VCSEL after carefully polishing the host substrate. Alternative approaches, such as epitaxial DBRs and nanoporous GaN DBRs, have been grown on top of the host substrate, and VCSELs with long optical GaN cavities have been proposed in the literature for better thermal stability. Although these approaches have been successful to some extent, the main concerns are issues such as the high cost of GaN substrates and the unavailability of larger sized GaN substrates even at a high price. Meanwhile, the proposed epitaxial DBR methods increase the growth time, and furthermore, maintaining the quality of the device layers is an obstacle, and it is necessary to deal with the removal of the expensive GaN substrate in the case of long GaN resonators and nanoporous GaN DBR resonators.

[0007] VCSELs with long optical cavities and curved lenses refocus the electric field onto the gain medium, thereby reducing diffraction losses due to the long cavity length [NPL2–NPL4]. Until 2022, Sony's long cavity design held the performance record with a CW output power of 15.8 mW, a threshold current of 0.25 mA, and a wall-plug efficiency (WPE) of 9.5%. Long optical GaN cavity VCSEL designs achieve excellent results by utilizing a significant portion of the host substrate in the cavity design. The substrate is redesigned with curved mirrors after grinding away the unnecessary portions, a process that is also tedious, time-consuming, and expensive. Curved mirrors are necessary in long optical cavity designs because they prevent diffraction and scattering losses. Because the typical gain of the active region of a nitride VCSEL is ~1%, in long optical GaN cavities, diffraction losses can rapidly degrade device performance for cavities longer than 10 micrometers. Sony's curved mirror VCSEL cavity is ~28 micrometers. This essentially leads to the greatest amount of difficulty with polishing as the cavity approaches the active region, a procedure that limits the scaling of GaN cavities.

[0008] Meanwhile, epitaxial designs using AlGaN / GaN or AlInN / GaN mirror pairs have also recently attracted attention [NPL05-NPL06], with the latter demonstrating superior performance due to the lattice matching of AlInN to GaN. However, the need for more than 40 AlInN / GaN layers to achieve reasonable reflectivity (>99.5% on the emitting side) and maintaining uniform growth conditions for better quality and improved yields can make epitaxial DBR designs difficult to achieve.

[0009] More recently, nanoporous GaN DBR (NP-GaN DBR) designs [NPL7–NPL10] have also gained popularity due to their relative ease of fabrication, their lattice match to GaN, and their high achievable refractive index difference. This high index difference allows a 99.5% reflectivity to be achieved with only 17 periods at a realistic porosity of 36%. Since the first NP-GaN DBR was first demonstrated in 2015, several groups have successfully achieved lasing with NP-GaN DBR designs. NP-GaN DBR layers offer better thermal stability than dielectric DBR mirrors. However, the common challenge of thinning and grinding the expensive host GaN substrate after realizing the NP-GaN DBR layer on the substrate remains.

[0010] To push nitride VCSELs into production, solutions are needed to achieve better crystalline quality for the device layers and to obtain stability with respect to thermal evacuation. Substrate removal techniques such as photoelectrochemical (PEC) [NPL11] and epitaxial lateral overgrowth (ELO)-assisted thermal delamination [NPL12-NPL16] are better options for future VCSEL designs. Because the ELO method can utilize large-sized foreign substrates, designing a hybrid VCSEL consisting of an n-side NP GaN DBR and a p-side dielectric DBR will be a more favorable option. Summary of the Invention [Problem to be solved by the invention]

[0011] Considering all these drawbacks, it is an object of the present invention to provide a III-nitride VCSEL with a nanoporous GaN DBR, and a method for fabricating a III-nitride VCSEL with a nanoporous GaN DBR, with improved device performance in terms of thermal and optical properties. [Means for solving the problem]

[0012] To overcome the limitations of the prior art mentioned above, the present invention discloses a III-nitride based VCSEL, which includes a III-nitride active region between a p-type (hole-injecting) III-nitride layer and an n-type (electron-injecting) III-nitride layer, and a curved mirror or simply a flat dielectric mirror designed on or above the p-side III-nitride layer.

[0013] Although ELO growth techniques generally result in thicker III-nitride layers, in our design, the growth of the NP GaN DBR layer was performed after the thick ELO-based unintentionally doped layer. Thus, the actual thicknesses of the device layers, n-GaN, active region, p-AlGaN electron blocking layer, and p-GaN layer (and possibly the current-spreading tunnel junction (p++ / n++GaN)) can be controlled for either short optical cavities (<10λ) or large cavities (>10λ).

[0014] The VCSEL further includes one or more tunnel junction layers on the p-side III-nitride layer, and a curved mirror or a flat dielectric mirror is formed on or above the tunnel junction layers such that the tunnel junction layers are between the curved mirror and the p-type III-nitride layer.

[0015] The VCSEL further includes a second n-type III-nitride region on or above the tunnel junction layer, and the curved or flat mirror includes the second n-type III-nitride region and the second type III-nitride region that is designed as a lens or left as a flat surface for DBR mirror placement.

[0016] The second III-nitride n-type region acts as a current spreading layer and has an etched surface with curvature for long cavity VCSELs or remains flat for short cavity VCSELs. The second III-nitride region comprises n-type GaN or unintentionally doped GaN.

[0017] The VCSEL further includes one or more transparent conductive oxide (TCO) layers on the p-type III-nitride layer as intracavity contact layers, and the curved mirror is formed on or above the TCO layers, which may be composed of indium tin oxide, ZnO.

[0018] In the case of a long cavity, the curved mirror comprises a transparent dielectric material, the surface of the dielectric material is curved, and a DBR made of a thin dielectric film is disposed on the surface of the dielectric material.

[0019] Also, in the case of long cavity VCSELs, the dielectric material (which may be a transparent oxide or polymer) is removed by wet or dry etching after DBR deposition, and the void is then either filled with a thermally conductive gas or left as an void.

[0020] The VCSEL further includes periodic selectively doped GaN layers on or above the ELO base layer, from which NP-GaN flat DBR mirrors are formed during the VCSEL fabrication process.

[0021] The VCSEL further includes a separate island III-nitride ELO base layer for improved accessibility to electrochemical etching chemistries, and pore formation is achieved in the selectively doped GaN layer by electrochemical etching.

[0022] The NP-GaN layer has better thermal and electrical conductivity than the dielectric DBR mirror. The NP-GaN layers also share the same surface as the active layer, and the resulting configuration is a series of parallel NP-GaN layers separated by non-porous GaN layers. The flat DBR mirror in this VCSEL design is a nano-porous DBR layer.

[0023] The crystal orientation of the III-nitride layers in the VCSEL can be c-plane, semipolar, or nonpolar. [Brief explanation of the drawings]

[0024] [Figure 1A] FIG. 1A is a schematic diagram showing a foreign substrate with a III-nitride template. [Figure 1B] FIG. 1B is a schematic diagram showing dielectric mask open area patterning into the III-nitride growth layer. [Figure 1C] FIG. 1C is a schematic diagram showing a stripe design, each housing a VCSEL device. [Figure 2A] FIG. 2A is a schematic diagram of the base ELO III-nitride layer after growth. [Figure 2B] FIG. 2B is a schematic diagram showing edge growth on an ELO base. [Figure 2C] FIG. 2C is a schematic diagram of the planarized ELO base. [Figure 3A] FIG. 3A is a schematic diagram of the processed short cavity VCSEL design prior to removal from the host substrate. [Figure 3B] FIG. 3B shows the processed VCSEL. [Figure 3C] FIG. 3C shows a top view and an overhead view of a typical VCSEL chip. [Figure 4A] FIG. 4A is a schematic diagram of a processed long cavity VCSEL design with a GaN lens prior to removal from the host substrate. [Figure 4B] FIG. 4B is a processed VCSEL with a GaN lens. [Figure 4C] FIG. 4C is a processed VCSEL with a dielectric lens. [Figure 4D] FIG. 4D is a processed VCSEL with an air lens. [Figure 4E] FIG. 4E shows a top view and an overhead view of a typical VCSEL chip. DETAILED DESCRIPTION OF THE INVENTION

[0025] The teachings of the present invention can be readily understood by considering the following detailed description, taken in conjunction with the accompanying drawings, which are presented by way of example only, in which: With reference to the accompanying drawings, a general overview illustrating a vertical cavity surface emitting laser (VCSEL) and a method for manufacturing a VCSEL according to the present disclosure is set forth below: For ease of understanding, where possible, identical reference numerals are used to indicate identical elements common to the figures.

[0026] In the following embodiments, a description is provided with reference to the drawings. The use of NP-GaN DBR flat mirrors on ELO base layers and curved or flat DBR mirrors on the p-side of III-nitride VCSELs has been proposed as a viable method to improve device performance, both thermally and optically.

[0027] Technical Disclosure: The following disclosure is divided into four sections: the first describes the preparation of the ELO base layer; the second provides information on the growth of the NP-GaN DBR and device layers; and the third and fourth sections describe short and long cavity VCSELs, respectively.

[0028] Section 1: Preparation of ELO base The ELO method for forming the III-nitride semiconductor islands may include growth by metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc. The III-nitride semiconductor layers are sized to form one or more of the III-nitride semiconductor islands. Alternatively, the ELO III-nitride layers may initially be coalesced so that they can be later separated into individual devices.

[0029] The ELO layer has two portions: an aperture region, which generally has more defects than its control region extending above the ELO mask. The control region extends bidirectionally from the aperture region onto the ELO mask and is called the ELO wing. The VCSEL light-emitting aperture is formed on the ELO wing. Furthermore, the present invention may use heterosubstrates to grow the III-nitride semiconductor island layers that form the bars. For example, the present invention may use GaN templates grown on heterosubstrates such as sapphire, Si, SiC, SiN, GaAs, Ga2O3, LiAlO2, and ScAlMgO4 (SAM).

[0030] Furthermore, the ELO method can significantly reduce dislocation and stacking fault densities, which are important issues when using heterosubstrates, when non-Basel GaN crystal planes are used. Therefore, the present invention can simultaneously solve many types of problems associated with the use of heterosubstrates. For example, in a laser device, the interface between the ELO mask and the III-nitride template layer may be smoothed to prevent light emission from the interface.

[0031] 1A, 1B, and 1C are schematic diagrams illustrating a method that includes providing a III-nitride based substrate 10, such as GaN on Si, GaN on sapphire, GaN on ScAlMgO (SAM), or a bulk GaN substrate. In the case of a foreign substrate, a III-nitride template 11 may be deposited on the substrate 10, and the template 11 may be designed as a uniform layer on the host foreign substrate 10, or the template 11 may be designed only as open-area stripes 12. The III-nitride stripes 12 that comprise the host substrate 10 are stripes such as those shown in the schematic diagram of FIG. 1C. The open-area stripes 12 may be modified to be confined to a single device by shortening their length, or to be confined to multiple devices by increasing their length.

[0032] 1C, a dielectric mask 13 is formed on or above a GaN-based substrate 10. Specifically, the dielectric mask 13 is placed in direct contact with the substrate 10 or indirectly via a template layer grown by MOCVD or the like, and is made of a group III nitride-based semiconductor deposited on the substrate 10, leaving open area stripes 12.

[0033] The dielectric mask 13 may be formed from an insulator film, such as SiO2 film or SiN, deposited on the substrate 10 by, for example, plasma-enhanced chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc. The SiO2 film is then patterned by photolithography and etching using a predetermined photomask to include open areas as shown in Figures 1B and 1C. The design of this dielectric film has profound effects on subsequent device processing and operation.

[0034] As shown in the schematic diagrams of FIGS. 2A, 2B, and 2C, an epitaxial III-nitride layer 14, such as a GaN-based layer, is grown on a GaN-based substrate and a dielectric mask 13 by ELO. Growth of the ELO III-nitride layer 14 occurs first within the open area on the GaN-based substrate and then laterally from the open area onto the dielectric mask. Growth of the ELO III-nitride layer is stopped or interrupted before the ELO III-nitride layer from adjacent open areas can coalesce on the dielectric mask. Alternatively, growth of the ELO III-nitride layer may continue and coalesce with adjacent ELO III-nitride layers. Wings 15 of the ELO III-nitride layer are regions of reduced defect density on either side of the open area. In the ELO growth method, the fill factor, which is the ratio between the open area and the dielectric mask, can significantly deviate from 1, resulting in greater accumulation of III-nitride atoms at the edges of the III-nitride layer compared to the center of the layer, as shown in FIG. 2B. This can be seen as edge growth, which can be detrimental if allowed to continue during the growth of the NP GaN layer and the VCSEL device layers. In FIG. 2C, the III-nitride ELO base layer thus deposited is polished to obtain a flat surface, if desired. Because the surfaces of these layers are obtained using epitaxial growth, a slight chemical-mechanical polishing or dry or wet etching should be sufficient to obtain a flat layer.

[0035] Section 2: Growth of NP-GaN DBR and device layers on ELO base NP-GaN DBRs are a promising solution for GaN-based VCSELs because they can offer better thermal stability compared to dielectric DBRs, their lattice matching ability to GaN makes them desirable for growth and fabrication, and they offer a high refractive index contrast. The formation of NP-GaN DBRs has been extensively studied, and the etching procedure is well understood. At a constant applied bias, the size and shape of the pores are controlled by the n-type doping and the crystal orientation of the layer exposed to an oxalic acid solution during electrochemical etching (EC). As the etching progresses, first, the applied negative bias creates a hole inversion layer at the electrolyte / n-GaN interface. Second, the n-GaN surface is oxidized due to the presence of holes at the inversion surface. Third, the oxidized GaN decomposes into Ga3+ and nitrogen gas, which eventually migrates freely into the electrolyte, leaving behind voids called nanoporous regions. After planarization of the III-nitride layer 14, a semiconducting nanoporous GaN DBR section 16a is grown on the ELO base layer, as shown in Figure 3A. The nanoporous GaN DBR section is composed of unintentionally doped (UID) GaN and n + -GaN([Si]~10 19 / cm 3 ) periodic superlattice, and then the device layers include a III-nitride n-GaN 17 layer, a III-nitride active layer 18, a III-nitride p-type electron blocking layer (EBL) 19, a p-type III-nitride layer 20, and a p ++ After this growth, the sample is treated with a chemical solution such as BHF to form a GaN layer 21. ++ It is then reintroduced into the MOCVD reactor to grow a GaN layer 22, completing the tunnel junction.

[0036] Next, reactive ion etching (RIE) is used to remove the n ++ / p ++ The buried tunnel junction opening is defined by etching through the GaN layer and deep into the p-GaN 20. Finally, the n-GaN and UID GaN layers are grown on top of the NP GaN layer. The controllable thickness of the newly regrown n-GaN and UID GaN layers results in either a short cavity VCSEL or a long cavity VCSEL. There are three specific subcategories identified under long cavity VCSELs: (i) GaN lenses, (ii) dielectric lenses, and (iii) air / gas lenses. The initially formed NP GaN layer is later transformed into the DBR mirror 16b using the EC process described above. Therefore, the NP DBR layer is indistinguishable until the porous and non-porous layers are formed by an electrochemical etching process.

[0037] Section 3: Short cavity VCSELs For example, for a short cavity VCSEL, after growing the NP DBR superlattice, we assumed that light emission would come from the NP-GaN DBR, and therefore optimized the porosity and number of DBR layers to achieve a value of ~99.5. The device layers for a short cavity with a thickness of less than 10λ were designed using n-GaN 17, active region 18, p-AlGaN 19, p-GaN 20, and tunnel junction layers. Next, the current spreading layer (n-GaN) 25 for the buried tunnel junction was tailored to accommodate all design parameters according to the short cavity VCSEL requirements. The current injection aperture was formally defined during the tunnel junction burying process, and then a slightly larger mesa was tailored to contact the n-GaN layer 17 for metal contact. This etched large mesa and the isolated island-like nature of the ELO bar help to more effectively activate the p-type GaN. Next, an insulating layer 23 was placed to avoid short circuits between the p-contact layer 26 and the n-contact layer 27. Next, selectively, a mesa was opened at the top of the device by photolithography, centered on the current opening. After patterning, a 16-period dielectric DBR 24 consisting of SiO2 / Ta2O5 periods was deposited on the top surface. Next, a SiO2 or protective film was deposited (not shown) to protect the device from NP DBR etching and provide electrical insulation.

[0038] The optical reflectance of the DBR mirror 16b is lower than that of the dielectric DBR 24. For example, the optical reflectance of the DBR mirror 16b is 99.995 to 99.997. For example, the optical reflectance of the dielectric DBR 24 is 99.998.

[0039] Next, the sample was subjected to EC etching by immersing it in oxalic acid under a bias voltage to etch the NP DBR 16b. Next, p- and n-contact pads were selectively patterned by removing the insulating layer using photolithography, followed by deposition of metal contacts, Ti / Au. The VCSEL device was then separated from the host substrate by either thermal delamination, laser lift-off, or chemical lift-off, as described above, resulting in the overall image shown in Figure 3B. If necessary, a heat sink 28 was then attached to the III-nitride layer 14 side. As can be seen in Figure 3B, although the NP-GaN DBR side is the light-emitting side, there is still a significant III-nitride layer from the lift-off interface down to the CMP line. However, this can be controlled during the CMP polishing itself. Contrary to other procedures, the remaining layers in this invention are grown using ELO and are therefore crystallographically pure, and the interface surface roughness is designed to be sub-nanometer on the lift-off side without introducing CMP or any other polishing techniques. In this particular invention, the dielectric mask is prepared to be greater than 300 nm thick, preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask is designed to be sub-nanometer (e.g., 2 nm) to allow for replication on the lift-off interface.

[0040] Figure 3C is a schematic diagram of typical dimensions of a VCSEL device, which is fabricated in a two-dimensional array of ELO bars on a host substrate. As shown in the small image, light emission was selected to be from the bottom, i.e., the NP-GaN DBR side, so a complementary metal-oxide-semiconductor logic gate substrate may preferably be integrated on top of these devices.

[0041] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. The separate ELO base layer simplifies the deep trench definition procedure to access the NP layer and facilitate activation of p-GaN. 3. The lift-off interface did not require further polishing after removal from the host substrate.

[0042] Section 4: Long cavity VCSELs (i) GaN lens VCSEL For example, for a long-cavity VCSEL with a cavity thickness greater than 10λ, after growing a superlattice of NP DBR 16b, we assumed that the light emission would come from the NP-GaN DBR 16b, and therefore the porosity and number of DBR layers were optimized to achieve a value of ~99.5. As shown, the device layers for a long cavity greater than 10λ were designed using n-GaN, an active region, p-AlGaN 19 and p-GaN 20, and tunnel junction layers 21 and 22. Next, the current spreading layer 25 for the buried tunnel junction was adjusted to match the design parameters according to the long-cavity VCSEL requirements. The only difference compared to a short-cavity VCSEL is the thickness of the layer used to embed the tunnel junction. In this case, a significantly thicker n-GaN 27 and UID GaN layer 14 were placed. Figure 4A shows a typical design still remaining on the host substrate.

[0043] The current injection aperture was formally defined during the tunnel junction implant process. Then, a photoresist lens was formed by photoresist reflow and imaged on the thick GaN layer using RIE to form the GaN lens 25A. Following this, a slightly larger mesa was aligned to contact the n-GaN layer 17 for metal contact. The isolated island nature of this large mesa and the ELO bar allows for more effective activation of the p-GaN 20. Next, an insulating layer 23 was deposited to prevent shorting between the p-contact layer 26 and the n-contact layer 27. Next, a selective mesa was opened by photolithography at the top of the device, centered on the current aperture above the curved GaN lens 25A. Next, a 16-period dielectric DBR 24 consisting of SiO2 / Ta2O5 periods was deposited on the top surface. Next, a SiO2 or protective film was deposited (not shown) to protect the device from NP DBR etching and provide electrical insulation. Next, EC etching was performed by immersing the sample in oxalic acid under a bias voltage, etching the NP DBR 16b. Next, photolithography was used to selectively pattern the p-contact pad and n-contact pad, and metal contacts, Ti / Au, were deposited. The VCSEL device was then separated from the host substrate, resulting in the overall image shown in Figure 4B. As can be seen from the overall image, the NP-GaN DBR side is the light-emitting side, but unlike existing conventional devices, there is still a significant III-nitride layer from the lift-off interface down to the CMP line. Contrary to other procedures, the additional layer below the NP-GaN DBR 16b in this invention is grown using ELO and therefore has excellent crystalline quality, and its thickness can be controlled during the epitaxial or CMP process. Furthermore, the interface surface roughness can be engineered to be less than sub-nanometer without introducing CMP or any polishing techniques, simply by designing the material and deposition technique of the dielectric mask 13. The dielectric mask is tailored to be a minimum thickness of 300 nm and preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask is designed to be less than sub-nanometer, allowing for replication on the lift-off interface.

[0044] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. The thick cavity GaN lens provides thermal stability to the structure. 3. The separate ELO base layer simplifies the deep trench definition procedure to access the NP layer and facilitate activation of p-GaN. 4. The lift-off interface did not require any polishing after removal from the host substrate.

[0045] (ii) Dielectric lens VCSEL For example, for a long-cavity VCSEL with a cavity thickness greater than 10λ, the design assumes that after the NP DBR superlattice is grown, light emission will come from the NP-GaN DBR 16b, and the porosity and number of DBR layers are optimized to achieve a value of ~99.5. Device layers for long cavities with thicknesses greater than 10λ present challenges for the device's active region 18. To fabricate a thick GaN lens 25A within a long cavity with a thickness of ~3 μm, the growth of n-GaN 25 is typically performed at a higher temperature than the previously grown active region 18, ultimately damaging the active region's quantum wells. On the other hand, if the growth temperature for a thick GaN cavity is reduced, crystal defects will be introduced, which will increase optical absorption and ultimately cause the VCSEL to cease lasing. To counter this, the lens material can be replaced with a dielectric material, which can be deposited at or near room temperature and prevents degradation of the active region 18. Dielectric materials are deposited when the optical cavity thickness is less than 10λ, i.e., similar to the short-cavity VCSELs described in Section 3. A properly optimized dielectric lens material can be nearly lossless. Immediately following the optical cavity, a thickness similar to that of the short cavity is created by the n-GaN 17, active region 18, and p-GaN 19, 20, as well as the tunnel junctions 21, 22 and current spreading layer 25. The current injection aperture is formally defined during the implantation process of the tunnel junctions 21, 22. In this design, a thick dielectric material such as SiO2 is first deposited on the GaN device layers of the short cavity. A photoresist lens is then formed by photoresist reflow and imaged onto the deposited dielectric material using RIE to form the dielectric lens. Following this, a slightly larger mesa is adjusted to contact the n-GaN region for metal contact. The isolated island-like nature of this mesa and ELO bar allows for more effective activation of the p-GaN. Next, an insulating layer 23 is deposited to avoid short circuits between the p-contact layer 26 and the n-contact layer 27. Next, a selective mesa is opened by photolithography at the top of the device, centered on the current aperture above the curved lens.Next, a 16-cycle dielectric DBR 24 consisting of SiO2 / Ta2O5 periods was deposited on top of the dielectric lens 29. An SiO2 or protective layer (not shown) was then placed to protect the device from NP DBR etching and provide electrical insulation. Next, EC etching was performed by immersing the sample in oxalic acid under a bias voltage to etch the NP DBR 16b. Next, p-contact and n-contact pads were selectively patterned using photolithography, and metal contacts, Ti / Au, were deposited. The VCSEL device was then separated from the host, resulting in the overall image shown in Figure 4C. As can be seen from the overall image, the NP-GaN DBR 16b side is the light-emitting side, but unlike existing conventional devices, there is still a significant III-nitride layer from the lift-off interface to the CMP line. Contrary to other procedures, the additional layer below the NP-GaN DBR 16b in this invention is grown using ELO, thus providing excellent crystalline quality, and its thickness can be controlled during epitaxial or CMP processes. Furthermore, the interface surface roughness is engineered to be less than sub-nanometer without introducing CMP or any polishing techniques simply by designing the dielectric mask material and deposition technique. The dielectric mask 13 is tailored to be a minimum of 300 nm thick, preferably a multi-layer combination of SiO2 and SiN. The surface roughness of the dielectric mask 13 is engineered to be less than sub-nanometer so that it can be replicated on the lift-off interface.

[0046] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. The thick resonator made by the dielectric lens is lossless. 3. No damage to the active layer. 4. The separate ELO base layer simplifies the deep trench definition procedure to access the NP layer and facilitate activation of p-GaN. 5. The lift-off interface did not require any polishing after removal from the host substrate.

[0047] (iii) Air-lens VCSEL This design is similar to the dielectric lens VCSEL, except that the curved surface is transferred onto the dielectric material. The dielectric material is deposited when the optical cavity thickness is less than 10λ, like the thickness of the short cavity VCSEL described in Section 3. A properly optimized dielectric lens material can be nearly lossless. Immediately after the optical cavity, a thickness similar to that of the short cavity is built up by n-GaN 17, active region 18, and p-GaN 19, 20, as well as tunnel junctions 21, 22 and current spreading layer 25. The current injection aperture is formally defined during the embedding process of the tunnel junctions 21, 22. In this design, a thick dielectric material such as SiO2 is first deposited on the short cavity GaN device layers. A photoresist lens is then formed by photoresist reflow, and then the upper DBR is deposited directly on the photoresist. The photoresist below the lens is then removed to form the air gap lens 30. The remaining fabrication procedures are similar to those for the VCSEL device described above. The device is shown schematically in Figure 4D.

[0048] Figure 4E is a schematic diagram of typical dimensions of a VCSEL device, which is fabricated in a two-dimensional array of ELO bars on a host substrate. As shown in the small image, a complementary metal-oxide-semiconductor logic gate substrate may be preferably integrated on top of these devices, since light emission was selected to be from the bottom side, i.e., the NP-GaN DBR 16b side.

[0049] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. Thick resonators made of dielectric materials are lossless. 3. The air inside the lens creates a better refractive index difference, thereby providing better reflection and simplifying the process. 4. No damage to the active layer. 5. The separate ELO base layer simplifies the deep trench definition procedure to access the NP layer and facilitate activation of p-GaN. 6. The lift-off interface did not require any polishing after removal from the host substrate.

[0050] Purpose illumination: GaN-based LEDs have brought about a dramatic change in residential and automotive lighting. Lighting combined with communication services is highly desired for future smart cities and smart infrastructures. VCSELs are a better alternative to LEDs and edge-emitting laser diodes. However, the lack of suitable profitable mass-production technology has prevented GaN VCSELs from entering the market. The procedures developed in the above embodiments can be used to mass-produce VCSEL units applicable to lighting applications. Visible Light Communication:

[0051] Laser light for future potential data transfer and communication applications through Light Fidelity (LiFi). With the rapid increase in IoT devices, the demand for data transmission continues to expand. The RF spectrum is becoming saturated, and new frequencies are needed to keep up with the continuously increasing demand. Applying GaN VCSELs to existing LED configurations is easier than replacing them with edge-emitting lasers. Therefore, the devices described in the above embodiments can serve the purpose. Near-eye display:

[0052] Near-eye displays represent the next big wave of consumer electronics. They are a key component of virtual reality (VR) and augmented reality (AR) technologies. Currently, microLEDs are the primary display choice. However, progress in VCSEL research has been limited, but VCSELs will undoubtedly be introduced as miniature displays and near-eye displays. Relatively low optical power is beneficial for maintaining eye safety. Low divergence and circular symmetry reduce additional optical elements, thus resulting in compactness. VCSELs' two-dimensional array integration capabilities are less complex than edge-emitting lasers. Therefore, VCSEL products manufactured using the invention can be applied to these applications.

[0053] advantage 1. Use of a sufficiently long cavity without excessive diffraction losses, with two reflecting mirrors defining the VCSEL cavity. 2. Good thermal management due to sufficient length of the resonator and / or placement of contacts on the nitride layer. 3. The process of including a GaN template in the device is associated with better thermal conductivity to the substrate material, thereby improving thermal performance. 4. Cheaper large template substrates such as GaN on sapphire can be used to advantage. 5. High-quality and larger-sized GaN substrates are very expensive. The present ELO technique can enable the use of foreign substrates in the fabrication of VCSELs. 6. The present invention is expected to provide significant improvements in performance and reduction in manufacturing costs, as well as elimination of complex procedures.

[0054] While the principles of this invention have been explained and illustrated in its preferred embodiments, it will be understood by those skilled in the art that the invention can be changed in arrangement and detail without departing from such principles. We therefore claim all modifications and variations that come within the spirit and scope of the following claims. [Explanation of symbols]

[0055] 10. Group III nitride substrates 11 Group III nitride templates 12 Opening area stripe 13 Dielectric Mask 14 UID GaN layer 15 Wing 16a Nanoporous GaN DBR section 16b NP DBR 17 n-GaN layer 18 Group III nitride active layer 19 Group III nitride p-type electron blocking layer (EBL) 20 p-type III-nitride layer 21 p ++ GaN layer 22n ++ GaN22 23 Insulating layer 24 Dielectric DBR 25 Current spreading layer (n-GaN) 26 p-contact layer 27 n-contact layer 28 Heatsink 29 Dielectric Lens 30 Air Gap Lens

Claims

1. an epitaxial lateral overgrown semiconductor portion comprising a Group III nitride active region between a hole-injecting Group III nitride layer and an electron-injecting Group III nitride layer; and a nanoporous III-nitride layer on the side of the electron-injecting III-nitride layer; an enhanced vertical cavity surface emitting laser (VCSEL), including:

2. 10. The VCSEL of claim 1, further comprising a curved or flat mirror on the side of the hole-injecting III-nitride layer, and a flat mirror on the side of the electron-injecting III-nitride layer.

3. 10. The VCSEL of claim 1, further comprising a nanoporous III-nitride GaN layer disposed between an unintentionally doped (UID) GaN layer and the III-nitride active region.

4. The VCSEL of claim 3 , wherein the UID GaN layer is substantially free of a Group III-nitride template.

5. The VCSEL of claim 3 , wherein the UID GaN layer is formed by epitaxial lateral overgrowth.

6. The VCSEL of claim 3 , wherein the interface of the UID GaN layer is not included in the host substrate and is part of the VCSEL optical cavity.

7. The VCSEL of claim 3 , wherein the interface surface roughness between the UID GaN layer and the dielectric mask is on the order of sub-nanometer.

8. 8. The VCSEL of claim 7, wherein no chemical mechanical polishing (CMP), etching, or grinding was used to smooth the interface surface of the UID GaN layer.

9. 3. The VCSEL of claim 2, wherein the flat mirror on the side of the hole-injecting III-nitride layer constitutes a dielectric mirror for a short cavity VCSEL.

10. 3. The VCSEL of claim 2, wherein the curved mirror is disposed on or above the p-GaN layer and comprises a GaN lens.

11. 3. The VCSEL of claim 2, wherein the curved mirror is disposed on or above the p-GaN layer and comprises a dielectric lens.

12. The VCSEL of claim 11 , wherein the material of the dielectric lens comprises a transparent oxide.

13. The VCSEL of claim 11 , wherein the material of the dielectric lens comprises a polymer.

14. The VCSEL of claim 2 , wherein the curved mirror is disposed on or above the p-GaN layer and comprises an air lens.

15. 10. The VCSEL of claim 1, further comprising a curved DBR made of a dielectric DBR.

16. The VCSEL of any one of claims 1 to 15, wherein the crystal orientation of the III-nitride layer is c-plane, semi-polar, or non-polar.

17. forming a Group III nitride template on a substrate; forming a dielectric mask on the Group III nitride template; forming UID GaN by epitaxial growth from the open areas of the dielectric mask; and forming a nanoporous GaN DBR on the UID GaN.

18. The method of claim 17 , wherein the nanoporous GaN DBR comprises a plurality of DBR mirrors.

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