A voltage regulating control method and system for a power regulator

Abstract

The application discloses a voltage regulation control method and system for a power regulator, and belongs to the technical field of voltage regulation, which specifically comprises the following steps: collecting parameters of a power grid side and a load side, including current and voltage, and establishing an operation model of the power regulator based on parameter identification; according to the operation model and a target output voltage, a reference voltage sequence is calculated in combination with power quality and efficiency constraints; the state of the power grid and the load is monitored in real time; when voltage fluctuation or abnormality is detected, the reference voltage sequence is projected to a safe operation envelope, and hierarchical de-rating control is performed; a power regulator control signal is generated based on the corrected reference voltage sequence, and the operation model of the power regulator is calibrated through real-time feedback; the application can balance power quality and efficiency under normal working conditions, and can also maintain stable voltage control when the power grid fluctuates, the frequency deviates or the load suddenly changes, thereby avoiding resource waste caused by single shutdown or extensive de-rating.

Description

Technical Field

[0001] This invention belongs to the field of voltage regulation technology, specifically a voltage regulation control method and system for power regulators. Background Technology

[0002] Power regulators, as core devices for power conversion and voltage regulation, are widely used in industrial power supply, smart grids, rail transportation, new energy grid connection, and precision electronic equipment power supply. Their main function is to regulate and stabilize the voltage between the power grid and the load to meet the power quality requirements of industrial equipment, precision instruments, data centers, and new energy grid-connected systems. Existing power regulators mostly use power devices such as thyristors, IGBTs, or MOSFETs, achieving voltage regulation through phase control, pulse width modulation, or tap switching.

[0003] Traditional power regulators typically rely on thyristor rectification, phase-shift control, or pulse-width modulation (PWM) technology to regulate voltage by changing the conduction angle, duty cycle, or tap position. However, with the increasing complexity of power systems and the diversity of loads, existing voltage regulation methods suffer from the following problems: the uncertainty and complexity of the power grid environment make it difficult to cope with abnormal operating conditions, resulting in insufficient regulation capabilities. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a voltage regulation control method and system for power regulators. This novel voltage regulation control method enables multi-dimensional constraint management, abnormal operating condition projection, and graded derating control, and possesses self-learning and self-calibration capabilities, thereby improving the adaptability and stability of power regulators in dynamic environments.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A voltage regulation control method for a power regulator, comprising:

[0007] Collect parameters from the grid side and the load side, including current and voltage, and establish an operating model for the power regulator based on parameter identification;

[0008] Based on the aforementioned operating model and target output voltage, and combined with power quality and efficiency constraints, a reference voltage sequence is calculated.

[0009] The system monitors the power grid and load status in real time. When voltage fluctuations or anomalies are detected, the reference voltage sequence is projected onto the safe operation envelope, and graded derating control is performed.

[0010] The power regulator control signal is generated based on the corrected reference voltage sequence, and the operation model of the power regulator is calibrated through real-time feedback.

[0011] Specifically, the process of collecting parameters from the grid side and the load side, including current and voltage, and establishing an operating model for the power regulator based on parameter identification includes:

[0012] Set the reference phase on the grid side and trigger the first sampling cycle, dividing the voltage and current signals into raw data frames;

[0013] A temporal perturbation is introduced into the original data frame, and multi-dimensional operating quantities of the power grid and load are collected synchronously in multiple sampling periods to form a sequence dataset with perturbation tags;

[0014] The sequence dataset is segmented and cross-filtered to remove segments that do not meet the temporal consistency requirement, thereby obtaining candidate data for identification.

[0015] Based on the candidate data, a multidimensional parameter mapping relationship is established, and the equivalent parameters of the power grid and the equivalent parameters of the load are projected onto the unified operating model of the power regulator through a progressive iterative method.

[0016] Specifically, based on the aforementioned operating model and target output voltage, and considering power quality and efficiency constraints, a reference voltage sequence is calculated, including:

[0017] Within the prediction time domain window, the state variables and target output voltage of the running model are obtained, the power quality and efficiency constraints are analyzed, and they are divided into three types of constraints: time domain, frequency domain and energy domain. Corresponding weight scheduling tables and scene labels are generated.

[0018] Based on the aforementioned operating model and weight scheduling table, a set of discrete reference trajectories is constructed. At the same time, the voltage amplitude and phase sequence in each discrete reference trajectory are obtained, and a modulation space index is established based on the voltage amplitude and phase sequence.

[0019] Based on the modulation space index, the discrete reference trajectory is subjected to constraint consistency check, and the inconsistent constraint segments are segmented, pruned and replaced to obtain a feasible solution set. The constraint consistency check includes time domain boundary, frequency band occupancy, energy balance and sparsity constraints.

[0020] Based on scene labels, feasible solutions are sorted and selected according to preset priorities. Then, under the modulation clock, all solutions are quantized, limited, and zero-crossing aligned to obtain a reference voltage sequence.

[0021] Specifically, the constraint consistency check of the discrete reference trajectory based on the modulation spatial index, and the segmentation and replacement of inconsistent constraint segments, to obtain a feasible solution set, including:

[0022] Within a preset inspection window, the discrete reference trajectory is fragmented, and time stamps, spectral fingerprints, and modulation spatial indexes are written for each fragment to form an inspection fragment sequence.

[0023] The sequence of test segments is sequentially tested, segments that do not meet preset constraints are marked, and a list of temporal inconsistencies is generated.

[0024] For segments in the test segment sequence that meet the preset constraints, a joint test of frequency band occupancy and energy balance is performed. Segments that conflict with the prohibited frequency band table or energy quota table are added to the time domain inconsistency list, and a pruning instruction is generated for each conflict.

[0025] For segments that do not conflict after joint inspection, sparsity is determined, the boundary between the dense and sparse areas of switches is located, segments that fall into the restricted area are added to the inconsistency list, and replacement instructions and splicing anchors are generated.

[0026] According to the trimming and replacement instructions, inconsistent segments are trimmed at their splicing anchor points, and replacement segments are selected from the preset candidate segment library according to the modulation space index to complete the splicing verification, and a set of feasible solutions that meet the constraints of time domain boundary, frequency band occupancy, energy balance and sparsity is output.

[0027] Specifically, the step of sorting and selecting feasible solutions based on scene labels according to a preset priority, and quantizing, limiting, and zero-crossing aligning all solutions under the modulation space index to obtain a reference voltage sequence includes:

[0028] Based on scene labels, sorting rules are set for each feasible solution in the feasible solution set, and a priority sequence is formed;

[0029] At the modulation clock trigger point, the solution with the highest priority is selected as the master solution from the priority sequence;

[0030] The discrete reference trajectory of the master solution is subjected to amplitude and phase quantization processing under a modulation clock to obtain the preliminary quantized trajectory of the master solution;

[0031] The preliminary quantized trajectory of the master solution is compared point by point with the amplitude constraint and energy boundary. Segments that do not meet the conditions are marked and local replacements are performed by calling backup candidate solutions to generate a corrected trajectory.

[0032] Alignment anchors are set in the zero-crossing interval of the corrected trajectory, and the sampling points in the neighborhood of the alignment anchors are slightly shifted and spliced ​​for verification. Finally, a continuous reference voltage sequence that meets the constraint conditions is output.

[0033] Specifically, the real-time monitoring of the power grid and load status, when detecting voltage fluctuations or anomalies, projects the reference voltage sequence onto the safe operating envelope and performs graded derating control, including:

[0034] Under the synchronous reference, the state variables of the power grid side and the load side are collected to generate a continuous state vector stream, and a scene label and event counter are written for each sampling period.

[0035] A preset abnormal pattern library is used to perform sliding window comparison on the state vector stream, output abnormal event records according to the abnormal pattern library, and generate abnormal event levels according to the influence domain and duration of the abnormal event records.

[0036] A safe operation envelope is constructed based on the operation model and preset constraints of the power regulator. The safe operation envelope is discretized into a multi-level boundary set, and priority rules and start / stop conditions are configured for each level of boundary.

[0037] Within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero crossover anchor point to obtain the restricted voltage sequence.

[0038] The derating level is determined based on the restricted voltage sequence and the multi-level boundary set, a level transition table and a hold duration are generated, and the output control quantity is updated according to the level transition table under the modulation clock.

[0039] Specifically, within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero-crossing anchor point to obtain a restricted voltage sequence, including:

[0040] Receive projection instructions triggered by the abnormal event level, and select the boundary layer corresponding to that level in the multi-level boundary set in the safe operation envelope;

[0041] Within the boundary layer, the amplitude range of the reference voltage sequence is compressed segment by segment, and the compressed segments are written into a tag table;

[0042] The phase order of adjacent segments is rearranged according to the label table to conform to the phase sequence rules of the boundary layer;

[0043] The rearranged segments are remapped to the frequency range of the boundary layer, and splicing anchor points are generated.

[0044] At the splicing anchor point, the frequency band remapped segment is spliced ​​and verified with the unmodified segment to obtain a continuous restricted voltage sequence.

[0045] Specifically, based on the restricted voltage sequence and multi-level boundary set, the derating level is determined, a level transition table and hold duration are generated, and the output control quantity is updated according to the transition table under the modulation clock, including:

[0046] The restricted voltage sequence is compared segment by segment with the multi-level boundary set to generate a judgment table of boundary hit mark, duration period and segment position, and the candidate derating level set is determined based on the judgment table.

[0047] Based on the candidate reduction level set and the abnormal event level, the current reduction level is selected and its adjacent levels are determined, resulting in a level relationship set that includes entry conditions and removal conditions;

[0048] Construct a hierarchy transition table on the set of hierarchy relationships and configure the retention time for each transition path;

[0049] Under the modulation clock, the current level is periodically evaluated according to the level transition table and the holding time. If the entry condition is met, the level switch is performed at the zero crossover anchor point. If the condition is not met, the existing level is maintained and the timing state is updated.

[0050] Write the level change result and timing status back to the event counter and safe operation envelope, and select the corresponding output control quantity according to the current level.

[0051] A voltage regulation control system for a power regulator, used to implement the voltage regulation control method for a power regulator, includes: a model building module, a voltage sequence calculation module, a voltage regulation control module, and a feedback adjustment module;

[0052] The model building module is used to collect parameters from the grid side and the load side, including current and voltage, and to build an operating model of the power regulator based on parameter identification.

[0053] The voltage sequence calculation module is used to calculate a reference voltage sequence based on the operating model and the target output voltage, combined with power quality and efficiency constraints.

[0054] The voltage regulation control module is used to monitor the power grid and load status in real time. When voltage fluctuations or abnormalities are detected, the reference voltage sequence is projected onto the safe operation envelope and graded derating control is performed.

[0055] The feedback adjustment module generates a power regulator control signal based on the corrected reference voltage sequence and calibrates the power regulator's operating model through real-time feedback.

[0056] Specifically, the voltage regulation control module includes: an abnormal event level generation unit, a limited voltage sequence calculation unit, and a voltage regulation control unit;

[0057] The abnormal event level generation unit is used to collect the state variables of the power grid side and the load side, analyze and output abnormal event records, and generate abnormal event levels according to the impact domain and duration of the abnormal event records.

[0058] The restricted voltage sequence calculation unit is used to perform amplitude compression, phase rearrangement and frequency band remapping on the reference voltage sequence in sequence according to the priority rules within the projection window corresponding to the event level, and to complete the segment replacement at the zero crossover anchor point to obtain the restricted voltage sequence.

[0059] The voltage regulation control unit is used to determine the derating level, generate a level transition table and a hold duration, and update the output control quantity according to the level transition table under the modulation clock.

[0060] Compared with the prior art, the beneficial effects of the present invention are:

[0061] This invention proposes a voltage regulation control method and system for power regulators. By establishing an online operation model of the power grid and load, a reference voltage sequence is obtained by combining the target voltage and multi-dimensional constraints. When an anomaly is detected, the sequence is projected onto the safe operation envelope. Combined with a graded derating and self-calibration mechanism, a closed-loop control is formed, realizing dynamic, layered, and gradual voltage regulation. This method can balance power quality and efficiency under normal operating conditions, and can also maintain stable voltage control when there are grid fluctuations, frequency deviations, or load changes. It avoids the resource waste caused by single shutdowns or extensive derating. At the same time, it has continuous online learning and adaptive capabilities, enabling the power regulator to maintain long-term reliable operation in complex operating conditions, improving the level of regulation and the stability of voltage regulation control. Attached Figure Description

[0062] Figure 1 A flowchart of a voltage regulation control method for a power regulator is provided by the present invention;

[0063] Figure 2 This invention provides an architecture diagram of a voltage regulation control system for a power regulator. Detailed Implementation

[0064] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0065] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0066] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. In addition, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0067] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0068] Example 1

[0069] Please see Figure 1 The present invention provides an embodiment of a method comprising the following specific steps:

[0070] Step S1: Collect parameters from the grid side and the load side, including current and voltage, and establish an operating model for the power regulator based on parameter identification.

[0071] The specific steps of step S1 are as follows:

[0072] Step S101: Set the reference phase on the grid side and trigger the first sampling cycle to divide the voltage and current signals into raw data frames.

[0073] In this embodiment, zero-crossing detection and phase tracking are performed on the grid-side voltage signal to determine the reference phase point of the grid fundamental wave. This reference point allows the initial trigger time to be locked in the sampling clock, ensuring that the acquisition of voltage and current signals is carried out under unified phase conditions and avoiding sampling errors caused by phase drift. The establishment of the original data frame is not just a simple signal segmentation, but provides a standardized reference in terms of time axis and phase for subsequent parameter identification and model construction. By marking the phase zero point at the beginning of each data frame, the timing correspondence between subsequent current, voltage, and power information is ensured. Furthermore, a redundant sampling or sliding sampling strategy is introduced when dividing the original data frame, so that there is partial overlap between adjacent data frames. This strategy can enhance the robustness of data under noise interference or grid fluctuations, and ensure the continuity and stability of the reference phase determination in actual operation.

[0074] Step S102: Introduce timing perturbations into the original data frame and synchronously collect multi-dimensional operating quantities of the power grid and load within multiple sampling periods to form a sequence dataset with perturbation tags.

[0075] In this embodiment, within a preset sampling period, a small periodic offset or randomization disturbance is applied to the reference clock, so that the sampling points of each data frame exhibit a controllable slight displacement on the time axis. While introducing the timing disturbance, the voltage, current and related state quantities of the grid side and the load side are synchronously collected in multiple sampling periods. Since the disturbance label is recorded in each data frame, a sequence dataset with disturbance label is formed.

[0076] Step S103: Perform segment comparison and cross-filtering on the sequence dataset to remove segments that do not meet the temporal consistency requirement, and obtain candidate data for identification.

[0077] In this embodiment, the sequence dataset is segmented according to temporal perturbation labels and sampling windows, so that each segment has clear start and end marks and phase correspondence. Then, comparisons are made between adjacent segments to check whether their timestamps, phase points, and perturbation offsets are consistent. If some segments cause phase drift or time misalignment due to sampling loss, noise interference, or abnormal perturbation labels, they are determined to be segments that do not meet the temporal consistency requirements and are removed. After the above processing, the candidate data obtained has structured temporal integrity and interrelation.

[0078] Step S104: Establish a multi-dimensional parameter mapping relationship based on the candidate data, and project the equivalent parameters of the power grid and the equivalent parameters of the load onto the unified operating model of the power regulator through a progressive iteration method.

[0079] In this embodiment, the voltage, current, phase, and disturbance labels contained in the candidate data are categorized, and a multi-dimensional coordinate system is established according to the time sequence and disturbance conditions. Under this coordinate system, data points of different segments are mapped to corresponding parameter trajectories, which can characterize the response characteristics of the grid side and the load side under different disturbance states. Through the mapping relationship, the distribution areas of the grid equivalent parameters and the load equivalent parameters can be intuitively distinguished spatially. It should be noted that the multi-dimensional mapping relationship is not established all at once, but gradually converges through a progressive iteration. Specifically, the grid equivalent parameters and the load equivalent parameters are roughly estimated under the initial conditions, and then projected onto the grid subspace and load subspace of the operating model, respectively. In each iteration, the parameter mapping relationship is updated using new candidate data, and the boundaries and overlapping areas of the two types of parameters are corrected. After multiple progressive iterations, the projections of the grid and load parameters gradually approach the stable solution, and finally a consistent set of parameters can be formed in the unified power regulator operating model.

[0080] Step S2: Based on the operating model and target output voltage, and combined with power quality and efficiency constraints, calculate the reference voltage sequence.

[0081] The specific steps of step S2 are as follows:

[0082] Step S201: Obtain the state variables and target output voltage of the running model within the prediction time domain window, analyze the power quality and efficiency constraints, divide them into three types of constraints: time domain, frequency domain and energy, and generate corresponding weight scheduling tables and scene labels.

[0083] In this embodiment, the running model is invoked within a preset prediction time domain to extract multi-dimensional state variables, including voltage amplitude, current phase, power factor, and switching timing, while simultaneously introducing the target output voltage as a reference benchmark. Then, the constraints related to power quality and efficiency are analyzed and classified according to their mechanisms of action. Specifically, time-domain constraints include limitations such as voltage waveform offset, zero-crossing position, and transient change rate; frequency-domain constraints cover conditions such as harmonic amplitude distribution, bandwidth occupancy, and frequency band interference elimination; and energy constraints involve indicators such as active and reactive power quotas, loss boundaries, and energy transmission efficiency. After completing the constraint classification, weights are assigned to different time-domain, frequency-domain, and energy constraints and written into a weight scheduling table. At the same time, scenario labels are generated based on grid operating conditions, load type, and disturbance level, enabling each type of constraint to be dynamically invoked in specific scenarios.

[0084] Step S202: Based on the operating model and weight scheduling table, construct a set of discrete reference trajectories, and simultaneously obtain the voltage amplitude and phase sequence in each discrete reference trajectory, and establish a modulation space index based on the voltage amplitude and phase sequence.

[0085] In this embodiment, the weighted scheduling table obtained in step S201 is imported into the running model, and the target parameter range is dynamically allocated according to different constraint priorities. For example, a tolerance is set for transient voltage offset in the time domain, a limit is set for specific harmonic components in the frequency domain, and a limit is imposed on the power factor and loss range in the energy domain. Then, within the prediction time domain window, several reference trajectories that meet the constraints are generated by point-by-point iteration and multi-scene switching, and these trajectories are stored as a set in a discretized form. When constructing the set of discrete reference trajectories, each trajectory is decomposed into two core parts: a voltage amplitude sequence and a phase sequence. The voltage amplitude sequence reflects the voltage level at each sampling time, while the phase sequence describes the offset relationship with the grid fundamental reference. A modulation space index is established based on the voltage amplitude and phase sequence. Specifically, the amplitude and phase sequences are mapped to a discrete modulation space, and a unique index identifier is assigned to each trajectory.

[0086] Step S203: Perform constraint consistency checks on the discrete reference trajectory based on the modulation spatial index, and perform segment pruning and segment replacement on the inconsistent constraint segments to obtain a feasible solution set. The constraint consistency checks include time domain boundary, frequency band occupancy, energy balance and sparsity constraints.

[0087] The specific steps of step S203 are as follows:

[0088] Step S2031: Within the preset verification window, the discrete reference trajectory is fragmented, and time stamps, spectral fingerprints, and modulation spatial indexes are written for each fragment to form a verification fragment sequence.

[0089] In this embodiment, within a preset verification window, the discrete reference trajectory is segmented according to the time step and zero-crossing position, so that each segment contains an independent amplitude sequence and phase sequence, and can be uniquely located on the time axis. Each segment needs to be written with a time stamp, spectral fingerprint and modulation spatial index. The time stamp is used to accurately identify the start and end positions of the segment in the overall trajectory, the spectral fingerprint records the frequency domain attributes of the segment by extracting the main frequency band features, and the modulation spatial index serves as an identifier for cross-segment calling and comparison. After the above processing, the resulting verification segment sequence is a set of independently callable ordered segment sequences.

[0090] Step S2032: Perform sequential checks on the test segment sequence, mark segments that do not meet preset constraints, and generate a time-domain inconsistency list.

[0091] In this embodiment, the test segment sequence is unfolded sequentially according to its time-scale order, and the start and end times, phase continuity, and sampling step size of the segments are compared point by point in a preset test window. When it is found that the time span of a segment does not match the set sampling window, or the start and end points of the segment are not aligned with the zero-crossing position of the adjacent segments, the segment is determined to have temporal inconsistency and is marked. This sequential test is not limited to the direct comparison of adjacent segments, but also includes the coherence analysis of the overall segment sequence. All segments that are determined to not meet the preset constraints will be uniformly recorded in the temporal inconsistency list.

[0092] Step S2033: Perform a joint check of frequency band occupancy and energy balance on the segments in the test segment sequence that meet the preset constraints, add the segments that conflict with the disabled frequency band table or energy quota table to the time domain inconsistency list, and generate a pruning instruction for each conflict.

[0093] In this embodiment, the test segment sequence is subjected to spectral decomposition to extract the main frequency components of the segment within the target bandwidth range, and compared with the forbidden frequency band table. When the energy distribution of a segment falls into the forbidden frequency band, the segment is determined to be in conflict with the frequency band constraint. In terms of energy balance, the active and reactive components of the segment are accumulated and checked against the upper and lower limit ranges defined by the energy quota table. If the limit is exceeded, it is considered to be in imbalanced. All conflicting segments are added to the time-domain inconsistency list, and a corresponding pruning instruction is generated for each conflict. The pruning instruction records the segment range to be deleted or replaced, the associated spectral characteristics, and the energy constraint reference value.

[0094] Step S2034: Perform sparsity determination on the non-conflicting segments after joint inspection, locate the boundary between the dense and sparse areas of the switches, add the segments that fall into the restricted area to the inconsistency list, and generate replacement instructions and splicing anchor points.

[0095] In this embodiment,

[0096] Step S2035: According to the trimming and replacement instructions, the inconsistent segments are segmented and trimmed at their splicing anchor points, and replacement segments are selected from the preset candidate segment library according to the modulation space index to complete the splicing verification, and a feasible solution set that satisfies the constraints of time domain boundary, frequency band occupancy, energy balance and sparsity is output.

[0097] In this embodiment, the modulation spatial index recorded in the segment is expanded into a switching time series, and the time interval distribution between adjacent switching events is calculated within a preset observation window. If the interval distribution of the segment is consistently lower than the sparsity threshold, it is marked as a dense switching region; if the segment interval is consistently higher than the threshold, it is marked as a sparse region. Both dense and sparse regions are prohibited areas in the operation constraints of the power regulator. Dense regions may cause excessive resource consumption in the high-frequency band, while sparse regions may cause control response lag. When it is determined that a segment, in whole or in part, falls into the prohibited area, it is directly added to the inconsistency list, and a replacement instruction is generated at the start and end positions of the segment. The final inconsistency list not only includes conflicting segments in the time domain, frequency domain, and energy dimension, but also integrates the non-compliant parts under the switching sparsity constraint.

[0098] Step S204: Based on the scene label, sort and select the feasible solution set according to the preset priority, and quantize, limit and zero-crossing align all solutions under the modulation clock to obtain the reference voltage sequence.

[0099] The specific steps of step S204 are as follows:

[0100] Step S2041: Based on the scene labels, set sorting rules for each feasible solution in the feasible solution set and form a priority sequence.

[0101] In this embodiment, each feasible solution is classified and identified based on the previously generated scenario labels, such as distinguishing between normal operating conditions, voltage fluctuation conditions, load change conditions, and frequency deviation conditions. Each scenario label corresponds to a set of constraint weights. When a feasible solution is classified into a certain scenario category, its internal parameters need to be reordered according to the constraint priority under that scenario. The setting of the sorting rules does not rely solely on a single indicator, but rather comprehensively weights time-domain constraints, frequency-domain constraints, and energy constraints according to scenario weights. Through multi-dimensional weighting, each feasible solution will obtain a comprehensive priority value under its corresponding scenario, and all feasible solutions will form an ordered priority sequence based on their comprehensive priority values.

[0102] Step S2042: At the modulation clock trigger point, select the solution with the highest priority from the priority sequence as the master solution.

[0103] In this embodiment, the modulation clock typically operates at a fixed sampling frequency, and each trigger point corresponds to a new modulation period. Within each period, a priority sorting mechanism ensures that the selected master solution is the one that best meets the requirements of the current operating conditions.

[0104] Step S2043: The discrete reference trajectory of the master solution is subjected to amplitude and phase quantization processing under a modulation clock to obtain the preliminary quantized trajectory of the master solution.

[0105] In this embodiment, at each sampling point of the modulation clock, the voltage amplitude and phase of the main solution trajectory are truncated and rounded with a preset quantization step, so that the amplitude is mapped to a finite set of levels and the phase is mapped to a discrete set of angles. The amplitude quantization result of each sampling period needs to be compared with the result of the adjacent period. If the deviation exceeds the threshold, it is compensated by fine-tuning the phase quantization result to maintain the overall smoothness of the trajectory. At the same time, the quantization of the frequency component also needs to maintain consistency with the modulation space index to ensure that the trajectory matches the preset constraint framework in both the amplitude and phase dimensions. The final preliminary quantization trajectory is completely synchronized with the modulation clock in terms of timing and is represented as a set of finite discrete points in terms of data structure.

[0106] Step S2044: Compare the preliminary quantized trajectory of the master solution point by point with the amplitude constraint and energy boundary, mark the segments that do not meet the conditions and call the backup candidate solution for local replacement to generate the corrected trajectory.

[0107] In this embodiment, the voltage amplitude and phase are compared point by point at the sampling points of the modulation clock to check whether they fall within the range specified by the amplitude limiting constraint. At the same time, it is checked whether the contribution of each sampling point in the cumulative energy curve exceeds the energy boundary. If a segment exceeds the limit in amplitude or energy distribution, the segment is immediately marked and the triggered constraint type and position index are recorded. The marked unqualified segments are not directly discarded, but are partially replaced by calling the backup candidate solution. The backup candidate solution is provided by the set of suboptimal solutions retained in the previous step S2042. Each candidate solution has compatibility with the main solution in terms of timing and scene label. During the local replacement process, the segment corresponding to the backup candidate solution is first mapped to the same interval of the current modulation clock, and its boundary is interpolated and smoothed to ensure seamless connection with the preceding and following parts of the original trajectory. The obtained corrected trajectory retains the basic structure of the main solution as a whole, while realizing compliant adjustment for amplitude limiting constraint and energy boundary locally.

[0108] Step S2045: Set alignment anchor points in the zero-crossing interval of the corrected trajectory, and perform micro-shifting and splicing verification on the sampling points in the neighborhood of the alignment anchor points, and finally output a continuous reference voltage sequence that meets the constraint conditions.

[0109] In this embodiment, the zero-crossing interval of the voltage waveform is located in the correction trajectory, and alignment anchor points are set at symmetrical positions within this interval. The anchor points serve as connection reference points to ensure phase continuity between preceding and following segments when the voltage crosses zero, avoiding discontinuities or distortions in the trajectory during switching. After the anchor points are determined, the sampling points in their neighborhood need to be slightly shifted. This slight shift refers to making minor adjustments to adjacent sampling points on the time axis while ensuring that the amplitude and phase do not exceed the amplitude limit constraints and energy boundaries, making the connection between segments smoother. Subsequently, the slightly shifted sampling points are spliced ​​with the preceding and following segments, and consistency checks are performed at the splicing point, including amplitude continuity checks, phase monotonicity checks, and frequency band integrity checks. The final output reference voltage sequence is globally continuous, locally smooth, and satisfies the previously set multidimensional constraints.

[0110] Step S3: Monitor the grid and load status in real time. When voltage fluctuations or abnormalities are detected, project the reference voltage sequence onto the safe operation envelope and perform graded derating control.

[0111] The specific steps of step S3 are as follows:

[0112] Step S301: Acquire the state variables of the power grid side and the load side under the synchronization reference, generate a continuous state vector stream, and write the scene label and event counter for each sampling period.

[0113] In this embodiment, a phase-locked loop (PLL) reference signal is used to correct the sampling clock, ensuring that all sampling points use the zero-crossing or a specific phase point of the grid fundamental frequency as a reference. Subsequently, within each sampling period, voltage, current, and frequency offset from the grid side are simultaneously acquired, along with state variables such as voltage, current, and power factor from the load side. After obtaining the aforementioned sampling data, a continuous state vector stream is generated by sequentially concatenating them. Each state vector contains multi-dimensional data from both the grid and load sides. Simultaneously, a scene label is added to each sampling period during state vector generation, resulting in a state vector stream that is not only temporally continuous but also semantically rich in labels and event markers.

[0114] Step S302: Preset an anomaly pattern library, perform sliding window comparison on the state vector stream, output anomaly event records according to the anomaly pattern library, and generate anomaly event levels according to the influence domain and duration of the anomaly event records.

[0115] In this embodiment, feature templates for multiple typical operational anomalies are preset in the anomaly pattern library, such as voltage dips, voltage surges, frequency shifts, harmonic distortions, and load mutations. For each type of anomaly, corresponding time-domain waveform features, frequency-domain component distributions, and energy mutation thresholds are extracted. During operation, the state vector flow is expanded in a sliding window manner, with each window covering several consecutive sampling periods. The multidimensional state data within the window is sequentially matched and compared with the anomaly pattern library. If the matching result exceeds the set similarity threshold, it can be determined that a corresponding anomaly exists within the window, and an anomaly event record is generated at the output end. All anomaly events are summarized in the form of records and classified into different anomaly levels according to their impact domain and duration. For example, transient disturbances can be judged as low-level, while long-term global fluctuations are upgraded to high-level, resulting in the final anomaly event level.

[0116] Step S303: Construct a safe operation envelope based on the power regulator's operation model and preset constraints, discretize the safe operation envelope into a multi-level boundary set, and configure priority rules and start / stop conditions for each level of boundary.

[0117] In this embodiment, the power grid equivalent parameters and load equivalent parameters identified in the early stage are imported into the operating model of the power regulator. Combined with constraints such as power quality, efficiency limits, and device operating range, the operating space is analyzed. During the analysis, the allowable ranges of voltage amplitude, phase, bandwidth occupancy, and energy quota under different operating conditions are calculated respectively, and these ranges are projected into a multi-dimensional envelope interval. This envelope interval defines the safety boundary that the regulator must follow when there are grid disturbances or load changes. The envelope interval is not a single boundary, but is discretized into a set of boundaries at multiple levels. For example, the first level boundary can correspond to the limitation under slight fluctuation conditions, the second level boundary corresponds to the contraction range under moderate disturbance conditions, and the higher level is for the extreme operation under severe fault conditions. Each level contains specific amplitude upper limit, phase offset tolerance, and energy constraint boundary, forming a layered and progressive protection framework.

[0118] Furthermore, while constructing multi-level boundary sets, priority rules and start / stop conditions are configured for each level. Priority rules are used to determine the order of boundary calls when multiple constraints are triggered simultaneously, while start / stop conditions specify the criteria for boundary entry and exit, such as using anomaly level, event duration, or cumulative energy deviation as triggering criteria.

[0119] Step S304: Within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero crossover anchor point to obtain the restricted voltage sequence.

[0120] The specific steps of step S304 are as follows:

[0121] Step S3041: Receive the projection command triggered by the abnormal event level, and select the boundary layer corresponding to the level in the multi-level boundary set in the safe operation envelope.

[0122] In this embodiment, the abnormal event level generated by the preceding step S302 is parsed into a projection instruction. This instruction carries parameters such as abnormal type, influence domain, and duration. After receiving the projection instruction, the control logic will perform a matching search in the multi-level boundary set of the safe operation envelope. Since the multi-level boundary set has predefined boundary layers corresponding to different abnormal levels, it can quickly locate the level that matches the current abnormality and determine the voltage amplitude limit, phase tolerance range, and energy distribution boundary covered by that level.

[0123] Step S3042: Compress the amplitude range of the reference voltage sequence segment by segment within the boundary layer, and write the compressed segments into the tag table.

[0124] Step S3043: Rearrange the phase order of adjacent segments according to the label table to make them conform to the phase sequence rules of the boundary layer.

[0125] In this embodiment, the marker table records the phase start point, end point, and adjacent relationships of each segment before correction, and also provides the reference phase order under the boundary layer requirements. After retrieving the marker table, the control logic first identifies whether there are any inversions, jumps, or discontinuities in the phase connection between adjacent segments, and includes the parts that do not conform to the boundary layer rules in the rearrangement list. Then, by adjusting the arrangement order of the segments on the time axis, the phase evolution direction is made consistent with the boundary layer rules to avoid phase misalignment when the trajectory crosses segments. In the rearrangement process, the segments are not simply swapped, but constrained by the phase continuity condition. The final trajectory strictly conforms to the boundary layer rules in phase evolution, and achieves smooth connection between adjacent segments.

[0126] Step S3044: Perform frequency band remapping on the rearranged segments to map them to the frequency range of the boundary layer and generate splicing anchor points.

[0127] In this embodiment, the rearranged trajectory segment undergoes spectral analysis to extract its main frequency components and harmonic distribution, which are then compared with the target frequency range defined by the boundary layer. When some frequency components in the segment exceed the allowable range, the control logic redistributes these components to the effective frequency band defined by the boundary layer by adjusting the sampling point interval or phase step. Frequency band remapping is not just a simple frequency shift, but a multi-dimensional adjustment combining segment characteristics and boundary layer rules. For example, when the high-order harmonic energy in the segment is too high, it can be weakened and dispersed to adjacent frequency bands through remapping. When low-frequency components are insufficient, the gap is filled by frequency domain compensation, so that the overall spectrum of the segment is closer to the template requirements of the target boundary layer. After remapping, splicing anchor points are generated at the boundary of the segment. The splicing anchor points are used to identify the docking positions of different segments in the two dimensions of time and frequency, ensuring that the amplitude, phase and spectrum can be consistently connected in the subsequent splicing process.

[0128] Step S3045: At the splicing anchor point, the frequency band remapped segment and the unmodified segment are spliced ​​and verified to obtain a continuous restricted voltage sequence.

[0129] In this embodiment, pre-generated splicing anchor points are invoked at the segment boundary positions. The anchor points contain time markers, phase alignment information, and amplitude reference values. The control logic compares the remapped segment and the unmodified segment point by point at the anchor points to check the differences between them in amplitude, phase, and sampling interval. When the difference exceeds a set threshold, it is adjusted by interpolation correction or micro-shift. The splicing verification is not limited to direct comparison of boundary points, but also includes continuity checks of neighboring intervals. The final constrained voltage sequence is a continuous waveform on the time axis, maintains a consistent distribution characteristic in the frequency domain, and meets the boundary conditions of the safe operation envelope.

[0130] Step S305: Determine the derating level based on the restricted voltage sequence and multi-level boundary set, generate a level transition table and hold duration, and update the output control quantity according to the level transition table under the modulation clock.

[0131] The specific steps of step S305 are as follows:

[0132] Step S3051: Compare the restricted voltage sequence with the multi-level boundary set segment by segment to generate a decision table of boundary hit marks, duration period and segment position, and determine the candidate derating level set based on the decision table.

[0133] In this embodiment,

[0134] Step S3052: Based on the candidate reduction level set and the abnormal event level, select the current reduction level and determine its adjacent levels to obtain a level relationship set including entry conditions and release conditions.

[0135] In this embodiment, the restricted voltage sequence is divided according to the modulation period, and each segment retains key information such as amplitude, phase, and energy components. Then, a multi-level boundary set is invoked to examine each segment individually to see if its amplitude reaches the boundary threshold, if its phase shift exceeds the tolerance range, and if its energy quota exceeds the defined range. When any segment is detected to have reached or exceeded the boundary conditions, a boundary hit marker is generated at that segment. The hit marker is not isolated but is statistically analyzed in conjunction with the duration period and segment location. The duration period is used to determine whether a boundary trigger is a short-term disturbance or a long-term anomaly, while the segment location identifies the temporal distribution of the trigger point throughout the sequence. Based on the judgment table, a candidate derating level set can be determined. The candidate set typically contains multiple level intervals, corresponding to different boundary levels and trigger intensities.

[0136] Step S3053: Construct a level transition table on the set of level relationships and configure the retention time for each transition path.

[0137] In this embodiment, the hierarchical order and adjacency relationships between candidate levels are clearly defined in the hierarchical relationship set, such as unidirectional promotion or bidirectional fallback paths between low, medium, and high levels. Then, based on this, transition paths are generated one by one, and entry and exit conditions are added to each path to ensure logical coherence in the switching between different levels, rather than arbitrary jumps. A hold duration is configured on each transition path. The hold duration specifies that after a level transition is completed, a certain period of time must be maintained before another switch can occur.

[0138] Step S3054: Under the modulation clock, perform a periodic evaluation of the current level according to the level transition table and the holding duration. If the entry conditions are met, perform a level switch at the zero crossover anchor point. If the conditions are not met, maintain the existing level and update the timing state.

[0139] In this embodiment, the state of the current level is determined within each modulation clock cycle to check whether the entry conditions specified in the transition table are met, including factors such as the number of boundary hits, duration, and energy deviation. When the conditions are met, the control logic will perform level switching at the zero-crossing anchor point to ensure that the switching process is aligned with the zero-crossing point of the waveform, thereby avoiding abrupt changes in the amplitude and phase of the voltage sequence. If the evaluation result shows that the conditions are insufficient, the current level remains unchanged, and the timing state is updated to the next cycle until the transition conditions are met. The final control effect is that, under the precise drive of the modulation clock, the switching of the derating level is consistent with the zero-crossing point, the level stability is guaranteed, and the trajectory continuity is maintained.

[0140] Step S3055: Write the level change result and timing status back to the event counter and safe operation envelope, and select the corresponding output control quantity according to the current level.

[0141] In this embodiment, after the cycle evaluation is completed under the modulation clock, if a level switch occurs, the new level marker and the corresponding hold timer state are first written back to the event counter to record the number of switching occurrences, duration, and triggered boundary layer information. Simultaneously, this level information is written to the safe operating envelope, enabling the envelope to dynamically adjust its constraints based on the latest level in subsequent cycles, achieving bidirectional consistency between the operating boundary and the derating level. After the write-back operation is completed, the corresponding output control quantity must be selected according to the current level. The output control quantity is typically preset as a voltage amplitude template, phase modulation template, or energy distribution template for different levels. By matching the correspondence between the current level and the template library, control instructions conforming to the level constraints can be quickly extracted and loaded for execution in the next cycle of the modulation clock. If the current level remains unchanged, the output control quantity directly uses the existing template, only updating the timer state to record the continuation of the current cycle. The final output control quantity maintains a strict correspondence with the current level, while both the event counter and the safe operating envelope retain the latest level state.

[0142] Step S4: Generate the power regulator control signal based on the corrected reference voltage sequence, and calibrate the power regulator's operating model through real-time feedback.

[0143] Example 2

[0144] Please see Figure 2 Another embodiment of the present invention provides: a voltage regulation control system for a power regulator, comprising: a model building module, a voltage sequence calculation module, a voltage regulation control module, and a feedback adjustment module;

[0145] The model building module is used to collect parameters from the grid side and the load side, including current and voltage, and to build an operating model of the power regulator based on parameter identification.

[0146] The voltage sequence calculation module is used to calculate a reference voltage sequence based on the operating model and the target output voltage, combined with power quality and efficiency constraints.

[0147] The voltage regulation control module is used to monitor the power grid and load status in real time. When voltage fluctuations or abnormalities are detected, the reference voltage sequence is projected onto the safe operation envelope and graded derating control is performed.

[0148] The feedback adjustment module generates a power regulator control signal based on the corrected reference voltage sequence and calibrates the power regulator's operating model through real-time feedback.

[0149] The voltage regulation control module includes: an abnormal event level generation unit, a limited voltage sequence calculation unit, and a voltage regulation control unit;

[0150] The abnormal event level generation unit is used to collect the state variables of the power grid side and the load side, analyze and output abnormal event records, and generate abnormal event levels according to the impact domain and duration of the abnormal event records.

[0151] The restricted voltage sequence calculation unit is used to perform amplitude compression, phase rearrangement and frequency band remapping on the reference voltage sequence in sequence according to the priority rules within the projection window corresponding to the event level, and to complete the segment replacement at the zero crossover anchor point to obtain the restricted voltage sequence.

[0152] The voltage regulation control unit is used to determine the derating level, generate a level transition table and a hold duration, and update the output control quantity according to the level transition table under the modulation clock.

[0153] In addition, the parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of the corresponding technical solutions in the prior art have not been described in detail, so as to avoid excessive elaboration.

[0154] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A voltage regulation control method for a power regulator, applied to a power regulator containing controllable rectifier / inverter or solid-state switching devices, characterized in that, include: Collect parameters from the grid side and the load side, including current and voltage, and establish an operating model for the power regulator based on parameter identification; Based on the aforementioned operating model and target output voltage, and combined with power quality and efficiency constraints, a reference voltage sequence is calculated. The system monitors the power grid and load status in real time. When voltage fluctuations or anomalies are detected, the reference voltage sequence is projected onto the safe operation envelope, and graded derating control is performed. The power regulator control signal is generated based on the corrected reference voltage sequence, and the operation model of the power regulator is calibrated through real-time feedback. The real-time monitoring of the power grid and load status, when detecting voltage fluctuations or anomalies, projects the reference voltage sequence onto the safe operating envelope and performs graded derating control, including: Under the synchronous reference, the state variables of the power grid side and the load side are collected to generate a continuous state vector stream, and a scene label and event counter are written for each sampling period. A preset abnormal pattern library is used to perform sliding window comparison on the state vector stream, output abnormal event records according to the abnormal pattern library, and generate abnormal event levels according to the influence domain and duration of the abnormal event records. A safe operation envelope is constructed based on the operation model and preset constraints of the power regulator. The safe operation envelope is discretized into a multi-level boundary set, and priority rules and start / stop conditions are configured for each level of boundary. Within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero crossover anchor point to obtain the restricted voltage sequence. The derating level is determined based on the restricted voltage sequence and the multi-level boundary set, a level transition table and a hold duration are generated, and the output control quantity is updated according to the level transition table under the modulation clock.

2. The voltage regulation control method for a power regulator as described in claim 1, characterized in that, The process involves collecting parameters from both the grid and load sides, including current and voltage, and establishing an operating model for the power regulator based on these parameters. Set the reference phase on the grid side and trigger the first sampling cycle, dividing the voltage and current signals into raw data frames; A temporal perturbation is introduced into the original data frame, and multi-dimensional operating quantities of the power grid and load are collected synchronously in multiple sampling periods to form a sequence dataset with perturbation tags; The sequence dataset is segmented and cross-filtered to remove segments that do not meet the temporal consistency requirement, thereby obtaining candidate data for identification. Based on the candidate data, a multidimensional parameter mapping relationship is established, and the equivalent parameters of the power grid and the equivalent parameters of the load are projected onto the unified operating model of the power regulator through a progressive iterative method.

3. The voltage regulation control method for a power regulator as described in claim 2, characterized in that, Based on the aforementioned operating model and target output voltage, and considering power quality and efficiency constraints, a reference voltage sequence is calculated, including: Within the prediction time domain window, the state variables and target output voltage of the running model are obtained, the power quality and efficiency constraints are analyzed, and they are divided into three types of constraints: time domain, frequency domain and energy domain. Corresponding weight scheduling tables and scene labels are generated. Based on the aforementioned operating model and weight scheduling table, a set of discrete reference trajectories is constructed. At the same time, the voltage amplitude and phase sequence in each discrete reference trajectory are obtained, and a modulation space index is established based on the voltage amplitude and phase sequence. Based on the modulation space index, the discrete reference trajectory is subjected to constraint consistency check, and the inconsistent constraint segments are segmented, pruned and replaced to obtain a feasible solution set. The constraint consistency check includes time domain boundary, frequency band occupancy, energy balance and sparsity constraints. Based on scene labels, feasible solutions are sorted and selected according to preset priorities. Then, under the modulation clock, all solutions are quantized, limited, and zero-crossing aligned to obtain a reference voltage sequence.

4. The voltage regulation control method for a power regulator as described in claim 3, characterized in that, The constraint consistency check of the discrete reference trajectory based on the modulation spatial index is performed, and the segments with inconsistent constraints are segmented, pruned, and replaced to obtain a feasible solution set, including: Within a preset inspection window, the discrete reference trajectory is fragmented, and time stamps, spectral fingerprints, and modulation spatial indexes are written for each fragment to form an inspection fragment sequence. The sequence of test segments is sequentially tested, segments that do not meet preset constraints are marked, and a list of temporal inconsistencies is generated. For segments in the test segment sequence that meet the preset constraints, a joint test of frequency band occupancy and energy balance is performed. Segments that conflict with the prohibited frequency band table or energy quota table are added to the time domain inconsistency list, and a pruning instruction is generated for each conflict. For segments that do not conflict after joint inspection, sparsity is determined, the boundary between the dense and sparse areas of switches is located, segments that fall into the restricted area are added to the inconsistency list, and replacement instructions and splicing anchors are generated. According to the trimming and replacement instructions, inconsistent segments are trimmed at their splicing anchor points, and replacement segments are selected from the preset candidate segment library according to the modulation space index to complete the splicing verification, and a set of feasible solutions that meet the constraints of time domain boundary, frequency band occupancy, energy balance and sparsity is output.

5. The voltage regulation control method for a power regulator as described in claim 4, characterized in that, The feasible solution set is sorted and selected according to a preset priority based on scene labels, and all solutions are quantized, limited, and zero-crossing aligned under the modulation space index to obtain a reference voltage sequence, including: Based on scene labels, sorting rules are set for each feasible solution in the feasible solution set, and a priority sequence is formed; At the modulation clock trigger point, the solution with the highest priority is selected as the master solution from the priority sequence; The discrete reference trajectory of the master solution is subjected to amplitude and phase quantization processing under a modulation clock to obtain the preliminary quantized trajectory of the master solution; The preliminary quantized trajectory of the master solution is compared point by point with the amplitude constraint and energy boundary. Segments that do not meet the conditions are marked and local replacements are performed by calling backup candidate solutions to generate a corrected trajectory. Alignment anchors are set in the zero-crossing interval of the corrected trajectory, and the sampling points in the neighborhood of the alignment anchors are slightly shifted and spliced ​​for verification. Finally, a continuous reference voltage sequence that meets the constraint conditions is output.

6. The voltage regulation control method for a power regulator as described in claim 5, characterized in that, Within the projection window corresponding to the event level, the reference voltage sequence is sequentially subjected to amplitude compression, phase rearrangement, and frequency band remapping according to the priority rules, and segment replacement is completed at the zero-crossing anchor point to obtain a restricted voltage sequence, including: Receive projection instructions triggered by the abnormal event level, and select the boundary layer corresponding to that level in the multi-level boundary set in the safe operation envelope; Within the boundary layer, the amplitude range of the reference voltage sequence is compressed segment by segment, and the compressed segments are written into a tag table; The phase order of adjacent segments is rearranged according to the label table to conform to the phase sequence rules of the boundary layer; The rearranged segments are remapped to the frequency range of the boundary layer, and splicing anchor points are generated. At the splicing anchor point, the frequency band remapped segment is spliced ​​and verified with the unmodified segment to obtain a continuous restricted voltage sequence.

7. The voltage regulation control method for a power regulator as described in claim 6, characterized in that, Based on the constrained voltage sequence and multi-level boundary set, the derating level is determined, a level transition table and hold duration are generated, and the output control quantity is updated according to the transition table under the modulation clock, including: The restricted voltage sequence is compared segment by segment with the multi-level boundary set to generate a judgment table of boundary hit mark, duration period and segment position, and the candidate derating level set is determined based on the judgment table. Based on the candidate reduction level set and the abnormal event level, the current reduction level is selected and its adjacent levels are determined, resulting in a level relationship set that includes entry conditions and removal conditions; Construct a hierarchy transition table on the set of hierarchy relationships and configure the retention time for each transition path; Under the modulation clock, the current level is periodically evaluated according to the level transition table and the holding time. If the entry condition is met, the level switch is performed at the zero crossover anchor point. If the condition is not met, the existing level is maintained and the timing state is updated. Write the level change result and timing status back to the event counter and safe operation envelope, and select the corresponding output control quantity according to the current level.

8. A voltage regulation control system for a power regulator, used to implement the voltage regulation control method for a power regulator according to any one of claims 1-7, characterized in that, include: The module includes a model building module, a voltage sequence calculation module, a voltage regulation control module, and a feedback adjustment module. The model building module is used to collect parameters from the grid side and the load side, including current and voltage, and to build an operating model of the power regulator based on parameter identification. The voltage sequence calculation module is used to calculate a reference voltage sequence based on the operating model and the target output voltage, combined with power quality and efficiency constraints. The voltage regulation control module is used to monitor the power grid and load status in real time. When voltage fluctuations or abnormalities are detected, the reference voltage sequence is projected onto the safe operation envelope and graded derating control is performed. The feedback adjustment module generates a power regulator control signal based on the corrected reference voltage sequence and calibrates the power regulator's operating model through real-time feedback.

9. A voltage regulation control system for a power regulator as described in claim 8, characterized in that, The voltage regulation control module includes: an abnormal event level generation unit, a limited voltage sequence calculation unit, and a voltage regulation control unit; The abnormal event level generation unit is used to collect the state variables of the power grid side and the load side, analyze and output abnormal event records, and generate abnormal event levels according to the impact domain and duration of the abnormal event records. The restricted voltage sequence calculation unit is used to perform amplitude compression, phase rearrangement and frequency band remapping on the reference voltage sequence in sequence according to the priority rules within the projection window corresponding to the event level, and to complete the segment replacement at the zero crossover anchor point to obtain the restricted voltage sequence. The voltage regulation control unit is used to determine the derating level, generate a level transition table and a hold duration, and update the output control quantity according to the level transition table under the modulation clock.

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