Process angle self-adjusting circuit and method for controlling duration of overvoltage existence

Abstract

The application belongs to the field of radio frequency circuits, and particularly relates to a process angle self-adjusting circuit and method for controlling the duration of an overshoot voltage, comprising: a decision voltage generation circuit, configured to generate a decision voltage and output the decision voltage to the positive input terminals of an upper limit comparator and a lower limit comparator; a window voltage generation circuit, configured to generate a window voltage comprising an upper limit window voltage and a lower limit window voltage, output the upper limit window voltage to the negative input terminal of the upper limit comparator, and output the lower limit window voltage to the negative input terminal of the lower limit comparator; the upper limit comparator, configured to compare the decision voltage and the upper limit window voltage and output a high level or a low level; and the lower limit comparator, configured to compare the decision voltage and the lower limit window voltage and output a high level or a low level. The application successfully realizes process angle control over the existing time performance of an overshoot voltage by controlling the access number of time control devices of an overshoot voltage generation module.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of radio frequency circuit, and particularly relates to a process angle self-adjusting circuit and method for controlling the duration of an overshoot voltage. BACKGROUND

[0002] In a radio frequency circuit, a circuit such as a power amplifier has a power fluctuation that is troublesome to trim. A certain duration of an overshoot voltage is introduced in a power supply module LDO to solve the problem at a minimum cost. This depends on an overshoot voltage generation module, but a conventional overshoot voltage generation module usually has poor process angle resistance, and it is difficult to achieve similar overshoot voltage duration performance at all process angles.

[0003] Therefore, how to make the duration of the overshoot voltage similar at all process angles has become a technical problem to be solved. SUMMARY

[0004] The first aspect of the application provides a process angle self-adjusting circuit for controlling the duration of an overshoot voltage, which solves the problem that a conventional overshoot voltage generation module usually has poor process angle resistance and it is difficult to achieve similar overshoot voltage duration performance at all process angles.

[0005] The first aspect of the application provides a method for controlling the duration of an overshoot voltage.

[0006] The process angle self-adjusting circuit for controlling the duration of an overshoot voltage according to the first aspect of the application comprises a decision voltage generation circuit, a window voltage generation circuit, an upper limit comparator, a lower limit comparator, and two MOS tube switches.

[0007] The decision voltage generation circuit is configured to generate a decision voltage and output the decision voltage to the positive input terminals of the upper limit comparator and the lower limit comparator.

[0008] The window voltage generation circuit is configured to generate a window voltage comprising an upper limit window voltage and a lower limit window voltage, output the upper limit window voltage to the negative input terminal of the upper limit comparator, and output the lower limit window voltage to the negative input terminal of the lower limit comparator.

[0009] The upper limit comparator compares the decision voltage and the upper limit window voltage and outputs a high level or a low level, which is used to control the closing or opening of one of the two MOS tube switches.

[0010] The lower limit comparator compares the decision voltage and the lower limit window voltage and outputs a high level or a low level, which is used to control the closing or opening of the other MOS tube switch.

[0011] Further, when the decision voltage is lower than the lower limit window voltage, the upper limit comparator and the lower limit comparator both output a high level to control the two MOS tube switches to be all closed.

[0012] Further, when the decision voltage is within the voltage window, the upper limit comparator outputs a high level and the lower limit comparator outputs a low level, and one MOS switch is turned off.

[0013] Further, when the decision voltage is higher than the upper limit window voltage, both the upper limit comparator and the lower limit comparator output a low level, and all MOS switches are turned off.

[0014] According to the method for controlling the duration of the overvoltage according to the second aspect of the present application, the method comprises:

[0015] generating a decision voltage;

[0016] generating a window voltage comprising an upper limit window voltage and a lower limit window voltage;

[0017] comparing the decision voltage with the window voltage, and generating two levels for controlling the closing or opening of the MOS switches according to the comparison result, so as to control the state of the two MOS switches, wherein the state comprises all closed, all open, or one closed and one open;

[0018] controlling the access of the delay device in the overvoltage generation circuit according to the state of the two MOS switches.

[0019] Further, the comparison of the decision voltage with the window voltage and the generation of the two levels for controlling the closing or opening of the MOS switches according to the comparison result, so as to control the state of the two MOS switches, comprises:

[0020] when the decision voltage is lower than the lower limit window voltage, outputting two high levels to control the two MOS switches to be all closed;

[0021] when the decision voltage is within the voltage window, outputting one high level and one low level to turn off one MOS switch;

[0022] when the decision voltage is higher than the upper limit window voltage, outputting two low levels to turn off all MOS switches.

[0023] Compared with the prior art, the present application has the beneficial effect that the present application introduces logical control in the existing overvoltage generation module, controls the access number of the time control device (such as resistor-capacitor) of the overvoltage generation module, and successfully realizes the process corner control on the existing time performance of the overvoltage. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a schematic diagram of the process corner self-adjusting circuit for controlling the duration of the overvoltage provided by the embodiments of the present application;

[0025] Figure 2is a traditional overvoltage waveform diagram of an overvoltage generation circuit provided by an embodiment of the present application;

[0026] Figure 3 is an overvoltage waveform diagram of an overvoltage generation circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0028] In view of the fact that the power amplifier and other circuits in the prior art have power fluctuations that are difficult to adjust, it is easier to solve this problem in an analog LDO (low dropout linear regulator) used for power supply than in a power amplifier. However, the traditional overvoltage generation module usually has poor process angle resistance, and it is difficult to achieve similar delay performance in the full process angle. The present application provides a process angle self-adjusting circuit for controlling the duration of the overvoltage, which realizes automatic adjustment of the duration of the overvoltage by sequentially electrically connecting a decision voltage generation circuit, a window voltage generation circuit, a comparator and a MOS tube switch. The duration of the overvoltage is adjusted to be approximately the same as the duration of the TT (Typical-Typical, typical- typical) process angle. The TT process angle refers to the process parameters of the NMOS transistor and the PMOS transistor being at typical values during chip manufacturing; the FS process angle refers to the parameters of the NMOS transistor being at a fast value and the parameters of the PMOS transistor being at a slow value; the SF process angle refers to the parameters of the NMOS transistor being at a slow value and the parameters of the PMOS transistor being at a fast value; and the FF process angle refers to the NMOS and PMOS being in the fastest state. The parameters of the NMOS transistor or the parameters of the PMOS transistor refer to various physical and electrical characteristics that affect the performance of the transistor, including mobility, threshold voltage, leakage current, transconductance, output impedance, saturation current and parasitic capacitance.

[0029] Please refer to Figure 1 An embodiment of the present application provides a process angle self-adjusting circuit for controlling the duration of the overvoltage. It includes a decision voltage generation circuit, a window voltage generation circuit, an upper limit comparator, a lower limit comparator and two MOS tube switches.

[0030] The main function of the decision voltage generation circuit is to generate a stable reference voltage. A stable reference voltage can be generated as a decision voltage by dividing the voltage of a stable power supply through a resistor divider, or by using other existing circuits that can generate a stable reference voltage. In the present application, no limitation is made.

[0031] The window voltage generating circuit defines a voltage window including an upper limit window voltage and a lower limit window voltage by generating two stable reference voltages, which can be generated by two resistive voltage dividers or other existing circuits capable of generating two stable reference voltages, and the embodiments of the present application do not make any limitation.

[0032] The decision voltage is adjusted so as to be within the voltage window, higher than the upper limit window voltage, or lower than the lower limit window voltage.

[0033] The comparator is used to compare two input voltages and output a high level or a low level, which is connected to the control end of the MOS switch and controls the closing and opening of the MOS switch.

[0034] The output end of the decision voltage generating circuit is connected to the positive input end of the upper limit comparator and the lower limit comparator, and the window voltage generating circuit includes two output ends outputting two voltages of different sizes, wherein the output end outputting the upper limit window voltage is connected to the negative input end of the upper limit comparator, and the output end outputting the lower limit window voltage is connected to the negative input end of the lower limit comparator.

[0035] The upper limit comparator compares the decision voltage and the upper limit window voltage and outputs a high level or a low level, which is used to control the closing or opening of one of the MOS switches. In the embodiment, the upper limit comparator compares the decision voltage and the upper limit window voltage, outputs a high level when the decision voltage is less than the upper limit window voltage, and the high level can control the closing of the MOS switch; and outputs a low level when the decision voltage is higher than the upper limit window voltage, and the low level can control the opening of the MOS switch.

[0036] The lower limit comparator compares the decision voltage and the lower limit window voltage and outputs a high level or a low level, which is used to control the closing or opening of the other MOS switch. When the decision voltage is less than the lower limit window voltage, the lower limit comparator outputs a high level, and the high level can control the closing of the MOS switch; and when the decision voltage is higher than the lower limit window voltage, the lower limit comparator outputs a low level, and the low level can control the opening of the MOS switch.

[0037] The control process includes: when the decision voltage is lower than the lower limit window voltage, the upper limit comparator and the lower limit comparator output high level, all the MOS switch are closed, the access number of the delay control device is reduced by two groups, the delay control device refers to the time control device for controlling the overshoot voltage generation module, such as resistance, capacitance or the combination of resistance and capacitance, the delay control device is controlled to be accessed or disconnected through the MOS switch, when the MOS switch is closed, the delay control device is not accessed to the circuit, when the MOS switch is disconnected, the delay control device is accessed to the circuit, the existence time of the overshoot of the SS process angle (slow-slow process angle) is shortened to the existence time under the TT process angle; when the decision voltage is in the voltage window, the upper limit comparator outputs high level, the lower limit comparator outputs low level, one MOS switch is disconnected, and the access number of the delay control device is only increased by one group, the existence time of the overshoot of the TT, FS (Fast-Slow) and SF (Slow-Fast) process angles is maintained at the standard of the existence time under the TT process angle. When the decision voltage is higher than the upper limit window voltage, the upper limit comparator and the lower limit comparator both output low level, all the MOS switches are disconnected, and the access number of the delay control device is increased by two groups, the delay time of the FF process angle is prolonged to the standard of the time under the TT process angle.

[0038] In another aspect, the application provides a method for controlling the existence time of the overshoot voltage, which includes:

[0039] Generating a decision voltage; the decision voltage is generated by a circuit capable of generating an output voltage, and the output voltage can be adjusted.

[0040] Generating a window voltage including an upper limit window voltage and a lower limit window voltage; the size of the upper limit window voltage and the lower limit window voltage needs to be combined with the decision voltage, so that the decision voltage is between the window voltage, or greater than the upper limit window voltage or less than the lower limit window voltage when adjusted.

[0041] Comparing the decision voltage with the window voltage, and generating two levels for controlling the closing or opening of the MOS switch according to the comparison result, which is used to control the state of the two MOS switches, including all closed, all disconnected or one closed and one disconnected;

[0042] Controlling the access of the delay control device in the overshoot voltage generation circuit according to the state of the two MOS switches.

[0043] In an embodiment, the decision voltage is compared with the window voltage, and two levels for controlling the closing or opening of the MOS switch are generated according to the comparison result, which is used to control the state of the two MOS switches, including:

[0044] When the decision voltage is lower than the lower limit window voltage, two high levels are output, two MOS switch are closed, the access number of two sets of delay control devices is reduced, the delay control device refers to the time control device of the overshoot voltage generation module, such as resistance, capacitance or the combination of resistance and capacitance, the delay control device is controlled to be connected or disconnected through the MOS switch, when the MOS switch is closed, the delay control device is not connected to the circuit, when the MOS switch is disconnected, the delay control device is connected to the circuit, the existence time of the overshoot of the SS process angle (slow-slow process angle) is shortened to the existence time under the TT process angle;

[0045] When the decision voltage is in the voltage window, one high level and one low level are output, one MOS switch is disconnected, and the access number of one set of delay control devices is increased, the existence time of the overshoot of the TT, FS (fast-slow) and SF (slow-fast) process angles is maintained at the standard of the existence time under the TT process angle;

[0046] When the decision voltage is higher than the upper limit window voltage, two low levels are output, all the MOS switches are disconnected, and the access number of two sets of delay control devices is increased, the delay time of the FF process angle is extended to the standard of the time under the TT process angle.

[0047] Figure 2 The waveform diagram of the traditional overshoot voltage generation module is shown in FIG. 1. The waveform shown is the waveform of the output voltage VOUT of the overshoot voltage generation module.

[0048] Figure 3 The output voltage waveform diagram of the overshoot voltage generation module after applying the process angle self-adjusting circuit for controlling the existence time of the overshoot voltage is shown in FIG. 2.

[0049] Please refer to Figure 2 and Figure 3 , respectively, at temperatures of 25℃, -40℃ and 95℃, the existence time of the overshoot under the SS process angle and the FF process angle is very different from the existence time under the TT process angle, the existence time of the overshoot under the FS process angle and the SF process angle is close to the existence time under the TT process angle. After applying the process angle self-adjusting circuit, as shown in Figure 3 , the existence time of the overshoot under the five process angles is all adjusted to be similar.

[0050] The above only describes the preferred embodiments of the present application and is not used to limit the present application, any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A process angle self-adjusting circuit for controlling the duration of overshoot voltage, characterized in that, include: The circuit consists of a decision voltage generation circuit, a window voltage generation circuit, an upper limit comparator, a lower limit comparator, and two MOSFET switches. The decision voltage generation circuit is used to generate a decision voltage and output it to the positive input terminals of the upper limit comparator and the lower limit comparator; The window voltage generation circuit is used to generate a window voltage including an upper window voltage and a lower window voltage, output the upper window voltage to the negative input terminal of the upper window comparator, and output the lower window voltage to the negative input terminal of the lower window comparator. The upper limit comparator compares the decision voltage and the upper limit window voltage, and outputs a high level or a low level to control the closing or opening of one of the MOSFET switches; The lower limit comparator compares the decision voltage and the lower limit window voltage, and outputs a high level or a low level to control the closing or opening of another MOSFET switch; When the decision voltage is lower than the lower limit window voltage, both the upper limit comparator and the lower limit comparator output a high level, controlling both MOSFET switches to close completely. When the decision voltage is within the voltage window, the upper limit comparator outputs a high level and the lower limit comparator outputs a low level, thus disconnecting one MOSFET switch. When the decision voltage is higher than the upper limit window voltage, both the upper limit comparator and the lower limit comparator output a low level, and all MOSFET switches are turned off.

2. A method for controlling the duration of overshoot voltage, characterized in that, include: Generate a decision voltage; Generate a window voltage that includes an upper window voltage and a lower window voltage; The decision voltage is compared with the window voltage, and two control levels for the MOSFET switches are generated based on the comparison result to control the state of the two MOSFET switches, including both closed, both open, or one closed and one open. The connection of the delay control device in the overshoot voltage generation circuit is controlled according to the state of the two MOSFET switches.

3. The method for controlling the duration of overshoot voltage according to claim 2, characterized in that, The comparison of the decision voltage with the window voltage, and the generation of two control levels for the closing or opening of the MOSFET switches based on the comparison result, are used to control the state of the two MOSFET switches, including: When the decision voltage is lower than the lower limit window voltage, two high levels are output to control both MOSFET switches to be closed. When the decision voltage is within the voltage window, output a high level and a low level to disconnect a MOSFET switch. When the decision voltage is higher than the upper limit window voltage, two low levels are output, and all MOSFET switches are turned off.

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