Capacitor mismatch error shaping circuit and method suitable for multi-bit quantization Sigma-Delta ADC

Abstract

The invention discloses a capacitor mismatch error shaping circuit and method suitable for a multi-bit quantization Sigma-Delta ADC, and belongs to the technical field of integrated circuits, and the capacitor mismatch error shaping circuit comprises a data weight averaging module which is used for adopting a data weight averaging technology for high-bit quantization code words, and correcting the high-bit quantization code words according to the data weight averaging technology; averaging the mismatch error of the capacitor corresponding to the high-order quantization code word to obtain an averaged high-order capacitor; and the mismatch error shaping module is used for taking the averaged high-order capacitance as a reference, adopting a mismatch error shaping technology, keeping low-order feedback of the current low-order quantization code word of the lower polar plate of the capacitive digital-to-analog converter during Sigma-Delta ADC sampling, and realizing subtraction operation between two adjacent low-order quantization code words. According to the invention, the error caused by the mismatch of the CDAC capacitor fed back by the multi-bit quantization Sigma-Delta ADC can be effectively suppressed, the linearity of the system is improved, and the circuit overhead is remarkably reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a capacitor mismatch error shaping circuit and method suitable for a multi-bit quantization Sigma-Delta ADC. BACKGROUND

[0002] Analog-to-digital converter (ADC) as a bridge connecting the analog domain and the digital domain, its performance is related to the quality of signal conversion, in today's signal processing system, a high-performance analog-to-digital converter is indispensable. Analog-to-digital converters can be divided into Nyquist type and oversampling type according to the relationship between their sampling frequency and input signal bandwidth, the former has a sampling frequency of about twice the input signal bandwidth, allowing a higher input signal bandwidth, mainly used in high-bandwidth fields, successive approximation register (SAR) analog-to-digital converters, pipeline analog-to-digital converters and parallel comparison (Flash) analog-to-digital converters belong to this category. The sampling frequency of the latter is generally much higher than the input signal bandwidth, which is generally a Sigma-Delta analog-to-digital converter. Although oversampling limits the allowable input signal bandwidth, making it unsuitable for high-speed scenarios, the noise shaping characteristics and oversampling technology of Sigma-Delta analog-to-digital converters make it easy to achieve high resolution and have good performance in high-precision application scenarios.

[0003] Early Sigma-Delta analog-to-digital converters use single-bit quantization, but as new application scenarios emerge, people's requirements for the accuracy of analog-to-digital converters are getting higher and higher, and multi-bit quantization technology is widely used. Compared with single-bit quantization, multi-bit quantization produces less quantization noise, and Sigma-Delta analog-to-digital converters of the same order can achieve higher accuracy. At the same time, the quantization step of multi-bit quantization is smaller, and compared with single-bit quantization, the output fluctuation of the analog-to-digital converter is smaller, and it has higher stability under the same order.

[0004] Although multi-bit quantization can greatly improve the accuracy and stability of Sigma-Delta analog-to-digital converters, in the actual manufacturing process of the circuit, due to the limitations of the process, the size of the capacitors in the digital-to-analog converter (DAC) unit cannot be completely consistent, resulting in a deviation between the analog voltage obtained by the feedback loop through the DAC and the ideal situation. This non-linear error caused by the mismatch between the capacitors in the DAC unit is called mismatch error or mismatch noise, and the capacitor mismatch error will be directly transferred to the Sigma-Delta analog-to-digital converter loop, increasing the non-linearity of the system, limiting the signal-to-noise ratio and other performances of the analog-to-digital converter, and the mismatch error has become the main factor restricting the accuracy of multi-bit quantization Sigma-Delta analog-to-digital converters.

[0005] To ensure the high-precision characteristics of multi-bit quantization Sigma-Delta analog-to-digital converters, dynamic element matching technology (DEM) is generally used to suppress or compensate for mismatch errors. Among various DEM technologies, data weighted averaging (DWA) is widely used due to its simple implementation. The core idea of DWA is to use the characteristic that the average error of all DAC unit capacitors is 0, to select each capacitor in a cycle until all capacitors are selected, and to repeat this process to average the mismatch error. However, since binary code needs to be converted into thermometer code, the circuit area increases by a factor of two for each additional bit. The exponential increase in DWA circuit area with the number of quantization bits makes this technology generally only applicable to quantization bits below 5.

[0006] Mismatch error shaping (MES) was first applied to the mismatch error shaping of noise shaping successive approximation analog-to-digital converters. The specific idea is to use the largest element size as a reference, considering that mismatch errors only exist in other low-order elements. The low-order code word of the last sampling is retained in each sampling to directly construct a first-order shaping function for the mismatch error. The advantage is that the implementation is relatively simple, does not increase additional circuitry, and the circuit structure is much simpler than DWA in the case of a large number of quantization bits. However, the operation of introducing the last low-order code word during sampling greatly reduces the allowable range of the input signal. To ensure that the quantizer is not saturated, the maximum amplitude of the input signal is only about half of the full-scale input.

[0007] Therefore, it is necessary to improve the traditional mismatch error shaping scheme to meet the design requirements of high-precision Sigma-Delta analog-to-digital converters with more bits of quantization. SUMMARY

[0008] The present application provides a capacitor mismatch error shaping circuit and method suitable for multi-bit quantization Sigma-Delta ADCs to solve the technical problem of excessive circuit overhead of traditional mismatch error shaping schemes in high-precision Sigma-Delta analog-to-digital converters with more bits of quantization.

[0009] To solve the above technical problems, the present application provides the following technical solutions: In one aspect, the application provides a capacitor mismatch error shaping circuit suitable for multi-bit quantization Sigma-Delta ADC, which is used for processing a DAC array to realize capacitor mismatch error shaping; wherein the DAC array is divided into two segments, the first N / 2 bits are recorded as high-bit quantization code words, and the last N / 2 bits are recorded as low-bit quantization code words; wherein N is the total number of bits of the DAC array; the capacitor mismatch error shaping circuit comprises: a data weight average module, which is used for, for high-bit quantization code words, adopting a data weight average technique to average the mismatch error of the capacitor corresponding to the high-bit quantization code words, and obtaining the averaged high-bit capacitor; a mismatch error shaping module, which is used for, taking the averaged high-bit capacitor as a reference, adopting a mismatch error shaping technique to keep the current low-bit quantization code word of the lower plate of the low-bit feedback capacitor type digital-to-analog converter during Sigma-Delta ADC sampling, and realizing the difference operation between adjacent two low-bit quantization code words.

[0010] Further, the data weight average module is specifically used for: taking the high-bit quantization code word as input, selecting a corresponding number of 1bit DAC units in turn according to the input N / 2-bit binary code, until all 1bit DAC units are selected, and selecting the first 1bit DAC unit as the starting position to realize the averaging of the capacitor mismatch error corresponding to the high-bit quantization code word.

[0011] Further, the data weight average module comprises: a thermometer code decoder, which is used for converting the input high-bit quantization code word into a multi-bit thermometer code; a two-input back-end carry adder, which is used for summing and taking modulo M of the binary code input at the current clock and the pointer address of the last clock to obtain a new pointer address; wherein M is the total number of bits of the thermometer code; a logarithmic shift circuit, which is used for performing a corresponding shift operation on the input thermometer code according to the new pointer address, and outputting the shifted data to the 1bit DAC unit.

[0012] Further, the thermometer code decoder is composed of NAND gates, NOR gates and inverters.

[0013] Further, the two-input back-end carry adder is composed of four one-bit full adders in series.

[0014] Further, the logarithmic shift circuit is composed of a plurality of transmission gates; wherein the transmission gate adopts a complementary CMOS structure, i.e. a PMOS tube and an NMOS tube are connected in a butt joint manner.

[0015] Further, the mismatch error shaping module comprises a plurality of MES multiplexers.

[0016] Further, the MES multipath gating switch is a three-to-one switch, and an output of the MES multipath gating switch is connected to a lower plate of a 1bit DAC unit capacitor; in a reset state, the output of the MES multipath gating switch is a common mode level, and the connected 1bit DAC unit capacitor is fully discharged; in a working state, the MES multipath gating switch keeps the output of a corresponding high or low level according to the current input low bit quantization code word.

[0017] In another aspect, the application further provides a capacitive mismatch error shaping method suitable for a multi-bit quantization Sigma-Delta ADC, which is implemented by using the capacitive mismatch error shaping circuit, and the method comprises the following steps: The DAC array to be processed is divided into two segments, the former N / 2 bits are recorded as high bit quantization code words, and the latter N / 2 bits are recorded as low bit quantization code words; wherein, N is the total number of bits of the DAC array; By using the data weight average module, for the high bit quantization code word, the data weight average technology is used to average the mismatch error of the capacitors corresponding to the high bit quantization code word, and the averaged high bit capacitor is obtained. By using the mismatch error shaping module, the averaged high bit capacitor is taken as a reference, the mismatch error shaping technology is used to keep the current low bit quantization code word of the lower plate of the low bit feedback capacitor type digital-to-analog converter during the sampling of the Sigma-Delta ADC, and the difference operation between two adjacent low bit quantization code words is implemented.

[0018] The technical scheme provided by the application has at least the following beneficial effects: Different from the traditional DWA circuit, the capacitive mismatch error shaping circuit provided by the application combines the DWA technology and the MES technology, and is applied to the capacitive mismatch error shaping of the multi-bit quantization Sigma-Delta analog-to-digital converter. The DAC array is divided into two segments of high bits and low bits, the DWA technology is applied to average the mismatch error of the high bit capacitors, and the averaged high bit capacitor can be regarded as a reference of the MES of the low bit capacitors. The combination of the two methods not only ensures the suppression effect on the mismatch error, but also avoids the excessive circuit overhead of the traditional DWA scheme. The application can effectively suppress the error caused by the mismatch of the feedback DAC capacitors of the multi-bit quantization Sigma-Delta ADC, improve the linearity of the system, and significantly reduce the circuit overhead compared with the traditional DWA scheme. BRIEF DESCRIPTION OF DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the logic of the high-bit codeword DWA algorithm implemented by the data weight averaging module provided in this embodiment of the invention; Figure 3 This is a schematic diagram of the mismatch error shaping module provided in this embodiment of the invention applied to the first-stage integrator in the loop of a Sigma-Delta analog-to-digital converter; Figure 4 This is the signal flow graph of a second-order feedforward Sigma-Delta ADC that does not contain the capacitor mismatch error shaping circuit of this invention; Figure 5 This is the signal flow graph of a second-order feedforward Sigma-Delta ADC containing the capacitor mismatch error shaping circuit of the present invention; Figure 6 This is a schematic diagram of the dynamic performance of a second-order feedforward Sigma-Delta ADC before and after implementing the capacitor mismatch error shaping circuit of the multi-bit quantization Sigma-Delta ADC according to the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0022] First, it should be noted that in the embodiments of the present invention, the words "exemplarily," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplarily" is intended to present the concept in a specific manner. Furthermore, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either one or the other.

[0023] First Embodiment

[0024] This embodiment provides a capacitor mismatch error shaping circuit suitable for multi-bit quantized Sigma-Delta ADCs, used to process the DAC array and achieve capacitor mismatch error shaping; wherein, the DAC array is divided into high and low segments, the first N / 2 bits are denoted as the high-order codeword, and the last N / 2 bits are denoted as the low-order codeword; where N is the total number of bits in the DAC array; as shown Figure 1 As shown, the capacitor mismatch error shaping circuit includes: The data weight averaging module is used to average the mismatch error of the capacitors corresponding to the high-order quantized codewords using data weight averaging technology; the averaged high-order capacitors can be regarded as the reference for the low-order capacitor MES. The mismatch error shaping module is used to maintain the current second-lowest quantization codeword of the lower plate of the low-bit feedback capacitor type digital-to-analog converter during Sigma-Delta ADC sampling using mismatch error shaping technology, and to perform difference operations between two adjacent low-bit quantization codewords.

[0025] The circuit structure and working principle of this embodiment will be described in detail below, taking the application of the circuit of this embodiment to a second-order feedforward Sigma-Delta ADC with an 8-bit loop quantizer as an example.

[0026] like Figure 1 As shown, the input to the data weight averaging module is the high 4 bits of the quantization result, and the output is 15 DWA strobe signals. These signals are connected to the lower plates of the capacitors of the 15 1-bit DAC units corresponding to the high 4 bits of the codeword, thus selecting 15 different 1-bit DAC units. Its function is to sequentially select a corresponding number of 1-bit DAC units based on the input 4-bit binary codeword until all 1-bit DAC units have been selected. Then, it restarts the selection process, starting from the first 1-bit DAC unit, to achieve the averaging of the mismatch error corresponding to the high-bit codeword.

[0027] Specifically, the data weight averaging module mainly consists of a thermometer code decoder, a 4-bit adder with carry-back, and a logarithmic shift circuit. The thermometer decoder converts the high 4 bits of the current clock quantization result into 15-bit thermometer codes corresponding to the 15 1-bit DAC units, representing the number of 1-bit DAC units to be selected. The 4-bit adder with carry-back sums the current clock input binary code with the pointer address of the previous clock, modulo 15, and takes the remainder to obtain a new pointer address, thus implementing the data weight averaging logic. The logarithmic shift circuit performs a corresponding shift operation on the input thermometer code based on the pointer address of the current clock and outputs the shifted data to the 1-bit DAC units. Its output is 15 DWA strobe signals, connected to the lower plates of the capacitors of the 15 1-bit DAC units, sequentially selecting the number of 1-bit DAC units corresponding to the high 4 bits of the binary code based on the output of the 4-bit adder with carry-back.

[0028] In this embodiment, the thermometer code decoder is a decoder that decodes a 4-bit unsigned input binary code into a 15-bit thermometer code output, mainly composed of NAND gates, NOR gates, and inverters. The 4-bit adder with carry-back is composed of four 1-bit full adders connected in series to realize the summation operation of two 4-bit binary codes. The output carry signal of the fourth-order adder is connected to the input carry signal of the first-order adder to realize the operation S(n)=[S(n-1)+x(n)]mod(15), where S(n) and x(n) are the output and input 4-bit binary codes of the 4-bit adder with carry-back at the nth clock cycle, respectively. The logarithmic shift circuit is mainly composed of multiple transmission gates, which adopt a complementary CMOS structure, that is, the PMOS transistors are connected to the NMOS transistors. The control signal for the logarithmic shift circuit is the output signal of the adder mentioned above. Based on the 4-bit binary code at the output, the corresponding transmission gate is selected, and the input signal of the logarithmic shift circuit is shifted accordingly to select different 1-bit DAC units.

[0029] The data weight averaging module implements the logic of the high-bit codeword DWA algorithm as follows: Figure 2 As shown, the core idea of ​​DWA is to select unit elements in the DAC in a round-robin fashion. Since in both full-scale output and output 0, all 15 1-bit DAC units are either selected or none are selected, these two output scenarios can be considered to be free of mismatch error, meaning the average mismatch error can be considered to be 0. Data weighted averaging (DWA) utilizes this principle, aiming to give each unit element the same weight in selection, thus averaging out the error. This is equivalent to first-order shaping of the mismatch error. Figure 2Given a DWA logic diagram with the input sequence {7, 6, 3, 2, 5}, the DWA pointer is initially located at 1-bit DAC unit 1. When the first input 7 arrives, DAC units 1 through 7 are selected, and the DWA pointer moves to DAC unit 8. The second input 6 selects 6 DAC units starting from DAC unit 8, and the DWA pointer moves to DAC unit 14. When the next input 3 arrives, two DAC units are selected starting from DAC unit 14. Since all DAC units have been selected once, the selection restarts from DAC unit 1. Therefore, the three selected DAC units for this input are DAC unit 14, DAC unit 15, and DAC unit 1, and the DWA pointer moves to DAC unit 2. This cycle repeats as described above.

[0030] The mismatch error shaping module includes four identical MES multiplexers (such as...). Figure 1 (The structure shown in the lower right dashed box) Each MES multiplexer is a 3-to-1 switch, with its output connected to the lower plate of a 1-bit DAC unit capacitor. Its output is determined by the reset signal Rst and the lower 4 bits of the output codeword Bi. In the reset state, i.e., when Rst is active, the output is at a common-mode level, fully discharging the connected 1-bit DAC unit capacitor. In the operating state, it maintains the corresponding high or low level output according to the current ADC output codeword. For a detailed explanation of the working principle of this MES multiplexer, please refer to [link to relevant documentation]. Figure 3 The LSB section: Above the capacitor marked LSB is the lower plate of the "1-bit DAC unit capacitor" mentioned in this paragraph, where the connection is... Figure 1 The output signal of the MES multiplexer switch is shown in the dashed box at the bottom right. The entire feedback DAC has three operating states, initially undergoing a reset phase. Figure 3 When all switches are closed, the Rst signal is high, making... Figure 1 The Out output of the MES multiplexer in the lower right dashed box is connected to the common-mode level Vcm, while the PMOS and NMOS transistors connected to VDD and Gnd are cut off. Therefore, the Out signal is at the common-mode level, and all the upper and lower plates of the LSB capacitors are at the common-mode level, thus being fully discharged. After the reset phase, the Rst signal goes low, causing the NMOS and PMOS transistors in the Out-Vcm connection path to be cut off. At this time, the i-th Out signal is determined by the quantization code Bi of that bit to output a high or low level. Therefore, the lower plate of the LSB capacitor will maintain the high or low level corresponding to the current quantization code. Since the quantization code is in the sampling phase of the integrator ( Figure 3 The update is performed at the end of the above process, thus implementing the difference operation between two adjacent LSB quantization results during the integration process of the integrator, as described below.

[0031] Figure 3 This is a schematic diagram of applying the mismatch error shaping module of this embodiment to the first-stage integrator in the Sigma-Delta analog-to-digital converter loop. During the integrator's sampling clock, the capacitors of the high-order MSB are fully discharged, while the lower plates of the low-order LSB capacitors maintain the high / low level states corresponding to the low-order codewords of the previous quantization result. This is equivalent to adding an extra analog voltage corresponding to the low-order codewords of the previous quantization result during sampling. During the integrator's integration clock, similar to a traditional integrator, the potentials of the lower plates of all capacitors in the feedback DAC are determined by the codeword of the current quantization result. The integration process subtracts the current quantization result and calculates the difference between two adjacent low-order codewords. The time-domain expression of the overall discrete-time integrator can be described as: Vout(n) = Vout(n-1) + Vin(n) - D MSB (n)-[D LSB (n)-D LSB (n-1)].

[0032] The application effect of the circuit in this embodiment will be verified below.

[0033] Figure 4 This is the signal flow graph of a second-order feedforward Sigma-Delta ADC without the circuitry of this embodiment. The quantization noise E... q and mismatch noise E m The noise transfer functions are NTF and NTF respectively. Eq =(1-z -1 ) 2 and NTF Em =(1-z -1 ) 2 -1. The quantization error introduced by the quantizer will be shaped by the second order of the Sigma-Delta loop, but the mismatch error introduced by the feedback DAC will be injected directly from the ADC input terminal along with the input signal. It cannot be shaped by the Sigma-Delta loop and will cause serious nonlinearity when mixed with the input signal.

[0034] Figure 5 This is the signal flow graph of a second-order feedforward Sigma-Delta ADC containing the circuitry of this embodiment. The quantization noise E... q and mismatch noise E m The noise transfer functions are NTF and NTF respectively. Eq =(1-z -1 ) 2 and NTF Em =-z -1 [(1-z -1 )+(1-z -1 ) 2 The quantization error is a second-order integer, while the mismatch error is basically a first-order integer.

[0035] Figure 6 This is a schematic diagram illustrating the dynamic performance of the second-order feedforward Sigma-Delta ADC before and after applying the circuit of this embodiment. For example... Figure 6 As shown, the top two curves represent the output spectra of the 8-bit quantized second-order feedforward Sigma-Delta ADC before and after applying the circuit of this embodiment, respectively, with a mismatch standard deviation of 1% between the DAC unit capacitors. The third curve represents the ideal output spectrum without mismatch. The simulation results are consistent with the theoretical derivation. In the absence of mismatch, only quantization error exists. The quantization error is shaped by the second-order Sigma-Delta loop, and the output spectrum exhibits a characteristic of 40dB per decade in the low-frequency range, indicating that the quantization error is shaped by the second order. After mismatch is introduced, many harmonic components appear in the spectrum. The main constraint on ADC performance at this point is the mismatch error introduced by the unit capacitance mismatch of the 8-bit feedback DAC. This manifests in the spectrum as a raised noise floor and the introduction of harmonic components, significantly reducing the ADC's signal-to-noise ratio (SNR) and spurious-free dynamic range. The mismatch error shaping circuit can greatly reduce the nonlinearity introduced by the mismatch. The spectrum shows a significant reduction in harmonic components compared to the case without the shaping circuit, and the mismatch noise also exhibits first-order shaping characteristics. In the low-frequency range, the mismatch noise is shaped by a function with a slope of approximately 20 dB per decade, pushing most of the noise power to the high-frequency range, consistent with theoretical derivations. Compared to the unshaping case, the SNR is improved by more than 30 dB, equivalent to an improvement of approximately 5 effective bits.

[0036] In summary, this embodiment provides a capacitor mismatch error shaping circuit suitable for multi-bit quantized Sigma-Delta ADCs. Unlike traditional DWA circuits, this embodiment combines DWA and MES technologies for capacitor mismatch error shaping in multi-bit quantized Sigma-Delta analog-to-digital converters. The DAC array is divided into high-order and low-order segments. DWA is applied to the high-order segments to average the mismatch error of the high-order capacitors. The averaged high-order capacitors can then be used as a reference for the low-order capacitor MES. This combination of methods ensures effective suppression of mismatch errors while avoiding the excessive circuit overhead of traditional DWA solutions. It effectively suppresses errors caused by capacitor mismatch in the feedback DAC of multi-bit quantized Sigma-Delta ADCs, improves system linearity, and significantly reduces circuit overhead compared to traditional DWA solutions.

[0037] Second Embodiment

[0038] This embodiment provides a capacitance mismatch error shaping method suitable for multi-bit quantization Sigma-Delta ADCs, implemented using the aforementioned capacitance mismatch error shaping circuit. The method includes: The DAC array to be processed is divided into two segments. The first N / 2 bits are denoted as the high-order quantization codeword, and the last N / 2 bits are denoted as the low-order quantization codeword; where N is the total number of bits in the DAC array. Using the data weight averaging module, for the high-order quantized codeword, the data weight averaging technique is used to average the mismatch error of the capacitor corresponding to the high-order quantized codeword, and the averaged high-order capacitor is obtained. Using the mismatch error shaping module, with the averaged high-order capacitance as a reference, the mismatch error shaping technique is employed to maintain the current second-lowest quantization codeword of the lower plate of the low-order feedback capacitor type digital-to-analog converter during Sigma-Delta ADC sampling, thereby realizing the difference operation between two adjacent low-order quantization codewords.

[0039] It should be noted that the process steps in the capacitance mismatch error shaping method for multi-bit quantized Sigma-Delta ADCs in this embodiment correspond one-to-one with the functions implemented by the functional modules in the capacitance mismatch error shaping circuit of the first embodiment described above; therefore, they will not be repeated here.

[0040] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0041] Furthermore, the term "and / or" merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. A and B can be singular or plural. Additionally, the character " / " in this text generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship; please refer to the context for specific interpretations. "At least one" refers to one or more, while "more" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0042] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention. It should be pointed out that although preferred embodiments of the present invention have been described, those skilled in the art, once they understand the basic inventive concept of the present invention, can make several improvements and modifications without departing from the principles described herein. These improvements and modifications should also be considered within the scope of protection of the present invention. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

Claims

1. A capacitor mismatch error shaping circuit suitable for multi-bit quantized Sigma-Delta ADCs, used to process DAC arrays to achieve capacitor mismatch error shaping; characterized in that, The DAC array is divided into two segments, with the first N / 2 bits designated as the high-order quantization codeword and the last N / 2 bits designated as the low-order quantization codeword; where N is the total number of bits in the DAC array; the capacitor mismatch error shaping circuit includes: The data weight averaging module is used to average the mismatch error of the capacitor corresponding to the high-order quantized codeword using data weight averaging technology, and obtain the averaged high-order capacitance. The mismatch error shaping module is used to maintain the current second-lowest quantization codeword of the lower plate of the low-bit feedback capacitor type digital-to-analog converter during Sigma-Delta ADC sampling, using the averaged high-bit capacitor as a reference and employing mismatch error shaping technology, so as to realize the difference operation between two adjacent low-bit quantization codewords.

2. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 1, characterized in that, The data weight averaging module is specifically used for: Using the high-order quantization codeword as input, the corresponding number of 1-bit DAC units are selected sequentially according to the input N / 2-bit binary code, until all 1-bit DAC units have been selected. Then, the selection is restarted with the first 1-bit DAC unit as the starting position, so as to achieve the averaging of the capacitor mismatch error corresponding to the high-order quantization codeword.

3. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 1, characterized in that, The data weight averaging module includes: A thermometer code decoder is used to convert the input high-bit quantization codeword into a multi-bit thermometer code. The two-input carry-back adder is used to sum the binary code of the current clock input with the pointer address of the previous clock, and then take the remainder modulo M to obtain the new pointer address; where M is the total number of bits in the thermometer code; The logarithmic shift circuit is used to perform corresponding shift operations on the input thermometer code according to the new pointer address, and output the shifted data to the 1-bit DAC unit.

4. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 3, characterized in that, The thermometer code decoder consists of NAND gates, NOR gates, and inverters.

5. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 3, characterized in that, The two-input carry-back adder is composed of four one-bit full adders connected in series.

6. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 3, characterized in that, The logarithmic shift circuit consists of multiple transmission gates; wherein, the transmission gates adopt a complementary CMOS structure, that is, the PMOS transistors and NMOS transistors are connected.

7. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 1, characterized in that, The mismatch error shaping module includes multiple MES multiplex switches.

8. The capacitor mismatch error shaping circuit for multi-bit quantization Sigma-Delta ADC as described in claim 7, characterized in that, The MES multiplexer is a 3-to-1 switch, and its output is connected to the lower plate of a 1-bit DAC unit capacitor. In the reset state, the output of the MES multiplexer is at a common-mode level, which fully discharges the connected 1-bit DAC unit capacitor. In the working state, the MES multiplexer maintains the corresponding high or low level output according to the currently input low-order quantization codeword.

9. A method for shaping capacitance mismatch error in a multi-bit quantized Sigma-Delta ADC using the capacitance mismatch error shaping circuit for multi-bit quantized Sigma-Delta ADCs as described in any one of claims 1 to 8, characterized in that, The method includes: The DAC array to be processed is divided into two segments. The first N / 2 bits are denoted as the high-order quantization codeword, and the last N / 2 bits are denoted as the low-order quantization codeword; where N is the total number of bits in the DAC array. Using the data weight averaging module, for the high-order quantized codeword, the data weight averaging technique is used to average the mismatch error of the capacitor corresponding to the high-order quantized codeword, and the averaged high-order capacitor is obtained. Using the mismatch error shaping module, with the averaged high-order capacitance as a reference, the mismatch error shaping technique is employed to maintain the current second-lowest quantization codeword of the lower plate of the low-order feedback capacitor type digital-to-analog converter during Sigma-Delta ADC sampling, thereby realizing the difference operation between two adjacent low-order quantization codewords.

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