Semiconductor device and forming method thereof

Abstract

The present disclosure relates to methods, devices, systems, and techniques for managing contact structures in semiconductor devices. An exemplary semiconductor device includes a first semiconductor structure. The first semiconductor structure includes: a first stack of conductive layers and isolation layers alternating with each other in a first direction; a second stack of conductive layers and isolation layers alternating with each other in the first direction; the semiconductor layer is positioned between the first stacking body and the second stacking body along the first direction; a contact structure connected to the semiconductor layer, where the contact structure extends in the first direction through the first stack, the semiconductor layer, and the second stack; and a channel structure extending in the first direction through the first stack, the semiconductor layer, and the second stack, where the semiconductor layer is in contact with a channel layer of the channel structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing contact structures in semiconductor devices.

[0004] One aspect of this disclosure is a semiconductor device. The semiconductor device includes a first semiconductor structure. The first semiconductor structure includes: a first stack of conductive and insulating layers alternating with each other along a first direction; a second stack of conductive and insulating layers alternating with each other along the first direction; a semiconductor layer located between the first and second stacks along the first direction; a contact structure connected to the semiconductor layer, wherein the contact structure extends along the first direction through the first stack, the semiconductor layer, and the second stack; and a channel structure extending along the first direction through the first stack, the semiconductor layer, and the second stack, wherein the semiconductor layer contacts the channel layer of the channel structure.

[0005] In some embodiments, the first stack includes at least a first stack, the first stack including one or more of the conductive and insulating layers in the first stack, and the contact structure includes a first segment extending through the first stack along the first direction.

[0006] In some embodiments, the first stack further includes a second stack comprising one or more of the conductive and insulating layers in the first stack, and the contact structure further includes a second segment extending through the second stack along the first direction and a third segment extending through the second stack.

[0007] In some embodiments, the channel structure includes a first segment, a second segment, and a third segment, wherein the first segment of the channel structure extends through the first stack along the first direction, the second segment of the channel structure extends through the second stack along the first direction, and the third segment of the channel structure extends through the second stack along the first direction.

[0008] In some implementations, the number of one or more conductive layers in the first stack is in the range of 3 to 10.

[0009] In some embodiments, the semiconductor device further includes a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure along the first direction via a bonding structure. The second semiconductor structure includes control circuitry configured to control the channel structure of the first semiconductor structure.

[0010] In some embodiments, the first semiconductor structure includes a first interconnect layer coupled to the contact structure, and the first interconnect layer is coupled to the second semiconductor structure via the bonding structure.

[0011] In some embodiments, the second semiconductor structure includes a second interconnect layer coupled to the first interconnect layer via the bonding structure.

[0012] In some embodiments, the channel structure includes a first end coupled to a first bit line extending along a second direction perpendicular to the first direction and a second end coupled to a second bit line extending along the second direction, the first bit line being coupled to the control circuitry of the second semiconductor structure, and the first bit line being coupled to the second bit line via a bit line contact structure extending along the first direction.

[0013] In some embodiments, the contact structure includes at least one of a metallic material, polycrystalline silicon, or titanium nitride (TiN).

[0014] Another aspect of this disclosure is a method comprising: forming a first stack of a first semiconductor structure, wherein the first stack includes sacrificial layers and isolation layers alternating with each other along a first direction; forming a second stack of the first semiconductor structure, wherein the second stack includes sacrificial layers and isolation layers alternating with each other along the first direction; forming a semiconductor layer of the first semiconductor structure, wherein the semiconductor layer is located between the first stack and the second stack along the first direction; forming a contact structure of the first semiconductor structure, wherein the contact structure is connected to the semiconductor layer and extends through the first stack, the semiconductor layer and the second stack along the first direction; and forming a channel structure of the first semiconductor structure, wherein the channel structure extends through the first stack, the semiconductor layer and the second stack along the first direction, and the channel layer of the channel structure is in contact with the semiconductor layer.

[0015] In some embodiments, forming the first stack includes forming a first stack and a second stack of the first stack, wherein each of the first stack and the second stack includes one or more of the sacrificial layers and isolation layers in the first stack; forming the contact structure includes forming a first segment of a contact hole extending through the first stack in the first direction and a second segment of the contact hole extending through the second stack in the first direction; and forming the channel structure includes forming a first segment of a channel hole extending through the first stack in the first direction and a second segment of the channel hole extending through the second stack in the first direction, wherein the first segment of the channel hole and the first segment of the contact hole are formed by a first etching process, and the second segment of the channel hole and the second segment of the contact hole are formed by a second etching process.

[0016] In some embodiments, the semiconductor layer forming the first semiconductor structure includes forming a first stop layer, a sacrificial array common source (ACS) layer, and a second stop layer on top of the first stack, the sacrificial ACS layer being located between the first stop layer and the second stop layer along the first direction; and forming the second stack includes forming the second stack on top of the second stop layer.

[0017] In some embodiments, forming the contact structure includes forming a third segment extending along the first direction through the second stack, the second stop layer, the sacrificial ACS layer, and the first stop layer of the contact hole; and forming the channel structure includes forming a third segment extending along the first direction through the second stack, the second stop layer, the sacrificial ACS layer, and the first stop layer of the channel hole, wherein the third segment of the channel hole and the third segment of the contact hole are formed by a third etching process.

[0018] In some embodiments, forming the contact structure includes: depositing a dielectric material and a conductive material into the contact hole to form a dielectric layer and a conductive layer of the contact structure, respectively; and forming the channel structure includes forming a channel layer and a memory film in the channel hole, wherein the memory film surrounds the channel layer.

[0019] In some embodiments, forming the semiconductor layer of the first semiconductor structure includes: removing the sacrificial ACS layer to form a space; removing a portion of the memory film of the channel structure to expose a portion of the channel layer of the channel structure; removing a portion of the dielectric layer of the contact structure to expose a portion of the conductive layer of the contact structure; and depositing semiconductor material into the space to form the semiconductor layer.

[0020] In some embodiments, the method further includes replacing the sacrificial layer in the first stack and the sacrificial layer in the second stack with a conductive layer.

[0021] In some embodiments, the method further includes: forming a bit line and a first interconnect layer on a first side of the first semiconductor structure, wherein the first interconnect layer is coupled to the channel structure and the contact structure, and the first bit line extends along a second direction perpendicular to the first direction and is coupled to a first end of the channel structure; forming a second semiconductor structure including control circuitry configured to control the channel structure and the second interconnect layer of the first semiconductor structure; and bonding the first side of the first semiconductor structure to the second semiconductor structure via a bonding structure, wherein the first interconnect layer is coupled to the second interconnect layer via the bonding structure.

[0022] In some embodiments, the method further includes: forming a second bit line extending along the second direction on a second side of the first semiconductor structure; and forming a bit line contact structure extending along the first direction, wherein the bit line contact structure is coupled to the first bit line and the second bit line.

[0023] Another feature of this disclosure is a memory system. The memory system includes: a memory device including a first semiconductor structure; and a memory controller coupled to and configured to control the memory device. The first semiconductor structure includes: a first stack of conductive and insulating layers alternating with each other along a first direction; a second stack of conductive and insulating layers alternating with each other along the first direction; a semiconductor layer located between the first and second stacks along the first direction; a contact structure connected to the semiconductor layer, wherein the contact structure extends along the first direction through the first stack, the semiconductor layer, and the second stack; and a channel structure extending along the first direction through the first stack, the semiconductor layer, and the second stack, wherein the semiconductor layer contacts the channel layer of the channel structure.

[0024] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0025] Figures 1A-1C An exemplary semiconductor device is shown.

[0026] Figure 2A-Figure 2ZZ An exemplary process for manufacturing a semiconductor device is shown.

[0027] Figure 3 A flowchart illustrating an exemplary process for manufacturing a semiconductor device is shown.

[0028] Figure 4 A block diagram of an exemplary system is shown.

[0029] Similar reference numerals and designations in the various figures denote similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative and are not necessarily drawn to scale. Detailed Implementation

[0030] In some 3D NAND memory devices, the memory cells of the memory array are interconnected using vertical channels and led out by a unified array common source (ACS) and drain metal lines (e.g., bit lines). The channel saturation current (Ion) of the memory device characterizes its performance. In some implementations, the channel saturation current Ion can influence the threshold voltage (Vt) distribution, thereby degrading the memory device's performance (e.g., generating more programming / read / verification errors). Furthermore, because the bit lines are connected to the page buffer, the level of the channel saturation current Ion can also affect the functionality of the page buffer. For example, if the channel saturation current of the memory device is too low, the page buffer may fail to function, potentially leading to a range of reliability issues for the memory device. As the number of layers in a 3D NAND memory device increases, the channel length also increases, resulting in a decrease in the channel saturation current, which reduces the reliability and performance of the memory device in several ways. Additionally, a larger ACS resistance can lead to source line noise problems. Therefore, it is desirable to maintain or increase the channel saturation current of the 3D NAND memory device and reduce the ACS resistance when stacking more layers.

[0031] To address one or more of the aforementioned problems, the techniques described in this disclosure allow an ACS layer to be formed in the middle (e.g., vertically) of a memory array and two bit lines to be formed on both sides (e.g., top and bottom) of the memory array. In one or more embodiments of this disclosure, an exemplary semiconductor device is provided. The semiconductor device may be a memory device (e.g., a 3D NAND memory device). The semiconductor device includes two stacks of alternating conductive and insulating layers in a vertical direction. The semiconductor device also includes a semiconductor layer (e.g., an ACS layer) located vertically between the two stacks. A contact structure of the semiconductor device is connected to the semiconductor layer and extends vertically through the two stacks and the semiconductor layer. A channel structure of the semiconductor device also extends vertically through the two stacks and the semiconductor layer. The semiconductor layer contacts the channel layer of the channel structure.

[0032] Implementation of this disclosure can provide one or more of the following technical advantages and / or benefits. First, the equivalent channel length of the memory array of the memory device can be reduced, thereby increasing the channel saturation current Ion. In some embodiments, the operations of this disclosure can be introduced to form an ACS layer in the middle of the memory array, and by using bit line contact structures to connect the top and bottom bit lines, the channel length of the memory array of the memory device is approximately halved by electrically connecting the two channels in parallel. Furthermore, the contact structures can reduce the length of the conductive path between the ACS layer and the control circuitry, thereby reducing the ACS resistance. Therefore, the reliability and performance of the 3D memory device can be improved.

[0033] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc. The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Alternatively or concurrently, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0034] It should be noted that, Figure 1A-1C The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of the components in the semiconductor device. The substrate of the semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed, and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to the X and Y directions. As used in this disclosure, when the substrate is positioned in the lowest plane of the semiconductor device in the Z direction, a component (e.g., a layer or device) is defined "above," "on top of," or "below" another component (e.g., a layer or device) of the semiconductor device relative to the substrate in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0035] Figure 1AA side view of an exemplary semiconductor device 100 along a horizontal direction (e.g., the Y direction) is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include semiconductor structures 102 and 104 connected together. In some embodiments, the semiconductor device 100 is a bonded chip including semiconductor structure 102 stacked on semiconductor structure 104. For example, semiconductor structure 102 is bonded to semiconductor structure 104 along a vertical direction (e.g., the Z direction) via bonding structure 103. In other words, semiconductor structures 102 and 104 may be joined along the Z direction at bonding structure 103 between semiconductor structures 102 and 104.

[0036] Semiconductor structure 102 includes conductive layers 106A and isolation layers 106B alternating with each other along the Z-direction. Each of the conductive layers 106A and isolation layers 106B can extend in a horizontal plane (e.g., an XY plane perpendicular to the Z-direction). The conductive layers 106A and isolation layers 106B in semiconductor structure 102 can be divided by semiconductor layer 112 into stacks 108 and 110 arranged along the Z-direction. In other words, semiconductor layer 112 is located along the Z-direction between the stack 108 composed of conductive layers 106A and isolation layers 106B and the stack 110 composed of conductive layers 106A and isolation layers 106B. The thickness of conductive layers 106A can be the same or different from each other, for example, in the range of 10-500 nm, for example, about 35 nm. The thickness of isolation layers 106B can also be the same or different from each other, for example, in the range of 10-500 nm, for example, about 25 nm. It should be noted that... Figure 1A or Figure 1B The number of conductive layers 106A and isolation layers 106B shown is for illustrative purposes only, and any suitable number of conductive layers 106A and isolation layers 106B may be included in the stack 108 or stack 110 of the semiconductor structure 102. Conductive layer 106A may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicide, or any combination thereof. Isolation layer 106B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, isolation layer 106B may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0037] In some implementation methods ( Figures 1A-1CIn (not shown), stack 108 or stack 110 includes a liner. Each of the liners may cover part or all sides of the corresponding conductive layer 106A and is located between the conductive layer 106A and two isolation layers 106B adjacent to the corresponding conductive layer 106A. The liners may include a high-k dielectric material (e.g., Al2O3). In some examples, the conductive layer 106A includes a metallic material (e.g., W) and an adhesive material (e.g., TiN), and the adhesive material may be deposited between the metallic material and the high-k dielectric material. In some examples, the conductive layer 106A includes a metallic material (e.g., W), and the liner includes an adhesive material (e.g., TiN) and a high-k dielectric material.

[0038] In some embodiments, both stack 108 and stack 110 may include one or more layers. For example, as Figure 1A As shown, the stack 108 may include a stack 108a, and the stack 108a includes one or more conductive layers 106A and insulating layers 106B in the stack 108. In some cases, such as Figure 1A As shown, the stack 108 may include another stack 108b, which includes one or more conductive layers 106A and insulating layers 106B in the stack 108. The stack 108a may be stacked on top of the stack 108b along the Z-direction. In some embodiments, the stack 108a may be the stack furthest from the semiconductor layer 112 in the stack of semiconductor structure 102. In some embodiments, the stack 108a may have fewer conductive layers 106A and insulating layers 106B than the stack 108b. For example, the number of conductive layers 106A in the stack 108a is in the range of 3 to 10, and the number of conductive layers 106A in the stack 108b is in the range of 150 to 500.

[0039] Semiconductor layer 112 may extend in the XY plane (e.g., perpendicular to the Z direction). In some embodiments, semiconductor layer 112 may include a first semiconductor layer 112a, a second semiconductor layer 112b, and an intermediate semiconductor layer 112c. The material of the first semiconductor layer 112a and the second semiconductor layer 112b may include polysilicon, such as undoped polysilicon. The intermediate semiconductor layer 112c may include doped polysilicon, such as p-doped or n-doped polysilicon. Semiconductor layer 112 may be used as an array common source (ACS) of a memory cell array (e.g., formed by the channel structure 116 described below) in semiconductor device 100. In some embodiments, semiconductor layer 112 may also be referred to as an ACS layer.

[0040] Semiconductor structure 102 includes one or more contact structures 114 connected to semiconductor layer 112. Each contact structure 114 may extend along the Z-direction through stack 108, semiconductor layer 112, and stack 110. Contact structures 114 may include any suitable conductive material, such as W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, contact structures 114 include at least one of a metallic material, polysilicon, or TiN.

[0041] In some embodiments, the contact structure 114 may include multiple segments. Each of the multiple segments extends through a corresponding layer of the stack 108 or stack 110. For example, as Figure 1A As shown, the contact structure 114 includes a first segment 114-1 extending through the stack 108a in the Z direction, a second segment 114-2 extending through the stack 108b in the Z direction, and a third segment 114-3 extending through the stack 110 in the Z direction.

[0042] Semiconductor structure 102 includes an array of channel structures 116. Each channel structure 116 may extend along the Z direction through stack 108, semiconductor layer 112, and stack 110. In some examples, channel structure 116 may have a cylindrical or pillar shape and may include a high-K layer 116a, a barrier layer surrounded by the high-K layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer 116c surrounded by the tunneling layer, a core-filling layer 116d surrounded by the channel layer 116c, and a channel plug 116e formed above the core-filling layer 116d and in contact with the channel layer 116c. In some embodiments, the channel layer 116c may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer (collectively referred to as memory film 116b) may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0043] In some implementations, each channel structure 116 may include multiple segments. Each segment extends through a corresponding layer of the stack 108 or stack 110. For example, as Figure 1A As shown, the channel structure 116 includes a first segment 116-1 extending through the stack 108a in the Z direction, a second segment 116-2 extending through the stack 108b in the Z direction, and a third segment 116-3 extending through the stack 110 in the Z direction.

[0044] Semiconductor layer 112 may contact the channel layer 116c of each corresponding channel structure in the array of channel structures 116. Semiconductor layer 112 may contact one or more contact structures 114. For example... Figure 2A As shown, the semiconductor layer 112 can contact the channel layer 116c and the contact structure 114 in a horizontal direction (e.g., the X direction or any suitable direction in the XY plane). In other words, a portion of the semiconductor layer 112, the channel layer 116c, and the contact structure 114 can be arranged in a horizontal direction.

[0045] The channel structure 116 has two ends 118a and 118b disposed opposite to each other along the Z direction. Bit line 120 is coupled to the channel layer 116c at end 118a. In some embodiments, the channel layer 116c at end 118a includes a channel plug 116e. Bit line 122 is coupled to the channel layer 116c at end 118b. In some embodiments, the channel layer 116c at end 118b includes another channel plug. Bit lines 120 and 122 may extend along the Y direction. In some embodiments, bit lines 120 and 122 are disposed on two opposite sides of a structure formed by the stack 108, semiconductor layer 112, and stack 110. In some embodiments, bit line 120 is located along the Z direction between semiconductor structure 104 and semiconductor layer 112, and semiconductor layer 112 is located along the Z direction between bit line 122 and semiconductor structure 104. Connector 124 is coupled to an end of contact structure 114. The interconnect 124 may comprise any suitable conductive material, such as W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof. The interconnect 124 may also extend along the Y direction (e.g., parallel to bit lines 120 and 122). In some embodiments, the interconnect 124 may be one of bit lines 120 and 122 (e.g., as shown in the image). Figure 1A On the same side as bit line 120 shown. In other words, connection line 124 is located between contact structure 114 and semiconductor structure 104 along the Z direction.

[0046] like Figure 1AAs shown, semiconductor structure 104 may include a substrate 126, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. Semiconductor structure 104 may include peripheral circuitry 128 on and / or within the substrate 126. In some embodiments, peripheral circuitry 128 may include control circuitry configured to control the channel structure 116 of semiconductor structure 102. In some embodiments, peripheral circuitry 128 includes one or more transistors. In some examples, peripheral circuitry 128 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and semiconductor structure 104 may also be formed on a semiconductor die, which may be referred to as a control die, CMOS die, or CMOS wafer. In some embodiments, semiconductor structure 102 may be referred to as an array die or array wafer.

[0047] like Figure 1A As shown, the bonding structure 103 may include bonding layers 130 and 132, which are bonded at a bonding interface 134 therebetween. Bonding layer 130 may include a plurality of bonding contacts 131 and a dielectric material for electrically isolating the bonding contacts 131. Bonding contacts 131 may include a conductive material such as Cu. The remaining region of bonding layer 130 may be formed of a dielectric material such as silicon oxide. The surrounding dielectric material in bonding contacts 131 and bonding layer 130 may be used for mixed bonding. Bonding layer 132 may include a plurality of bonding contacts 133 and a dielectric material for electrically isolating the bonding contacts 133. Bonding contacts 133 may include a conductive material such as Cu. The remaining region of bonding layer 132 may be formed of a dielectric material such as silicon oxide. The surrounding dielectric material in bonding contacts 133 and bonding layer 132 may be used for mixed bonding. Bonding contact 131 may contact bonding contact 133 at bonding interface 134. In some embodiments, bonding layer 130 may be considered part of semiconductor structure 102, and bonding layer 132 may be considered part of semiconductor structure 104. Semiconductor structure 104 may be bonded to semiconductor structure 102 face-to-face at bonding interface 134. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), bonding interface 134 is disposed between bonding layers 130 and 132, which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive), and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, bonding interface 134 is the location where bonding layers 130 and 132 meet and bond. In some examples, bonding interface 134 may be a layer of a specific thickness, comprising the top surface of bonding layer 132 and the bottom surface of bonding layer 130.

[0048] In some embodiments, semiconductor structure 102 includes an interconnect layer 136. Interconnect layer 136 may be coupled to interconnect line 124 and bit line 120, and may be configured to transmit electrical signals to and from interconnect line 124 and bit line 120. Specifically, contact structure 114 is coupled to interconnect layer 136 via interconnect line 124, and channel structure 116 is coupled to interconnect layer 136 via bit line 120. Interconnect layer 136 may be located in the Z-direction between stack body 110 and bonding layer 130. Interconnect layer 136 may be coupled to semiconductor structure 104 via bonding structure 103. For example, interconnect layer 136 may be coupled to bonding contacts 131 of bonding layer 130. Interconnect layer 136 may include multiple interconnects (also referred to as “contacts”), including lateral interconnects and vertical interconnect access (VIA) contacts. Interconnect layer 136 may further include one or more interlayer dielectric (ILD) layers, wherein interconnects and VIA contacts may be formed. That is, interconnect layer 136 may include interconnects and VIA contacts in multiple ILD layers. The interconnects in interconnect layer 136 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0049] In some embodiments, semiconductor structure 104 includes an interconnect layer 138. Interconnect layer 138 is located along the Z-direction between bonding layer 132 and peripheral circuitry 128. Interconnect layer 138 can be coupled to bonding contacts 133 of bonding layer 132. In other words, interconnect layer 136 of semiconductor structure 102 is coupled to interconnect layer 138 of semiconductor structure 104 via bonding structure 103, and peripheral circuitry 128 of semiconductor structure 104 is coupled to semiconductor structure 102 via interconnect layer 138 and bonding structure 103. Similar to interconnect layer 136, interconnect layer 138 may also include multiple interconnects, including lateral interconnects and VIA contacts. Interconnect layer 138 may also include one or more ILD layers, in which interconnects and VIA contacts can be formed. That is, interconnect layer 138 may include interconnects and VIA contacts in multiple ILD layers. Interconnects in interconnect layer 138 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer can be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0050] Figure 1B A side view of the semiconductor device 100 along another horizontal direction (e.g., the X direction) is shown. In some embodiments, such as Figure 1BAs shown, the semiconductor device 100 includes one or more gate line structures 140. The gate line structures 140 may extend in a horizontal direction (e.g., the X direction) to divide the semiconductor structure 102 into multiple blocks (e.g., memory blocks). Each of the gate line structures 140 may extend in a Z direction through the stack 108, the semiconductor layer 112, and the stack 110. In some embodiments, the gate line structures 140 do not contact the semiconductor layer 112. For example, a dielectric spacer (e.g., silicon oxide) may isolate the gate line structures 140 from the semiconductor layer 112 (e.g., in the XY plane). In some embodiments, the gate line structures 140 may comprise any suitable semiconductor material, such as polysilicon.

[0051] like Figure 1B As shown, the semiconductor device 100 may include one or more bit line contact structures 142. Each bit line contact structure 142 may extend along the Z direction and couple a bit line (e.g., bit line 120) on one side of the channel structure 116 (e.g., along the Z direction) and couple another bit line (e.g., bit line 122) on the other side of the channel structure 116 (e.g., along the Z direction). The bit line contact structure 142 may not extend through the stack 108, the semiconductor layer 112, and the stack 110. For example, as Figure 1B As shown, the bit line contact structure 142 can be disposed in a region adjacent to the edges of the stack 108, semiconductor layer 112, and stack 110 in a horizontal direction (e.g., in the Y direction). In this way, the fabrication of the bit line contact structure 142 can be more efficient, since it may take a long time to form holes extending through the stack 108, semiconductor layer 112, and stack 110 (e.g., by etching).

[0052] Semiconductor device 100 may include top select gates (TSGs) 144a and 144b disposed along the Z-direction on both sides of semiconductor structure 102. Each of TSGs 144a and 144b can divide a memory block into multiple portions. In some cases, such as Figure 1B As shown, each TSG (e.g., TSG 144a or TSG 144b) may extend through (e.g., along the Z direction) one or more outermost conductive layers 106A in the stack 108 or stack 110 of the semiconductor structure 102.

[0053] In some embodiments, the semiconductor structure 102 may include one or more array regions ( Figure 1A (not shown in the image) and one or more connection regions configured to provide conductive connections for one or more array regions. Figure 1A(Not shown in the image). The array region may be adjacent to the connection region along the X direction. In practice, any suitable arrangement of various regions in the semiconductor structure 102 can be applied. For example, the semiconductor structure 102 may have two connection regions and an array region arranged along the X direction between the two connection regions. In some other cases, the semiconductor structure 102 may have two array regions and a connection region located along the X direction between the two array regions. In some embodiments, the semiconductor structure 102 may include a dummy channel structure for process variation control during manufacturing and / or for additional mechanical support. Figure 1A (Not shown in the diagram). In some embodiments, the dummy channel structure is located in the connection region. For example, some dummy channel structures may be located in the edge or peripheral region of the connection region. In some cases, the edge region of the connection region is adjacent to the array region. In other cases, the edge region of the connection region is adjacent to the gate line structure (e.g., as shown in the diagram). Figure 1B The gate line structure 140 shown is adjacent to the gate line structure 140. In some embodiments, the dummy channel structure is in the array region (e.g., the region adjacent to the connection region). In some embodiments, the array of contact structure 114 and channel structure 116 can be in the array region. In some embodiments, the array of contact structure 114 and channel structure 116 can be in any other suitable region (e.g., the connection region).

[0054] Figure 1C The edge of the semiconductor device 100 is shown. Figure 1A The cross-sectional view of the cutting line AA'. (See diagram below.) Figure 1C As shown, the connection line 124 and bit line 120 can extend parallel to each other along the Y direction. Each bit line 120 can be connected to a corresponding channel structure 116. The connection line 124 can be connected to multiple contact structures 114 and has a wider width (e.g., dimension along the X direction) than the bit line 120. In this way, the resistance (e.g., ACS resistance) caused by the contact structures 114 and connection line 124 can be reduced, thereby improving the performance of the semiconductor device 100.

[0055] Figure 2A-2Z This illustrates the manufacture of semiconductor devices (e.g., Figure 1A-1C An exemplary process of the semiconductor device 100 shown. Figure 2A-2Z A side view of an exemplary semiconductor structure at various stages of the manufacturing process is shown.

[0056] like Figure 2AAs shown, a semiconductor structure 200a is formed. The semiconductor structure 200a includes a substrate 201 and a stack 208a of a sacrificial layer 206D and an isolation layer 206B. The sacrificial layer 206D and the isolation layer 206B may alternate with each other along a vertical direction (e.g., the Z direction). Each of the substrate 201 and the sacrificial layer 206D and the isolation layer 206B may extend in an XY plane. The semiconductor structure 200a can be formed, for example, by depositing the stack 208a of the sacrificial layer 206D and the isolation layer 206B on top of the substrate 201. The isolation layer 206B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the sacrificial layer 206D may include a dielectric material different from the dielectric material of the isolation layer 206B. For example, the isolation layer 206B may include silicon oxide, and the sacrificial layer 206D may include silicon nitride.

[0057] Figure 2B A semiconductor structure 200b is shown, including one or more contact holes 213-1 and one or more channel holes 215-1. The contact holes 213-1 and channel holes 215-1 extend along the Z-direction through a stack 208a and into a substrate 201. In some embodiments, the contact holes 213-1 and channel holes 215-1 can be formed by the same etching process (e.g., a first etching process). Due to the etching process, in some embodiments, the diameters (e.g., the cross-sectional dimensions of each hole in the horizontal direction) of the contact holes 213-1 and channel holes 215-1 can gradually decrease from top to bottom in the vertical direction. Therefore, the size of the bottom region of each of the contact holes 213-1 and channel holes 215-1 can be determined by the height of the stack 208a in the vertical direction (e.g., the Z-direction). When the stack 208a has fewer layers, its height can be smaller, and therefore the bottom regions of the contact holes 213-1 and channel holes 215-1 can be larger. This is illustrated in some later processes below (e.g., as shown in reference). Figure 2B-2ZZ As described, the dimensions of the bottom regions of contact holes 213-1 and channel holes 215-1 can determine the contact structure formed in these holes (e.g., Figure 2ZZ Contact structure 214) or channel structure (e.g., Figure 2ZZ The size of the landing area at one end of the channel structure 216). If the landing area has a larger size, it may be easier to connect the conductive structure to the landing area at one end of the contact structure or channel structure. Therefore, the stack 208a can have fewer layers, allowing the landing area at one end of the contact structure or channel structure formed later to have a larger size. In some embodiments, the number of sacrificial layers 206D in the stack 208a can be in the range of 3 to 10.

[0058] like Figure 2CAs shown, a semiconductor structure 200c is formed by filling contact holes 213-1 and channel holes 215-1 with, for example, a filling material (e.g., polysilicon).

[0059] Figure 2D A semiconductor structure 200d is shown, comprising a stack 208b of sacrificial layer 206D and isolation layer 206B. The sacrificial layer 206D and isolation layer 206B in the stack 208b may alternate with each other in a vertical direction (e.g., the Z direction). The stacks 208a and 208b may form a stack body 208. The semiconductor structure 200d may be formed, for example, by depositing the sacrificial layer 206D and isolation layer 206B on top of the stack 208a. In some embodiments, the number of sacrificial layers 206D in the stack 208b may be in the range of 150 to 500.

[0060] Figure 2E A semiconductor structure 200e is shown, including contact holes 213-2 and channel holes 215-2 in a stack 208b. Contact holes 213-2 and channel holes 215-2 can be formed by the same etching process (e.g., a second etching process). Contact holes 213-2 and channel holes 215-2 can extend through the stack 208b in the Z direction. Each of the contact holes 213-2 can be disposed on top of a corresponding contact hole 213-1 and expose the fill material in the contact hole 213-1. Each of the channel holes 215-2 can be disposed on top of a corresponding channel hole 215-1 and expose the fill material in the channel hole 215-1. Figure 2E As shown, the filling material in the contact hole 213-1 and the channel hole 215-1 can be removed so that each contact hole 213-2 is connected to the corresponding contact hole 213-1, and each channel hole 215-2 is also connected to the corresponding channel hole 215-1.

[0061] like Figure 2F As shown, a semiconductor structure 200f is formed by filling contact holes 213-1 and 213-2 and channel holes 215-1 and 215-2 with, for example, a filling material (e.g., polysilicon).

[0062] Figure 2GSemiconductor structure 200g is shown. Semiconductor structure 200g can be formed by sequentially depositing a stop layer (also called a semiconductor layer) 212a, an isolation layer 209a, a sacrificial array common source (ACS) layer 211, an isolation layer 209b, and a stop layer (also called a semiconductor layer) 212b on top of a stack 208 (e.g., a top stack 208b). Semiconductor structure 200g also includes a stack 210 of sacrificial layers 206D and isolation layers 206B alternating with each other in a vertical direction (e.g., the Z direction). Stack 210 can be stacked on top of the stop layer 212b. In some embodiments, the number of sacrificial layers 206D in stack 210 can be in the range of 150 to 500.

[0063] Stop layers 212a and 212b may comprise a semiconductor material such as polysilicon. Isolation layers 209a and 209b may comprise a dielectric material. In some embodiments, the dielectric material of isolation layers 209a and 209b may be the same as the dielectric material of isolation layer 206B (e.g., silicon oxide). The sacrificial ACS layer 211 may comprise a material having a higher etch selectivity than stop layers 212a and 212b. In other words, the material of the sacrificial ACS layer 211 may be etched away at a higher etch rate than that of stop layers 212a and 212b. For example, the material of the sacrificial ACS layer 211 may be the same as the material of sacrificial layer 206D (e.g., silicon nitride). In another example, the material of the sacrificial ACS layer 211 may be carbon-doped polysilicon.

[0064] Figure 2H Semiconductor structure 200h including contact holes 213 and channel holes 215 is shown. Semiconductor structure 200h can be formed by using the same etching process (e.g., a third etching process) to form contact holes 213-3 and channel holes 215-3. Contact holes 213-3 and channel holes 215-3 can extend along the Z-direction through stack 210, stop layer 212b, isolation layer 209b, sacrificial ACS layer 211, isolation layer 209a, and stop layer 212a. Each of the contact holes 213-3 can be disposed on top of a corresponding contact hole 213-2 and expose the filling material in the contact hole 213-2. Each of the channel holes 215-3 can be disposed on top of a corresponding channel hole 215-2 and expose the filling material in the channel hole 215-2. Figure 2HAs shown, the filler material in contact holes 213-1 and 213-2, and channel holes 215-1 and 215-2 can be removed. In this way, each contact hole 213-3, its corresponding contact hole 213-2, and its corresponding contact hole 213-1 are connected to form a contact hole 213. Contact holes 213-1, 213-2, and 213-3 can be considered as the first segment, second segment, and third segment of contact hole 213, respectively. Similarly, each channel hole 215-3, its corresponding channel hole 215-2, and its corresponding channel hole 215-1 are connected to form a channel hole 215. Channel holes 215-1, 215-2, and 215-3 can be considered as the first segment, second segment, and third segment of channel hole 215, respectively.

[0065] like Figure 2I As shown, a semiconductor structure 200i is formed by filling contact holes 213 and channel holes 215 with, for example, a filling material (e.g., polysilicon).

[0066] Figure 2J Semiconductor structure 200j is shown. Semiconductor structure 200j can be formed by depositing a dielectric layer 217 on top of semiconductor structure 200i. Dielectric layer 217 can include any suitable dielectric material, such as silicon oxide. Openings 219 can be formed in dielectric layer 217 to expose the filler material in contact holes 213. The filler material in contact holes 213 can then be removed.

[0067] like Figure 2K As shown, the semiconductor structure 200k is formed by depositing a dielectric layer 221 on the inner sidewall and bottom of each contact hole 213. The dielectric layer 221 may comprise any suitable dielectric material, such as silicon oxide.

[0068] like Figure 2L As shown, a semiconductor structure 200l is formed by filling contact holes 213 with conductive material. The conductive material may include any suitable conductive material, such as W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the conductive material includes at least one of a metallic material, polysilicon, or TiN.

[0069] Figure 2MA semiconductor structure 200m is shown, comprising a contact structure 214 in each contact hole 213. The semiconductor structure 200m can be formed by removing excess conductive material on top of the dielectric layer 217 through a planarization process such as chemical mechanical polishing (CMP). A portion of the conductive material in the contact holes 213 can also be removed, such that the remaining portion of the conductive material in the contact holes 213 is below the fill material in the channel holes 215. The contact structure 214 comprises the remaining conductive material (also referred to as a conductive layer) in each contact hole 213. In some embodiments, the dielectric layer 221 may also be considered part of the contact structure 214. In some embodiments, the top of the contact structure 214 (e.g., the end away from the substrate 201 along the Z direction) may be below (e.g., closer to the substrate 201 along the Z direction) the top of the fill material in the channel holes 215.

[0070] like Figure 2N As shown, a semiconductor structure 200n is formed by filling the contact hole 213 and the opening 219 with dielectric material to cover the contact structure 214.

[0071] like Figure 2O As shown, the semiconductor structure 200o is formed by removing the dielectric layer 217 to expose the filling material in the channel hole 215. The contact structure 214 can still be covered by the dielectric material in the contact hole 213.

[0072] like Figure 2P As shown, the semiconductor structure 200p is formed by removing the filling material in the channel hole 215.

[0073] Figure 2Q A semiconductor structure 200q is shown, comprising a corresponding channel structure 216 in each channel via 215. The channel structure 216 can be formed by sequentially depositing a high-k layer 216a, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer 216c, and a core-filling layer 216d into the channel via 215. In some embodiments, the channel layer 216c may comprise silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The tunneling layer may comprise silicon oxide, silicon nitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The charge trapping layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer (collectively referred to as memory film 216b) may comprise an ONO dielectric (silicon oxide-silicon nitride-silicon oxide). The channel structure 216 has two ends 218a and 218b disposed opposite to each other along the Z-direction. The channel structure 216 also includes a channel plug 216e formed at the end 218a. The channel plug 216e may be above the core filler layer 216d and in contact with the channel layer 216c.

[0074] like Figure 2R As shown, a semiconductor structure 200r including space 223 is formed by removing the sacrificial ACS layer 211. Space 223 may expose a portion of the dielectric layer 221 of the contact structure 214 (which contacts the sacrificial ACS layer 211). Space 223 may also expose the dielectric material that contacts the sacrificial ACS layer 211 and surrounds the channel structure 216. The sacrificial ACS layer 211 can be removed by any suitable method. In some embodiments, a gate line slit extending along the Z direction and exposing the sacrificial ACS layer 211 may be formed. Figure 2R (Not shown in the diagram). For example, the gate line slit can extend from the top of the semiconductor structure 200r to the stop layer 212a. The sacrificial ACS layer 211 can be etched by filling the gate line slit with an etching solution.

[0075] like Figure 2S As shown, a semiconductor structure 200s is formed by extending space 223. The portion of dielectric layer 221 exposed by space 223 can be removed. Therefore, the conductive layer of contact structure 214 can be exposed by extending space 223. The channel layer 216c of channel structure 216 can also be exposed by removing portions of memory film 216b and the high-k layer 216a of channel structure 216, as well as the dielectric material surrounding portions of high-k layer 216a. Isolation layers 209a and 209b can also be removed.

[0076] like Figure 2T As shown, a semiconductor structure 200t including a semiconductor layer 212 is formed. The semiconductor layer 212 includes a stop layer (also referred to as a semiconductor layer) 212a, a stop layer (also referred to as a semiconductor layer) 212b, and a semiconductor layer 212c. The semiconductor layer 212c can be formed by depositing a semiconductor material (e.g., n-doped polysilicon) into the extended space 223. As a result, the semiconductor layer 212c is connected to the conductive layer of the contact structure 214 and to the channel layer 216c of the channel structure 216.

[0077] Figure 2U The semiconductor structure 200u is shown. A sacrificial layer 206D (e.g., in...) is shown in stacks 208 and 210. Figure 2T In the semiconductor structure 200t, a conductive layer 206A is used instead. This can be achieved, for example, by... Figure 1B The opening formed at the location of the gate line structure 140 is etched away to remove the sacrificial layer 206D. Then, the sacrificial layer 206D can be replaced to form a conductive layer 206A to form a new stack 208 and a new stack 210.

[0078] like Figure 2VAs shown, a semiconductor structure 200v is formed, including a corresponding conductive contact 225 connected to each channel structure 216 and a corresponding conductive contact 227 connected to each contact structure 214. The conductive contacts 225 may be located on one side of the semiconductor structure 220v (e.g., the side away from the substrate 201, such as...). Figure 2V As shown in the diagram, and contacts one end of the channel structure 216 on that side (e.g., channel plug 216e). The conductive contact 227 may be on that side and contacts one end of the contact structure on that side.

[0079] Figure 2W A semiconductor structure 200w is shown, including bit lines 220 and interconnects 224. Bit lines 220 and interconnects 224 may be formed on the same side as conductive contacts 225 and 227. Each bit line 220 may be coupled to a corresponding channel structure 216 via one of the conductive contacts 225. The interconnects 224 may be coupled to one or more contact structures 214 via corresponding conductive contacts 227. Bit lines 220 and interconnects 224 extend along the Y direction. The semiconductor structure 200w also includes an interconnect layer 236 formed on the same side as the bit lines 220 and interconnects 224 (which may be referred to as the first side). The interconnect layer 236 may be coupled to the bit lines 220 and interconnects 224 and may be configured to transmit electrical signals to and from the channel structure 216 (e.g., via bit lines 220 and conductive contacts 225) and the contact structure 214 (e.g., via interconnects 224 and conductive contacts 227).

[0080] Figure 2X A semiconductor structure 200x is shown, which can be formed by bonding a semiconductor structure 200w to a semiconductor structure 204. In some embodiments, the semiconductor structure 200w and the semiconductor structure 204 can be fabricated in parallel. The semiconductor structure 204 may be... Figure 1A-1B An example of a semiconductor structure 104. In some implementations, such as Figure 2X As shown, the semiconductor structure 204 may include a substrate 226 and peripheral circuitry 228. The peripheral circuitry 228 may include control circuitry configured to control the channel structure 216 of the semiconductor structure 200w. In some embodiments, the semiconductor structure 204 further includes an interconnect layer 238 above the peripheral circuitry 228 to transmit electrical signals to and from the peripheral circuitry 228. Note that in... Figure 2X In this configuration, semiconductor structure 200w is flipped vertically. Semiconductor structure 200w can be bonded to and coupled to semiconductor structure 204 using any suitable bonding method. For example, bonding layer 230 can be formed on one side of semiconductor structure 200w (e.g., the first side where bit line 220, interconnect line 224, and interconnect layer 236 are located). Bonding layer 230 can be coupled to... Figure 1AThe bonding layer 230 is similar to or the same as the bonding layer 130. The bonding layer 230 may include conductive bonding contacts and a dielectric material that isolates the bonding contacts in a horizontal direction (e.g., the X direction). An interconnect layer 236 may be coupled to the bonding contacts of the bonding layer 230. A bonding layer 232 may be formed on top of the interconnect layer 238 of the semiconductor structure 204. The bonding layer 232 may be connected to... Figure 1A The bonding layer 132 is similar to or identical to the bonding layer 232. Similarly, the bonding layer 232 may include conductive bonding contacts and a dielectric material that isolates the bonding contacts in a horizontal direction (e.g., the X direction). The interconnect layer 238 may be coupled to the bonding contacts of the bonding layer 232. In some embodiments, the bonding layer 230 may be bonded to the bonding layer 232 using a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive), and both metal-to-metal bonding and dielectric-to-dielectric bonding may be achieved simultaneously. That is, the bonding contacts in the bonding layer 230 are bonded to the bonding contacts in the bonding layer 232, and the dielectric material in the bonding layer 230 is bonded to the dielectric material in the bonding layer 232. The bonding layers 230 and 232 may form a bonding structure 203. In other words, interconnect layer 236 is coupled to interconnect layer 238 via bonding structure 203 (e.g., conductive bonding contacts in bonding structure 203).

[0081] Figure 2Y A semiconductor structure 200y can be formed by removing the substrate 201 of the semiconductor structure 200w.

[0082] Figure 2Z A semiconductor structure 200z can be formed by depositing a dielectric layer 229 on top of a semiconductor structure 200w. The dielectric layer 229 may include any suitable dielectric material, such as silicon oxide. In some embodiments, a planarization process (e.g., CMP) may be applied on top of the semiconductor structure 200z (and also on top of the new semiconductor structure 200w) to form a smooth top surface.

[0083] Figure 2ZZ Semiconductor structure 200zz is shown, including semiconductor structure 202 formed from semiconductor structure 200w. Semiconductor structure 202 can be formed by forming bit lines 222 in semiconductor structure 200w. Bit lines 222 extend along the Y direction and can be formed in dielectric layer 229. Bit lines 222 are located along the Z direction on a second side of semiconductor structure 202 opposite to the first side (e.g., as shown in reference). Figure 2W(as described). In other words, the second side is further away from the semiconductor structure 204 along the Z direction than the first side. Each bit line 222 can be coupled to a corresponding channel structure 216. For example, the bit line 222 can be coupled to the end of the channel layer 216c of the channel structure 216 on the second side. Bit line contact structures (e.g., with) can be formed in the semiconductor structure 202. Figure 1B The bit line contact structure 142 (similar or identical to the bit line contact structure) couples the bit line 222 to the corresponding bit line 220 on the first side. The corresponding bit line 220 is coupled to the other end of the channel layer 216c of the channel structure 216 (e.g., channel plug 216e) on the first side. The semiconductor structure 200zz can be as follows: Figure 1A-1C An example of semiconductor device 100 is shown. Semiconductor structure 202 of semiconductor structure 200zz may be similar to or the same as semiconductor structure 102 of semiconductor device 100, and semiconductor structure 204 of semiconductor structure 200zz may be similar to or the same as semiconductor structure 104 of semiconductor device 100.

[0084] Figure 3 A flowchart of an exemplary process 300 is shown. Process 300 can be performed to form a semiconductor device (e.g., Figure 1A-1C The semiconductor device 100 shown. Figure 2A-2ZZ Describe process 300. Process 300 may include forming Figure 2A-2ZZ This refers to one or more steps in the manufacturing process of a semiconductor structure. It should be understood that the operations shown in process 300 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 3 The different sequences shown will be executed.

[0085] At operation 302, a first semiconductor structure is formed (e.g., Figure 2G-2T The first stack of semiconductor structures (200g-200t) (e.g., Figure 2G The stack 208), the first stack comprising sacrificial layers (e.g., along a first direction (e.g., the Z direction) alternating with each other. Figure 2G The sacrificial layer 206D) and the isolation layer (e.g., Figure 2G (Isolation layer 206B).

[0086] At operation 304, a first semiconductor structure is formed (e.g., Figure 2G-2T The second stack of semiconductor structures (200g-200t) (e.g., Figure 2G The stack body 210), the second stack body includes sacrificial layers that alternate with each other along the first direction (e.g., Figure 2G The sacrificial layer 206D) and the isolation layer (e.g., Figure 2G(Isolation layer 206B).

[0087] At operation 306, a semiconductor layer of the first semiconductor structure is formed (e.g., ...). Figure 2T (Semiconductor layer 212). The semiconductor layer is located between the first stack and the second stack along the first direction.

[0088] At operation 308, a contact structure is formed to create the first semiconductor structure (e.g., Figure 2T (Contact structure 214). The contact structure is connected to the semiconductor layer and extends along a first direction through the first stack, the semiconductor layer, and the second stack.

[0089] At operation 310, a channel structure of the first semiconductor structure is formed (e.g., Figure 2T The channel structure 216). The channel structure extends along a first direction through the first stack, the semiconductor layer, and the second stack. The channel layer of the channel structure (e.g., Figure 2T The channel layer 216c is in contact with the semiconductor layer.

[0090] In some embodiments, forming the first stack includes forming a first layer of the first stack (e.g., Figure 2A The stack 208a) and the second stack of the first stack (e.g., Figure 2D The stack 208b). Each of the first and second stacks includes one or more sacrificial layers and isolation layers in the first stack. Forming a contact structure includes a first segment extending through the first stack in a first direction (e.g., forming a contact hole). Figure 2B The contact hole 213-1) and the second segment of the second stack extending along the first direction through the second layer (e.g., Figure 2E Contact hole 213-2). Forming a channel structure includes forming a first segment extending along a first direction through the first stack (e.g., forming a channel hole). Figure 2B The channel hole 215-1) and the channel hole extending along the first direction through the second segment of the second stack (e.g., Figure 2E The channel hole 215-2). By the first etching process (e.g., reference). Figure 2B The first etching process described herein forms the first segment of the channel hole and the first segment of the contact structure. A second etching process (e.g., referenced...) Figure 2E The second etching process described forms the second section of the channel hole and the second section of the contact structure.

[0091] In some embodiments, the semiconductor layer forming the first semiconductor structure includes forming a first stop layer on top of the first stack (e.g., Figure 2G Stopping layer 212a), sacrificial array common source (ACS) layer (e.g., Figure 2GThe sacrifice of ACS layer 211) and the second stopping layer (e.g., Figure 2G Stop layer 212b). The sacrificial ACS layer is located between the first stop layer and the second stop layer along the first direction. This forms a second stack (e.g., Figure 2G The stack 210 includes a second stack formed on top of the second stop layer (e.g., as referenced). Figure 2G (As described).

[0092] In some embodiments, forming the contact structure includes forming a third segment extending in a first direction through the second stack, the second stop layer, the sacrificial ACS layer, and the first stop layer (e.g., forming a contact hole). Figure 2H Contact holes 213-3). The channel structure includes a third segment extending in a first direction through the second stack, the second stop layer, the sacrificial ACS layer, and the first stop layer to form the channel hole (e.g., Figure 2H The channel hole 215-3). By a third etching process (e.g., as referenced). Figure 2H The third etching process described above forms the third section of the channel hole and the third section of the contact structure.

[0093] In some embodiments, forming the contact structure includes depositing dielectric and conductive materials into the contact hole (e.g., Figure 2K-2N In the contact hole 213), dielectric layers (e.g., to form contact structures) are respectively formed. Figure 2K The dielectric layer 221) and the conductive layer of the contact structure (e.g., the conductive layer surrounded by the dielectric layer 221, as shown in the reference). Figure 2K The formation of the channel structure includes the formation of channel holes (e.g., Figure 2Q A channel layer is formed in the channel hole 215 (e.g., Figure 2Q The channel layer 216c) and the memory film (e.g., Figure 2Q (Memory film 216b). The memory film surrounds the channel layer.

[0094] In some implementations, the semiconductor layer forming the first semiconductor structure includes: removing the sacrificial ACS layer to form a space (e.g., Figure 2R Space 223); Remove a portion of the memory film of the channel structure to expose a portion of the channel layer of the channel structure (e.g., as referenced). Figure 2S (as described); removing a portion of the dielectric layer of the contact structure to expose a portion of the conductive layer of the contact structure (e.g., as referenced). Figure 2S As described); and semiconductor materials (e.g., as referenced) Figure 2T The described n-doped polysilicon is deposited into space to form a semiconductor layer (e.g., as referenced). Figure 2T (As described).

[0095] In some embodiments, process 300 further includes: utilizing a conductive layer (e.g., Figure 2U-2ZZ The conductive layer 206A is replaced (e.g., as referenced). Figure 2U (As described) Sacrificial layers in the first stack and sacrificial layers in the second stack.

[0096] In some embodiments, process 300 further includes: on a first side of the first semiconductor structure (e.g., as referenced) Figure 2W The first line is formed on the first side as described. Figure 2W One of the bit lines 220) and the first interconnect layer (e.g., Figure 2W Interconnect layer 236). The first interconnect layer is coupled to the channel structure and the contact structure. The first line extends along a second direction perpendicular to the first direction (e.g., the Y direction) and is coupled to the first end of the channel structure (e.g., the first end of the first line). Figure 2W The channel plug 216e). Process 300 also includes: forming a second semiconductor structure (e.g., Figure 2X The second semiconductor structure includes a control circuit (e.g., a semiconductor structure 204) configured to control the channel structure of the first semiconductor structure. Figure 2X The peripheral circuit 228) and the second interconnect layer (e.g., Figure 2X Interconnect layer 238). Process 300 also includes: via bonding structures (e.g., Figure 2X The bonding structure 203) bonds the first side of the first semiconductor structure (e.g., as shown in reference). Figure 2X (As described) to the second semiconductor structure. The first interconnect layer is coupled to the second interconnect layer via a bonding structure.

[0097] In some embodiments, process 300 further includes: on the second side of the first semiconductor structure (e.g., as referenced) Figure 2ZZ A second bit line extending in the second direction is formed on the described second side (e.g., Figure 2ZZ One of the bit lines 222), and forming a bit line contact structure extending along the first direction (e.g., as referenced). Figure 2ZZ The described bit line contact structure is coupled to the first bit line and the second bit line.

[0098] Figure 4 A block diagram of an exemplary system 400 is shown. According to one or more embodiments of this disclosure, system 400 may have one or more semiconductor devices (e.g., memory devices). System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage. Figure 4As shown, system 400 may include a host device 408 and a memory system 402 having one or more memory devices 404 and a memory controller 406. The host device 408 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 408 may be configured to send data to or receive data from one or more memory devices 404.

[0099] Memory device 404 can be any memory device disclosed in this disclosure, such as Figure 1A-1C The memory device shown is an example of a NAND flash memory. A memory controller 406 (also referred to as controller circuitry) is coupled to the memory device 404 and the host device 408. According to embodiments of this disclosure, the memory device 404 may include a plurality of conductive interconnects through a cover layer contacting conductive pads in a conductive pad layer, and the memory controller 406 may be coupled to the memory device 404 via at least one of the plurality of conductive interconnects. The memory controller 406 is configured to control the memory device 404. For example, the memory controller 406 may be configured to operate a plurality of channel structures via word lines. The memory controller 406 may manage data stored in the memory device 404 and communicate with the host device 408.

[0100] In some embodiments, the memory controller 406 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 406 is designed / configured to operate in high duty cycle environments such as SSDs, or in embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptops, and in enterprise memory arrays. The memory controller 406 may be configured to control the operation of the memory device 404, such as read, erase, and program (or write) operations. The memory controller 406 may also be configured to manage various functions regarding data stored or to be stored in the memory device 404, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 404. The memory controller 406 may also perform any other appropriate function, such as formatting the memory device 404.

[0101] The memory controller 406 can communicate with external devices (e.g., host device 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0102] The memory controller 406 and one or more memory devices 404 can be integrated into various types of storage devices, for example, included in the same package such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 402 can be implemented and packaged into different types of end electronic products. Figure 4 In one example shown, the memory controller 406 and a single memory device 404 may be integrated into a memory card 402. The memory card 402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMC), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0103] The embodiments of the subjects, actions, and operations described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in a combination of one or more of them. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing apparatus. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of these, or as part thereof. The computer storage medium is not a propagation signal.

[0104] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will be able to implement such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not).

[0105] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can also, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0106] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something in the case of a layer with an intermediate feature or in between. Furthermore, “above” or “over” means not only “on” something, but can also include “on” or “over” something in the case of no intermediate feature or in between (i.e., directly on) something.

[0107] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to include different orientations of the apparatus in use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0108] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0109] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire bottom or upper layer structure, or may have a range smaller than that of the bottom or upper layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than the thickness of that continuous structure. For example, a layer may be located between any set of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (in which contacts, interconnects, and / or vertical interconnect vias (vias)) and one or more dielectric layers.

[0110] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step, which is set during the design phase of the product or process along with a range of values ​​that are higher and / or lower than the expected value. As used herein, the range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10%–30% of the value (e.g., ±0.10%, ±0.20%, or ±0.30% of the value).

[0111] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0112] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate.

[0113] This disclosure provides numerous different implementations or examples for carrying out various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include implementations in which the first and second features can be in direct contact, and may also include implementations in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0114] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance given herein, such adjustments and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed implementations.

[0115] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims (as defined by the claims themselves), but rather as descriptions of features that may be specific to particular embodiments of the invention. Certain features described in this disclosure in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed, in some cases one or more features from the claimed combination may be excluded from the combination, and the claims may be for sub-combinations or variations thereof.

[0116] Similarly, although operations are shown in the accompanying drawings and described in the claims in a specific order, this should not be construed as requiring such operations to be performed in the specific order or sequence shown, or to perform all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0117] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require a specific order or sequence to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0118] The breadth and scope of this disclosure should not be limited by any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device comprising a first semiconductor structure, wherein, The first semiconductor structure includes: A first stack of conductive layers and insulating layers alternating with each other along a first direction; A second stack of conductive and insulating layers alternating with each other along the first direction; A semiconductor layer located between the first stack and the second stack along the first direction; A contact structure connected to the semiconductor layer, wherein the contact structure extends along the first direction through the first stack, the semiconductor layer, and the second stack; and A channel structure extending along the first direction through the first stack, the semiconductor layer, and the second stack, wherein the semiconductor layer is in contact with the channel layer of the channel structure.

2. The semiconductor device according to claim 1, wherein, The first stack includes at least a first stack, the first stack including one or more of the conductive layers and insulating layers in the first stack, and the contact structure includes a first segment extending through the first stack along the first direction.

3. The semiconductor device according to claim 2, wherein, The first stack further includes a second stack comprising one or more of the conductive and insulating layers in the first stack, and the contact structure further includes a second segment extending through the second stack along the first direction and a third segment extending through the second stack.

4. The semiconductor device according to claim 3, wherein, The trench structure includes a first section, a second section, and a third section. The first section of the trench structure extends through the first stack along the first direction, the second section of the trench structure extends through the second stack along the first direction, and the third section of the trench structure extends through the second stack along the first direction.

5. The semiconductor device according to claim 2, wherein, The number of one or more conductive layers in the first stack is in the range of 3 to 10.

6. The semiconductor device according to any one of claims 1 to 5, further comprising a second semiconductor structure, wherein, The second semiconductor structure is bonded to the first semiconductor structure along the first direction via a bonding structure, and the second semiconductor structure includes a control circuit configured to control the channel structure of the first semiconductor structure.

7. The semiconductor device according to claim 6, wherein, The first semiconductor structure includes a first interconnect layer coupled to the contact structure, and the first interconnect layer is coupled to the second semiconductor structure through the bonding structure.

8. The semiconductor device according to claim 7, wherein, The second semiconductor structure includes a second interconnect layer coupled to the first interconnect layer via the bonding structure.

9. The semiconductor device according to claim 6, wherein, The channel structure includes a first end and a second end, the first end being coupled to a first bit line extending along a second direction perpendicular to the first direction, the second end being coupled to a second bit line extending along the second direction, the first bit line being coupled to the control circuit of the second semiconductor structure, and the first bit line being coupled to the second bit line through a bit line contact structure extending along the first direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The contact structure includes at least one of a metallic material, polycrystalline silicon, or titanium nitride (TiN).

11. A method comprising: A first stack forming a first semiconductor structure, wherein the first stack includes sacrificial layers and isolation layers alternating with each other along a first direction; A second stack forming the first semiconductor structure, wherein the second stack includes sacrificial layers and isolation layers alternating with each other along the first direction; A semiconductor layer forming the first semiconductor structure, wherein the semiconductor layer is located between the first stack and the second stack along the first direction; A contact structure forming the first semiconductor structure, wherein the contact structure is connected to the semiconductor layer and extends along the first direction through the first stack, the semiconductor layer, and the second stack; and A channel structure is formed to form the first semiconductor structure, wherein the channel structure extends along the first direction through the first stack, the semiconductor layer and the second stack, and the channel layer of the channel structure is in contact with the semiconductor layer.

12. The method according to claim 11, wherein: Forming the first stack includes: forming a first stack and a second stack of the first stack, each of the first stack and the second stack including one or more of the sacrificial layer and isolation layer in the first stack; Forming the contact structure includes: forming a first segment of a contact hole extending along the first direction through the first stack and a second segment of the contact hole extending along the first direction through the second stack; and Forming the channel structure includes: forming a first segment of the channel hole extending through the first stack along the first direction and a second segment of the channel hole extending through the second stack along the first direction, wherein the first segment of the channel hole and the first segment of the contact hole are formed by a first etching process, and the second segment of the channel hole and the second segment of the contact hole are formed by a second etching process.

13. The method according to claim 12, wherein: The semiconductor layer forming the first semiconductor structure includes: a first stop layer, a sacrificial array common source (ACS) layer, and a second stop layer formed on top of the first stack, wherein the sacrificial ACS layer is located between the first stop layer and the second stop layer along the first direction; and Forming the second stack includes forming the second stack on top of the second stop layer.

14. The method of claim 13, wherein: The contact structure includes: a third segment forming the contact hole extending along the first direction through the second stack, the second stop layer, the sacrificial ACS layer, and the first stop layer; and Forming the channel structure includes forming a third section of the channel hole extending along the first direction through the second stack, the second stop layer, the sacrificial ACS layer, and the first stop layer, wherein the third section of the channel hole and the third section of the contact hole are formed by a third etching process.

15. The method of claim 14, wherein: Forming the contact structure includes: depositing a dielectric material and a conductive material into the contact hole to form a dielectric layer and a conductive layer of the contact structure, respectively; and Forming the channel structure includes forming a channel layer and a memory film in the channel holes, wherein the memory film surrounds the channel layer.

16. The method according to claim 15, wherein, The semiconductor layer forming the first semiconductor structure includes: Remove the sacrificial ACS layer to form space; Remove a portion of the memory film of the channel structure to expose a portion of the channel layer of the channel structure; Removing a portion of the dielectric layer of the contact structure to expose a portion of the conductive layer of the contact structure; and Semiconductor material is deposited into the space to form the semiconductor layer.

17. The method of claim 16, further comprising: The sacrificial layer in the first stack and the sacrificial layer in the second stack are replaced with a conductive layer.

18. The method of claim 17, further comprising: A first bit line and a first interconnect layer are formed on a first side of the first semiconductor structure, wherein the first interconnect layer is coupled to the channel structure and the contact structure, and the first bit line extends along a second direction perpendicular to the first direction and is coupled to a first end of the channel structure; A second semiconductor structure is formed, including control circuitry configured to control the channel structure and second interconnect layer of the first semiconductor structure; and The first side of the first semiconductor structure is bonded to the second semiconductor structure through a bonding structure, wherein the first interconnect layer is coupled to the second interconnect layer through the bonding structure.

19. The method of claim 18, further comprising: A second bit line extending along the second direction is formed on the second side of the first semiconductor structure; as well as A bit line contact structure is formed extending along the first direction, wherein the bit line contact structure is coupled to the first bit line and the second bit line.

20. A memory system, comprising: A memory device, the memory device including a first semiconductor structure; as well as A memory controller, coupled to and configured to control the memory device. The first semiconductor structure includes: A first stack of conductive layers and insulating layers alternating with each other along a first direction; A second stack of conductive and insulating layers alternating with each other along the first direction; A semiconductor layer located between the first stack and the second stack along the first direction; A contact structure connected to the semiconductor layer, wherein the contact structure extends along the first direction through the first stack, the semiconductor layer, and the second stack; and A channel structure extending along the first direction through the first stack, the semiconductor layer, and the second stack, wherein the semiconductor layer is in contact with the channel layer of the channel structure.

Images