4F2 storage unit, memory and preparation method of 4F2 storage unit

Abstract

The invention relates to the technical field of storage equipment, and discloses a 4F2 storage unit, a memory and a preparation method of the 4F2 storage unit, and the 4F2 storage unit comprises a substrate; the semiconductor material column is epitaxially grown on the surface of one side of the substrate along the thickness direction; the middle dielectric layer covers the surface of the semiconductor material column; the conductive connecting layer covers the surface of one side, far away from the substrate, of the intermediate dielectric layer; the semiconductor material column, the intermediate dielectric layer and the conductive connection layer form a bottom capacitor; the transistor structure is positioned on the surface of one side, far away from the substrate, of the conductive connecting layer; and the top capacitor is positioned on one side, far away from the substrate, of the transistor structure. By epitaxially growing the semiconductor material columns and the transistor structure, the transistor structure can be ensured to have good performance. Bottom capacitors can be formed based on the semiconductor material columns, so that the 4F2 storage unit has higher storage density.

Description

Technical Field

[0001] This application relates to the field of storage device technology, and in particular to a 4F2 storage cell, a memory, and a method for manufacturing the 4F2 storage cell. Background Technology

[0002] Most current DRAM (Dynamic Random Access Memory) uses the 6F2 architecture, but in order to improve the storage density of devices and as the size of devices continues to shrink, the 4F2 architecture is the architecture for the next stage of DRAM.

[0003] The mainstream 4F2 architecture employs a vertical transistor structure, with a transistor at the bottom and a storage capacitor at the top of each memory cell. However, as 4F2 DRAM continues to shrink, the challenge of balancing storage density and device performance remains. Therefore, providing a 4F2 memory cell with higher storage density is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application discloses a 4F2 memory cell, a memory, and a method for fabricating the 4F2 memory cell, which has higher storage density.

[0005] In a first aspect, this application provides a 4F2 memory cell, comprising: a substrate; a semiconductor material pillar epitaxially grown along the thickness direction on one side surface of the substrate; an intermediate dielectric layer covering an end face of the semiconductor material pillar away from the substrate and extending from the end face to cover the sidewall of the semiconductor material pillar; a conductive interconnect layer covering the surface of the intermediate dielectric layer away from the substrate; the semiconductor material pillar, the intermediate dielectric layer, and the conductive interconnect layer forming a bottom capacitor; a transistor structure located on the surface of the conductive interconnect layer away from the substrate; the transistor structure includes a source, a channel, a drain, another channel, and a source epitaxially grown sequentially along the thickness direction, each of the two channels being connected to a gate metal through a gate dielectric layer, one gate metal forming a word line, the other gate metal forming another word line, the drain being connected to a bit line, and the conductive interconnect layer being in contact with the bottom source of the transistor structure; and a top capacitor located on the side of the transistor structure away from the substrate, the top capacitor being in contact with the top source of the transistor structure.

[0006] By epitaxially growing semiconductor material pillars and transistor structures, fewer defects and a more complete structure can be ensured in the transistor structure, thereby guaranteeing higher yield, larger capacity, and lower power consumption for 4F2 memory cells. The semiconductor material pillars can also form bottom capacitors, resulting in capacitors at both the top and bottom of the transistor structure, thus enabling higher storage density for 4F2 memory cells.

[0007] In one possible implementation, the substrate comprises a silicon substrate, and the semiconductor material pillars comprise silicon-germanium material pillars; the source and drain comprise phosphorus-doped silicon, and the channel comprises boron-doped silicon; or, the source and drain comprise phosphorus-doped silicon, and the channel comprises undoped silicon; or, the source and drain comprise boron-doped silicon, and the channel comprises phosphorus-doped silicon. The silicon-germanium material pillars can be fabricated on the surface of the silicon substrate via epitaxial growth, thereby enabling the fabrication of high-quality transistor structures with boron-doped or phosphorus-doped silicon as the source, drain, and gate, respectively, through epitaxial growth, resulting in high-performance 4F2 memory cells.

[0008] In one possible implementation, the contact point between the bit line and the drain includes a metal silicide contact point; and / or, the contact point between the transistor structure and at least one of the bottom capacitor and the top capacitor includes a metal silicide contact point. By providing metal silicide contact points, contact resistance can be reduced, thereby reducing RC and delay, and improving device performance.

[0009] In one possible implementation, the metal silicide contact point includes any one of the following: TiSi x Contact point, MoSi x Contact point, CoSi x Contact point, WSi x Contact points. Using contact points made of the following materials can reduce contact resistance, thereby reducing RC and delay, and improving device performance.

[0010] In one possible implementation, the device further includes: a bottom electrode layer covering the end face of the semiconductor material pillar away from the substrate and extending from the end face to cover the sidewall of the semiconductor material pillar; and an intermediate dielectric layer covering the surface of the bottom electrode layer away from the substrate. The additional bottom electrode layer can further improve the electrical properties of the bottom capacitor, such as capacitance, thereby further enhancing the device's performance.

[0011] In one possible implementation, the top capacitor includes: a top bottom electrode in contact with the source electrode at the top of the transistor structure; the top bottom electrode includes an electrode sidewall extending in the thickness direction; a top intermediate layer covering the surface of the top bottom electrode; the top intermediate layer covering the surface of the electrode sidewall; and a top top electrode covering the top intermediate layer. By providing a top bottom electrode with electrode sidewalls, and based on this structure, the top intermediate layer and top top electrode can be configured to ensure a larger capacitance, thereby further improving the performance of the device.

[0012] Secondly, this application provides a memory including 4F2 memory cells as described in any of the preceding claims, wherein a plurality of the 4F2 memory cells are arranged in an array. The 4F2 memory cells in this memory, through epitaxial growth of semiconductor material pillars and transistor structures, ensure that the transistor structure has good performance. Based on these semiconductor material pillars, bottom capacitors can be formed, thereby ensuring that capacitors are provided at both the top and bottom ends of the transistor structure, thus enabling the 4F2 memory cells to have higher storage density, ultimately improving the storage density of the memory.

[0013] Thirdly, this application provides a method for fabricating a 4F2 memory cell, comprising: epitaxially growing a semiconductor material layer, a first sacrificial layer, a second sacrificial layer, and a transistor structure layer sequentially along the thickness direction on a substrate surface; the transistor structure layer comprising a source, a channel, a drain, a channel, and a source sequentially epitaxially grown along the thickness direction; etching the epitaxially grown film layer on the substrate surface along the thickness direction to form a semiconductor material pillar based on the semiconductor material layer and a transistor structure based on the transistor structure layer; selectively removing the first sacrificial layer, forming a first gap between the second sacrificial layer and the semiconductor material pillar, and disposing an intermediate dielectric layer based on the first gap; the intermediate dielectric layer covering the end face of the semiconductor material pillar away from the substrate and extending from the end face to cover the semiconductor material pillar. Material pillar sidewall; selectively remove the second sacrificial layer to form a second gap between the intermediate dielectric layer and the transistor structure, and provide a conductive connection layer based on the second gap; the conductive connection layer covers the surface of the intermediate dielectric layer away from the substrate, and the conductive connection layer is in contact with the bottom source of the transistor structure; fabricate a word line connected to one of the channels, another word line connected to the other channel, and a bit line connected to the drain, and fabricate a top capacitor located on the side of the transistor structure away from the substrate to complete the fabrication of the 4F2 memory cell; each of the channels is connected to a gate metal through a gate dielectric layer, one gate metal forms one word line, and the other gate metal forms another word line; the top capacitor is in contact with the top source of the transistor structure.

[0014] Epitaxial growth can ensure good performance of transistor structures. By selectively etching to remove the first sacrificial layer to form a first gap, then placing an intermediate dielectric layer within the first gap, and finally removing the second sacrificial layer to form a second gap, with the remaining space used to place a conductive interconnect layer, the bottom capacitor can be fabricated after the epitaxial growth process is complete. This allows the 4F2 memory cell to achieve higher storage density.

[0015] In one possible implementation, the semiconductor material layer, the first sacrificial layer, and the second sacrificial layer are silicon-germanium material layers with different component ratios; the selective removal of the first sacrificial layer includes: selectively removing the first sacrificial layer based on the silicon-germanium component ratio in the first sacrificial layer; the selective removal of the second sacrificial layer includes: selectively removing the second sacrificial layer based on the silicon-germanium component ratio in the second sacrificial layer. Selecting silicon-germanium material layers can meet the material composition requirements of epitaxial growth processes. Furthermore, by setting different silicon-germanium component ratios in different layers, selective etching can be facilitated.

[0016] In one possible implementation, etching the epitaxially grown film on the substrate surface along the thickness direction includes: first etching the epitaxially grown film on the substrate surface along the thickness direction to form a first etching trench extending along a first direction; the first etching trench extending to the substrate in the thickness direction; filling the first etching trench with a first dielectric layer; the top of the first dielectric layer being not lower than the second sacrificial layer; second etching the epitaxially grown film on the substrate surface along the thickness direction to form a second etching trench extending along a second direction; and retaining a portion of the semiconductor material layer at the bottom of the second etching trench in the thickness direction to form an interconnect structure.

[0017] This process can form 4F2 memory cells arranged in an array. By setting a first dielectric layer in the first etching trench, the transistor structure will not shift during the subsequent removal of the sacrificial layer to form gaps, thus ultimately forming a 4F2 memory cell with a bottom capacitor. Furthermore, by retaining a portion of the semiconductor material layer to form the interconnect structure, the circuit structure of the bottom capacitor can be avoided from being re-fabricated.

[0018] In one possible implementation, after setting the conductive interconnect layer based on the second gap, the method further includes: filling the second etched trench with a second dielectric layer, the top of the second dielectric layer being no lower than the conductive interconnect layer. The second dielectric layer can protect the bottom capacitors when setting word lines and bit lines, thus ensuring the integrity of the device structure.

[0019] In one possible implementation, after forming the semiconductor material pillars based on the semiconductor material layer, the method further includes thinning the semiconductor material pillars. Thinning the semiconductor material pillars reduces the area occupied by the pillars, thereby further increasing the array density of the 4F2 memory cells.

[0020] In one possible implementation, fabricating a top capacitor located on the side of the transistor structure away from the substrate includes: depositing a top dielectric layer on top of the transistor structure; etching the top dielectric layer to form a hole structure exposing the transistor structure; depositing a conductive material within the hole structure to form a top bottom electrode; the top bottom electrode contacting an exposed source electrode, the top bottom electrode forming an electrode sidewall extending in the thickness direction based on the conductive material deposited on the sidewall of the hole structure; depositing a top intermediate layer on the surface of the top bottom electrode; the top intermediate layer covering the surface of the electrode sidewall; and depositing a top top electrode on the surface of the top intermediate layer.

[0021] By setting a top bottom electrode with electrode sidewalls, and setting a top intermediate layer and a top top electrode based on this structure, the top capacitor can be guaranteed to have a larger capacitance, thereby further improving the performance of the device. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a 4F2 memory cell provided in this embodiment;

[0024] Figure 2 This is a schematic diagram of another 4F2 memory cell provided in this embodiment;

[0025] Figure 3 This is a schematic diagram of the structure of a top capacitor provided in this embodiment;

[0026] Figure 4 This is a schematic diagram of another top capacitor structure provided in this embodiment;

[0027] Figures 5 to 11 A process flow diagram of a 4F2 memory cell fabrication method provided in an embodiment of the present invention;

[0028] Figures 12 to 17 This is a process flow diagram of a specific 4F2 memory cell fabrication method provided in an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures:

[0030] 1-Substrate;

[0031] 2- Bottom capacitor;

[0032] 21-Semiconductor material column;

[0033] 201 - Semiconductor material layer;

[0034] 22-Intermediate dielectric layer;

[0035] 202 - First Sacrifice Layer;

[0036] 23-Conductive interconnect layer;

[0037] 203 - Second Sacrificial Layer;

[0038] 204 - First gap;

[0039] 205 - Second gap;

[0040] 24 - Bottom electrode layer;

[0041] 3-Transistor structure;

[0042] 31-Source pole;

[0043] 32-Ditch;

[0044] 33-Drain;

[0045] 4-line;

[0046] 5-bit line;

[0047] 6-Top capacitor;

[0048] 7-First etching groove;

[0049] 8-Second etching groove;

[0050] 9-First dielectric layer;

[0051] 10 - Second dielectric layer. Detailed Implementation

[0052] The 4F2 memory cell provided in this application is mainly used in 4F2 architecture DRAM as the basic memory cell of the memory device, which can significantly improve the storage density of the memory device.

[0053] Example 1

[0054] Please refer to Figures 1 to 4 , Figure 1 This is a schematic diagram of the structure of a 4F2 memory cell provided in this embodiment; Figure 2 This is a schematic diagram of another 4F2 memory cell provided in this embodiment; Figure 3 This is a schematic diagram of the structure of a top capacitor provided in this embodiment; Figure 4 This is a schematic diagram of another top capacitor structure provided in this embodiment.

[0055] See Figure 1 In this embodiment, the 4F2 memory cell includes: a substrate 1; a semiconductor material pillar 21 epitaxially grown along the thickness direction on one side surface of the substrate 1; an intermediate dielectric layer 22 covering the end face of the semiconductor material pillar 21 away from the substrate 1 and extending from the end face to cover the sidewall of the semiconductor material pillar 21; a conductive interconnect layer 23 covering the surface of the intermediate dielectric layer 22 away from the substrate 1; the semiconductor material pillar 21, the intermediate dielectric layer 22, and the conductive interconnect layer 23 forming a bottom capacitor 2; and a transistor junction located on the surface of the conductive interconnect layer 23 away from the substrate 1. Structure 3; The transistor structure 3 includes a source 31, a channel 32, and a drain 33 epitaxially grown sequentially along the thickness direction. Each of the two channels 32 is connected to a gate metal through a gate dielectric layer. One gate metal forms a word line 4, and the other gate metal forms another word line 4. The drain 33 is connected to a bit line 5. The conductive connection layer 23 is in contact with the bottom source 31 of the transistor structure 3. A top capacitor 6 is located on the side of the transistor structure 3 away from the substrate 1, and the top capacitor 6 is in contact with the top source 31 of the transistor structure 3.

[0056] The substrate 1 described above forms the basic structure of a 4F2 memory cell. The bottom capacitor 2, transistor structure 3, and top capacitor 6 are all disposed on one side surface of the substrate 1. The bottom capacitor 2, transistor structure 3, and top capacitor 6 are arranged along the thickness direction and are stacked, with the bottom capacitor 2 located below the transistor structure 3 and the top capacitor 6 located above the transistor structure 3. In this embodiment, the substrate 1 can specifically be a silicon substrate 1, but it can also be a substrate 1 of other materials, which is not specifically limited here.

[0057] A semiconductor material pillar 21 is disposed on one side surface of the substrate 1. Specifically, the semiconductor material pillar 21 is a pillar-shaped structure formed on the surface of the substrate 1 based on an epitaxial growth process. This semiconductor material pillar 21 not only forms the bottom capacitor 2, serving as one terminal of the bottom capacitor 2, but also supports the transistor structure 3 above it and the top capacitor 6. It should be noted that in this embodiment, the semiconductor material pillar 21 and each film layer in the transistor structure 3 can be formed in a single continuous epitaxial growth process, rather than through multiple discontinuous epitaxial growth processes. This effectively ensures the growth quality of each film layer in the transistor structure 3 and guarantees the performance of the transistor structure 3.

[0058] The aforementioned intermediate dielectric layer 22 needs to cover the end face of the semiconductor material pillar 21 away from the substrate 1, and extend from the end face to cover the sidewall of the semiconductor material pillar 21. That is, on the cross-section of the 4F2 memory cell along the thickness direction, the intermediate dielectric layer 22 will surround the semiconductor material pillar 21 on three sides, so that there is sufficient relative area between the semiconductor material pillar 21 and the intermediate dielectric layer 22, ultimately enabling the bottom capacitor 2 to have a sufficient capacitance value. Specifically, the intermediate dielectric layer 22 serves as a film layer in the middle of the capacitor to improve the capacitance value. The intermediate dielectric layer 22 can be an HK (High K) material, such as HfO, ZrO, HfZrO, TaO, NbO, and other materials with high k values ​​and combinations thereof. The specific material of the intermediate dielectric layer 22 is not specifically limited in this embodiment, as long as it has a K value that meets the requirements.

[0059] The aforementioned conductive connection layer 23 covers the surface of the intermediate dielectric layer 22 away from the substrate 1. Since the intermediate dielectric layer 22 covers the end face and sidewalls of the semiconductor material pillars 21, the conductive connection layer 23 also covers the end face and sidewalls of the semiconductor material pillars 21. That is, on the cross-section of the 4F2 memory cell along its thickness direction, the conductive connection layer 23 will also surround the semiconductor material pillars 21 on three sides. This conductive connection layer 23 will be used as the other electrode of the bottom capacitor 2. Firstly, the conductive connection layer 23 and the semiconductor material pillars 21 are isolated from each other through the intermediate dielectric layer 22 to form the bottom capacitor 2. Semiconductor material pillars 21 are arranged in an array on one side of the substrate 1 to form an array of 4F2 memory cells, while the conductive connection layers 23 between different bottom capacitors 2 are isolated from each other. In this embodiment, the conductive connection layer 23 is connected to the transistor structure 3 so that the bottom capacitor 2 can release electrical signals based on the control of the transistor structure 3. The conductive connection layer 23 can be a metal layer, and its material can be TiN / W, etc., without specific limitations.

[0060] It should be noted that the intermediate dielectric layer 22 is specifically prepared based on the first gap 204 left after the selective etching of the first sacrificial layer 202, while the conductive connection layer 23 is specifically prepared based on the second gap 205 left after the selective etching of the second sacrificial layer 203. The first sacrificial layer 202 and the second sacrificial layer 203 mentioned above can be films prepared on the surface of the semiconductor material pillar 21 away from the substrate 1 by epitaxial growth process. The semiconductor material layer 201, the first sacrificial layer 202, the second sacrificial layer 203, and each film layer of the transistor structure 3 corresponding to the semiconductor material pillar 21 can be films prepared on the surface of the substrate 1 by a single continuous epitaxial growth process. The semiconductor material pillar 21 and the transistor structure 3 can then be formed by etching and other processes. The intermediate dielectric layer 22 is specifically prepared based on the first gap 204 left after selective etching of the first sacrificial layer 202. The conductive connection layer 23 is specifically prepared based on the second gap 205 left after selective etching of the second sacrificial layer 203. The specific details of the preparation process will be described in detail in the following embodiments and will not be repeated here.

[0061] It should be noted that when multiple 4F2 memory cells are arranged in an array on one side of the substrate 1, adjacent bottom capacitors 2 can form a connection structure based on the residual semiconductor material layer 201, connecting adjacent semiconductor interconnect pillars. Specifically, this connection structure can be formed by the residual semiconductor material layer 201 on the surface of the substrate 1 during the etching process of forming the semiconductor interconnect pillars, allowing the bottom capacitors 2 to be interconnected. The intermediate dielectric layer 22 between adjacent bottom capacitors 2 can also be interconnected. Because the intermediate dielectric layer 22 has a high K value, it will not affect the connection relationship between the bottom capacitors 2. The conductive interconnect layer 23 between adjacent bottom capacitors 2 is not connected. This conductive interconnect layer 23 is mainly used to connect with the transistor structure 3, realizing the electrical connection between the transistor structure 3 and the bottom capacitors 2.

[0062] The aforementioned transistor structure 3 is located on the surface of the conductive connection layer 23 away from the substrate 1, meaning that the transistor structure 3 will contact the conductive connection layer 23 to achieve electrical connection. This transistor structure 3 is a vertical transistor structure. In terms of material type, this transistor structure 3 comprises five layers epitaxially grown along the thickness direction: source 31, channel 32, drain 33, channel 32, and source 31. From a material perspective, the source 31 and drain 33 can be made of the same material, while the channel 32 is made of a different material than the source 31 and drain 32. The channel 32 serves as a switch between the source 31 and drain 32. Typically, a gate dielectric layer is disposed outside the channel 32, and the thickness of this gate dielectric layer is usually around 5 nm. A gate metal layer is disposed outside the gate dielectric layer; that is, the channel 32 needs to be connected to a gate metal layer through a gate dielectric layer to form the gate. In this embodiment, the transistor structure 3 has two channels 32 to form two gates; two sources 31 and one drain 33 are provided, with the drain 33 disposed between adjacent channels 32, and the upper and lower ends of the transistor structure are the sources 31. Since the transistor structure 3 is specifically vertical, it has a bottom source 31, which is closer to the bottom capacitor 2. This bottom source 31 contacts the conductive connection layer 23, thus electrically connecting the transistor structure 3 to the bottom capacitor 2. Correspondingly, the transistor structure 3 also has a top source 31, which is farther from the bottom capacitor 2. This top source 31 contacts the subsequent top capacitor 6, thus electrically connecting the transistor structure 3 to the top capacitor 6.

[0063] In this embodiment, the transistor structure 3 connects two word lines 4 and one bit line 5. Since capacitors are connected to the top and bottom ends of the transistor structure 3, and the word lines 4 control the corresponding capacitors, the transistor structure 3 connects two word lines 4. Specifically, the gate metal connected to one channel 32 in the transistor structure 3 forms one word line 4, and the gate metal connected to the other channel 32 forms another word line 4. That is, the two gates formed by the transistor structure 3 are respectively connected to word lines 4. The word line 4 near the bottom capacitor 2 is used to control the bottom capacitor 2, and the corresponding word line 4 near the top capacitor 6 is used to control the top capacitor 6. The bit line 5 is connected to the drain 33 between the two gates 32 to facilitate the transmission of the electrical signals stored in the 4F2 memory cell. In practice, one word line connects one column or one row of 4F2 memory cells; its specific structure can be set according to the actual situation and is not specifically limited here.

[0064] The aforementioned top capacitor 6 is specifically located on the side of transistor structure 3 away from substrate 1. This top capacitor 6 is in contact with the source 31 located at the top of transistor structure 3, thereby achieving electrical connection between the top capacitor 6 and transistor structure 3. The word line 4 connected to the channel 32 near the top capacitor 6 in transistor structure 3 is used to control the top capacitor 6. The specific structure of the top capacitor 6 can be referenced from existing technologies, and its fabrication process can also refer to the specific process of placing a capacitor on the top of a transistor in a 4F2 memory cell, and is not specifically limited here.

[0065] In this embodiment, the transistor structure 3, from bottom to top along the thickness direction, specifically includes: a bottom source 31 for contacting the conductive connection layer 23 → a channel 32 with a word line 4 for controlling the bottom capacitor 2 → a drain 33 with a bit line 5 → a channel 32 with a word line 4 for controlling the top capacitor 6 → a top source 31 for contacting the top capacitor 6. This transistor structure 3 can realize the most basic signal readout function mentioned above. Of course, other structures can be added to the transistor structure 3, which are not specifically limited here.

[0066] In one feasible example, the substrate 1 includes a silicon substrate 1, and the semiconductor material pillar 21 includes a silicon-germanium material pillar; the source 31 and the drain 33 include phosphorus-doped silicon, and the channel 32 includes boron-doped silicon; or, the source 31 and the drain 33 include phosphorus-doped silicon, and the channel 32 includes undoped silicon; or, the source 31 and the drain 33 include boron-doped silicon, and the channel 32 includes phosphorus-doped silicon. The silicon substrate 1 is a commonly used substrate 1 for fabricating memory devices. The silicon-germanium material pillars made of silicon-germanium material meet the requirements of epitaxial growth processes based on the silicon substrate 1. Correspondingly, boron-doped or phosphorus-doped silicon, as well as undoped silicon, also meet the requirements of epitaxial growth processes based on the silicon substrate 1. Therefore, high-quality transistor structures 3 can be fabricated through epitaxial growth, resulting in high performance for the 4F2 memory cell. It should be noted that the aforementioned channel 32, source 31, and drain 33 are silicon doped with different types of impurities to achieve corresponding functions. Specifically, in the preparation of boron-doped silicon and phosphorus-doped silicon, doping can be achieved by adding dopants during epitaxial growth. The final doping effect can be adjusted by changing the concentration of the dopant. Alternatively, after epitaxial growth, a dopant-containing gas, liquid, or solid can be brought into contact with the corresponding film layer, and the dopant can be incorporated into the source / drain layer of the film layer via thermal diffusion. The specific doping process is not limited in this embodiment and depends on the specific circumstances.

[0067] Correspondingly, the first sacrificial layer 202 and the second sacrificial layer 203 can also be silicon-germanium material layers to meet the requirements of epitaxial growth on the surface of the silicon substrate 1, ensuring that the semiconductor material pillar 21 and the transistor structure 3 can be fabricated based on the same continuous epitaxial growth process. The first sacrificial layer 202 and the second sacrificial layer 203, like the semiconductor material pillar 21, use silicon-germanium materials. The main difference lies in the different silicon and germanium composition ratios of each film layer, facilitating the selective removal of each sacrificial layer through etching. For example, if the silicon-germanium composition in the semiconductor material pillar 21 is 90%:10%, the silicon-germanium composition in the first sacrificial layer 202 is 50%:50%, and the silicon-germanium composition in the second sacrificial layer 203 is 10%:90%, then when selectively removing the first sacrificial layer 202, it can be selectively removed based on its compositional differences with almost no impact on the second sacrificial layer 203. When selectively removing the second sacrificial layer 203, it can be done based on its compositional differences. Although these two selective removal methods may affect the semiconductor material pillar 21, this can be avoided by thickening and increasing the height of the semiconductor material pillar 21, and reserving a portion of the volume of the semiconductor material pillar 21 for use as the thinner layer to be removed in the process of selectively removing the corresponding sacrificial layer. The specific parameters mentioned above are for illustrative purposes only and are not intended to limit the specific content.

[0068] In one feasible example, the bit line 5 includes a metal bit line 5, and the contact point between the bit line 5 and the drain 33 includes a metal silicide contact point; and / or, the contact point between the transistor structure 3 and at least one of the bottom capacitor 2 and the top capacitor 6 includes a metal silicide contact point, the thickness of which is typically 2nm to 3nm. The bottom capacitor 2 is connected to a source 31 of the transistor structure 3 via a conductive connection layer 23, which is typically made of metal, and the source 31 connected to the conductive connection layer 23 is typically made of silicon. Correspondingly, the component connecting the top capacitor 6 to the source 31 in the transistor structure 3 is also typically made of metal, and the bit line 5 connecting to the drain 33 in the transistor is also typically a metal bit line 5. To reduce the contact resistance between the source 31, drain 33, and the various metal materials, this embodiment specifically allows for the following: the contact point between the bit line 5 and the drain 33 can be a metal silicide contact point; and the contact point between the transistor structure 3 and at least one of the bottom capacitor 2 and the top capacitor 6 can be a metal silicide contact point. Setting the material of these contact points to metal silicide can effectively reduce the contact resistance between the various metal components and the transistor structure 3, thereby reducing RC and delay, and improving device performance. Specifically, the aforementioned metal silicide contact points include any one of the following: TiSi. xContact point, MoSi x Contact point, CoSi x Contact point, WSi x Contact points. The contact points made of the above-mentioned materials can effectively reduce contact resistance, thereby reducing RC and delay, and improving device performance.

[0069] See Figure 2 Specifically, in this embodiment, the 4F2 memory cell may further include: a bottom electrode layer 24 covering the end face of the semiconductor material pillar 21 away from the substrate and extending from the end face to cover the sidewall of the semiconductor material pillar 21; and an intermediate dielectric layer 22 covering the surface of the bottom electrode layer 24 away from the substrate 1. The bottom capacitor 2 mentioned above is specifically composed of a three-layer structure: the semiconductor material pillar 21, the intermediate dielectric layer 22, and the conductive connection layer 23. To further improve the capacitance and other electrical properties of the bottom capacitor 2, a bottom electrode layer 24 can be inserted between the semiconductor material pillar 21 and the intermediate dielectric layer 22, thereby forming a four-layer structure for the bottom capacitor 2. The bottom electrode layer 24 is made of metal. The bottom electrode layer 24 needs to cover the end face of the semiconductor material pillar 21 away from the substrate 1 and extend from the end face to cover the sidewall of the semiconductor material pillar 21. That is, in the cross-section of the 4F2 memory cell along the thickness direction, the bottom electrode layer 24 will surround the semiconductor material pillar 21 on three sides, thereby ensuring that the bottom electrode layer 24 has sufficient area to ultimately give the bottom capacitor 2 a sufficient capacitance value. The bottom electrode layer 24 mentioned above is specifically based on the third gap left after selective etching of the third sacrificial layer. The third sacrificial layer can be a film layer prepared on the surface of the semiconductor material pillar 21 away from the substrate 1 by epitaxial growth process. Its specific composition can be set with reference to the composition of the first sacrificial layer 202 and the second sacrificial layer 203. The third sacrificial layer can also be made of silicon-germanium material. The ratio of silicon to germanium in the third sacrificial layer needs to be different from the composition of the semiconductor material pillar 21, the first sacrificial layer 202 and the second sacrificial layer 203. The specific ratio of the components is not specifically limited here.

[0070] See Figure 3 as well as Figure 4In this embodiment, the top capacitor 6 may specifically include: a top bottom electrode 61 in contact with the source 31 at the top of the transistor structure 3; the top bottom electrode 61 includes an electrode sidewall extending along the thickness direction; a top intermediate layer 62 covering the surface of the top bottom electrode; the top intermediate layer 62 covering the surface of the electrode sidewall; and a top top electrode 63 covering the top intermediate layer. The top bottom electrode 61 is in contact with the source 31 at the top of the transistor structure 3, and a metal silicide contact point may be provided between them. The top bottom electrode 61 of this structure has a high surface area, thereby giving the top capacitor 6 a large capacitance value. The top bottom electrode 61 of this structure can be based on a hole structure, the details of which can be found in the prior art and will not be repeated here. The material of the top intermediate layer 62 is usually HK material, while the top top electrode 63 can be a stacked material of metal and SiGe. In the array structure, the top top electrode 63 needs to be interconnected.

[0071] Depending on the size of the hole structure, if there is no gap after the top bottom electrode 61 and the top intermediate layer 62 are set within the hole structure, then the top top electrode 63 will not extend into the middle of the top intermediate layer 62 but will only surround the top intermediate layer 62 from the outside to form the top capacitor 6. However, if there is a gap after the top bottom electrode 61 and the top intermediate layer 62 are set within the hole structure, then the top top electrode 63 can extend into the middle of the top intermediate layer 62, thereby further increasing the relative area between the top top electrode 63 and the top intermediate layer 62, and thus increasing the capacitance value of the top capacitor 6. The specific structure of the top capacitor 6 is not limited in this embodiment and depends on the specific circumstances.

[0072] The 4F2 memory cell provided in this embodiment, through epitaxial growth of semiconductor material pillars 21 and transistor structure 3, ensures that the transistor structure 3 has good performance. Based on the semiconductor material pillars 21, a bottom capacitor 2 can be formed, thus providing capacitors at both the top and bottom ends of the transistor structure 3, thereby enabling the 4F2 memory cell to have higher storage density.

[0073] Example 2

[0074] This embodiment also provides a memory, which includes a 4F2 memory cell provided in the above embodiments, and multiple 4F2 memory cells are arranged in an array. The specific structure of the 4F2 memory cell has been described in detail in the above embodiments, and will not be repeated here.

[0075] Since the memory provided in this embodiment is equipped with the above-mentioned 4F2 memory cells, the memory can have a higher storage density.

[0076] Example 3

[0077] Please refer to Figures 5 to 11 , Figures 5 to 11 This is a process flow diagram of a 4F2 memory cell fabrication method provided in an embodiment of the present invention.

[0078] See Figure 5 In this embodiment, the method for fabricating the 4F2 memory cell includes:

[0079] S101: A semiconductor material layer, a first sacrificial layer, a second sacrificial layer, and a transistor structure layer are epitaxially grown sequentially along the thickness direction on the substrate surface.

[0080] In this embodiment, the transistor structure layer includes a source 31, a channel 32, a drain 33, and another channel 32 epitaxially grown sequentially along the thickness direction. The stacked structure of this transistor structure layer corresponds to transistor structure 3 in the above embodiment; for details, please refer to the above embodiment, which will not be repeated here.

[0081] See Figure 6 In this step, a semiconductor material layer 201, a first sacrificial layer 202, a second sacrificial layer 203, and a source 31, a channel 32, a drain 33, and another channel 32 are sequentially epitaxially grown along the thickness direction on the surface of substrate 1 through a continuous epitaxial growth process to ensure that the subsequently formed transistor structure 3 has good performance. When a bottom electrode layer 24 needs to be set, in this step, a semiconductor material layer 201, a third sacrificial layer, a first sacrificial layer 202, a second sacrificial layer 203, and a source 31, a channel 32, a drain 33, and another channel 32 are sequentially epitaxially grown along the thickness direction on the surface of substrate 1 through a continuous epitaxial growth process.

[0082] Specifically, the aforementioned semiconductor material layer 201, the first sacrificial layer 202, and the second sacrificial layer 203 can be silicon-germanium material layers with different component ratios, so that the first sacrificial layer 202 and the second sacrificial layer 203 can be selectively removed in subsequent steps based on the difference in component ratios. For example, the silicon-germanium composition in the semiconductor material layer 201 can be set to 90%:10%, with a thickness of approximately 300 nm; the silicon-germanium composition in the first sacrificial layer 202 can be set to 50%:50%, with a thickness of approximately 5 nm; and the silicon-germanium composition in the second sacrificial layer 203 can be set to 10%:90%, with a thickness of approximately 5 nm.

[0083] S102: Etch the epitaxially grown film layer on the substrate surface along the thickness direction to form a semiconductor material pillar based on the semiconductor material layer and a transistor structure based on the transistor structure layer.

[0084] See Figure 7In this step, the epitaxially grown film layer from the previous steps will be etched to form the semiconductor material pillar 21 and the transistor structure 3. A first sacrificial layer 202 and a second sacrificial layer 203 remain between the top surface of the semiconductor material pillar 21 and the transistor structure 3. For specific etching processes, please refer to the prior art, which will not be elaborated here.

[0085] S103: Selectively remove the first sacrificial layer, form a first gap between the second sacrificial layer and the semiconductor material pillar, and set an intermediate dielectric layer based on the first gap.

[0086] In this embodiment, the intermediate dielectric layer 22 at least covers the end face of the semiconductor material pillar 21 away from the substrate 1, and extends from the end face to cover the sidewall of the semiconductor material pillar 21. The specific details of the intermediate dielectric layer 22 have been described in detail in the above embodiments and will not be repeated here.

[0087] See Figure 8 as well as Figure 9 In this step, the first sacrificial layer 202 is selectively removed to form a first gap 204 between the second sacrificial layer 203 and the semiconductor material pillar 21. Specifically, this step may include selectively removing the first sacrificial layer 202 based on the silicon-germanium composition ratio in the first sacrificial layer 202. The removal can be achieved by first selectively oxidizing the first sacrificial layer 202 according to its specific composition ratio, and then removing the oxidized silicon and germanium. Alternatively, other methods can be used to selectively remove the first sacrificial layer 202 to form the first gap 204.

[0088] In this step, an intermediate dielectric layer 22, covering at least the exposed end face of the semiconductor material pillar 21, can be formed based on the first gap 204. This intermediate dielectric layer 22 can also cover the sidewalls of the semiconductor material pillar 21. Specifically, in this step, a High K material, such as HfO, ZrO, HfZrO, TaO, NbO, or combinations thereof with high k values, can be filled onto the device surface based on the first gap 204. Then, an anisotropic etching process is performed on the intermediate dielectric layer 22 to form an intermediate dielectric layer 22 that covers at least the end face of the semiconductor material pillar 21 away from the substrate 1, and also covers the sidewalls of the semiconductor material pillar 21. Afterwards, an isotropic etching process can be used to thin the intermediate dielectric layer 22, completing the fabrication of the intermediate dielectric layer 22. The specific details of the etch-back process and the isotropic etching process can be found in existing technologies and will not be elaborated here. The final thickness of the intermediate dielectric layer 22 formed in this step is between 3 nm and 5 nm.

[0089] S104: Selectively remove the second sacrificial layer, form a second gap between the intermediate dielectric layer and the transistor structure, and set a conductive connection layer based on the second gap.

[0090] In this embodiment, the conductive connection layer 23 at least covers the surface of the intermediate dielectric layer 22 away from the substrate 1, and the conductive connection layer 23 is in contact with the source 31 at the bottom of the transistor structure 3. The specific details of the conductive dielectric layer have been described in detail in the above embodiments and will not be repeated here.

[0091] See Figure 10 as well as Figure 11 In this step, the second sacrificial layer 203 is selectively removed to form a second gap 205 between the intermediate dielectric layer 22 and the transistor structure 3. Specifically, this step may include selectively removing the second sacrificial layer 203 based on the silicon-germanium composition ratio in the second sacrificial layer 203. The process for selectively removing the second sacrificial layer 203 in this step can be the same as or different from the process for selectively removing the first sacrificial layer 202. Both can be achieved through dry etching (such as ICP (Inductively Coupled Plasma), CCP (Apacitively Coupled Plasma), etc.) or wet (solution) etching, as long as selective etching is achieved based on the compositional differences. No specific limitation is made here.

[0092] Subsequently, in this step, a conductive connection layer 23 can be formed based on the second gap 205, at least located on the end face of the semiconductor material pillar 21 facing the transistor structure 3. This conductive connection layer 23 can also cover the sidewall of the semiconductor material pillar 21. Specifically, in this step, a metal, such as TiN / W, can be filled onto the device surface based on the second gap 205, and may also include a metal silicide contact material, such as TiSi. x CoSi x Then, through a reverse etching process, the conductive interconnect layer 23 is anisotropically etched to form a conductive dielectric layer covering the surface of the intermediate dielectric layer 22. The conductive interconnect layers 23 between adjacent 4F2 memory cells are not connected to each other. Of course, the specific details of the reverse etching process can be found in existing technologies, and will not be elaborated here. In this step, the conductive interconnect layer 23 must be in contact with the source 31 of the lowest layer in the transistor structure 3.

[0093] In this embodiment, the bottom capacitor 2 can have a SiGe / High K / metal structure. In another feasible example, to improve the electrical performance of the bottom capacitor 2, its structure can be transformed into a SiGe / metal / High K / metal structure. In this case, during epitaxial growth in S201, a third sacrificial layer is additionally provided between the semiconductor material layer 201 and the first sacrificial layer 202. The semiconductor material layer 201, the third sacrificial layer, the first sacrificial layer 202, and the second sacrificial layer 203 can be four silicon-germanium material layers with different component ratios. Before selectively removing the first sacrificial layer 202 in S206, the third sacrificial layer is selectively removed using a process similar to S207 to form a third gap at the corresponding position. Based on this third gap, a bottom electrode layer 24 is formed, which at least covers the exposed end face of the semiconductor material pillar 21. The bottom electrode layer 24 can also cover the sidewall of the semiconductor material pillar 21. The material of this bottom electrode layer is typically metal to improve the electrical performance of the bottom capacitor 2. Subsequently, based on S206, the first sacrificial layer 202 can be selectively removed to form a first gap 204 at the corresponding position, and an intermediate dielectric layer 22 can be prepared based on the first gap 204. Then, based on S207, the second sacrificial layer 203 can be selectively removed to form a second gap 205 at the corresponding position, and a conductive connection layer 23 can be prepared based on the second gap 205, forming a SiGe / metal / High k / metal bottom capacitor 2 structure. The process of this structure is basically the same as the process described above. The process of preparing the bottom electrode layer is largely the same as the process of preparing the intermediate dielectric layer 22 and the process of preparing the conductive connection layer 23, and will not be described in detail here.

[0094] S105: Fabricate a word line connected to one channel, another word line connected to another channel, and a bit line connected to the drain, and fabricate a top capacitor located on the side of the transistor structure away from the substrate to complete the fabrication of the 4F2 memory cell.

[0095] See Figure 1 In this embodiment, each of the channels 32 is connected to a gate metal through a gate dielectric layer. One gate metal forms one word line 4, and another gate metal forms another word line 4. The top capacitor 6 is in contact with the source 31 at the top of the transistor structure 3. In this step, word lines 4, bit lines 5, word lines 4, and top capacitors 6 can be fabricated sequentially from bottom to top to complete the fabrication of the 4F2 memory cell. Specific details regarding word lines 4, bit lines 5, and top capacitors 6 can be found in the above embodiment, and the specific fabrication processes for word lines 4, bit lines 5, and top capacitors 6 can be found in existing technologies, and will not be elaborated here. When fabricating the corresponding word line 4, a gate dielectric layer in contact with the corresponding channel 32 can be fabricated first, and then a gate metal connected to the gate dielectric layer can be fabricated, making the gate metal interconnects well connected to the word line 4.

[0096] The method for fabricating a 4F2 memory cell provided in this embodiment ensures that the transistor structure 3 has good performance by using an epitaxial growth process to fabricate the transistor structure 3. Furthermore, by selectively etching to first remove the first sacrificial layer 202 to form a first gap 204, and then setting an intermediate dielectric layer 22 based on the first gap 204, followed by removing the second sacrificial layer 203 to form a second gap 205, and finally setting a conductive interconnect layer 23 in the remaining second gap 205, the bottom capacitor 2 can be fabricated after the epitaxial growth process is completed, thereby enabling the 4F2 memory cell to have a higher storage density.

[0097] The specific details of the method for preparing a 4F2 memory cell provided by the present invention will be described in detail in the following embodiments.

[0098] Example 4

[0099] Please refer to Figures 12 to 17 , Figures 12 to 17 This is a process flow diagram of a specific 4F2 memory cell fabrication method provided in an embodiment of the present invention.

[0100] See Figure 12 In this embodiment, the method for fabricating the 4F2 memory cell includes:

[0101] S201: A semiconductor material layer, a first sacrificial layer, a second sacrificial layer, and a transistor structure layer are epitaxially grown sequentially along the thickness direction on the substrate surface.

[0102] This step is basically the same as S101 in the above embodiment. For details, please refer to the above embodiment. It will not be repeated here.

[0103] S202: The epitaxial film layer grown on the substrate surface is etched for the first time along the thickness direction to form a first etch groove extending along the first direction.

[0104] In this embodiment, the first etching groove 7 extends to the substrate 1 in the thickness direction. The first direction and the second direction described below are two intersecting directions in a plane, and the first direction and the second direction can be perpendicular to each other.

[0105] See Figure 13 In this step, the epitaxially grown film layer is etched along the thickness direction to form a first etch trench 7 extending along the first direction. Specifically, the etch trench extends into the substrate 1 to etch through the semiconductor material layer 201 from the transistor structure layer. The width of the first etch trench 7 can be around 20 nm, and the corresponding width of the material layer located between the first etch trenches 7 is around 30 nm.

[0106] S203: Fill the first etching groove with the first dielectric layer.

[0107] See Figure 14 In this embodiment, the top of the first dielectric layer 9 is not lower than the second sacrificial layer 203. The material of the first dielectric layer 9 can be SiO or similar. In this embodiment, the transistor structure layer is fixed in the thickness direction based on the first dielectric layer 9 to ensure that a gap can be formed below the transistor structure 3 after the sacrificial layer is etched away. Therefore, the top of the first dielectric layer 9 is not lower than the second sacrificial layer 203 to ensure that the first dielectric layer 9 is in contact with the transistor structure layer, thereby fixing the transistor structure layer. The top of the first dielectric layer 9 is flush with the transistor structure layer.

[0108] S204: The epitaxial film layer grown on the substrate surface is etched a second time along the thickness direction to form a second etch groove extending along the second direction.

[0109] See Figure 15 In this embodiment, a portion of the semiconductor material layer 201 is retained at the bottom of the second etching groove 8 in the thickness direction to form a connection structure.

[0110] In this step, the epitaxially grown film layer is etched along the thickness direction to form a second etch trench 8 extending in the second direction. At this point, an array of columnar structures can be formed based on the first etch trench 7 and the second etch trench 8, thereby forming 4F2 memory cells based on each columnar structure. During the etching of the second etch trench 8 in this step, the depth of the second etch trench 8 is less than the total thickness of the epitaxially grown film layer, so that a portion of the semiconductor material layer 201 is retained at the bottom of the second etch trench 8. This retained semiconductor material layer 201 connects to the bottom capacitor 2 of adjacent 4F2 memory cells, thus serving as a connection structure for interconnecting the bottom capacitors 2. Of course, depending on design requirements, the semiconductor material layer 201 can be left unretained at the bottom of the etch trench to form a connection structure, or additional connection structures can be added through other processes; no specific limitation is made here. The second etch trench 8 can expose the first sacrificial layer 202 and the second sacrificial layer 203 to facilitate selective etching of the sacrificial layers.

[0111] S205: Thinning of semiconductor material pillars.

[0112] See Figure 16 In this step, the semiconductor material pillar 21 can be thinned using an isotropic etching process. The space freed up by this thinning can be used to set the intermediate dielectric layer 22 and the conductive interconnect layer 23, preventing the area of ​​the bottom capacitor 2 from exceeding the area of ​​the transistor structure 3 excessively, thereby improving the density of the 4F2 memory cells. Of course, in this embodiment, the semiconductor material pillar 21 can also be left unthinned, which would reduce the density of the 4F2 memory cells. The specific details need to be set according to the actual situation and are not specifically limited here.

[0113] S206: Selectively remove the first sacrificial layer, form a first gap between the second sacrificial layer and the semiconductor material pillar, and set an intermediate dielectric layer based on the first gap.

[0114] S207: Selectively remove the second sacrificial layer, form a second gap between the intermediate dielectric layer and the transistor structure, and provide a conductive connection layer based on the second gap.

[0115] The above S206 to S207 are basically the same as S103 to S104 in the above embodiments. For details, please refer to the above embodiments, and will not be repeated here.

[0116] S208: Fill the second etching groove with a second dielectric layer.

[0117] See Figure 17 In this embodiment, the top of the second dielectric layer 10 is not lower than the conductive connection layer 23. The second dielectric layer 10 mainly protects the bottom capacitor 2, preventing subsequent fabrication of the word line 4, bit line 5, and top capacitor 6 from affecting the structure of the bottom capacitor 2. The material of the second dielectric layer 10 can be SiN, etc., and is not specifically limited here. In this step, the second dielectric layer 10 is filled into the second etching trench 8 and then etched back to ensure that the second dielectric layer 10 is neither lower than the electrical connection layer nor higher than the gate 32 near the bottom capacitor 2, thus ensuring that the word line 4 can form good contact with the gate 32.

[0118] S209: Fabricate a word line connected to one channel, another word line connected to another channel, and a bit line connected to the drain, and fabricate a top capacitor located on the side of the transistor structure away from the substrate to complete the fabrication of the 4F2 memory cell.

[0119] This step is basically the same as S105 in the above embodiment. For details, please refer to the above embodiment, and it will not be repeated here. The 4F2 memory cell prepared in this embodiment has a transistor structure 3 that can control the upper and lower capacitors.

[0120] Specifically, the fabrication of the top capacitor 6 located on the side of the transistor structure 3 away from the substrate in this step includes: depositing a top dielectric layer on top of the transistor structure 3; etching the top dielectric layer to form a hole structure exposing the transistor structure; depositing conductive material within the hole structure to form a top bottom electrode 61; the top bottom electrode 61 contacting the exposed source electrode 31, and the top bottom electrode forming an electrode sidewall extending in the thickness direction based on the conductive material deposited on the sidewall of the hole structure; depositing a top intermediate layer 62 on the surface of the top bottom electrode 61; the top intermediate layer 62 covering the surface of the electrode sidewall; and depositing a top top electrode 63 on the surface of the top intermediate layer 62.

[0121] In fabricating the top capacitor 6, a relatively thick top dielectric layer is typically first deposited on the surface of the transistor structure 3 to form a deep via structure. A conductive material is then deposited within this via structure to form the top bottom electrode 61. Specifically, the conductive material deposited on the sidewalls of the via structure forms electrode sidewalls extending along the thickness direction. The top dielectric layer is then removed to expose the inner and outer surfaces of the electrode sidewalls, allowing the subsequently deposited top intermediate layer 62 to cover these surfaces, increasing the contact area between the top intermediate layer 62 and the top bottom electrode 61. A top top electrode 63 is then deposited on the surface of the top intermediate layer 62, and its formation depends on the presence of gaps between the top intermediate layers 62. Figure 3 as well as Figure 4 The top capacitor has a 6-structure.

[0122] This embodiment provides a method for fabricating a 4F2 memory cell, which includes a process for forming a first gap 204 and a second gap 205, thereby enabling the fabrication of the bottom capacitor 2. Theoretically, this process will not interfere with the specific structure of the transistor structure 3 and the top capacitor 6, ensuring that the 4F2 memory cell has good electrical performance.

[0123] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A 4F2 memory cell, characterized in that, include: Substrate; A semiconductor material pillar epitaxially grown along the thickness direction on one side surface of the substrate; An intermediate dielectric layer covers the end face of the semiconductor material pillar away from the substrate and extends from the end face to cover the sidewall of the semiconductor material pillar; A conductive interconnect layer covering the surface of the intermediate dielectric layer away from the substrate; The semiconductor material pillar, the intermediate dielectric layer, and the conductive connection layer form a bottom capacitor; A transistor structure located on the surface of the conductive connection layer away from the substrate; the transistor structure includes a source, a channel, a drain, a channel, and a source epitaxially grown sequentially along the thickness direction, each of the two channels being connected to a gate metal through a gate dielectric layer, one gate metal forming a word line, the other gate metal forming another word line, the drain being connected to a bit line, and the conductive connection layer being in contact with the source at the bottom of the transistor structure; A top capacitor located on the side of the transistor structure away from the substrate, the top capacitor being in contact with the top source electrode of the transistor structure.

2. The 4F2 memory cell according to claim 1, characterized in that, The substrate includes a silicon substrate, and the semiconductor material pillars include silicon-germanium material pillars; The source and the drain comprise phosphorus-doped silicon, and the channel comprises boron-doped silicon; or, the source and the drain comprise phosphorus-doped silicon, and the channel comprises undoped silicon; or, the source and the drain comprise boron-doped silicon, and the channel comprises phosphorus-doped silicon.

3. The 4F2 memory cell according to claim 2, characterized in that, The bit line includes a metal bit line, and the contact point between the bit line and the drain includes a metal silicide contact point; and / or, the contact point between the transistor structure and at least one of the bottom capacitor and the top capacitor includes a metal silicide contact point.

4. The 4F2 memory cell according to claim 3, characterized in that, The metal silicide contact point includes any one of the following: TiSi x Contact point, MoSi x Contact point, CoSi x Contact point, WSi x Contact point.

5. The 4F2 memory cell according to claim 1, characterized in that, Also includes: A bottom electrode layer that covers the end face of the semiconductor material pillar away from the substrate and extends from the end face to cover the sidewall of the semiconductor material pillar; The intermediate dielectric layer covering the surface of the bottom electrode layer away from the substrate.

6. The 4F2 memory cell according to claim 1, characterized in that, The top capacitor includes: A top bottom electrode that contacts the source electrode at the top of the transistor structure; the top bottom electrode includes an electrode sidewall extending in the thickness direction; A top intermediate layer covering the surface of the top bottom electrode; the top intermediate layer covering the surface of the electrode sidewall; Top electrode covering the top middle layer.

7. A memory, characterized in that, It includes the 4F2 memory cells as described in any one of claims 1 to 6, wherein a plurality of the 4F2 memory cells are arranged in an array.

8. A method for fabricating a 4F2 memory cell, characterized in that, include: A semiconductor material layer, a first sacrificial layer, a second sacrificial layer, and a transistor structure layer are epitaxially grown sequentially along the thickness direction on the substrate surface; The transistor structure layer includes a source, a channel, a drain, a channel, and a source that are epitaxially grown sequentially along the thickness direction; The epitaxially grown film layer on the substrate surface is etched along the thickness direction to form a semiconductor material pillar based on the semiconductor material layer and a transistor structure based on the transistor structure layer; The first sacrificial layer is selectively removed, a first gap is formed between the second sacrificial layer and the semiconductor material pillar, and an intermediate dielectric layer is formed based on the first gap; The intermediate dielectric layer covers the end face of the semiconductor material pillar away from the substrate and extends from the end face to cover the sidewall of the semiconductor material pillar; The second sacrificial layer is selectively removed, a second gap is formed between the intermediate dielectric layer and the transistor structure, and a conductive connection layer is formed based on the second gap; The conductive connection layer covers the surface of the intermediate dielectric layer away from the substrate, and the conductive connection layer is in contact with the source electrode at the bottom of the transistor structure; The fabrication of the 4F2 memory cell is completed by fabricating a word line connected to one of the channels, another word line connected to the other channel, a bit line connected to the drain, and a top capacitor located on the side of the transistor structure away from the substrate. Each channel is connected to a gate metal through a gate dielectric layer, one gate metal forms one word line, and the other gate metal forms another word line. The top capacitor is in contact with the source at the top of the transistor structure.

9. The method according to claim 8, characterized in that, The semiconductor material layer, the first sacrificial layer, and the second sacrificial layer are silicon-germanium material layers with different component ratios; The selective removal of the first sacrificial layer includes: Based on the silicon to germanium composition ratio in the first sacrificial layer, the first sacrificial layer is selectively removed; The selective removal of the second sacrificial layer includes: The second sacrificial layer is selectively removed based on the silicon to germanium composition ratio in the second sacrificial layer.

10. The method according to claim 8, characterized in that, Etching the epitaxially grown film on the substrate surface along the thickness direction includes: The epitaxially grown film layer on the substrate surface is etched for the first time along the thickness direction to form a first etching trench extending along a first direction; the first etching trench extends to the substrate in the thickness direction; A first dielectric layer is filled into the first etching groove; the top of the first dielectric layer is not lower than the second sacrificial layer. The epitaxial film layer grown on the substrate surface is etched a second time along the thickness direction to form a second etching trench extending along the second direction; a portion of the semiconductor material layer is retained at the bottom of the second etching trench in the thickness direction to form a connection structure.

11. The method according to claim 10, characterized in that, After the conductive connection layer is formed based on the second gap, the method further includes: A second dielectric layer is filled in the second etching groove, and the top of the second dielectric layer is not lower than the conductive connection layer.

12. The method according to claim 8, characterized in that, After forming the semiconductor material pillar based on the semiconductor material layer, the process further includes: The semiconductor material pillar is thinned.

13. The method according to claim 8, characterized in that, Fabricating the top capacitor located on the side of the transistor structure away from the substrate includes: A top dielectric layer is disposed on top of the transistor structure; The top dielectric layer is etched to form a hole structure that exposes the transistor structure; A top bottom electrode is formed by depositing conductive material within the hole structure; the top bottom electrode is in contact with the exposed source electrode, and the top bottom electrode forms an electrode sidewall extending in the thickness direction based on the conductive material deposited on the sidewall of the hole structure. A top intermediate layer is deposited on the surface of the top bottom electrode; the top intermediate layer covers the surface of the electrode sidewall. A top electrode is deposited on the surface of the top intermediate layer.

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