A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, which comprises a substrate, a buffer layer on the substrate, a barrier layer on the buffer layer, a gate cap layer on a partial region of the barrier layer, a dielectric layer covering the gate cap layer and a partial barrier layer, and a source electrode and a drain electrode on both sides of the dielectric layer. The gate cap layer comprises a p-type semiconductor layer on the barrier layer and a gate on the p-type semiconductor layer. The dielectric layer is manufactured by a sidewall process, the thickness of the covered region of the barrier layer by the dielectric layer is different from the thickness of other regions of the barrier layer, and the width of the dielectric layer near the barrier layer is greater than the width of the dielectric layer far from the barrier layer. The thickness of the sidewall of the dielectric layer after etching by the sidewall process is thinner, the covered region of the dielectric layer on the barrier layer is smaller, and the drift region area of the semiconductor device is smaller, so that the specific on-resistance of the semiconductor device is reduced, and the current density of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] The third generation semiconductor material has good properties such as wide band gap, high critical breakdown field, high electron saturation velocity, and strong radiation resistance, and is widely used in the fields of optoelectronics, radio frequency and power electronics, and is the most optimal material system for preparing high-power radio frequency electronic devices and high-efficiency power electronic devices. Among them, the p-type gate gallium nitride high electron mobility transistor (HEMT) as an enhancement type device is promoting the development of gallium nitride power devices with its normally-off characteristics.

[0003] With the development of semiconductor devices in the field of low-voltage logic control, higher demands are put forward for low-voltage semiconductor devices with small size and high current density. In traditional semiconductor manufacturing, the source and drain need to be aligned with the gate through a photolithography process. However, this photolithography alignment process has alignment errors, so a tolerance space needs to be reserved, resulting in a larger device size and lower current density. SUMMARY

[0004] In a first aspect, the present application provides a semiconductor device, comprising:

[0005] a substrate;

[0006] a buffer layer on the substrate;

[0007] a barrier layer on the buffer layer;

[0008] a gate cap layer on part of the barrier layer; the gate cap layer comprises a p-type semiconductor layer on the barrier layer and a gate on the p-type semiconductor layer;

[0009] a dielectric layer covering the gate cap layer and part of the barrier layer; the thickness of the covered area of the barrier layer by the dielectric layer is different from the thickness of other areas of the barrier layer, and the width of the side of the dielectric layer close to the barrier layer is greater than the width of the side away from the barrier layer;

[0010] a source and a drain on both sides of the dielectric layer.

[0011] In some embodiments, the orthographic projection of the dielectric layer on the barrier layer has a width of 50-200 nm in a first direction; the first direction is the direction in which the source points to the drain.

[0012] In some embodiments, the sidewall of the dielectric layer is arc-shaped.

[0013] In some embodiments, the thickness of the region of the barrier layer covered by the dielectric layer is greater than the thickness of other regions of the barrier layer.

[0014] In some embodiments, the semiconductor device further comprises:

[0015] An n-type semiconductor layer on the barrier layer on both sides of the dielectric layer; the source and the drain are on the n-type semiconductor layer.

[0016] In some embodiments, the material of the buffer layer, the barrier layer and the p-type semiconductor layer is gallium nitride or gallium arsenide.

[0017] In some embodiments, the semiconductor device further comprises:

[0018] A first interposed layer between the substrate and the buffer layer; and / or,

[0019] A second interposed layer between the buffer layer and the barrier layer.

[0020] A second aspect of the embodiments of the present application provides a method for manufacturing a semiconductor device, comprising:

[0021] Forming a buffer layer, a barrier layer and a p-type semiconductor layer on a substrate in sequence;

[0022] Forming a gate metal layer and a first dielectric layer on the p-type semiconductor layer in sequence;

[0023] Etching the first dielectric layer to define a gate region;

[0024] Etching the gate metal layer and the p-type semiconductor layer outside the gate region to expose the barrier layer, forming a gate cap layer;

[0025] Forming a second dielectric layer on the gate cap layer and the exposed barrier layer;

[0026] Etching the second dielectric layer by a sidewall process to expose the barrier layer or the buffer layer; the etched second dielectric layer covers the gate cap layer and part of the barrier layer near the gate cap layer, and the width of the etched second dielectric layer near the barrier layer is greater than the width of the etched second dielectric layer far from the barrier layer;

[0027] Forming a source and a drain on the exposed barrier layer or buffer layer on both sides of the etched second dielectric layer.

[0028] In some embodiments, the etching the second dielectric layer by the sidewall process specifically comprises:

[0029] Etching the second dielectric layer by using halogen gas and / or halogen compound gas, and removing part or all of the barrier layer.

[0030] In some embodiments, after the etching of the second dielectric layer by using the sidewall process, before the forming of the source and the drain, further comprising:

[0031] Forming an n-type semiconductor layer on the barrier layer or the buffer layer exposed on both sides of the etched second dielectric layer.

[0032] The application provides a semiconductor device and a manufacturing method thereof, comprising: a substrate, a buffer layer on the substrate, a barrier layer on the buffer layer, a gate cap layer on a partial region of the barrier layer, a dielectric layer covering the gate cap layer and part of the barrier layer, a source and a drain on both sides of the dielectric layer. The gate cap layer comprises: a p-type semiconductor layer on the barrier layer and a gate on the p-type semiconductor layer. The dielectric layer is manufactured by using a sidewall process, the thickness of the barrier layer covered by the dielectric layer is different from the thickness of other regions of the barrier layer, and the width of the dielectric layer close to the barrier layer is greater than the width of the dielectric layer far from the barrier layer. The thickness of the sidewall of the dielectric layer after the etching by using the sidewall process is thinner, the region of the dielectric layer covering the barrier layer is smaller, and the drift region area of the semiconductor device is smaller, so that the specific on-resistance of the semiconductor device is reduced and the current density of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments of the application. Obviously, the drawings introduced below are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0034] Figure 1 One of the structure schematic diagrams of the semiconductor device provided by the embodiments of the application;

[0035] Figure 2 The second of the structure schematic diagrams of the semiconductor device provided by the embodiments of the application;

[0036] Figure 3 The third of the structure schematic diagrams of the semiconductor device provided by the embodiments of the application;

[0037] Figure 4 The fourth of the structure schematic diagrams of the semiconductor device provided by the embodiments of the application;

[0038] Figure 5 The fifth of the structure schematic diagrams of the semiconductor device provided by the embodiments of the application;

[0039] Figure 6 A flow chart of a method for manufacturing a semiconductor device is provided in embodiments of the present application.

[0040] Figure 7 A schematic diagram of a manufacturing process of a semiconductor device is provided in embodiments of the present application.

[0041] Figure 8 A schematic diagram of another manufacturing process of a semiconductor device is provided in embodiments of the present application. DETAILED DESCRIPTION

[0042] In order to make the above objectives, features and advantages of the present application more apparent, further description will be made to the present application with reference to the accompanying drawings and embodiments. However, the example embodiments can be implemented in various forms, and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to fully convey the ideas of the example embodiments to those skilled in the art. The same reference signs in the drawings represent the same or similar structures, and thus repeated description thereof will be omitted. The expressions of position and direction described in the present application are described with reference to the drawings, but can be changed as needed, and the changes made are included in the protection scope of the present application. The drawings of the present application are only used to illustrate the relative positional relationship and do not represent the true proportions.

[0043] The third generation semiconductor material has good properties such as wide band gap, high critical breakdown field, high electron saturation velocity, and strong radiation resistance, and is widely used in the fields of optoelectronics, radio frequency and power electronics, and is the most optimal material system for preparing high-power radio frequency electronic devices and high-efficiency power electronic devices. With the development of semiconductor devices in the field of low-voltage logic control, higher demands are put forward for low-voltage semiconductor devices with small size and high current density.

[0044] In the traditional semiconductor manufacturing process, the preparation of the source and the drain needs to be aligned with the gate through a photolithography process. However, the process of photolithographic alignment can produce errors, and a certain tolerance space must be reserved, so that the size of the semiconductor device is larger, and thus the current density is lower.

[0045] The self-alignment technology uses the gate itself as a mask to define the source and the drain, thereby avoiding alignment errors and reducing the size of the device. However, the semiconductor device prepared by the current self-alignment technology has the problem of a large area of the drift region, thereby limiting the improvement of the current density of the semiconductor device.

[0046] Therefore, embodiments of the present application provide a semiconductor device which can effectively reduce the area of the drift region and improve the current density of the semiconductor device.

[0047] Figure 1 Figure 1 shows a structure of a semiconductor device according to an embodiment of the present application.

[0048] As shown in Figure 1, the semiconductor device according to an embodiment of the present application comprises a substrate 1, a buffer layer 2, a barrier layer 3, a gate cap layer 4, a dielectric layer 5, a source 61 and a drain 62. Figure 1

[0049] The substrate 1 is located at the bottom layer of the semiconductor device, and is used to support the functional film layers thereon and provide a lattice template for epitaxial growth. The material of the substrate 1 can be silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium nitride (GaN), etc.

[0050] The buffer layer 2 is located on the substrate 1. The buffer layer 2 is used to reduce the lattice mismatch between the epitaxial layer and the substrate 1, and to block the upward diffusion of impurities in the substrate 1, thereby avoiding the degradation of the performance of the semiconductor device. The buffer layer 2 comprises a plurality of sub-film layers which are sequentially stacked on the substrate 1, as shown in Figure 2. The sub-film layers of the buffer layer 2 are not limited in number. Figure 2 As shown in Figure 2, the sub-film layer on the side of the buffer layer 2 away from the substrate 1 is a channel layer 21. The channel layer 21 is the core region for carrier transport, and is usually a high-mobility material such as intrinsic semiconductor material. The material of the buffer layer 2 can be gallium nitride (GaN), gallium arsenide (GaAs), etc. The overall thickness of the buffer layer 2 ranges from 100 nm to 1 μm.

[0051] The barrier layer 3 is located on the buffer layer 2. The barrier layer 3 has a larger band gap than the buffer layer 2, and forms a heterostructure with the buffer layer 2 to induce the generation of two-dimensional electron gas (2DEG) on the upper surface of the side of the buffer layer 2 away from the substrate 1. The material of the barrier layer 3 can be aluminum gallium nitride (AlGaN), and the thickness of the barrier layer 3 ranges from 1 nm to 25 nm.

[0052] The gate cap layer 4 is located on part of the barrier layer 3. The gate cap layer 4 comprises a p-type semiconductor layer 41 on the barrier layer 3 and a gate 42 on the p-type semiconductor layer 41. The p-type semiconductor layer 41 is used to deplete the two-dimensional electron gas in the channel layer 21, so that the device is in an off state and an enhancement-mode device is obtained. The gate 42 is in electrical contact with the p-type semiconductor layer 41, and the gate 42 controls the on-off of the conduction channel between the source 61 and the drain 62 by applying a voltage. The p-type semiconductor layer 41 can be a Mg-doped GaN layer, and the Mg doping concentration ranges from 5 × 10 18 ~10 × 10 19 cm -3 ​The thickness of the p-type semiconductor layer 41 ranges from 10 nm to 200 nm. The material of the gate 42 can be at least one of titanium nitride (TiN), titanium (Ti), nickel (Ni), and gold (Au), for example, the material of the gate 42 can be titanium nitride, nickel / gold alloy, or titanium / gold alloy, etc., which is not specifically limited herein.

[0053] The dielectric layer 5 covers the gate cap layer 4 and the portion of the barrier layer 3 near the gate cap layer 4. The material of the dielectric layer 5 can be silicon oxide, silicon nitride, aluminum oxide, etc. The dielectric layer 5 defines and restricts the range of the drift region. The region of the barrier layer 3 covered by the dielectric layer 5 forms a space for the carrier to drift freely, and the coverage and morphology thereof determine the size of the drift region. The drift region refers to the region in the semiconductor device that allows the carrier (electron or hole) to move freely under the action of the electric field. As shown in FIG. 1, regions L1 and L2 are drift regions, and L3 is a channel region. The drift region is the region of the barrier layer 3 covered by the dielectric layer 5 but not covered by the gate cap layer. Figure 1

[0054] In the embodiments of the present application, the dielectric layer 5 is etched by a sidewall process. The sidewall of the dielectric layer 5 after etching is arc-shaped. The thickness of the region of the barrier layer 3 covered by the dielectric layer 5 is different from the thickness of other regions of the barrier layer 3. The width of the dielectric layer 5 near the barrier layer 3 is greater than the width of the dielectric layer 5 away from the barrier layer 3. Compared with the photolithography process, the thickness of the sidewall of the dielectric layer 5 after etching by the sidewall process is thinner, and the region of the barrier layer 3 covered by the dielectric layer 5 is smaller. Therefore, the semiconductor device has a smaller drift region. Under the same applied voltage, the reduction of the drift region area increases the electric field strength inside the drift region, and reduces the on-resistance. The stronger electric field drives the carrier (electron or hole) to move at a higher average drift speed, and reduces the on-resistance, so that the current passing through per unit area increases, that is, the current density of the semiconductor device increases.

[0055] The source 61 and the drain 62 are located on both sides of the dielectric layer 5. The dielectric layer made by the sidewall process can be automatically aligned and define the regions of the source 61 and the drain 62. The thickness of the sidewall of the dielectric layer 5 after etching by the sidewall process is thinner, which reduces the distance between the source 61 and the drain 62. The source 61 and the drain 62 can form ohmic contact with the 2DEG. The source 61 serves as the supply end of the carrier and can provide electrons or holes as carriers. The drain 62 serves as the collection end of the carrier and is responsible for receiving the carrier transmitted through the drift region, thereby forming a current path in the semiconductor device. The material of the source 61 and the drain 62 can include at least one of titanium, aluminum, gold, nickel, and titanium nitride, for example, the material of the source 61 and the drain 62 can be titanium / aluminum / gold alloy, titanium / aluminum / nickel / gold alloy, or titanium nitride / titanium / aluminum alloy, etc., which is not specifically limited herein.

[0056] ​In the embodiments of the present application, the medium layer 5 is made by using a sidewall process. The width of the medium layer 5 along the first direction X after etching can be reduced to 50-200 nm. Figure 1 As shown in FIG. 6, the first direction X is the direction in which the source electrode 61 points to the drain electrode 62. After the medium layer 5 is etched by using the sidewall process, the thickness of the sidewall of the medium layer 5 is thinner, so that the width of the drift region along the first direction X is also reduced. When the applied voltage is the same, the smaller the area of the drift region is, the smaller the specific on-resistance will be. The reduction of the specific on-resistance reduces the resistance of the carrier transmission, and generates a greater driving force for the carrier, so that the movement speed of the carrier in the drift region is accelerated, and more carriers can pass through the drift region from the source electrode 61 to the drain electrode 62 per unit time. The increase of the movement speed of the carrier increases the amount of electric charge per unit area per unit time, thereby increasing the current density of the semiconductor device.

[0057] In the embodiments of the present application, the whole medium layer covering the gate cap layer 4 and the barrier layer 3 is first formed by a deposition process, and then etched by using a sidewall process. The sidewall process has anisotropy, and the etching rate along the vertical direction is faster, so that the medium layer in the horizontal direction can be quickly removed. Due to the height difference between the gate cap layer 4 and the barrier layer, the medium layer covering the gate cap layer 4 can be retained more. After the medium layer 5 is etched by using the sidewall process, the sidewall is arc-shaped, and the width of the sidewall close to the barrier layer 3 is greater than that of the sidewall away from the barrier layer 3. The greater the thickness of the gate cap layer 4 is, the more the medium layer 5 retained at the sidewall is, and the thicker the thickness of the sidewall of the medium layer 5 after etching by using the sidewall process is. Therefore, the width of the medium layer 5 along the first direction X on the barrier layer 3 increases with the increase of the thickness of the gate cap layer.

[0058] In some embodiments, as shown in FIG. 8, the thickness of the barrier layer 3 in the region covered by the medium layer 5 is greater than that of the other regions of the barrier layer 3, so that the contact resistance between the source electrode 61 or the drain electrode 62 and the channel layer 21 is reduced, thereby forming a better ohmic contact between the source electrode 61, the drain electrode 62 and the channel layer 21. Figure 2 In some embodiments, as shown in FIG. 9, the thickness of the barrier layer 3 in the region covered by the source electrode 61 and the drain electrode 62 is 0, so that the source electrode 61 or the drain electrode 62 directly contacts the channel layer 21, the contact resistance between the source electrode 61 or the drain electrode 62 and the channel layer 21 is reduced, thereby forming a better ohmic contact between the source electrode 61, the drain electrode 62 and the channel layer 21.

[0059] Figure 3 In some embodiments, as shown in FIG. 10, the thickness of the barrier layer 3 in the region covered by the source electrode 61 and the drain electrode 62 is 0, so that the source electrode 61 or the drain electrode 62 directly contacts the channel layer 21, the contact resistance between the source electrode 61 or the drain electrode 62 and the channel layer 21 is reduced, thereby forming a better ohmic contact between the source electrode 61, the drain electrode 62 and the channel layer 21.

[0060] In some embodiments, as shown in FIG. 11, the thickness of the barrier layer 3 in the region covered by the source electrode 61 and the drain electrode 62 is 0, so that the source electrode 61 or the drain electrode 62 directly contacts the channel layer 21, the contact resistance between the source electrode 61 or the drain electrode 62 and the channel layer 21 is reduced, thereby forming a better ohmic contact between the source electrode 61, the drain electrode 62 and the channel layer 21. Figure 4 ​As shown, the semiconductor device further comprises an n-type semiconductor layer 7 on the barrier layer 3 on both sides of the dielectric layer 5, and a source electrode 61 and a drain electrode 62 on the n-type semiconductor layer 7. The n-type semiconductor layer 7 is used to further reduce the contact resistance between the source electrode 61, the drain electrode 62 and the underlying barrier layer 3 structure by providing a high concentration of electron carriers. The n-type semiconductor layer 7 is a Si heavily doped n-type GaN layer, which has a higher electron concentration than a normal n-type GaN, and thus can promote the transmission of carriers, reduce the energy loss of carrier transmission, reduce the contact resistance, and thus improve the current density of the semiconductor device.

[0061] In some embodiments, as shown in Figure 5 As shown, the semiconductor device further comprises a first interlayer 8 and / or a second interlayer 9. The first interlayer 8 is located between the substrate 1 and the buffer layer 2, and is used to achieve lattice matching. The material of the first interlayer 8 can be aluminum nitride (AlN), an aluminum gallium nitride / aluminum nitride (AlGaN / AlN) superlattice, an aluminum nitride / gallium nitride (AlN / GaN) superlattice, etc. The second interlayer 9 is located between the buffer layer 2 and the barrier layer 3, and is used to improve the performance of the two-dimensional electron gas. The thickness of the second interlayer 9 ranges from 1 nm to 3 nm, and the material of the second interlayer 9 can be aluminum nitride (AlN), indium aluminum nitride (InAlN), a gallium nitride / aluminum nitride (GaN / AlN) superlattice, etc.

[0062] Based on the same inventive concept, the embodiments of the present application also provide a method for manufacturing a semiconductor device, as shown in Figure 6 As shown, the method comprises the following steps:

[0063] S601, sequentially forming a buffer layer, a barrier layer and a p-type semiconductor layer on a substrate;

[0064] S602, sequentially forming a gate metal layer and a first dielectric layer on the p-type semiconductor layer;

[0065] S603, etching the first dielectric layer to define a gate region;

[0066] S604, etching the gate metal layer and the p-type semiconductor layer outside the gate region to expose the barrier layer, and forming a gate cap layer;

[0067] S605, forming a second dielectric layer on the gate cap layer and the exposed barrier layer;

[0068] S606, etching the second dielectric layer by a sidewall process to expose the barrier layer or the buffer layer; the etched second dielectric layer covers the gate cap layer and part of the barrier layer near the gate cap layer, the sidewall of the etched second dielectric layer is arc-shaped, and the width of the sidewall near the barrier layer is greater than the width of the sidewall far from the barrier layer;

[0069] S607, forming a source electrode and a drain electrode on the exposed barrier layer or buffer layer on both sides of the etched second dielectric layer.

[0070] The embodiment of the present application adopts a sidewall process to etch the second dielectric layer. Compared with a photolithography process, the sidewall process makes the second dielectric layer covering the sidewall of the gate cap layer thinner after etching, the orthographic projection of the second dielectric layer on the barrier layer is smaller in the direction from the source electrode to the drain electrode, and the area of the barrier layer covered by the second dielectric layer is smaller, so that the semiconductor device has a smaller drift region. Therefore, the specific on-resistance of the semiconductor device can be reduced, and the current density of the semiconductor device can be improved.

[0071] Specifically, in step S601, as shown in (a) of FIG. 1, a buffer layer 2, a barrier layer 3 and a p-type semiconductor layer 41 can be sequentially formed on a substrate 1 by epitaxy technology. Figure 7

[0072] The material of the substrate 1 can be Si, SiC, Al2O3, GaN, etc. The material of the buffer layer 2 can be GaN, GaAs, etc. The overall thickness of the buffer layer 2 is 100 nm to 1 μm. The material of the barrier layer 3 can be AlGaN, and the thickness of the barrier layer 3 is 1 nm to 25 nm. The p-type semiconductor layer 41 can be a Mg-doped GaN layer, and the Mg doping concentration is 5×10 18 ~10×10 19 cm -3 The thickness of the p-type semiconductor layer 41 is 10 nm to 200 nm.

[0073] In step S602, as shown in (b) of FIG. 1, a deposition process is adopted to sequentially form a gate metal layer 42 and a first dielectric layer 51 on the p-type semiconductor layer 41. Figure 7

[0074] The material of the gate metal layer 42 can be at least one of titanium nitride (TiN), titanium (Ti), nickel (Ni) and gold (Au). The material of the first dielectric layer 51 can be silicon oxide, silicon nitride, aluminum oxide, etc.

[0075] In step S603, the first dielectric layer 51 is etched, and the specific process of defining the gate region is as follows: a photoresist is formed on the surface of the first dielectric layer 51, and the photoresist is patterned, the first dielectric layer 51 exposed by the photoresist is etched, the pattern of the photoresist is transferred to the first dielectric layer 51, and the remaining first dielectric layer is defined as the gate region.

[0076] In step S604, as shown in (c) of FIG. 1, a deposition process is adopted to form a second dielectric layer 61 on the gate region and the exposed barrier layer 3. Figure 7 ​​As shown in (c), the gate metal layer 42 and the p-type semiconductor layer 41 outside the gate region are etched to expose the barrier layer 3, forming the gate cap layer 4. Specifically, dry etching technology can be used to etch the gate metal layer 42 and the p-type semiconductor layer 41 outside the gate region.

[0077] In step S605, as Figure 7 As shown in (d), a second dielectric layer 52 is formed on the gate cap layer 4 and the exposed barrier layer. Specifically, the entire second dielectric layer 52 covering the gate cap layer 4 and the barrier layer 3 can be formed by methods such as chemical vapor deposition (CVD).

[0078] In step S606, as Figure 7 As shown in (e), the second dielectric layer 52 is etched using a sidewall process to expose the barrier layer 3 or the buffer layer 2. The etched second dielectric layer 52 covers the gate cap layer 4 and part of the barrier layer 3 near the gate cap layer 4. The sidewall of the etched second dielectric layer 52 is arc-shaped, and the width on the side closer to the barrier layer 3 is greater than the width on the side farther from the barrier layer 3.

[0079] Sidewall etching is an anisotropic etching technique used in semiconductor fabrication. It features a faster etching rate along the vertical direction, allowing for rapid removal of the horizontal second dielectric layer. Because the sidewalls of the gate cap layer 4 provide physical protection for the second dielectric layer attached to its surface, more of the second dielectric layer at the sidewalls of the gate cap layer 4 is preserved. After sidewall etching, the second dielectric layer 52 has an arc-shaped sidewall, with a wider width near the barrier layer 3 than the side farther from it. Compared to photolithography, the second dielectric layer 52 etched using sidewall etching has a thinner sidewall covering the gate cap layer 4, and the area covered by the barrier layer 3 is smaller. Therefore, the semiconductor device has a smaller drift region.

[0080] In step S606, the second dielectric layer is etched using a sidewall process, specifically including: etching the second dielectric layer 52 using a halogen gas and / or a halogen compound gas, and removing part or all of the barrier layer 3. For example, a mixed gas of chlorine and boron trichloride can be used to etch the second dielectric layer and the barrier layer. After part or all of the barrier layer 3 is etched by the gas, the contact resistance between the source 61 or drain 62 and the buffer layer 2 is reduced, thereby forming a better ohmic contact between the source 61, drain 62, and buffer layer 2.

[0081] In the dry etching process, the etching gas mainly includes halogen elements and their compounds. According to the type of the material to be etched, the gas combination containing fluorine, chlorine, bromine and other elements is selected, such as fluorides (SF6, NF3), chlorides (Cl2) and halogenated methane (CHF3, CClF3) and the like. In the process of semiconductor manufacturing, plasma etching technology and gas cluster ion beam etching technology are mainly used to realize precise etching. The plasma etching technology excites the gas into high-activity plasma through inductively coupled or capacitively coupled plasma source. Active ions and material surfaces undergo physical bombardment and chemical reaction, thereby realizing anisotropic high-precision etching. The gas cluster ion beam etching technology forms clusters by high-pressure gas, and impacts the material surface to realize nanoscale etching.

[0082] In step S607, as shown in (f) of Figure 7 Specifically, the metal stack of the source 61 and the drain 62 can be formed by a sputtering process, and then the metal layer outside the source 61 and the drain 62 region is removed by etching technology, and a metal post-annealing process is performed in a N2 atmosphere.

[0083] After etching the second dielectric layer 52 by the sidewall process, the source 61 and the drain 62 regions of the device are defined automatically and accurately without additional photolithography steps, which simplifies the manufacturing process and improves the manufacturing efficiency of the semiconductor device.

[0084] In some embodiments, as shown in (f) of Figure 8 After etching the second dielectric layer by the sidewall process in step S606, the manufacturing method further includes: forming an n-type semiconductor layer 7 on the barrier layer 3 or the buffer layer 2 exposed on both sides of the etched second dielectric layer 52 before forming the source and the drain in step S607.

[0085] Specifically, the n-type semiconductor layer 7 is an n-type heavily doped Si GaN layer, and its electron concentration is greater than that of ordinary n-type GaN. Therefore, the n-type semiconductor layer 7 can promote the transmission of carriers, reduce the energy loss of carrier transmission, and reduce the contact resistance, thereby improving the current density of the semiconductor device.

[0086] In the semiconductor device provided by the embodiment of the present application, the sidewall of the medium layer 5 is arc-shaped by etching the medium layer 5 through the sidewall process, the thickness of the covered area of the barrier layer 3 by the medium layer 5 is different from the thickness of other areas of the barrier layer 3, and the width of the medium layer 5 close to the barrier layer 3 is greater than the width of the medium layer 5 far from the barrier layer 3. The thickness of the sidewall of the medium layer 5 after etching through the sidewall process is thinner, the area of the barrier layer 3 covered by the medium layer 5 is smaller, and thus the area of the drift region of the semiconductor device is smaller, thereby reducing the specific on-resistance of the semiconductor device and improving the output current density of the semiconductor device.

[0087] Although preferred embodiments of the present application have been described, those skilled in the art who understand the inventive concept after having been given the benefit of the present disclosure can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to cover all such changes and modifications that fall within the scope of the present application.

[0088] Obviously, various modifications and changes can be made to the present application without departing from the spirit and scope of the present application. Accordingly, it is intended that the present application embrace all such modifications and changes as fall within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized by, The application relates to a semiconductor device, comprising: a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer; a gate cap layer on part of the barrier layer; the gate cap layer comprises a p-type semiconductor layer on the barrier layer and a gate on the p-type semiconductor layer; a dielectric layer covering the gate cap layer and part of the barrier layer; the thickness of the part of the barrier layer covered by the dielectric layer is greater than the thickness of other parts of the barrier layer; the width of the dielectric layer near the barrier layer is greater than the width of the dielectric layer far from the barrier layer; a source and a drain on both sides of the dielectric layer. The orthogonal projection of the dielectric layer on the barrier layer has a width of 50-200 nm in a first direction; the first direction is the direction in which the source points to the drain. The sidewall of the dielectric layer is arc-shaped. The application further relates to a semiconductor device, comprising: an n-type semiconductor layer on the barrier layer on both sides of the dielectric layer; the source and the drain are on the n-type semiconductor layer. The materials of the buffer layer, the barrier layer and the p-type semiconductor layer are gallium nitride or gallium arsenide. The application further relates to a semiconductor device, comprising: a first insertion layer between the substrate and the buffer layer; and / or a second insertion layer between the buffer layer and the barrier layer. The application relates to a semiconductor device, comprising: sequentially forming a buffer layer, a barrier layer and a p-type semiconductor layer on a substrate; sequentially forming a gate metal layer and a first dielectric layer on the p-type semiconductor layer; etching the first dielectric layer to define a gate region; etching the gate metal layer and the p-type semiconductor layer outside the gate region to expose the barrier layer and form a gate cap layer; forming a second dielectric layer on the gate cap layer and the exposed barrier layer; etching the second dielectric layer by a sidewall process to expose the barrier layer or the buffer layer; the etched second dielectric layer covers the gate cap layer and part of the barrier layer near the gate cap layer, and the width of the etched second dielectric layer near the barrier layer is greater than the width of the etched second dielectric layer far from the barrier layer; the thickness of the part of the barrier layer covered by the second dielectric layer is greater than the thickness of other parts of the barrier layer; and forming a source and a drain on the exposed barrier layer or buffer layer on both sides of the etched second dielectric layer. The etching of the second dielectric layer by the sidewall process specifically comprises: etching the second dielectric layer by a halogen gas and / or a halogen compound gas, and removing part or all of the barrier layer.

2. The semiconductor device of claim 1, wherein, After the etching of the second dielectric layer by the sidewall process, before the formation of the source and the drain, the application further comprises: forming an n-type semiconductor layer on the exposed barrier layer or buffer layer on both sides of the etched second dielectric layer.

3. The semiconductor device of claim 1, wherein, ​ 4. The semiconductor device according to any one of Claims 1 to 3, wherein ​ ​ 5. The semiconductor device according to any one of Claims 1 to 3, wherein ​ 6. The semiconductor device according to any one of Claims 1 to 3, wherein ​ ​ ​ ​ 7. A method of manufacturing a semiconductor device, characterized by ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 8. The manufacturing method as described in claim 7, characterized in that, ​ ​ 9. The manufacturing method as described in claim 7, characterized in that, ​ ​

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