Method for selectively growing carbon-germanium-silicon-doped inner base region of heterojunction transistor

Abstract

The invention discloses a method for selectively growing a carbon-germanium-silicon-doped inner base region of a heterojunction transistor. The method comprises the following steps: sequentially depositing a first dielectric layer, an outer base region layer and a second dielectric layer on a silicon substrate; etching the second dielectric layer and the outer base region polycrystalline silicon layer downwards to form an inner base region window; forming a third dielectric layer on the inner side wall of the inner base region window; etching the first dielectric layer at the bottom of the inner base region window to obtain an inner base region growth window; and selectively growing a buffer layer, an inner base region layer and a cap layer in the inner base region growth window in sequence. According to the invention, the carbon-doped germanium silicon is selectively grown based on a self-alignment mode, so that the inner base region is formed through epitaxy, the smaller area of the inner base region can be realized, the connection between the inner base region and the outer base region is more stable, the frequency characteristic and the stability of the carbon-doped germanium silicon heterojunction transistor are further improved, and the application technical field with higher requirements is met; and the electrical performance of the chip is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, and in particular relates to a method for selectively growing carbon-doped germanium-silicon inner base regions of heterojunction transistors. Background Technology

[0002] SiGe bipolar and SiGe BiCMOS processes replace the silicon-doped base region with Ge-Si material by introducing SiGe heterojunction technology. 1-X Ge X This process involves forming a SiGe heterojunction bipolar transistor (SiGe HBT). Further, the SiGe inner base region is doped with a specific amount of carbon (C) to suppress boron (B) impurities. Compared to conventional silicon-based bipolar and BiCMOS processes, this technique using SiGe:C as the inner base region of a heterojunction transistor significantly improves the high-frequency and noise characteristics of the bipolar transistor, making it widely applicable in high-speed and low-noise applications such as high-speed amplifiers, RF amplifiers, logarithmic amplifiers, and low-noise amplifiers. The high mobility and low noise characteristics of the SiGe:C epitaxial base region are key technologies for SiGe bipolar and SiGe BiCMOS processes. While selective SiGe:C epitaxial growth is more challenging than non-selective growth, its unique self-aligned growth method can reduce device size, lower contact resistance between the inner and outer base regions, and reduce parasitic junction capacitance, thereby further optimizing and improving device performance. Therefore, it is necessary to develop a selective growth method for the inner base region of SiGe:C heterojunction transistors to improve the frequency characteristics of SiGe heterojunction bipolar transistors. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0005] A method for selectively growing carbon-doped germanium-silicon inner base regions in heterojunction transistors includes the following steps:

[0006] S100. Take a silicon substrate, wherein at least two field oxygen isolation regions are formed between the internal spaces of the silicon substrate;

[0007] S200, A first dielectric layer, an outer base region layer, and a second dielectric layer are sequentially deposited on the silicon substrate; the material of the outer base region layer is highly doped polycrystalline silicon.

[0008] S300, etch the second dielectric layer and the outer base region polysilicon layer downwards to form an inner base region window; the inner base region window is located in the region between two adjacent field oxygen isolation regions;

[0009] S400, A third dielectric layer is formed on the inner sidewall of the window in the inner base region;

[0010] S500. The first dielectric layer at the bottom of the inner base region window is etched by a wet etching process to obtain the inner base region growth window; the two ends of the inner base region growth window extend outward to below the outer base region polysilicon layer.

[0011] S600. Selectively grow a buffer layer, an inner base layer, and a capping layer sequentially in the growth window of the inner base region. The buffer layer and the capping layer are made of silicon, and the inner base layer is made of carbon-doped germanium silicon.

[0012] Furthermore, the first dielectric layer is made of silicon oxide, the second dielectric layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, and the third dielectric layer is made of silicon nitride.

[0013] Furthermore, in step S400, the method for forming a third dielectric layer on the inner sidewall of the inner base region window is to first deposit a third dielectric layer as a whole; then etch away the third dielectric layer at the bottom of the inner base region window and the third dielectric layer outside the inner base region window, while retaining the third dielectric layer on the inner sidewall of the inner base region window.

[0014] Furthermore, in step S500, the silicon substrate is annealed in a furnace tube at 800°C to 900°C before wet etching, thereby densifying the first dielectric layer.

[0015] Furthermore, in step S500, wet etching is performed using an HF solution with a ratio of 7:1 to 50:1.

[0016] Furthermore, the deposition thickness of the first dielectric layer is 150nm to 300nm; the growth thickness of the buffer layer is 20nm to 40nm; the growth thickness of the inner base region layer is 60nm to 120nm; and the growth thickness of the capping layer is 40nm to 80nm.

[0017] Furthermore, step S500 includes the following sub-steps:

[0018] S510. Place the silicon substrate with the inner base region growth window formed in the epitaxial equipment, form a vacuum environment and remove the native oxide layer of the inner base region growth window;

[0019] S520. A gaseous Si source is introduced into the epitaxial device, and a Si layer is selectively grown at the bottom of the growth window in the inner base region to form a buffer layer.

[0020] S530. In the epitaxial equipment, a gaseous Si source and a gaseous Ge source are introduced to selectively grow a germanium-silicon layer on the buffer layer, and a gaseous C source is introduced to dope the germanium-silicon layer with C components to form a carbon-doped germanium-silicon layer as the inner base region layer.

[0021] S540. A gaseous Si source is introduced into the epitaxial device, and a Si layer is selectively grown on the inner base region layer to form a capping layer, thereby forming the inner base region.

[0022] Furthermore, in step S520, at a growth temperature of 850°C to 900°C, SiH2Cl2 gas is used as a Si source to grow the buffer layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

[0023] Furthermore, in step S530, at a growth temperature of 750°C to 800°C, SiH2Cl2 gas and GeH4 gas are used as Si source and Ge source, respectively, to grow the germanium-silicon layer, and CH3SiH3 gas at a flow rate of 50 sccm to 100 sccm is used as C source for C component doping during the growth of the germanium-silicon layer; during the growth process, HCl gas at a flow rate of 120 sccm to 240 sccm is also used to suppress Si nucleation in the second dielectric layer and the third dielectric layer.

[0024] Furthermore, in step S540, at a growth temperature of 850°C to 900°C, SiH2Cl2 gas is used as the Si source to grow the capping layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

[0025] In this invention, by setting reasonable process conditions for different carbon-doped germanium-silicon epitaxial layers, selective growth of carbon-doped germanium-silicon epitaxial layers on silicon and polycrystalline silicon layers is achieved in a specific window structure of the carbon-doped germanium-silicon heterojunction transistor, thereby realizing the self-aligned fabrication of the carbon-doped germanium-silicon inner base region. The selective growth of the carbon-doped germanium-silicon inner base region of the heterojunction bipolar transistor is achieved through the introduction of C impurities in the SiGe epitaxial layer. Besides the advantages of lower parasitic resistance and capacitance in the selective SiGe inner base region and better and more stable connection between the inner and outer base regions, the introduction of carbon impurities also suppresses the diffusion of boron impurities in the SiGe inner base region, further improving the characteristic frequency of the SiGe heterojunction bipolar transistor. This can meet the requirements of higher and wider applications in high-speed technology fields, improving the electrical performance of the chip. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This is a flowchart of an embodiment of the method for selectively growing the inner base region of a germanium-silicon heterojunction transistor according to the present invention.

[0028] Figure 2 This is a schematic diagram of the structure on a silicon substrate.

[0029] Figure 3 This is a schematic diagram of the structure after forming a first dielectric layer, an outer base region polycrystalline silicon layer, and a second dielectric layer on a silicon substrate.

[0030] Figure 4 This is a schematic diagram of the structure after the inner base region window is formed.

[0031] Figure 5 This is a schematic diagram of the structure after the fourth dielectric layer is formed.

[0032] Figure 6 This is a schematic diagram of the structure after the growth window of the inner base region has been formed.

[0033] Figure 7 This is a schematic diagram of the structure after the buffer layer is formed.

[0034] Figure 8 This is a schematic diagram of the structure after the formation of the inner base layer.

[0035] Figure 9 This is a schematic diagram of the structure after the cap layer is formed.

[0036] The diagrams in the instruction manual are labeled as follows:

[0037] Silicon substrate-1; field oxygen isolation region-2; first dielectric layer-3; outer base region layer-4; second dielectric layer-5; third dielectric layer-6; buffer layer-7; inner base region layer-8; capping layer-9; inner base region window-11; inner base region growth window-12. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0039] like Figure 1 As shown, this invention discloses an embodiment of a method for selectively growing a carbon-doped germanium-silicon inner base region in a heterojunction transistor. The method for selectively growing a carbon-doped germanium-silicon inner base region in this embodiment includes the following steps:

[0040] S100, such as Figure 2 As shown, a silicon substrate 1 is provided, and at least two field oxygen isolation regions 2 are formed in the interior of the silicon substrate 1.

[0041] S200, such as Figure 3 As shown, a first dielectric layer 3, an outer base layer 4, and a second dielectric layer 5 are sequentially deposited on the silicon substrate 1. The outer base layer 4 is made of highly doped polycrystalline silicon. The first dielectric layer 3 and the second dielectric layer 5 are not limited in material or growth method, as long as the process of this embodiment can be implemented. For example, the first dielectric layer 3 can be made of silicon oxide, and the second dielectric layer 5 can be made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. This step may include the following sub-steps:

[0042] S210. A first dielectric layer 3 is formed on the silicon substrate 1 by depositing silicon oxide, wherein the deposition thickness of the first dielectric layer 3 is preferably 150 nm to 300 nm.

[0043] S220. An outer base region layer 4 is formed on the first dielectric layer 3 by depositing polysilicon. The outer base region layer 4 is used to form the outer base region of a transistor device. The outer base region layer 4 can be formed by in-situ doping of polysilicon, or by depositing polysilicon in a conventional manner followed by impurity implantation and annealing. Using highly doped polysilicon in the outer base region layer 4 can reduce the resistance of the outer base region.

[0044] S230, A second dielectric layer 5 is formed on the outer base layer 4 by depositing silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

[0045] S300, such as Figure 4 As shown, the second dielectric layer 5 and the outer base region layer 4 are etched downwards to form an inner base region window 11. The inner base region window 11 is located in the region between two adjacent field oxygen isolation regions 2. The inner base region window 11 can be formed by etching using processes such as photolithography. The specific process is a conventional technique and will not be described in detail here.

[0046] S400, such as Figure 5 As shown, a third dielectric layer 6 is formed on the inner sidewall of the inner base region window 11. The third dielectric layer 6 is not limited to any particular material or growth method, as long as the process of this embodiment can be implemented. For example, the third dielectric layer 6 can be made of silicon nitride. In this embodiment, the method for forming the third dielectric layer 6 on the inner sidewall of the inner base region window 11 is as follows: first, a silicon nitride layer (i.e., the third dielectric layer 6) is deposited as a whole; then, the silicon nitride layer at the bottom of the inner base region window 11 is etched away, leaving the silicon nitride layer on the inner sidewall of the inner base region window 11 to form the third dielectric layer 6. In this step, the silicon nitride layer deposited outside the inner base region window 11 is generally also removed simultaneously.

[0047] The silicon nitride layer at the bottom of the inner base region window 11 can be removed by anisotropic etching back. This removes the silicon nitride layer at the bottom of the inner base region window 11 while retaining the silicon nitride layer on the sidewall of the inner base region window 11, thus forming a third dielectric layer 6 on the sidewall of the inner base region window 11. The third dielectric layer 6 prevents damage to the second dielectric layer 5 outside the inner base region window 11 during subsequent wet etching, and prevents the sidewall of the outer base region layer 4 from being selectively grown during the growth of the buffer layer 7, inner base region layer 8, and capping layer 9 in the inner base region growth window 12, which could damage the window morphology and affect subsequent processes.

[0048] S500, such as Figure 6 As shown, the first dielectric layer 3 at the bottom of the inner base region window 11 is etched using a wet etching process to expose a flat silicon substrate 1 surface, resulting in an ideal inner base region growth window 12 for the self-aligned selective growth of carbon-doped germanium silicon (i.e., SiGe:C). In this embodiment, the two ends of the inner base region growth window 12 are inclined, thus giving the inner base region growth window 12 a structure that is wider at the top and narrower at the bottom.

[0049] The solution used in the wet etching process can be an HF solution with a ratio of 7:1 to 50:1. The inner base region growth window 12 extends outward at both ends to below the outer base region layer 4, thereby exposing the lower surface of the outer base region layer 4 near the inner base region window 11 to facilitate the connection between the inner base region and the outer base region.

[0050] In this step, the silicon substrate 1 can be annealed in a furnace tube at 800℃~900℃ to densify the first dielectric layer 3, thereby improving the density of the first dielectric layer 3 and preventing the etching rate of the first dielectric layer 3 from being too fast and unstable during the subsequent wet etching of the third dielectric layer 6 in the inner base region window 11, which would cause abnormal morphology at the end of the inner base region growth window 12; and can also improve the flatness of the silicon substrate 1 at the bottom of the inner base region window 11.

[0051] S600, Selectively grow a buffer layer 7, an inner base layer 8, and a capping layer 9 sequentially in the inner base region growth window 12. The buffer layer and capping layer are made of silicon, and the inner base region layer is made of carbon-doped germanium silicon. This step may include the following sub-steps:

[0052] S610. The silicon substrate 1 after forming the inner base region growth window 12 is placed in an epitaxial device to form a vacuum environment and remove the native oxide layer of the inner base region growth window 12. In this embodiment, H2 gas is used to rapidly bake the inner base region growth window 12 at 850°C to 950°C to remove the native oxide layer of the inner base region growth window 12.

[0053] S620, such as Figure 7As shown, a gaseous Si source is introduced into the epitaxial device, and a Si layer is selectively grown at the bottom of the growth window 12 in the inner base region to form a buffer layer 7; the growth thickness of the buffer layer 7 is preferably 20 nm to 40 nm. In this embodiment, SiH2Cl2 gas is used as the Si source to grow the buffer layer 7, so as to achieve stable growth of the buffer layer 7 inside the growth window 12 in the inner base region; and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second dielectric layer 5 and the third dielectric layer 6. The growth temperature of 850℃ to 900℃ used in this step can achieve stable growth of the buffer layer 7 at the end of the growth window 12 in the inner base region.

[0054] S630, such as Figure 8 As shown, a gaseous Si source and a gaseous Ge source are introduced into the epitaxial device to selectively grow a germanium-silicon layer on the buffer layer 7. A gaseous C source is then introduced to dope the germanium-silicon layer with C components, forming a carbon-doped germanium-silicon layer as the inner base region layer 8. The growth thickness of the inner base region layer 8 is preferably 60 nm to 120 nm. Since the thickness of the first dielectric layer 3 will decrease after densification by annealing, the buffer layer 7, the inner base region layer 8, and the capping layer 9 will fill the inner base region growth window 12.

[0055] In this embodiment, SiH2Cl2 gas and GeH4 gas are used as Si and Ge sources, respectively, for the growth of the germanium-silicon layer, and CH3SiH3 gas at a flow rate of 50 sccm to 100 sccm is used as the C source for C component doping during the growth of the germanium-silicon layer. During the growth process, HCl gas at a flow rate of 120 sccm to 240 sccm is also used to suppress Si nucleation in the second dielectric layer 5 and the third dielectric layer 6. The growth temperature of 750℃ to 800℃ used in this step ensures stable growth of the inner base layer 8 at the end of the inner base region growth window 12.

[0056] S640, such as Figure 9 As shown, a gaseous Si source is introduced into the epitaxial device to selectively grow a Si layer on the inner base region layer 8 to form a capping layer 9, thereby forming the inner base region. The growth thickness of the capping layer 9 is preferably 40 nm to 80 nm. In this embodiment, SiH2Cl2 gas is used as the Si source to grow the capping layer 9, so as to achieve selective growth of the capping layer 9 on the inner base region layer 8; and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second dielectric layer 5 and the third dielectric layer 6. The growth temperature of 850℃ to 900℃ used in this step can achieve stable growth of the capping layer 9 at the end of the growth window 12 in the inner base region.

[0057] The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor in this embodiment has at least the following advantages:

[0058] (1) By introducing the second dielectric layer 5 and the third dielectric layer 6, the polycrystalline silicon of the second dielectric layer 5 and the outer base layer 4 is blocked, thus avoiding the growth of carbon-doped germanium silicon on the sidewall of the outer base layer 4 during selective growth.

[0059] (2) Using an appropriate flow rate of HCl gas, self-aligned selective growth can be achieved in the growth window 12 of the inner base region, thereby further reducing the base region size and lowering the parasitic junction capacitance.

[0060] (3) By using SiH2Cl2 gas, GeH4 gas and CH3SiH3 gas as silicon source, germanium source and carbon source respectively, the buffer layer 7 can be grown at 850℃ to 900℃, the inner base layer 8 at 750℃ to 800℃ and the capping layer 9 at 850℃ to 900℃. This allows for a more ideal growth connection between the high-concentration doped polycrystalline silicon in the outer base layer 4 and the carbon-doped germanium silicon in the inner base region. This can reduce the contact resistance between the outer base region and the inner base region and improve the frequency characteristics of the SiGe HBT device.

[0061] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for selectively growing a carbon-doped germanium-silicon inner base region in a heterojunction transistor, characterized in that, Includes the following steps: S100. Take a silicon substrate, wherein at least two field oxygen isolation regions are formed between the internal spaces of the silicon substrate; S200, A first dielectric layer, an outer base region layer, and a second dielectric layer are sequentially deposited on the silicon substrate; the material of the outer base region layer is highly doped polycrystalline silicon. S300, etch the second dielectric layer and the outer base region polysilicon layer downwards to form an inner base region window; the inner base region window is located in the region between two adjacent field oxygen isolation regions; S400, A third dielectric layer is formed on the inner sidewall of the window in the inner base region; S500. The first dielectric layer at the bottom of the inner base region window is etched by a wet etching process to obtain the inner base region growth window; the two ends of the inner base region growth window extend outward to below the outer base region polysilicon layer. S600. Selectively grow a buffer layer, an inner base layer, and a capping layer sequentially in the growth window of the inner base region. The buffer layer and the capping layer are made of silicon, and the inner base layer is made of carbon-doped germanium silicon.

2. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 1, characterized in that: The first dielectric layer is made of silicon oxide, the second dielectric layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, and the third dielectric layer is made of silicon nitride.

3. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 1, characterized in that: In step S400, the method for forming a third dielectric layer on the inner sidewall of the inner base region window is to first deposit a third dielectric layer as a whole; then etch away the third dielectric layer at the bottom of the inner base region window and the third dielectric layer outside the inner base region window, while retaining the third dielectric layer on the inner sidewall of the inner base region window.

4. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 1, characterized in that: In step S500, the silicon substrate is annealed in a furnace tube at 800°C to 900°C before wet etching, thereby densifying the first dielectric layer.

5. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 1, characterized in that: In step S500, wet etching is performed using an HF solution with a ratio of 7:1 to 50:

1.

6. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 1, characterized in that: The deposition thickness of the first dielectric layer is 150nm to 300nm; the growth thickness of the buffer layer is 20nm to 40nm; the growth thickness of the inner base region layer is 60nm to 120nm; and the growth thickness of the capping layer is 40nm to 80nm.

7. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in any one of claims 1 to 6, characterized in that, The S500 step includes the following sub-steps: S510. Place the silicon substrate with the inner base region growth window formed in the epitaxial equipment, form a vacuum environment and remove the native oxide layer of the inner base region growth window; S520. A gaseous Si source is introduced into the epitaxial device, and a Si layer is selectively grown at the bottom of the growth window in the inner base region to form a buffer layer. S530. In the epitaxial equipment, a gaseous Si source and a gaseous Ge source are introduced to selectively grow a germanium-silicon layer on the buffer layer, and a gaseous C source is introduced to dope the germanium-silicon layer with C components to form a carbon-doped germanium-silicon layer as the inner base region layer. S540. A gaseous Si source is introduced into the epitaxial device, and a Si layer is selectively grown on the inner base region layer to form a capping layer, thereby forming the inner base region.

8. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 7, characterized in that: In step S520, at a growth temperature of 850℃~900℃, SiH2Cl2 gas is used as a Si source to grow a buffer layer, and HCl gas with a flow rate of 80sccm~160sccm is used to suppress Si nucleation in the second and third dielectric layers.

9. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 7, characterized in that: In step S530, at a growth temperature of 750℃ to 800℃, SiH2Cl2 gas and GeH4 gas are used as Si source and Ge source, respectively, to grow the germanium-silicon layer, and CH3SiH3 gas at a flow rate of 50 sccm to 100 sccm is used as C source for C component doping during the growth of the germanium-silicon layer; during the growth process, HCl gas at a flow rate of 120 sccm to 240 sccm is also used to suppress Si nucleation in the second dielectric layer and the third dielectric layer.

10. The method for selectively growing the carbon-doped germanium-silicon inner base region of a heterojunction transistor as described in claim 7, characterized in that: In step S540, at a growth temperature of 850°C to 900°C, SiH2Cl2 gas is used as the Si source to grow the capping layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

Images