Semiconductor structure and manufacturing method thereof
By using atomic layer deposition to form a stacked structure of zirconium oxide and doped layers in a semiconductor structure, the problem of low dielectric constant of silicon oxide layer is solved, and the performance of CMOS transistors is improved, especially carrier mobility and insulation properties.
Patent Information
- Application Number
- CN202511006332.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-12-12
AI Technical Summary
In existing technologies, the low dielectric constant of silicon oxide layers limits the size reduction of CMOS transistors, making it difficult to further improve transistor performance.
A gate dielectric layer is formed on a semiconductor layer using atomic layer deposition. By controlling the molar ratio of oxygen to zirconium in the zirconium oxide layer to be 1.8:1 to 1.95:1, and combining this with the use of doped layers, a stacked structure of multiple zirconium oxide and doped layers is formed.
It improves the electrical properties of the semiconductor structure, reduces the interface state defect density, increases carrier mobility, reduces leakage current, and enhances the insulation properties of the gate dielectric layer.
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Figure CN121126841A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method. Background Technology
[0002] With the continuous development of semiconductor technology, the size of Complementary Metal-Oxide-Semiconductor (CMOS) transistors needs to be continuously reduced to increase the transistor density on the chip. As transistor size needs to shrink, the size of the gate dielectric layer (e.g., silicon oxide layer) in the transistor also needs to be reduced. However, the relatively low dielectric constant of silicon oxide limits its size reduction.
[0003] Therefore, there is an urgent need to improve the material of the gate dielectric layer to improve the performance of transistors. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same.
[0005] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: providing a semiconductor layer; forming a gate dielectric layer on the semiconductor layer using an atomic layer deposition process, the gate dielectric layer comprising a plurality of zirconium oxide layers; the atomic layer deposition process comprising a plurality of first cycle cycles, each first cycle corresponding to the formation of a zirconium oxide layer; the first cycle comprising: introducing a first precursor containing zirconium; performing gas purging using a first cleaning step; introducing a second precursor containing oxygen, the second precursor and the first precursor reacting chemically to generate a zirconium oxide layer; performing gas purging using a second cleaning step; wherein the molar ratio between oxygen and zirconium in the zirconium oxide layer is 1.8:1 to 1.95:1.
[0006] In some embodiments, the duration of the second precursor being introduced in each of the first cycle periods ranges from 10 ms to 100 ms.
[0007] In some embodiments, the duration of the second cleaning step in each of the first cycle periods ranges from 5 seconds to 30 seconds.
[0008] In some embodiments, the gate dielectric layer further includes at least one doped layer; the atomic layer deposition process further includes at least one second cycle, each second cycle corresponding to the formation of a doped layer; the second cycle includes: introducing a third precursor containing a doped element; performing gas purging using a third cleaning step; introducing a fourth precursor containing an oxygen element, wherein the fourth precursor and the third precursor react chemically to generate a doped layer; and performing gas purging using a fourth cleaning step.
[0009] In some embodiments, the doped layer includes at least one of a yttrium oxide layer and a gadolinium oxide layer; the ratio between the number of the second cycle and the sum of the number of the first cycle and the second cycle ranges from 3% to 10%.
[0010] Secondly, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: a semiconductor layer; a gate dielectric layer disposed on the semiconductor layer, the gate dielectric layer comprising a plurality of zirconium oxide layers, wherein the molar ratio between oxygen and zirconium in the zirconium oxide layers ranges from 1.8:1 to 1.95:1.
[0011] In some embodiments, the crystal structure of the zirconium oxide layer is a cubic phase structure.
[0012] In some embodiments, the gate dielectric layer further includes at least one doped layer, the doped layer comprising at least one of a yttrium oxide layer and a gadolinium oxide layer; the ratio between the molar amount of the compound in the doped layer and the molar amount of the compound in the gate dielectric layer ranges from 3 mol% to 10 mol%.
[0013] In some embodiments, the semiconductor structure further includes: a gate electrode layer, wherein the gate dielectric layer is disposed between the semiconductor layer and the gate electrode layer; a source and a drain, wherein the source and the drain are both disposed in the semiconductor layer and respectively disposed on opposite sides of the gate electrode layer.
[0014] In some embodiments, the semiconductor layer includes a silicon layer.
[0015] This disclosure provides a semiconductor structure and a method for manufacturing the same. In this embodiment, the semiconductor structure includes a gate dielectric layer, which comprises multiple zirconium oxide layers. The molar ratio of oxygen to zirconium in the zirconium oxide layers is between 1.8:1 and 1.95:1. By limiting the range of the molar ratio of oxygen to zirconium in the zirconium oxide layers of the gate dielectric layer, the interface state defect density between the semiconductor layer and the zirconium oxide layers can be improved, thereby improving the electrical performance of the semiconductor structure. Attached Figure Description
[0016] Figure 1A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure;
[0017] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to other embodiments of this disclosure;
[0018] Figure 3 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;
[0019] Figure 4 Figure (a) is a schematic diagram of the band structure of the interface between the zirconium oxide layer and the silicon layer in Example 1; Figure (b) is a schematic diagram of the band structure of the interface between the zirconium oxide layer and the silicon layer in Example 2; and Figure (c) is a schematic diagram of the band structure of the interface between the zirconium oxide layer and the silicon layer in Comparative Example 1.
[0020] Figure 5 This is a schematic diagram showing the bandgap properties and bandgap of Examples 1, 2, and 1 Comparative Example;
[0021] Figure 6 Figure (a) shows the atomic structure of the zirconium oxide layer and the silicon layer in Example 1, and Figure (b) shows the difference in three-dimensional charge density between the zirconium oxide layer and the silicon layer in Example 1.
[0022] Figure 7 Figure (a) shows a schematic diagram of the atomic structure of the zirconium oxide layer and the silicon layer in Example 2, and Figure (b) shows a schematic diagram of the difference in three-dimensional charge density between the zirconium oxide layer and the silicon layer in Example 2.
[0023] Figure 8 Figure (a) shows the atomic structure of the zirconium oxide layer and the silicon layer in Comparative Example 1, and Figure (b) shows the difference in three-dimensional charge density between the zirconium oxide layer and the silicon layer in Comparative Example 1.
[0024] Figure 9 Figure (a) is a schematic diagram of the Baad charge in Example 1, Figure (b) is a schematic diagram of the Baad charge in Example 2, and Figure (c) is a schematic diagram of the Baad charge in Comparative Example 1.
[0025] Figure 10 This is a schematic diagram of the valence band offset and conduction band offset in Example 1, Example 2 and Comparative Example 1. Detailed Implementation
[0026] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0028] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0032] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.
[0033] Zirconia has a higher dielectric constant than silicon oxide, and using zirconia as the gate dielectric layer in transistors helps to reduce transistor size while maintaining low leakage current. However, the performance of transistors using zirconia as the gate dielectric layer needs further improvement.
[0034] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same.
[0035] refer to Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure. Figure 1 As shown, in a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising:
[0036] Step S110: Provide a semiconductor layer;
[0037] Step S120: Using atomic layer deposition (ALD) technology, a gate dielectric layer is formed on the semiconductor layer. The gate dielectric layer includes multiple zirconium oxide layers. The ALD process includes multiple first cycles, and each first cycle corresponds to the formation of one zirconium oxide layer.
[0038] Step S122: The first cycle includes: introducing a first precursor containing zirconium; purging with gas using a first cleaning step; introducing a second precursor containing oxygen, wherein the second precursor and the first precursor react chemically to generate a zirconium oxide layer; purging with gas using a second cleaning step; wherein the molar ratio between oxygen and zirconium in the zirconium oxide layer is 1.8:1 to 1.95:1.
[0039] In this embodiment of the present disclosure, a semiconductor layer is provided in step S110. Here, the semiconductor layer can be placed in the reaction chamber of an atomic layer deposition (ALD) apparatus to facilitate the subsequent formation of a gate dielectric layer using the ALD process.
[0040] In some embodiments, the semiconductor layer can be used to form the channel, source, and drain in a transistor. In one specific embodiment, the semiconductor layer may include a silicon layer.
[0041] In some embodiments, the method further includes: heating the reaction chamber to control the temperature of the reaction chamber to 250°C to 300°C and keeping it stable; evacuating the reaction chamber and introducing an inert gas into the reaction chamber to keep the gas pressure in the reaction chamber stable.
[0042] In this embodiment of the present disclosure, in step S120, an ALD process is used to form a gate dielectric layer on the semiconductor layer. The gate dielectric layer includes a plurality of stacked zirconium oxide layers. The ALD process includes a plurality of first cycle cycles, and each first cycle corresponds to the formation of a zirconium oxide layer.
[0043] Here, one zirconium oxide monolayer can be formed in each first cycle of the ALD process, and multiple zirconium oxide monolayers can be formed in multiple first cycles. The multiple stacked zirconium oxide layers together form the gate dielectric layer.
[0044] In this embodiment of the present disclosure, in step S122, each first cycle includes: introducing a first precursor containing zirconium into the reaction chamber, the first precursor being adsorbed onto the surface of the semiconductor layer; performing gas purging using a first cleaning step, the gas purging removing unreacted first precursor, at which point the surface of the semiconductor layer reaches a saturated adsorption state; introducing a second precursor containing oxygen into the reaction chamber, the second precursor and the first precursor reacting chemically to generate a zirconium oxide layer; performing gas purging using a second cleaning step, the gas purging removing unreacted second precursor; wherein the molar ratio between oxygen and zirconium in the zirconium oxide layer is 1.8:1 to 1.95:1.
[0045] In some embodiments, the molar ratio between oxygen and zirconium in the zirconium oxide layer can be, for example, 1.80:1, 1.82:1, 1.83:1, 1.85:1, 1.86:1, 1.88:1, 1.89:1, 1.90:1, 1.91:1, 1.92:1, 1.93:1, 1.94:1, or 1.95:1.
[0046] In some embodiments, the first precursor may also be referred to as a zirconium source, and the first precursor may include, but is not limited to, zirconium tetrachloride (ZrCl4) and tetra(dimethylamino)zirconium (TDMAZr). This disclosure does not specifically limit the type of the first precursor, as long as the first precursor can provide zirconium element for the formation of the zirconium oxide layer in the ALD process.
[0047] In some embodiments, the second precursor may also be referred to as an oxygen source, and the second precursor may include, but is not limited to, water (H2O) and ozone (O3). This disclosure does not specifically limit the type of the second precursor, as long as the second precursor can provide oxygen for the formation of the zirconium oxide layer in the ALD process.
[0048] In this embodiment, the molar ratio of oxygen to zirconium in the zirconium oxide layer determines the crystal structure of the zirconium oxide layer, which in turn determines the properties of the gate dielectric layer. The molar ratio of oxygen to zirconium in the zirconium oxide layer determines the interface state defect density, which has a negative impact on carrier migration. Limiting the range of the molar ratio of oxygen to zirconium in the zirconium oxide layer, i.e., limiting the oxygen content in the zirconium oxide layer, can improve the interface state defect density between the semiconductor layer and the zirconium oxide layer, thereby improving the electrical performance of the semiconductor structure.
[0049] In some embodiments, the duration of the second precursor being introduced in each first cycle ranges from 10 ms to 100 ms. By limiting the pulse duration of the second precursor, the amount of oxygen introduced can be adjusted, thereby controlling the molar ratio between oxygen and zirconium in the zirconium oxide layer.
[0050] In some embodiments, the duration of the second precursor being introduced in each first cycle may be, for example, 10ms, 20ms, 30ms, 40ms, 50ms, 60ms, 70ms, 80ms, 90ms or 100ms.
[0051] In some embodiments, the purpose of the gas purging in the first cleaning step is to remove excess first precursor, and the purging gas must not react with the first precursor; the purpose of the gas purging in the second cleaning step is to remove unreacted second precursor, and the purging gas must not react with the first precursor, the second precursor, or zirconium oxide. Nitrogen (N2) or an inert gas, such as helium (He) or argon (Ar), can be used for gas purging in both the first and second cleaning steps.
[0052] In some embodiments, the duration of the second cleaning step in each first cycle ranges from 5 s to 30 s. Here, extending the duration of gas purging can ensure complete oxygen source reaction while avoiding excessive oxidation caused by excessive oxygen source. The duration of the second cleaning step can be used to adjust the amount of oxygen source introduced, thereby controlling the molar ratio between oxygen and zirconium in the zirconium oxide layer.
[0053] In some embodiments, the duration of the second cleaning step in each first cycle may be, for example, 5s, 10s, 15s, 20s, 25s, or 30s.
[0054] In one specific embodiment, each first cycle may include the following steps: introducing zirconium tetrachloride into the reaction chamber, where zirconium tetrachloride can adsorb onto the surface of a semiconductor layer (e.g., a silicon layer) to form, for example, zirconium-oxygen bonds; performing gas purging to remove excess zirconium tetrachloride, at which point the zirconium tetrachloride adsorbed onto the silicon layer surface reaches saturation; introducing water vapor into the reaction chamber, where the water vapor can react with zirconium tetrachloride to form a zirconium oxide monolayer; and performing gas purging to remove excess water vapor in preparation for the next cycle.
[0055] Here, in the ALD process, each first cycle can form a zirconia monolayer. The thickness of the zirconia monolayer is a preset value. By limiting the number of first cycles in ALD, the total thickness of the zirconia layer can be precisely controlled.
[0056] refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to other embodiments of this disclosure. For example... Figure 2 As shown, in some embodiments, the gate dielectric layer further includes at least one doped layer; the atomic layer deposition process further includes at least one second cycle, each second cycle corresponding to the formation of one doped layer;
[0057] Step S124: The second cycle includes: introducing a third precursor containing doped elements; performing gas purging using a third cleaning step; introducing a fourth precursor containing oxygen elements, wherein the fourth precursor and the third precursor undergo a chemical reaction to generate a doped layer; and performing gas purging using a fourth cleaning step.
[0058] In this embodiment of the disclosure, an ALD process is used to form a gate dielectric layer on a semiconductor layer. The gate dielectric layer further includes at least one doped layer. The ALD process includes at least one second cycle, and each second cycle corresponds to the formation of a doped layer.
[0059] Here, a doped monolayer can be formed in each second cycle of the ALD process, and the doped monolayer can be inserted between adjacent zirconia monolayers. For example, one second cycle can be inserted after every 10 first cycles, that is, one doped monolayer can be inserted after every 10 zirconia monolayers are deposited.
[0060] In this embodiment of the present disclosure, in step S124, the second cycle includes: introducing a third precursor containing a dopant element into the reaction chamber; performing gas purging using a third cleaning step, wherein gas purging can remove unreacted third precursor; introducing a fourth precursor containing oxygen element, wherein the fourth precursor and the third precursor undergo a chemical reaction to generate a doped layer; and performing gas purging using a fourth cleaning step, wherein gas purging can remove unreacted fourth precursor.
[0061] In some embodiments, the third precursor may also be referred to as the doping source, and the doping element may include, but is not limited to, yttrium (Y) and gadolinium (Gd). The third precursor may include, but is not limited to, tris(tetramethylethylenediamine)yttrium (Y(thd)3) and tris(tetramethylethylenediamine)gadolinium (Gd(thd)3).
[0062] In some embodiments, the fourth precursor may also be referred to as an oxygen source, and the fourth precursor may include, but is not limited to, water (H2O) and ozone (O3). This disclosure does not specifically limit the type of the fourth precursor, as long as the fourth precursor can provide oxygen for the formation of the yttrium oxide layer or gadolinium oxide layer in the ALD process.
[0063] In some embodiments, the purpose of the gas purging in the third cleaning step is to remove excess third precursor, and the purging gas must not react with the third precursor; the purpose of the gas purging in the fourth cleaning step is to remove unreacted fourth precursor, and the purging gas must not react with the third precursor, the fourth precursor, or the doped layer. Nitrogen (N2) or an inert gas, such as helium (He) or argon (Ar), can be used for gas purging in the third and fourth cleaning steps.
[0064] In some embodiments, the duration of the fourth cleaning step in each second cycle is greater than 5 seconds. Here, extending the duration of gas purging can ensure complete oxygen source reaction while avoiding excessive oxidation caused by excessive oxygen source. The amount of oxygen source introduced can be adjusted by utilizing the duration of the fourth cleaning step.
[0065] In one specific embodiment, each second cycle may include the following steps: introducing tris(tetramethylethylenediamine)gadolinium into the reaction chamber; performing gas purging to remove excess tris(tetramethylethylenediamine)gadolinium; introducing water vapor into the reaction chamber, where the water vapor can react with the tris(tetramethylethylenediamine)gadolinium to form a gadolinium oxide monolayer; and performing gas purging to remove excess water vapor in preparation for the next cycle.
[0066] In some embodiments, the ratio between the number of second cycles and the sum of the number of first and second cycles ranges from 3% to 10%. Here, the gate dielectric layer includes a zirconium oxide layer and a doped layer, the ratio of the number of doped monolayers to (the number of zirconium oxide monolayers + the number of doped monolayers) ranges from 3% to 10%, and the ratio of the molar amount of the compound in the doped layer to (the molar amount of the compound in the zirconium oxide layer + the molar amount of the compound in the doped layer) ranges from 3 mol% to 10 mol%, that is, the ratio of the molar amount of the compound in the doped layer to the molar amount of the compound in the gate dielectric layer ranges from 3 mol% to 10 mol%. Limiting the above molar ratio range can improve the electrical performance of the semiconductor structure. In some specific embodiments, one second cycle can be performed after every 10 first cycles, that is, one doped monolayer can be deposited after every 10 zirconium oxide monolayers are deposited.
[0067] In some embodiments, the ratio between the number of second cycle periods and the sum of the number of first cycle periods and second cycle periods may be, for example, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%.
[0068] In this embodiment, the gate dielectric layer is doped to control the K value of the gate dielectric layer, making the K value range from 30 to 40. Introducing a doped layer into the gate dielectric layer can improve the dielectric constant of the gate dielectric layer, thereby improving the insulation properties of the gate dielectric layer and effectively reducing phenomena such as quantum tunneling.
[0069] In some embodiments, the thickness of the gate dielectric layer ranges from 4 nm to 6 nm.
[0070] In some embodiments, after the gate dielectric layer is deposited, it can be annealed. The annealing temperature range can be 700°C to 900°C, the annealing time can be 30s to 60s, and the annealing atmosphere can be nitrogen or an inert gas (e.g., helium or argon).
[0071] In some embodiments, the method further includes: doping the semiconductor layer to form a source and a drain.
[0072] In some embodiments, the method further includes forming a gate electrode layer on top of the gate dielectric layer, wherein the gate dielectric layer and the gate electrode layer together form a gate structure. The gate electrode layer can be a single-layer structure or a multi-layer structure. For example, the gate electrode layer may include an adhesion layer and a metal layer, wherein the adhesion layer may be, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN), and the metal layer may be, but is not limited to, tungsten (W) or aluminum (Al). The thickness of the adhesion layer can range from 5 nm to 10 nm, and the thickness of the metal layer can range from 100 nm to 200 nm.
[0073] In some embodiments, the semiconductor structure may include various types of transistors, including but not limited to planar field-effect transistors (FETs), vertical channel transistors (VCTs), and fin field-effect transistors (Fin FETs). The following description uses only the manufacturing method of a Fin FET as an example.
[0074] In some embodiments, the method may include: providing a silicon substrate; etching the silicon substrate to form discrete fins; forming an isolation structure on the substrate exposed by the fins, the isolation structure covering a portion of the sidewall surface of the fins, the top surface of the isolation structure being lower than the top surface of the fins; and forming a pseudo-gate structure spanning the fins, the pseudo-gate structure covering a portion of the top surface and sidewall surface of the fins. The pseudo-gate structure includes a pseudo-gate dielectric layer and a pseudo-gate electrode layer, the pseudo-gate dielectric layer being located between the fins and the pseudo-gate electrode layer.
[0075] In some embodiments, the method may further include: forming a sidewall on the sidewall of the dummy gate structure; etching fins on opposite sides of the dummy gate structure to form grooves in the fins; forming a doped epitaxial layer in the grooves, wherein the doped epitaxial layers on opposite sides of the dummy gate structure form source and drain electrodes respectively; forming an interlayer dielectric layer; removing the dummy gate structure; and forming a gate structure, wherein the gate structure includes a gate dielectric layer and a gate electrode layer, and the gate dielectric layer is located between the fins and the gate electrode layer.
[0076] refer to Figure 3 , Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 3 As shown, in a second aspect, embodiments of this disclosure provide a semiconductor structure 300, which includes: a semiconductor layer 302; and a gate dielectric layer 304 disposed on the semiconductor layer 302, the gate dielectric layer 304 including a plurality of zirconium oxide layers, wherein the molar ratio between oxygen and zirconium in the zirconium oxide layers ranges from 1.8:1 to 1.95:1.
[0077] In some embodiments, the zirconia layer has a cubic phase structure. Here, the cubic phase structure makes the zirconia layer more stable.
[0078] In some embodiments, the gate dielectric layer 304 further includes at least one doped layer, the doped layer including at least one of a yttrium oxide layer and a gadolinium oxide layer; the ratio between the molar amount of the compound in the doped layer and the molar amount of the compound in the gate dielectric layer 304 ranges from 3 mol% to 10 mol%.
[0079] like Figure 3 As shown, in some embodiments, the semiconductor structure 300 further includes: a gate electrode layer 306, a gate dielectric layer 304 disposed between the semiconductor layer 302 and the gate electrode layer 306; a source electrode 308 and a drain electrode 310, both of which are disposed in the semiconductor layer 302 and respectively disposed on opposite sides of the gate electrode layer 306.
[0080] In some embodiments, semiconductor layer 302 includes a silicon layer.
[0081] In some embodiments, in a planar field-effect transistor, the semiconductor layer extends horizontally, with both the source and drain electrodes disposed within the semiconductor layer, and a gate dielectric layer disposed on top of and in contact with the semiconductor layer. In a vertical transistor, the semiconductor body extends vertically, with the source and drain electrodes disposed on opposite sides of the semiconductor body along its extension direction, and a gate dielectric layer disposed on the sidewall of the semiconductor body and in contact with the semiconductor body.
[0082] Example 1
[0083] The silicon wafer is placed in the reaction chamber of the ALD (Alternating Current) equipment. The first cycle of the ALD process includes: introducing TDMAZr into the reaction chamber as a first precursor; purging the chamber with N2 gas in a first cleaning step; introducing H2O into the reaction chamber as a second precursor for 75 ms; and purging the chamber with N2 gas in a second cleaning step for 7 s. The first cycle is repeated to form multiple zirconium oxide layers on the silicon wafer.
[0084] Example 2
[0085] The silicon wafer is placed in the reaction chamber of the ALD (Alternating Current) equipment. The first cycle of the ALD process includes: introducing TDMAZr into the reaction chamber as a first precursor; purging the chamber with N2 gas in a first cleaning step; introducing H2O into the reaction chamber as a second precursor for 90 ms; and purging the chamber with N2 gas in a second cleaning step for 8 s. The first cycle is repeated to form multiple zirconium oxide layers on the silicon wafer.
[0086] Tests showed that the molar ratio of oxygen to zirconium in the zirconium oxide layer provided in Example 1 was 1.8:1, and the molar ratio of oxygen to zirconium in the zirconium oxide layer provided in Example 2 was 1.95:1. The molar ratio of oxygen to zirconium in the zirconium oxide layer provided in Comparative Example 1 was 2:1. Multiple zirconium oxide layers were fabricated on a silicon wafer using known manufacturing methods.
[0087] refer to Figure 4 , Figure 4 Figures (a), (b), and (c) are schematic diagrams of the band structure of the interface between the zirconium oxide layer and the silicon layer in Examples 1, 2, and 1, respectively. The valence band maximum (VBM) is slightly away from point Γ, and the conduction band minimum (CBM) is at point Γ, confirming that the band gap in Comparative Example 1 is an indirect band gap structure.
[0088] Combination Figure 5 As shown, the band gap properties in Examples 1 and 2 are direct band gap structures, while the band gap properties in Comparative Example 1 are indirect band gap structures. In a direct band gap structure, electron transitions do not require a change in momentum and have higher carrier mobility, while in an indirect band gap structure, electron transitions require a change in momentum and have lower carrier mobility.
[0089] refer to Figure 6 , Figure 7 and Figure 8 , Figure 6 (a) Figure Figure 7 Figure (a) and Figure 8 Figure (a) illustrates the atomic structures of the zirconium oxide and silicon layers in Examples 1, 2, and Comparative Example 1, respectively. Blue spheres represent silicon atoms, red spheres represent oxygen atoms, and green spheres represent zirconium atoms. In Example 1, the lattice constants are a = 5.44370, b = 5.44370, c = 26.22877, α = 90, β = 90, and γ = 90. In Example 2, the lattice constants are a = 5.44370, b = 5.44370, c = 42.40371, α = 90, β = 90, and γ = 90. In Comparative Example 1, the lattice constants are a = 5.44370, b = 5.44370, c = 36.93779, α = 90, β = 90, and γ = 90.
[0090] refer to Figure 6 , Figure 7 and Figure 8 , Figure 6 Chinese (b) map Figure 7 Chinese (b) map and Figure 8Figure (b) illustrates the differences in three-dimensional charge density between the zirconium oxide layer and the silicon layer in Examples 1, 2, and Comparative Example 1, respectively. Charge transfer occurs near the interface between the zirconium oxide layer and the silicon layer, with charge transferring from the silicon layer to the zirconium oxide layer.
[0091] refer to Figure 9 , Figure 9 Figures (a), (b), and (c) are schematic diagrams of Bader charge in Examples 1, 2, and 1, respectively. Figure 9 The horizontal axis represents the atom number, and the vertical axis represents the Baader charge; a positive vertical axis indicates that the atom gains an electron, and a negative vertical axis indicates that the atom loses an electron.
[0092] like Figure 9 As shown in Figure (a), in Example 1, most silicon atoms undergo charge transfer near 0, and silicon atoms near the interface lose electrons ranging from -2 to -1; most oxygen atoms gain 1.3 electrons; and zirconium atoms lose electrons ranging from -2.5 to -1.8.
[0093] like Figure 9 As shown in Figure (b), in Example 2, most silicon atoms undergo charge transfer near 0, and silicon atoms near the interface lose electrons ranging from -1.5 to -1; most oxygen atoms gain 1.3 electrons; and zirconium atoms lose electrons ranging from -2.55 to -2.
[0094] like Figure 9 As shown in Figure (c), in Comparative Example 1, most silicon atoms undergo charge transfer around 0, and silicon atoms near the interface lose electrons ranging from -1.5 to -1; most oxygen atoms gain 1.3 electrons; and zirconium atoms lose electrons around -2.55.
[0095] refer to Figure 10 , Figure 10 This is a schematic diagram of valence band offset and conduction band offset in Examples 1, 2, and Comparative Example 1. Figure 10 As shown, the valence band offset (VBO) refers to the energy difference between the tops of the valence band at the interface between the silicon layer and the zirconium oxide layer, and the conduction band offset (CBO) refers to the energy difference between the bottoms of the conduction band at the interface between the silicon layer and the zirconium oxide layer. In Examples 1 and 2, the valence band offset is greater than that in Comparative Example 1, and the conduction band offset is smaller than that in Comparative Example 1. Furthermore, both the valence band offset and the conduction band offset are greater than 1 eV, which effectively suppresses leakage current.
[0096] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0097] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.
Claims
1. A method of manufacturing a semiconductor structure, characterized by, The method comprises: providing a semiconductor layer; forming a gate dielectric layer on the semiconductor layer using an atomic layer deposition process, the gate dielectric layer comprising a plurality of zirconium oxide layers; the atomic layer deposition process comprising a plurality of first cycle periods, each of the first cycle periods corresponding to forming one zirconium oxide layer; each of the first cycle periods comprises: introducing a first precursor containing a zirconium element; performing a first cleaning step for gas purging; introducing a second precursor containing an oxygen element, the second precursor and the first precursor chemically reacting to form a zirconium oxide layer; performing a second cleaning step for gas purging; wherein a molar ratio between the oxygen element and the zirconium element in the zirconium oxide layer is 1.8:1 to 1.95:
1.
2. The production method according to claim 1, characterized by A duration of introducing the second precursor in each of the first cycle periods ranges from 10 ms to 100 ms.
3. The production method according to claim 1, characterized by, A duration of the second cleaning step in each of the first cycle periods ranges from 5 s to 30 s.
4. The production method according to claim 1, characterized by The gate dielectric layer further comprises at least one doped layer; the atomic layer deposition process further comprises at least one second cycle period, each of the second cycle periods corresponding to forming one doped layer; each of the second cycle periods comprises: introducing a third precursor containing a doping element; performing a third cleaning step for gas purging; introducing a fourth precursor containing an oxygen element, the fourth precursor and the third precursor chemically reacting to form a doped layer; performing a fourth cleaning step for gas purging.
5. The manufacturing method according to claim 4, wherein The doped layer comprises at least one of a yttrium oxide layer and a gadolinium oxide layer; a ratio between a number of the second cycle periods and a sum of the first cycle periods and the number of the second cycle periods ranges from 3% to 10%.
6. A semiconductor structure, characterized by The semiconductor structure comprises: a semiconductor layer; a gate dielectric layer disposed on the semiconductor layer, the gate dielectric layer comprising a plurality of zirconium oxide layers, a molar ratio between an oxygen element and a zirconium element in the zirconium oxide layers ranging from 1.8:1 to 1.95:
1.
7. The semiconductor structure of claim 6, wherein, A crystal structure of the zirconium oxide layers is a cubic phase structure.
8. The semiconductor structure of claim 6, wherein, The gate dielectric layer further comprises at least one doped layer, the doped layer comprising at least one of a yttrium oxide layer and a gadolinium oxide layer; a ratio between a molar amount of a compound in the doped layer and a molar amount of a compound in the gate dielectric layer ranges from 3 mol% to 10 mol%.
9. The semiconductor structure of claim 6, wherein, The semiconductor structure further comprises: a gate electrode layer, the gate dielectric layer being disposed between the semiconductor layer and the gate electrode layer; a source and a drain, the source and the drain both being disposed in the semiconductor layer and being disposed on opposite sides of the gate electrode layer, respectively.
10. The semiconductor structure of claim 6, wherein, The semiconductor layer comprises a silicon layer.