Semiconductor device and electronic apparatus

Abstract

The application discloses a semiconductor device and an electronic device. The semiconductor device comprises a first electrode, an active region and a second electrode which are sequentially stacked. The active region comprises a first doped structure, a second doped structure and a third doped structure which are stacked in a direction away from the first electrode. The first doped structure and the third doped structure are doped with a first conductive type, and the second doped structure is doped with a second conductive type. The second doped structure comprises a drift layer. At least one of the first electrode and the second electrode is provided with a relief window which is arranged through the thickness of the electrode. The active region can receive light through the relief window to form photo-generated carriers. According to the application, the semiconductor device can realize light-triggered avalanche breakdown. By adjusting the triggering relationship between the voltage and the external light, the semiconductor device can realize active degradation protection in the electronic device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and electronic apparatus. Background Technology

[0002] As a crucial component of power electronic converters, power semiconductor devices play a critical role in switching control. When power semiconductor devices and their driving sources malfunction, the converter, losing its switching control capability, is prone to safety hazards due to device control failure.

[0003] Therefore, it is necessary to provide a semiconductor device that can block degradation under controlled fault conditions to protect power electronic converters. Summary of the Invention

[0004] This application provides a semiconductor device and an electronic apparatus. The semiconductor device can reliably conduct under illumination conditions in a turned-off state, and reliably short-circuit breakdown of the semiconductor device can be formed by triggering illumination, thereby providing fault condition protection for the protected devices in the circuit.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, including a first electrode, an active region, and a second electrode stacked sequentially. The active region includes a first doped structure, a second doped structure, and a third doped structure stacked along a direction away from the first electrode. The first and third doped structures are of a first conductivity type, and the second doped structure is of a second conductivity type. The second doped structure includes a drift layer. At least one of the first and second electrodes has a clearance window that extends through its own thickness direction. The active region can receive light through the clearance window to form photogenerated carriers. The active region also includes a control portion disposed on one side of the drift layer in the stacking direction. The ion doping concentration of the control portion is greater than or equal to the ion doping concentration of the drift layer. The orthographic projection of the clearance window on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the control portion on a plane perpendicular to the stacking direction.

[0006] In some alternative embodiments, the orthographic projection of the avoidance window onto a plane perpendicular to the stacking direction falls within the orthographic projection range of the control unit onto a plane perpendicular to the stacking direction.

[0007] In some alternative embodiments, the control unit is located on the side of the drift layer facing the avoidance window.

[0008] In some optional embodiments, the first doped structure includes a first sub-section and a second sub-section stacked along a direction away from the first electrode, wherein the ion doping concentration of the first sub-section is greater than or equal to the ion doping concentration of the second sub-section.

[0009] In some alternative embodiments, the control unit is disposed on the side of the drift layer away from the second electrode, and the control unit forms an ohmic contact with the first electrode.

[0010] In some alternative embodiments, the orthographic projection of the control unit on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction.

[0011] In some alternative embodiments, the second doped structure further includes a buffer layer disposed on the side of the drift layer facing the first electrode, wherein the ion doping concentration of the buffer layer is greater than that of the drift layer.

[0012] In some alternative embodiments, the ion doping concentration of the buffer layer is greater than or equal to the ion doping concentration of the control unit.

[0013] Secondly, embodiments of this application provide a semiconductor device, which includes a first electrode, an active region, and a second electrode. The active region is disposed on one side of the first electrode along the thickness direction. The active region includes a first doped structure, a second doped structure, and a third doped structure stacked along the direction away from the first electrode. The first doped structure and the third doped structure are doped for a first conductivity type, and the second doped structure is doped for a second conductivity type. The second electrode is disposed on the side of the active region away from the first electrode. At least one of the first electrode and the second electrode has an avoidance window. The active region includes a first sub-region and a second sub-region. The size of the first sub-region in the stacking direction is less than or equal to the size of the second sub-region in the stacking direction. The orthographic projection of the first sub-region on a plane perpendicular to the stacking direction and the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction at least partially overlap.

[0014] Thirdly, embodiments of this application provide an electronic device, which includes a device to be protected, a light triggering device, and a semiconductor device. The semiconductor device is the semiconductor device provided in any embodiment of the first aspect or any embodiment of the second aspect, and the semiconductor device is electrically connected to the device to be protected. The light triggering device is connected in parallel with at least one of the semiconductor device and the device to be protected, and the light triggering device is configured to excite light at least directed toward the avoidance window in response to a first threshold voltage.

[0015] The semiconductor device in this application embodiment can generate photogenerated carriers in response to external light in the off state. These photogenerated carriers can intensify the electric field in the active region, thereby exciting more carriers to form a photocurrent. Ultimately, the photocurrent can induce avalanche breakdown within the device, releasing energy under overvoltage conditions. The semiconductor device actively protects key components of the converter from damage risks through breakdown. Specifically, when the protected device is under dangerous conditions such as overvoltage, the semiconductor device can reliably break down under light illumination to achieve degraded protection, preventing the protected device from deteriorating to damage, explosion, or other severe situations, thus achieving fault condition protection for the protected device. Furthermore, by providing a control unit that can receive light from the avoidance window, the avalanche breakdown formed by the semiconductor device under photo-induced conditions is accelerated, further improving the response speed under fault conditions. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of this application;

[0018] Figure 2 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of this application;

[0019] Figure 3 An example is shown. Figure 1 A magnified view of the active region;

[0020] Figure 4 An example is shown. Figure 1 A magnified view of the active region;

[0021] Figure 5 An example is shown. Figure 1 A magnified view of a portion of the active region;

[0022] Figure 6 An example is shown. Figure 1 A magnified view of the active region;

[0023] Figure 7 An example is shown. Figure 1 A magnified view of the active region;

[0024] Figure 8 An example is shown. Figure 1 A magnified view of a portion of the active region;

[0025] Figure 9This is a top view schematic diagram of a semiconductor device according to some embodiments of this application;

[0026] Figure 10 An example is shown. Figure 1 A magnified view of a portion of the active region;

[0027] Figure 11 An example is shown. Figure 1 A magnified view of the active region.

[0028] The accompanying drawings may not be drawn to scale.

[0029] The specific marking information in the attached diagram is as follows:

[0030] 110. First electrode; 111. First clearance window; 120. Second electrode; 121. Second clearance window; 130. Third electrode;

[0031] 200, Active region; 201, First sub-region; 202, Second sub-region; 210, First doped structure; 211, First sub-section; 212, Second sub-section; 220, Second doped structure; 221, Buffer layer; 222, Drift layer; 223, Control unit; 230, Third doped structure; 240, Fourth doped structure;

[0032] First direction Y; second direction X; stacking direction Z. Detailed Implementation

[0033] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0035] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0038] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0039] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0040] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0041] Power electronic converters, as the main devices for power conversion and regulation, are widely used in various fields such as electric vehicles, consumer electronics, and power systems. The efficient conversion of electrical energy in these converters highly depends on the power semiconductor devices used to perform switching control operations. These power semiconductor devices can construct the target waveform of voltage or current through periodic switching on and off.

[0042] However, power electronic converters may experience various potential failure risks during use, such as drive circuit malfunctions, leading to unexpected failures of power semiconductor devices and loss of switching function. Failure of power semiconductor devices can cause more serious damage to the converter's internal components or even trigger safety accidents, resulting in significant economic losses and safety risks.

[0043] Taking overvoltage conditions encountered by power electronic converters as an example, related technologies incorporate a breakdown diode structure within the power semiconductor device. This breakdown diode can undergo avalanche breakdown under overvoltage conditions, thereby enabling the semiconductor device to turn on automatically. However, this structure exhibits high temperature sensitivity, with the breakdown voltage drifting by up to 10% within the operating temperature range, thus its degraded protection effect for power electronic converters needs improvement. Furthermore, when the power semiconductor device is turned off, the avalanche current generated by the breakdown diode cannot trigger the device to turn on automatically, failing to provide degraded protection.

[0044] To address the problems of the prior art, embodiments of this application provide a semiconductor device and electronic apparatus that can reliably conduct under illumination conditions in a shutdown state, and reliably short-circuit breakdown of the semiconductor device by triggering illumination, thereby providing fault condition protection for components in the circuit.

[0045] The following combination Figures 1 to 11 The semiconductor devices provided in the embodiments of this application will be described.

[0046] Firstly, please refer to Figures 1 to 9 This application provides a semiconductor device, which includes a first electrode 110, an active region 200, and a second electrode 120 stacked sequentially. The active region 200 includes a first doped structure 210, a second doped structure 220, and a third doped structure 230 stacked along a direction away from the first electrode 110. The first doped structure 210 and the third doped structure 230 are doped with a first conductivity type, and the second doped structure 220 is doped with a second conductivity type. At least one of the first electrode 110 and the second electrode 120 has a clearance window that extends through its own thickness direction. The active region 200 can receive light through the clearance window to form photogenerated carriers.

[0047] In some of these embodiments, please refer to Figure 1 The first electrode 110 is the anode, the second electrode 120 is the gate, and the third electrode 130 is the cathode. The semiconductor device also includes a fourth doped structure 240 with a second conductivity type. The fourth doped structure 240 is located on the side of the third doped structure 230 facing away from the first electrode 110 and is in contact with the third electrode 130. Specifically, the orthogonal projection of the third electrode 130 onto the first electrode 110 falls within the orthogonal projection range of the fourth doped structure 240 onto the first electrode 110.

[0048] Optionally, the semiconductor device is a non-punch-through thyristor, and the second doped structure 220 includes a drift layer 222.

[0049] Optionally, the semiconductor device is a punch-through thyristor, and the second doped structure 220 includes a buffer layer 221 and a drift layer 222 stacked along the direction away from the first electrode 110, wherein the ion doping concentration of the buffer layer 221 is greater than the ion doping concentration of the drift layer 222.

[0050] Please see Figures 3 to 8 The active region 200 also includes a control unit 223, which is disposed on one side of the drift layer 222 in the stacking direction. The orthographic projection of the control unit 223 on a plane perpendicular to the stacking direction overlaps at least partially with the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction.

[0051] Optionally, the ion doping concentration of the control unit 223 is greater than or equal to the ion doping concentration of the drift layer 222. The control unit 223 can more efficiently excite the formation of photogenerated carriers than the drift layer 222, thereby accelerating the formation of photogenerated current in the active region 200 and inducing avalanche breakdown of the semiconductor device more quickly under the same overvoltage conditions, thus achieving the purpose of degradation protection.

[0052] Optionally, the first conductivity type doping is P-type doping, and the second conductivity type doping is N-type doping.

[0053] Optionally, the first conductivity type doping is N-type doping, and the second conductivity type doping is P-type doping.

[0054] For example, the P-type doped ion includes at least one of boron, aluminum, gallium, and indium.

[0055] For example, the N-type doped ions include at least one of arsenic, phosphorus, and antimony.

[0056] Optionally, the first electrode 110 may be a metal electrode.

[0057] Optionally, the second electrode 120 may be a metal electrode.

[0058] It is understood that in some embodiments, both the first electrode 110 and the second electrode 120 have clearance windows; in other embodiments, either the first electrode 110 or the second electrode 120 has a clearance window.

[0059] Therefore, by opening a clearance window in the first electrode 110 and / or the second electrode 120, external light can enter the active region 200 of the semiconductor device through the clearance window to form photogenerated carriers. These photogenerated carriers can create an electric field modulation effect within the active region 200. A positive feedback loop is formed between the electric field strength and the photogenerated current generated by the photogenerated carriers, inducing avalanche breakdown within the semiconductor device and resulting in energy release. Since illumination induces the formation of photogenerated carriers within the active region 200 and accelerates avalanche breakdown, the semiconductor device provided in this embodiment is more sensitive than existing overvoltage protection structures. Furthermore, by adding a control unit that at least partially corresponds to the clearance window, the photogenerated current can be generated more intensely within the semiconductor device, thereby accelerating avalanche breakdown and improving the blocking degradation protection performance of the semiconductor device.

[0060] Specifically, breakdown protection refers to the active breakdown of semiconductor devices to protect key components of the converter from damage. When the protected device is under dangerous conditions such as overvoltage, the semiconductor device can reliably break down under light conditions to achieve breakdown protection of the converter, preventing the protected device from degrading to severe conditions such as damage or explosion, and thus achieving fault protection for the protected device.

[0061] It is understood that the semiconductor device can be used in conjunction with a light-triggered device capable of emitting light toward the avoidance window under overvoltage conditions. For example, the light-triggered device is connected in parallel with the semiconductor device.

[0062] In other embodiments, the semiconductor device provided in this application is a field-blocking insulated-gate bipolar transistor (IGBT). Specifically, please refer to... Figure 2 The first electrode 110 is the collector, the second electrode 120 is the emitter, and the third electrode 130 is the gate. The third electrode 130 is provided with an insulating gap from the active region 200. The semiconductor device also includes a fourth doped structure 240 of a second conductivity type. The fourth doped structure 240 is formed by extending from the surface of the third doped structure 230 away from the first electrode 110 toward the first electrode 110. The orthogonal projection of the fourth doped structure 240 on the first electrode 110 overlaps with the orthogonal projection of the second electrode 120 on the first electrode 110, and the orthogonal projection of the fourth doped structure 240 on the first electrode 110 overlaps with the orthogonal projection of the third electrode 130 on the first electrode 110.

[0063] According to some embodiments of the first aspect of this application, the active region 200 includes a first sub-region and a second sub-region, wherein the orthographic projection of the first sub-region on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction, and the size of the first sub-region in the stacking direction is smaller than the size of the second sub-region in the stacking direction.

[0064] Optionally, the orthographic projection of the window on the plane perpendicular to the stacking direction falls within the orthographic projection range of the first sub-region on the plane perpendicular to the stacking direction.

[0065] Optionally, the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction overlaps with the orthographic projection of the first sub-region on a plane perpendicular to the stacking direction.

[0066] Optionally, the orthographic projection of the first sub-region onto a plane perpendicular to the stacking direction falls within the orthographic projection range of the avoidance window onto a plane perpendicular to the stacking direction.

[0067] Therefore, by thinning and avoiding the first sub-region corresponding to the window, the light loss incident on the active region 200 is reduced, the generation of photogenerated carriers is amplified, and the photo-triggering sensitivity of the semiconductor device is improved.

[0068] In some of the embodiments, the first electrode 110 has a first clearance window 111, which penetrates the first electrode 110 and extends into at least a portion of the first doped structure 210.

[0069] Optionally, the first clearance window 111 is set through the first doped structure 210.

[0070] Alternatively, the first clearance window 111 may extend into the second doped structure 220.

[0071] In some of the embodiments, the second electrode 120 has a second clearance window 121, which penetrates the second electrode 120 and extends into a portion of the third doped structure 230.

[0072] According to some embodiments of the first aspect of this application, please refer to Figure 3 or Figure 4 The semiconductor device is a non-punch-through device, and the first doped structure 210 includes a first sub-section 211 and a second sub-section 212 stacked along the direction away from the first electrode 110.

[0073] Optionally, the ion doping concentration of the first sub-part 211 is greater than the ion doping concentration of the second sub-part 212.

[0074] According to some embodiments of the first aspect of this application, the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction falls within the orthographic projection range of the control unit 223 on a plane perpendicular to the stacking direction.

[0075] Therefore, the control unit 223 covers the entire area in the active region where light enters, thereby intensifying the formation of photogenerated carriers inside the semiconductor device and accelerating the formation of avalanche breakdown or thermal breakdown of the semiconductor device under light-triggered conditions.

[0076] According to some other embodiments of the first aspect of this application, the orthographic projection of the control unit 223 on a plane perpendicular to the stacking direction falls within the orthographic projection range of the avoidance window on a plane perpendicular to the stacking direction.

[0077] According to some embodiments of the first aspect of this application, the control unit 223 is disposed on the side of the drift layer 222 facing the avoidance window, and the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction falls within the orthographic projection range of the control unit 223 on a plane perpendicular to the stacking direction.

[0078] Optionally, please refer to Figure 5 The semiconductor device is a through-hole device. The first electrode 110 has a first clearance window 111. At least part of the control part 223 is formed in the buffer layer 221 and is in contact with the drift layer 222.

[0079] Alternatively, the control section 223 is formed within the buffer layer 221 and is disposed in contact with the drift layer 222, and the dimension of the control section 223 in the stacking direction is smaller than the dimension of the buffer layer 221 in the stacking direction.

[0080] Optionally, please refer to Figure 6 The semiconductor device is a punch-through device. The second electrode 120 has a second clearance window 121. At least part of the control part 223 is formed in the third doped structure 230 and is in contact with the drift layer 222.

[0081] Alternatively, the control section 223 is formed within the third doped structure 230 and is disposed in contact with the drift layer 222, and the size of the control section 223 in the stacking direction is smaller than the size of the third doped structure 230 in the stacking direction.

[0082] Therefore, the control unit 223 can modulate the photogenerated electric field in the active region 200, increase the concentration of photogenerated carriers in the active region 200 under the same illumination conditions, and improve the photo-triggered avalanche breakdown sensitivity of the semiconductor device.

[0083] According to some embodiments of the first aspect of this application, the ion doping concentration of the control unit 223 is less than or equal to the ion doping concentration of the buffer layer 221.

[0084] Optionally, the first electrode 110 has a first clearance window 111, and the control unit 223 is disposed on the side of the drift layer 222 facing the first clearance window 111. The ion doping concentration of the control unit 223 is between the ion doping concentration of the buffer layer 221 and the ion doping concentration of the drift layer 222. The control unit 223 can more efficiently excite and form photogenerated carriers than the buffer layer 221, thereby accelerating the formation of photogenerated current in the active region 200 and inducing avalanche breakdown of the semiconductor device more quickly under the same overvoltage conditions, thereby achieving the purpose of degradation protection.

[0085] According to some embodiments of the first aspect of this application, the control unit 223 is disposed on the side of the drift layer 222 away from the second electrode 120, and the control unit 223 forms an ohmic contact with the first electrode 110.

[0086] This explanation will use an example where the first doping type is P-type and the second doping type is N-type. For details, please refer to [link to relevant documentation]. Figure 7 or Figure 8 The semiconductor device is a punch-through device. In the region corresponding to the avoidance window, the third doped structure 230 can form a bias PN junction with the second doped structure 220, so that the semiconductor device can directly respond to light and break down under overvoltage conditions.

[0087] Optionally, the ion doping concentration of the control unit 223 is lower than the ion doping concentration of the buffer layer 221.

[0088] Alternatively, the ion doping concentration of the control unit 223 is equal to the ion doping concentration of the drift layer 222.

[0089] Alternatively, the ion doping concentration of the control unit 223 is greater than the ion doping concentration of the drift layer 222.

[0090] According to some embodiments of the first aspect of this application, the orthographic projection of the control unit 223 on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction.

[0091] Optionally, the orthographic projection of the window on a plane perpendicular to the stacking direction is avoided from falling within the orthographic projection range of the control unit 223 on a plane perpendicular to the stacking direction.

[0092] Optionally, the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction overlaps with the orthographic projection of the control unit 223 on a plane perpendicular to the stacking direction.

[0093] Optionally, the orthographic projection of the control unit 223 on a plane perpendicular to the stacking direction falls within the orthographic projection range of the avoidance window on a plane perpendicular to the stacking direction.

[0094] Therefore, the control unit 223 can form a better modulation effect on the area directly irradiated by external light to increase the intensity of the photocurrent.

[0095] According to some embodiments of the first aspect of this application, the orthographic projection shape of the avoidance window on a plane perpendicular to the stacking direction is circular.

[0096] It is understood that a circle includes a perfect circle or other near-circular shapes formed by closed curves, such as an ellipse.

[0097] Therefore, the distribution area of ​​photogenerated carriers within the semiconductor device corresponds to the shape of the clearance window, forming a circular shape. This reduces the probability of electric field distortion within the device and improves the reliability of the semiconductor device. Furthermore, the circular clearance window can adapt to the shape of light rays incident on it.

[0098] According to some embodiments of the first aspect of this application, the avoidance window is opened on the second electrode 120, and the avoidance window is centrally symmetrically distributed with the center of the circle of the orthographic projection of the second electrode 120 on the plane perpendicular to the stacking direction as the center of symmetry.

[0099] For details, please continue reading Figure 9 The second electrode 120 has a second clearance window 121, which is a circular hole and is concentric with the second electrode 120.

[0100] Specifically, the second electrode 120 covers the portion of the active region 200 above the third electrode 130, and a terminal region is formed on the outer side of the active region 200. It is understood that an insulating medium is disposed between the second electrode 120 and the third electrode 130.

[0101] Optionally, the second clearance window 121 is formed by etching or other processes after the second electrode 120 is fabricated in a whole layer; or the second clearance window 121 and the second electrode 120 are fabricated simultaneously by vapor deposition or other processes.

[0102] Therefore, the photogenerated carriers formed by receiving light can be more evenly distributed in the active region, reducing the probability of unreliable breakdown in semiconductor devices during normal operation.

[0103] According to some embodiments of the first aspect of this application, the avoidance window is opened on the first electrode 110, and the avoidance window is centrally symmetrically distributed with the center of the circle of the orthographic projection of the first electrode 110 on a plane perpendicular to the stacking direction as the center of symmetry.

[0104] Secondly, please refer to Figure 10 or Figure 11 This application provides a semiconductor device, which includes a first electrode 110, an active region 200, and a second electrode 120 stacked sequentially. The active region 200 includes a first doped structure 210, a second doped structure 220, and a third doped structure 230 stacked along a direction away from the first electrode 110. The first doped structure 210 and the third doped structure 230 are doped with a first conductivity type, and the second doped structure 220 is doped with a second conductivity type. At least one of the first electrode 110 and the second electrode 120 has a clearance window that extends through its own thickness direction. The active region 200 can receive light through the clearance window to form photogenerated carriers.

[0105] Optionally, the first conductivity type doping is P-type doping, and the second conductivity type doping is N-type doping.

[0106] Optionally, the first conductivity type doping is N-type doping, and the second conductivity type doping is P-type doping.

[0107] For example, the P-type doped ion includes at least one of boron, aluminum, gallium, and indium.

[0108] For example, the N-type doped ions include at least one of arsenic, phosphorus, and antimony.

[0109] Optionally, the first electrode 110 may be a metal electrode.

[0110] Optionally, the second electrode 120 may be a metal electrode.

[0111] It is understood that in some embodiments, both the first electrode 110 and the second electrode 120 have clearance windows; in other embodiments, either the first electrode 110 or the second electrode 120 has a clearance window.

[0112] Optionally, the semiconductor device further includes a fourth doped structure 240, which is disposed on the side of the third doped structure 230 facing away from the first electrode 110.

[0113] Optionally, the second doped structure 220 includes a drift layer 222.

[0114] Optionally, the second doped structure further includes a buffer layer 221, which is disposed on the side of the drift layer 222 near the first electrode 110, and the ion doping concentration of the buffer layer 221 is greater than the ion doping concentration of the drift layer 222.

[0115] Optionally, the first doped structure 210 includes a first sub-section 211 and a second sub-section 212 stacked sequentially along a direction away from the first electrode 110, wherein the ion doping concentration of the first sub-section 211 is greater than or equal to the ion doping concentration of the second sub-section 212.

[0116] Therefore, by opening a clearance window in the first electrode 110 and / or the second electrode 120, external light can enter the active region 200 of the semiconductor device through the clearance window to form photogenerated carriers. These photogenerated carriers can create an electric field modulation effect within the active region 200. A positive feedback loop is formed between the electric field strength and the photogenerated current generated by the photogenerated carriers, inducing avalanche breakdown within the semiconductor device and releasing energy. The semiconductor device can actively trigger avalanche breakdown or thermal breakdown under overvoltage conditions, thereby achieving degraded protection relative to damage to the protected device. Since illumination induces the formation of photogenerated carriers within the active region 200 and accelerates avalanche breakdown, the semiconductor device provided in this embodiment is more sensitive than existing overvoltage protection structures.

[0117] Understandably, semiconductor devices can be used in conjunction with light-triggered devices that emit light toward the avoidance window under overvoltage conditions. Specifically, the light-triggered device and the semiconductor device are connected in parallel.

[0118] It should be noted that the semiconductor devices provided in the second aspect of this application include, but are not limited to, punch-through thyristors, non-punch-through thyristors, and field-blocking IGBTs.

[0119] According to some embodiments of the second aspect of this application, the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction falls within the orthographic projection range of the electrode on the plane perpendicular to the stacking direction.

[0120] Alternatively, the avoidance window can be prepared by an etching process.

[0121] For example, the first electrode 110 has a first clearance window 111, and the orthographic projection of the first clearance window 111 on a plane perpendicular to the stacking direction is surrounded by the orthographic projection of the first electrode 110 on a plane perpendicular to the stacking direction. In other words, the first electrode 110 forms a closure with respect to the first clearance window 111 along its perimeter, so that the portions of the first electrode 110 located on both sides of the clearance window in any direction can be connected and have the same potential.

[0122] Optionally, multiple first avoidance windows 111 are provided at intervals along the first direction.

[0123] For example, the second electrode 120 has a second clearance window 121, and the orthographic projection of the second clearance window 121 on a plane perpendicular to the stacking direction is surrounded by the orthographic projection of the second electrode 120 on a plane perpendicular to the stacking direction. In other words, the second electrode 120 forms a closure with respect to the second clearance window 121 along its perimeter, so that the portions of the second electrode 120 located on both sides of the clearance window in any direction can be connected and have the same potential.

[0124] Optionally, multiple second avoidance windows 121 are provided at intervals along the first direction.

[0125] Therefore, the setting of the avoidance window will not block the first electrode 110 or the second electrode 120 of the semiconductor device and thus affect the normal opening or closing of the device.

[0126] According to some embodiments of the second aspect of this application, the active region 200 includes a first sub-region 201 and a second sub-region 202. The orthographic projection of the first sub-region 201 on a plane perpendicular to the stacking direction and the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction at least partially overlap. The size of the first sub-region 201 in the stacking direction is smaller than the size of the second sub-region 202 in the stacking direction.

[0127] Optionally, the orthographic projection of the avoidance window on the plane perpendicular to the stacking direction falls within the orthographic projection range of the first sub-region 201 on the plane perpendicular to the stacking direction.

[0128] Optionally, the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction is set to overlap with the orthographic projection of the first sub-region 201 on a plane perpendicular to the stacking direction.

[0129] Optionally, the orthographic projection of the first sub-region 201 onto a plane perpendicular to the stacking aspect falls within the orthographic projection range of the avoidance window onto a plane perpendicular to the stacking aspect.

[0130] Therefore, by thinning and avoiding the first sub-region 201 corresponding to the window, the light loss of the active region 200 is reduced, the generation of photogenerated carriers is amplified, and the photo-triggering sensitivity of the semiconductor device is improved.

[0131] In some of these embodiments, please refer to Figure 10 The first electrode 110 has a first clearance window 111, which penetrates the first electrode 110 and extends into at least a portion of the first doped structure 210.

[0132] Optionally, the first clearance window 111 is set through the first doped structure 210.

[0133] Alternatively, the first clearance window 111 may extend into the second doped structure 220.

[0134] In some of these embodiments, please refer to Figure 11 The second electrode 120 has a second clearance window 121, which penetrates the second electrode 120 and extends into a portion of the third doped structure 230.

[0135] Thirdly, embodiments of this application provide an electronic device, which includes a device to be protected, a semiconductor device, and a light triggering device. The semiconductor device is the semiconductor device provided in any embodiment of the first aspect or any embodiment of the second aspect. The device to be protected is electrically connected to the semiconductor device. At least one of the semiconductor device and the device to be protected is connected in parallel with the light triggering device. The light triggering device is configured to excite light at least directed toward the avoidance window in response to a first threshold voltage.

[0136] Therefore, the semiconductor device can achieve avalanche breakdown through optical triggering when the protected device is under overvoltage conditions, forming an active and reliable breakdown to prevent the protected device from further developing into severe conditions such as overheating and explosion, thus achieving degraded protection of the protected device under overvoltage conditions. The electronic device provided in the third aspect of this application is not limited to withstand voltage protection of the protected device, but can also be adapted to degraded protection of the protected device under different severe conditions by adjusting the triggering mechanism of the optical triggering device.

[0137] Optionally, the electronic device includes a power electronic converter.

[0138] It is understood that since the electronic device provided in the third aspect of this application includes the semiconductor device provided in any of the first aspect or any of the second aspect, the electronic device in the third aspect of this application has the beneficial effects of the semiconductor device provided in any of the first aspect or any of the second aspect, which will not be repeated here.

[0139] Optionally, the light triggering device is disposed on the side of the semiconductor device where the clearance window is provided. For example, both the first electrode 110 and the second electrode 120 of the semiconductor device have clearance windows, and two light triggering devices are provided. Both light triggering devices are disposed in parallel with the semiconductor device, and the two light triggering devices are respectively used to excite light rays illuminating towards the first clearance window 111 and towards the second clearance window 121.

[0140] Optionally, the optical triggering device and the semiconductor device are connected via optical fiber. Specifically, the light-emitting end of the optical triggering device and the clearance window of the semiconductor device are connected via optical fiber to achieve directional transmission of light, enabling the semiconductor device to reliably break down when the optical triggering device meets the specified voltage conditions, thereby achieving fault protection for the device under protection.

[0141] It is understandable that the optical triggering device and the semiconductor device can also be connected through other existing optical interconnect structures to enable the transmission of light from the light-emitting end of the optical triggering device to the clearance window of the semiconductor device.

[0142] In one example, the electronic device is a submodule of a Modular Multilevel Converter (MMC), the device to be protected is a supporting capacitor, and the optical triggering device is connected in parallel with the supporting capacitor. Two semiconductor devices are used, serving as an upper and lower transistor. The first terminal of the upper transistor is connected to the first terminal of the supporting capacitor, and the second terminal of the lower transistor is connected to the second terminal of the supporting capacitor. The second terminal of the upper transistor is connected to the first terminal of the lower transistor, forming a first output terminal between the second terminal of the upper transistor and the first terminal of the lower transistor. A second output terminal is formed between the second terminal of the lower transistor and the second terminal of the supporting capacitor.

[0143] When the voltage across the supporting capacitor exceeds the first threshold voltage and the supporting capacitor is in an overvoltage state, the optical triggering device excites light to shine on the upper and lower transistors, causing the upper and lower transistors to break down reliably at the same time. As a result, the MMC submodule enters a reliable bypass conduction state, preventing the supporting capacitor from overheating and being damaged.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The device includes a first electrode, an active region, and a second electrode stacked sequentially. Both the first electrode and the second electrode are in contact with the active region. The active region includes a first doped structure, a second doped structure, and a third doped structure stacked along a direction away from the first electrode. The first doped structure and the third doped structure are of a first conductivity type, and the second doped structure is of a second conductivity type. The second doped structure includes a drift layer. In this configuration, at least one of the first electrode and the second electrode has a clearance window that extends through the electrode along its thickness direction. The active region can receive light through the clearance window to form photogenerated carriers. The active region also includes a control section disposed on one side of the drift layer in the stacking direction. The ion doping concentration of the control section is greater than or equal to the ion doping concentration of the drift layer. The orthographic projection of the clearance window on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the control section on a plane perpendicular to the stacking direction. The semiconductor device further includes a third electrode, wherein the first electrode is a collector, the second electrode is an emitter, and the third electrode is a gate, or the first electrode is an anode, the second electrode is a gate, and the third electrode is a cathode.

2. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the avoidance window onto a plane perpendicular to the stacking direction falls within the orthographic projection range of the control unit onto a plane perpendicular to the stacking direction.

3. The semiconductor device according to claim 1, characterized in that, The control unit is located on the side of the drift layer facing the avoidance window.

4. The semiconductor device according to claim 3, characterized in that, The first doped structure includes a first sub-section and a second sub-section stacked along a direction away from the first electrode, wherein the ion doping concentration of the first sub-section is greater than or equal to the ion doping concentration of the second sub-section.

5. The semiconductor device according to claim 1, characterized in that, The control unit is disposed on the side of the drift layer opposite to the second electrode, and the control unit forms an ohmic contact with the first electrode.

6. The semiconductor device according to claim 5, characterized in that, The orthographic projection of the control unit on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction.

7. The semiconductor device according to claim 3 or 5, characterized in that, The second doped structure further includes a buffer layer disposed on the side of the drift layer facing the first electrode, wherein the ion doping concentration of the buffer layer is greater than that of the drift layer.

8. The semiconductor device according to claim 7, characterized in that, The ion doping concentration of the buffer layer is greater than or equal to the ion doping concentration of the control unit.

9. A semiconductor device, characterized in that, include: First electrode; An active region is disposed on one side of the first electrode along the thickness direction and in contact with the first electrode. The active region includes a first doped structure, a second doped structure and a third doped structure stacked along the direction away from the first electrode. The first doped structure and the third doped structure are doped of a first conductivity type, and the second doped structure is doped of a second conductivity type. The second electrode is disposed on the side of the active region opposite to the first electrode and is in contact with the active region; Wherein, at least one of the first electrode and the second electrode has an avoidance window, the active region includes a first sub-region and a second sub-region, the size of the first sub-region in the stacking direction is less than or equal to the size of the second sub-region in the stacking direction, and the orthographic projection of the first sub-region on a plane perpendicular to the stacking direction at least partially overlaps with the orthographic projection of the avoidance window on a plane perpendicular to the stacking direction. The semiconductor device further includes a third electrode, wherein the first electrode is a collector, the second electrode is an emitter, and the third electrode is a gate, or the first electrode is an anode, the second electrode is a gate, and the third electrode is a cathode.

10. An electronic device, characterized in that, include: Device to be protected; The semiconductor device as described in any one of claims 1 to 9 is electrically connected to the device to be protected; A light triggering device is connected in parallel with at least one of the semiconductor device and the device to be protected, and the light triggering device is configured to excite light rays at least directed toward the avoidance window in response to a first threshold voltage.

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