Semiconductor device for image sensor and method of manufacturing semiconductor device for image sensor
By setting FD and TG on surfaces at different heights in a CMOS image sensor and growing an oxide layer on FD, the GIDL problem is solved and the performance of the image sensor is improved.
Patent Information
- Application Number
- CN202410733797.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-06
- Publication Date
- 2025-12-12
AI Technical Summary
Gate-induced drain leakage (GIDL) in CMOS image sensors leads to increased dark current and white defects, affecting image sensor performance.
By placing the floating diffusion (FD) and the transfer gate (TG) on surfaces at different heights, the sidewall space distance between the FD and TG is increased, and an oxide layer is grown on the FD to reduce the electric field strength of the TG sidewall space, thus avoiding the GIDL problem.
It effectively reduces the electric field intensity in the TG sidewall space, reduces dark current and white defects, and improves the performance of the image sensor.
Smart Images
Figure CN121126906A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the field of semiconductor, and more particularly, to a semiconductor device for an image sensor and a method of manufacturing a semiconductor device for an image sensor. BACKGROUND
[0002] Gate induced drain leakage (GIDL) generated in a complementary metal oxide semiconductor (CMOS) image sensor can cause problems such as an increase in dark current and an increase in white defects, which can lead to a performance degradation of the CMOS image sensor. Specifically, when the image sensor is in a transfer gate (TG) off state, a negative bias voltage needs to be applied to suppress the dark current generated under the TG, which can lead to a high voltage difference between the TG and a floating diffusion (FD) of the image sensor. Therefore, due to the GIDL problem, such a high voltage difference can generate dark current and punctate or cluster white defects in the FD region.
[0003] Therefore, how to avoid the GIDL problem in the image sensor becomes a problem to be solved urgently. SUMMARY
[0004] Embodiments of the present application provide a semiconductor device for an image sensor and related methods. According to the present application, the GIDL problem in the image sensor can be avoided.
[0005] According to a first aspect, embodiments of the present application provide a semiconductor device for an image sensor, the semiconductor device comprising: a semiconductor substrate, a transfer gate, and a floating diffusion; the semiconductor substrate comprising an upper surface for disposing the transfer gate and a lower surface opposite to the upper surface, wherein the upper surface comprises a first region and a second region; the transfer gate is formed on the first region, wherein at least a portion of the transfer gate is located above a first point in the first region, the height of the first point relative to the lower surface is greater than the height of the second region relative to the lower surface; the floating diffusion is formed in the semiconductor substrate, wherein the floating diffusion extends from the second region towards the lower surface.
[0006] Optionally, the image sensor can be a CMOS image sensor (CIS).
[0007] Optionally, a height of the first point relative to the lower surface is greater than or equal to a height of other points in the first region relative to the lower surface. In other words, the first point is one of the highest points in the first region relative to the lower surface.
[0008] According to the above technical solution, the FD and the TG are located on surfaces at different heights. That is, the distance between the sidewall space of the FD and the sidewall space of the TG can be increased, which can reduce the electric field intensity of the sidewall space of the TG. Therefore, the GIDL problem in the image sensor can be avoided.
[0009] In combination with the first aspect, in some embodiments, the semiconductor device further includes an oxide layer covering the second region.
[0010] According to the above technical solution, the oxide layer can be grown on the upper surface of the FD (i.e., the second region), which can avoid the out-diffusion occurring in the FD due to source and drain (S / D) annealing. Therefore, the charge leakage in the FD can be avoided.
[0011] In combination with the first aspect, in some embodiments, a thickness of the oxide layer covering the second region is greater than or equal to a thickness of the oxide layer covering the first region.
[0012] According to the above technical solution, after the oxide layer is grown on the upper surface of the semiconductor substrate, the thickness of the oxide layer remaining on the first region can be adjusted by etching. Therefore, the influence of the oxide layer on the subsequent ion implantation step can be reduced.
[0013] In combination with the first aspect, in some embodiments, the first region includes a recess, and at least a portion of the transfer gate is located in the recess.
[0014] According to the above technical solution, the TG can be a vertical transfer gate (VTG). Therefore, the saturated charge per unit volume of the semiconductor device can be increased.
[0015] In combination with the first aspect, in some embodiments, the second region is formed by etching the upper surface of the semiconductor substrate.
[0016] According to a second aspect, embodiments of the present application provide a method of manufacturing a semiconductor device for an image sensor, the method comprising: forming a semiconductor substrate, wherein the semiconductor substrate comprises an upper surface for disposing a transfer gate and a lower surface opposite to the upper surface, the upper surface comprising a first region and a second region; forming a transfer gate on the first region, wherein at least a portion of the transfer gate is located above a first point in the first region, the first point having a height relative to the lower surface greater than a height of the second region relative to the lower surface; forming a floating diffusion in the semiconductor substrate, wherein the floating diffusion extends from the second region towards the lower surface.
[0017] Optionally, the image sensor can be a CIS.
[0018] Optionally, the height of the first point relative to the lower surface is greater than or equal to a height of other points in the first region relative to the lower surface. In other words, the first point is one of the highest points in the first region relative to the lower surface.
[0019] In combination with the second aspect, in some embodiments, the method further comprises: forming an oxide layer covering the second region.
[0020] In combination with the second aspect, in some embodiments, a thickness of the oxide layer is greater than or equal to a thickness of an oxide layer covering the first region.
[0021] In combination with the second aspect, in some embodiments, the first region comprises a recess, and at least a portion of the transfer gate is located within the recess.
[0022] In combination with the second aspect, in some embodiments, the forming of the semiconductor substrate comprises: etching the upper surface of the semiconductor substrate to form the second region.
[0023] According to a third aspect, embodiments of the present application provide an image sensor comprising the semiconductor device of the first aspect or any possible implementation of the first aspect.
[0024] According to a fourth aspect, embodiments of the present application provide an electronic device comprising the image sensor of the third aspect or any possible implementation of the third aspect.
[0025] Optionally, the electronic device can comprise (or can be referred to as, but not limited to) the following devices, such as a digital camera, an industrial camera, a surveillance camera, a smartphone, a notebook computer, a computer, a tablet computer, a vehicle (such as a car, a truck, a bus, a train, etc.), a wearable device (such as a watch, glasses, a head-mounted device, etc.), or an apparatus comprising the above devices. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 A schematic of a CIS is shown.
[0027] Figure 2 A schematic of another CIS is shown.
[0028] Figure 3 A schematic of GIDL occurring in CMOS is shown.
[0029] Figure 4 An example of the GIDL problem in CIS is shown.
[0030] Figure 5 A relationship between GIDL and the distance of TG to FD is shown.
[0031] Figure 6 A schematic of a semiconductor device for an image sensor provided by some embodiments of the present application is shown.
[0032] Figure 7 An effect of the present application on the doping concentration of a semiconductor device is shown.
[0033] Figure 8 An effect of the present application on the electric field of a semiconductor device is shown.
[0034] Figure 9 A flowchart of a method of manufacturing a semiconductor device for an image sensor provided by some embodiments of the present application is shown.
[0035] Figure 10 An example of a flowchart for manufacturing a semiconductor device in the present application in practical applications is shown. DETAILED DESCRIPTION
[0036] The technical solutions in the present application are described below with reference to the accompanying drawings.
[0037] It should be noted that in the present application, unless the content clearly stipulates otherwise, when the term "comprises" or "includes" in the claims and / or the description is used in combination with, "one" can refer to "one", but also consistent with the meaning of "one or more", "at least one" and "one or more". Similarly, unless the content clearly stipulates otherwise, the word "another" can refer to at least the second or more.
[0038] In this application, the words "first", "second", etc. when used in relation to a term (e.g. a region or an operation step) are not intended to refer to an order or sequence of the term. For example, "first region" and "second region" refer to two different regions without specific indication, similarly, "first step" and "second step" refer to two different operation steps without specific indication, but it does not mean that the first step must occur before the second step. The true order depends on the logic of the two steps.
[0039] The term "coupled" or "connected" used herein can have several different meanings depending on the context in which these terms are used. For example, as used herein, the term "coupled" or "connected" can indicate that two elements or devices are directly connected to each other or connected to each other via one or more intermediate elements or devices according to a specific context. The term "and / or" in this document refers to any one or more items in the list.
[0040] In embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The term "and / or" describes the relationship between associated objects and means that there can be three relationships. For example, A and / or B can represent the following three cases: only A exists, A and B exist at the same time, only B exists, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between associated objects. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of one or more items. For example, at least one of a, b and c can represent: a; b; c; a and b; a and c; b and c, or a, b and c, where a, b and c can be singular or plural.
[0041] In order to facilitate understanding of embodiments of the present application, the terms related to the present application are simply explained as follows.
[0042] 1. CMOS image sensor (CIS)
[0043] An image sensor (also referred to as an imager) is a sensor that detects and transmits information used to form an image. It does this by converting the variable attenuation of light waves (as they pass through or reflect off an object) into a signal (i.e., a small array of electrical currents that convey information). These waves can be light or other electromagnetic radiation. Image sensors can be used in electronic imaging devices of both analog and digital types, which can include (or can be referred to as, but are not limited to) devices such as digital cameras, industrial cameras, security cameras, smartphones, laptops, computers, tablets, vehicles (e.g., cars, trucks, buses, trains, etc.), wearable devices (e.g., watches, glasses, headsets, etc.), or apparatuses that include the aforementioned devices. Two main types of digital image sensors are charge-coupled devices (CCDs) and active pixel sensors (i.e., CISs).
[0044] A CIS is configured by arranging a plurality of pixels in a necessary pattern, where a pixel includes a photo diode (PD) and at least one metal oxide semiconductor (MOS) transistor. The PD is a photoelectric conversion element that generates and accumulates signal charges according to the amount of light received, and the at least one MOS transistor is an element for transferring signal charges from the PD. In a pixel, signal charges are obtained by irradiating light, and the obtained signal charges are output as a pixel signal from the corresponding pixel. The pixel signal output above is processed by a given signal processing circuit, and output as an image signal and / or a video signal to the outside.
[0045] The MOS transistor includes a transfer gate (TG) and a floating diffusion (FD). The FD is a region for storing signal charges transferred from the PD. The PD can be formed in a semiconductor substrate (e.g., a silicon substrate) to extend from an upper surface of the semiconductor substrate toward a lower surface of the semiconductor substrate. The TG is used to control whether signal charges are transferred from the PD to the FD. The TG can be formed on the upper surface of the semiconductor substrate, and at least a portion of the TG is located above the upper surface of the semiconductor substrate.
[0046] Note that the MOS transistor and / or the CIS can include other components (e.g., a reset gate, a selection gate, a source follower readout transistor, etc.), but these have been omitted for clarity.
[0047] Figure 1 and Figure 2 Schematic diagrams of two CISs with different TG structures are shown.
[0048] Figure 1The CIS100 is shown, comprising a semiconductor substrate 110, TG 120, FD 130, and PD 140. (As shown...) Figure 1 As shown, the upper surface of the semiconductor substrate 110 is covered with an oxide layer 150. The oxide layer 150 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride (SiON).
[0049] PD 140 is formed in semiconductor substrate 110, below the upper surface of semiconductor substrate 110.
[0050] FD 130 is formed in the semiconductor substrate 110, below the upper surface of the semiconductor substrate 110. Specifically, FD 130 is formed on the upper surface of the semiconductor substrate 110 and extends in the depth direction (i.e., extends toward the lower surface of the semiconductor substrate 110). In other words, the upper surface of FD 130 coincides with at least a portion of the upper surface of the semiconductor substrate 110.
[0051] TG 120 is formed on the upper surface of the semiconductor substrate 110. Specifically, TG 120 is connected to the upper surface of the semiconductor substrate 110 through an oxide layer 150. Furthermore, TG 120 is completely located above at least a portion of the upper surface of the semiconductor substrate 110. Therefore, Figure 1 The TG 120 shown can also be referred to as a planar TG.
[0052] like Figure 1 As shown, TG 120 includes sidewall spaces 121 located at both ends of TG 120 in the horizontal direction.
[0053] Figure 2 A CIS200 is shown, comprising a semiconductor substrate 110, TG 220, FD 130, PD 241, and PD 242, wherein PD 241 and PD 242 may be referred to as PD 140. Figure 2 In the middle, to and Figure 1 The corresponding components are assigned the same symbol, and duplicate descriptions are omitted.
[0054] like Figure 2 As shown, TG 220 is formed on the upper surface of the semiconductor substrate 110. Specifically, TG 220 is connected to the upper surface of the semiconductor substrate 110 through an oxide layer 150. However, only a portion of TG 220 is located above the upper surface of the semiconductor substrate 110. A recess exists on the upper surface of the semiconductor substrate 110, and a portion of TG 220 is formed within this recess. This portion of TG 220 located within the recess is also connected to the semiconductor substrate 110 through the oxide layer 150. Therefore, Figure 2The TG 220 shown in the middle can also be referred to as a vertical TG (VTG).
[0055] As Figure 2 shown, the sidewall spaces 221 included in the TG 220 are located at both ends in the horizontal direction of the TG 120, above the upper surface of the semiconductor substrate 110.
[0056] 2. Gate induced drain leakage (GIDL)
[0057] The GIDL effect is a leakage mechanism in a MOS field effect transistor (MOSFET) due to a large field effect at the drain junction. The GIDL current can be used to indicate the severity of the GIDL problem. The GIDL current satisfies the following equation:
[0058] I D =A×E s ×exp[–3BT OX / (V DG –1.2)]
[0059] I D is the GIDL current. E s is the maximum electric field on the surface of the semiconductor substrate. T OX is the thickness of the gate oxide layer. V DG is the voltage of the drain and gate. A and B are constants for indirect phonon-assisted tunneling.
[0060] Figure 3 A schematic diagram showing GIDL occurring in a CMOS is shown. As Figure 3 shown, since the maximum electric field on the surface of the semiconductor substrate is usually located near the sidewall spaces of the TG, the GIDL problem usually occurs in these areas, which are indicated by the dashed boxes in the figure.
[0061] Specifically, when the image sensor is in a transfer gate (TG) off state, a negative bias voltage needs to be applied to suppress the dark current generated under the TG, which can cause a high voltage difference between the TG and the floating diffusion (FD) of the image sensor. Therefore, due to the GIDL problem, this high voltage difference can generate dark current and point or cluster white defects in the FD region. Figure 4 An example of the GIDL problem in a CIS is shown. As Figure 4 shown, the FD sharing pixel with the GIDL problem has a higher output code than the surrounding pixels.
[0062] In summary, the GIDL generated in the CIS can cause problems such as an increase in dark current, an increase in white defects, and the like, thereby causing serious problems such as a decrease in image quality. Therefore, how to avoid the GIDL problem in the image sensor becomes a problem to be solved urgently.
[0063] To avoid the GIDL problem, various methods are used to reduce the electric field on the silicon surface, such as using a lightly doped drain (LDD) structure, reducing the overlap gate-drain capacitance (Cgd), and using an elevated source drain (ESD) structure (also referred to as an elevated source / drain structure). As the integration level of the pixels in the CIS increases, the sidewall space of the TG decreases, thereby causing the distance between the FD and the TG to decrease. The short distance between the TG and the FD in the CIS still causes a high electric field to exist near the sidewall space of the TG, which makes it impossible to effectively avoid the GIDL problem. Figure 5 The relationship between the GIDL and the distance of the TG to the FD is shown. As shown in Figure 5 The GIDL can be avoided by increasing the distance between the VTG and the FD. Therefore, if the distance between the TG and the FD can be increased, the GIDL can be avoided.
[0064] Therefore, the present application provides a semiconductor device for an image sensor, in which the FD and the TG are located on surfaces at different heights. That is, the distance between the sidewall space of the FD and the TG can be increased, which can reduce the electric field strength at the sidewall space of the TG. Therefore, the GIDL problem in the image sensor can be avoided.
[0065] Figure 6 A schematic diagram of a semiconductor device for an image sensor provided by some embodiments of the present application is shown.
[0066] Reference Figure 6 The semiconductor device can include a semiconductor substrate 601, a TG 602, and an FD 603. The semiconductor substrate 601 can include an upper surface and a lower surface. The surface of the semiconductor substrate 601 for disposing the TG 602 can be referred to as the upper surface of the semiconductor substrate 601, and correspondingly, the surface opposite to the surface can be referred to as the lower surface of the semiconductor substrate 601. Optionally, the semiconductor substrate 601 can be a silicon substrate. It should be noted that the semiconductor substrate 601 can be made of other materials, such as sapphire, silicon carbide, silicon nitride, and the like.
[0067] As Figure 6As shown, the upper surface includes a first region for disposing the TG 602 and a second region for disposing the FD 603, the height of the first region relative to the lower surface is greater than the height of the second region relative to the lower surface. In other words, the TG 602 and the FD 603 are located on surfaces of different heights. The first region can be referred to as a convex surface, a convex portion, a bump or a high portion on the upper surface of the semiconductor substrate 601, and / or the second region can be referred to as a concave surface, a recess, a defect or a low portion on the upper surface of the semiconductor substrate 601.
[0068] In some embodiments of the present application, the second region can be formed by etching the upper surface of the semiconductor substrate 601. For example, a step of silicon etching can be performed on the upper surface of the semiconductor substrate 601, thus, the etched part can form the above-mentioned second region, and the unetched part can form the above-mentioned first region.
[0069] The TG 602 is formed on the first region, and at least a portion of the TG 602 is located above the first region. In other words, the projection of the TG 602 in the vertical direction is within the first region. Specifically, the TG 602 can be connected to the first region through the oxide layer 605.
[0070] In some embodiments of the present application, the TG 602 can be a VTG. That is, as shown in FIG. 6B, the TG 602 can include a plurality of TGs 602a, 602b, 602c and 602d arranged in a vertical direction. Figure 6 As shown, the first region can include a recess, and a portion of the TG 602 is located within the recess. It should be noted that, Figure 6 The structure of the TG 602 shown is only an example, but the TG can also have other structures, which are not limited in the present application. For example, the TG 602 can be a planar TG.
[0071] The FD 603 is formed in the semiconductor substrate 601, and the FD 603 extends from the second region toward the lower surface. In other words, the upper surface of the FD 603 coincides with at least a portion of the second region, and the projection of the FD 603 is within the projection of the second region in the vertical direction.
[0072] Therefore, the TG 602 and the FD 603 are located on surfaces of different heights. Therefore, the distance between the FD and the sidewall space of the TG can be increased, which can reduce the electric field strength of the sidewall space of the TG.
[0073] Figure 7 The influence of the present application on the doping concentration of the semiconductor device is shown. The left graph Figure 7 (a) shows the doping concentration distribution of the semiconductor substrate when the TG and the FD are disposed at the same height on the upper surface, and the right graph Figure 7Figure (b) shows the doping concentration distribution of the semiconductor substrate (i.e., the semiconductor device provided in this application) when TG and FD are set at different heights on the upper surface. Figure 7 As shown, the semiconductor device provided in this application reduces the doping concentration on the semiconductor substrate surface near the sidewall space of the TG. This is because, when the doping concentration in the FD remains constant, the distance between the sidewall spaces of the FD and TG becomes greater. In other words, the distance between the sidewall spaces of the FD and TG is inversely proportional to the doping concentration.
[0074] The electric field strength is proportional to the doping concentration. Therefore, the electric field strength on the semiconductor substrate surface near the sidewall space of TG can be reduced.
[0075] Figure 8 This illustrates the effect of this application on the electric field of a semiconductor device. (Left figure) Figure 8 As shown in (a) and (b), where (b) is a magnified view of the circular region in (a), the right figure shows the electric field distribution of the semiconductor substrate when TG and FD are set at the same height on the upper surface. Figure 8 As shown in (c) and (d), where (d) is a magnified view of the circular region in (c), the electric field distribution of the semiconductor substrate (i.e., the semiconductor device provided in this application) is shown when TG and FD are set at different heights on the upper surface. Figure 8 As shown, the electric field strength on the semiconductor substrate surface near the TG sidewall space in (c) is 7.99 × 10⁻⁶. 5 The electric field strength on the semiconductor substrate surface near the TG sidewall space in (d) is 7.22 × 10 V / cm. 5 V / cm. In other words, the semiconductor device provided in this application reduces the electric field strength on the surface of the semiconductor substrate near the TG sidewall space.
[0076] As mentioned earlier, the GIDL current is proportional to the maximum electric field on the surface of the semiconductor substrate. Therefore, GIDL problems in image sensors can be avoided.
[0077] In some embodiments of this application, the semiconductor device may further include an oxide layer 604 covering the second region. In other words, the oxide layer 604 can be grown on the upper surface (i.e., the second region) of the FD 603, which can prevent outward diffusion in the FD 603 due to source and drain (S / D) annealing. Therefore, charge leakage in the FD 603 can be avoided.
[0078] In some embodiments of the application, the thickness of the oxide layer 604 can be greater than or equal to the thickness of the oxide layer 605 covering the first region. For example, the oxide layer 604 and the oxide layer 605 can be grown together, and after the oxide layer has been grown on the upper surface of the semiconductor substrate 601, the thickness of the oxide layer 605 remaining on the first region can be adjusted by etching. Thus, the impact of the oxide layer on subsequent ion implantation steps can be reduced.
[0079] It should be noted that for simplicity, the semiconductor substrate 601, the TG 602, the FD 603, the oxide layer 604, and the oxide layer 605 are shown, but the semiconductor device can include one or more other components, which are not limited by the present application. For example, the semiconductor device can also include a PD 606 as shown, and / or the semiconductor device can also include one or more other components omitted in the above description. Figure 6 Figure 6 It should be noted that for simplicity, the semiconductor substrate 601, the TG 602, the FD 603, the oxide layer 604, and the oxide layer 605 are shown, but the semiconductor device can include one or more other components, which are not limited by the present application. For example, the semiconductor device can also include a PD 606 as shown, and / or the semiconductor device can also include one or more other components omitted in the above description.
[0080] Figure 9 A flowchart of a method of manufacturing a semiconductor device for an image sensor is shown.
[0081] In S901, a semiconductor substrate is formed.
[0082] The semiconductor substrate can include an upper surface on which the TG is disposed and a lower surface opposite to the upper surface. The upper surface can include a first region and a second region. The height of the first region relative to the lower surface is greater than the height of the second region relative to the lower surface.
[0083] In some embodiments of the application, the second region can be formed by etching the upper surface of the semiconductor substrate.
[0084] In S902, a TG is formed on the first region.
[0085] At least a portion of the TG is located above the first region.
[0086] In some embodiments of the application, the TG can be a VTG. That is, the first region can include a recess in which a portion of the TG is located.
[0087] In S903, an FD is formed in the semiconductor substrate.
[0088] The FD extends from the second region toward the lower surface.
[0089] In some embodiments of the application, the method can further include forming an oxide layer covering the second region. For example, a pad oxidation step can be performed to grow an oxide layer on the upper surface of the FD (i.e., the second region).
[0090] In some embodiments of the present application, the thickness of the oxide layer can be greater than or equal to the thickness of the oxide layer covering the first region. For example, after the liner oxidation step described above, an oxide etching step can be performed to adjust the thickness of the remaining oxide on the PD.
[0091] It should be noted that in practical applications, the above steps can be combined and / or exchanged in any order. For example, after the TG has been formed on the semiconductor substrate and during the FD is being formed on the semiconductor substrate, a silicon etching step can be performed to form the second region on the upper surface of the semiconductor substrate. Specifically, the silicon etching step can be performed between the FD photolithography step and the FD ion implantation step. The FD photolithography step and the FD ion implantation step are two steps of forming the FD. In other words, after the position where the FD is to be formed has been determined by the FD mask, a portion of the semiconductor substrate at the position can be etched to form a recess on the upper surface, and then ions can be implanted into the recess to form the FD. Therefore, the TG and the FD can be formed on surfaces at different heights.
[0092] Figure 10 An example of a flowchart for manufacturing the semiconductor device in the present application in practical applications is shown. As shown in Figure 10 The silicon etching, liner oxidation and oxide etching are three new steps to form the specific structure of the semiconductor device provided in the present application. The silicon etching step uses a conventional FD mask and the FD ion implantation step is performed after the silicon etching step. The liner oxidation step is adopted to avoid the out-diffusion that occurs in the FD region due to S / D annealing. The purpose of the oxide etching step is to adjust the thickness of the remaining oxide on the PD to minimize the impact on the subsequent ion implantation step, such as the pinning (PIN) ion implantation.
[0093] Embodiments of the present application also provide an image sensor. The image sensor can include one or more semiconductor devices provided in the present application, such as the semiconductor device as shown in Figure 6
[0094] Embodiments of the present application also provide an electronic device. The electronic device can include the image sensor provided in the present application.
[0095] Optionally, the electronic device can include (or can be referred to but not limited to) the following devices, such as a digital camera, an industrial camera, a security camera, a smartphone, a notebook computer, a computer, a tablet computer, a vehicle (such as a car, a truck, a bus, a train, etc.), a wearable device (such as a watch, glasses, a head-mounted device, etc.), or an apparatus including the above devices.
[0096] The present application includes various embodiments, including not only method embodiments, but also other embodiments, such as semiconductor device embodiments and image sensor related embodiments. Embodiments can incorporate features disclosed herein, alone or in combination.
[0097] Features disclosed herein in the context of any particular embodiment can also or instead be implemented in other embodiments. For example, method embodiments can also or instead be implemented in semiconductor device and / or image sensor embodiments.
[0098] While the present application has been with reference to illustrative embodiments, the present application is not to be construed as limited thereto. Various modifications and combinations of the illustrative embodiments along with other embodiments of the present application will be apparent to those skilled in the art in view of the foregoing description.
[0099] The above merely illustrates some specific implementation manners of the present application, and is not used to limit the protection scope of the present application. Changes or substitutions within the technical scope of the present application, which are easily conceived by those skilled in the art in view of the present application, should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A semiconductor device for an image sensor, characterized by, comprising: a semiconductor substrate (601), a transfer gate (602), and a floating diffusion (603); wherein the semiconductor substrate (601) includes an upper surface for disposing the transfer gate (602) and a lower surface opposite the upper surface, wherein the upper surface includes a first region and a second region; the transfer gate (602) is formed on the first region, wherein at least a portion of the transfer gate (602) is located above a first point in the first region, the first point having a height relative to the lower surface that is greater than a height of the second region relative to the lower surface; the floating diffusion (603) is formed in the semiconductor substrate (601), wherein the floating diffusion (603) extends from the second region toward the lower surface.
2. The semiconductor device according to claim 1, wherein the height of the first point relative to the lower surface is greater than or equal to a height of other points in the first region relative to the lower surface.
3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device further includes an oxide layer (604) covering the second region.
4. The semiconductor device according to claim 3, wherein a thickness of the oxide layer (604) covering the second region is greater than or equal to a thickness of an oxide layer (605) covering the first region.
5. The semiconductor device according to any one of claims 1 to 4, wherein the first region includes a recess, at least a portion of the transfer gate (602) is located within the recess.
6. The semiconductor device according to any one of claims 1 to 5, wherein the second region is formed by etching the upper surface of the semiconductor substrate (601).
7. A method of manufacturing a semiconductor device for an image sensor, characterized by, comprising: forming a semiconductor substrate, wherein the semiconductor substrate includes an upper surface for disposing a transfer gate and a lower surface opposite the upper surface, the upper surface including a first region and a second region; forming the transfer gate on the first region, wherein at least a portion of the transfer gate is located above a first point in the first region, the first point having a height relative to the lower surface that is greater than a height of the second region relative to the lower surface; forming a floating diffusion in the semiconductor substrate, wherein the floating diffusion extends from the second region toward the lower surface.
8. The method of claim 7, wherein, the height of the first point relative to the lower surface is greater than or equal to a height of other points in the first region relative to the lower surface.
9. The method according to claim 7 or 8, characterized in that, the method further comprising: forming an oxide layer covering the second region.
10. The method of claim 9, wherein, a thickness of the oxide layer is greater than or equal to a thickness of an oxide layer covering the first region.
11. The method according to any one of claims 7 to 10, characterized in that, the first region includes a recess, at least a portion of the transfer gate is located within the recess.
12. The method according to any one of claims 7 to 11, characterized in that, the forming a semiconductor substrate includes: etching the upper surface of the semiconductor substrate to form the second region.
13. An image sensor, comprising: at least one semiconductor device according to any one of claims 1 to 6.