Shifting register, driving circuit, driving method and display device

Abstract

The invention provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises: an input circuit configured to provide a clock signal from a clock end to a first node under the control of an input signal from an input end; a control circuit configured to provide a first power supply voltage of a first power supply to the first node under the control of an input signal and a clock signal; and an output circuit configured to provide the first power supply voltage or the second power supply voltage of the second power supply to the output end as an output signal under the control of the potential of the first node and the input signal.

Description

Shift register, driving circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Art

[0002] Current shift register circuits can achieve high-level shifting and high-level pulse width modulation, but they typically have complex circuit component connections and occupy a large space. Furthermore, due to the unstable pull-down capability of shift register circuits, the voltage waveforms output by each shift register stage in the driver circuit may vary, thus affecting display quality.

[0003] Summary of the Invention

[0004] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising: an input circuit configured to provide a clock signal from a clock end to a first node under the control of an input signal from an input end; a control circuit configured to provide a first power supply voltage of a first power supply to the first node under the control of the input signal and the clock signal; and an output circuit configured to provide the first power supply voltage or the second power supply voltage of a second power supply to an output end as an output signal under the control of the potential of the first node and the input signal.

[0006] According to an embodiment of the present disclosure, the output circuit is configured to provide the first power supply voltage or the second power supply voltage of the second power supply to the output terminal as an output signal under the control of the potential of the first node and the input signal, including: providing the first power supply voltage to the output terminal as an output signal under the control of the potential of the first node; and providing the second power supply voltage to the output terminal as an output signal under the control of the potential of the first node and the input signal.

[0007] According to an embodiment of the present disclosure, the output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; wherein, the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the output end; the control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the output end, and the second electrode of the second transistor is electrically connected to the second power supply; the control electrode of the third transistor is electrically connected to the input end, and the first electrode of the third transistor is electrically connected to the first node; the control electrode of the fourth transistor is electrically connected to the input end, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply; the first end of the first capacitor is electrically connected to the first power supply, and the second end of the first capacitor is electrically connected to the first node.

[0008] According to an embodiment of the present disclosure, the first transistor and the second transistor are transistors of different types.

[0009] According to an embodiment of the present disclosure, the control electrode of the second transistor includes a first control electrode and a second control electrode, the first control electrode of the second transistor is electrically connected to the second node, and the second control electrode of the second transistor is electrically connected to the third power supply; the control electrode of the fourth transistor includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor is electrically connected to the input terminal, and the second control electrode of the fourth transistor is electrically connected to the third power supply; wherein the third power supply voltage is less than the second power supply voltage.

[0010] According to an embodiment of the present disclosure, the input circuit is configured to provide a clock signal from a clock end to a first node under the control of an input signal from an input end, including: under the control of a first level of the input signal, when the clock signal switches from the first level to the second level, providing the second level of the clock signal to the first node.

[0011] According to an embodiment of the present disclosure, the input circuit includes a fifth transistor, a sixth transistor and a second capacitor; wherein the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the clock terminal, and the second electrode of the fifth transistor is electrically connected to the first node; the first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the clock terminal; the control electrode of the sixth transistor is electrically connected to the input terminal, the first electrode of the sixth transistor is electrically connected to the first power supply, and the second electrode of the sixth transistor is electrically connected to the third node.

[0012] According to an embodiment of the present disclosure, a control circuit is configured to provide a first power supply voltage of a first power supply to a first node under the control of an input signal and a clock signal, including: providing the first power supply voltage to the first node under the control of a second level of the clock signal and a second level of the input signal to control the potential of the first node to be a first level; and controlling the potential of the first node to remain at the first level under the control of the second level of the clock signal and a first level of the input signal.

[0013] According to an embodiment of the present disclosure, the control circuit includes a seventh transistor, an eighth transistor, and a third capacitor; wherein, a control electrode of the seventh transistor is electrically connected to a clock terminal, a first electrode of the seventh transistor is electrically connected to an input terminal, and a second electrode of the seventh transistor is electrically connected to a fourth node; a control electrode of the eighth transistor is electrically connected to the fourth node, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the first power supply; a first end of the third capacitor is electrically connected to the fourth node, and a second end of the third capacitor is electrically connected to the first power supply

[0014] According to a second aspect, the present disclosure provides a driving circuit, including M cascaded shift registers, an input terminal of the m-th shift register is electrically connected to an output terminal of the (m - 1)-th shift register, 1 < m ≤ M, m is an integer, and M is an integer greater than 1.

[0015] According to an embodiment of the present disclosure, the driving circuit further includes a first clock signal line and a second clock signal line; wherein, the m-th shift register is electrically connected to the first clock signal line, and the (m + 1)-th shift register is electrically connected to the second clock signal line.

[0016] According to a third aspect, the present disclosure provides a display device, including the driving circuit provided by the embodiments of the present disclosure.

[0017] According to a fourth aspect, the present disclosure provides a driving method, applied to the shift register provided by any one of the embodiments of the present disclosure, including: a first stage, the input signal is at a first level and the clock signal is at a second level; a second stage, the input signal is at a first level and the clock signal is at a first level; a third stage, the input signal is at a first level and the clock signal is at a second level; a fourth stage, the input signal is at a second level and the clock signal is at a first level; and a fifth stage, the input signal is at a second level and the clock signal is at a second level.

[0018] According to an embodiment of the present disclosure, in the first stage, under the control of the first level of the input signal and the second level of the clock signal, the second level of the clock signal is provided to the first node; and under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as an output signal.

[0019] According to an embodiment of the present disclosure, in the second stage, under the control of the first level of the input signal and the first level of the clock signal, the potential of the first node is controlled to be maintained at the second level; and under the control of the potential of the first node, the first power supply voltage is provided to the output end as an output signal.

[0020] According to an embodiment of the present disclosure, in the third stage, under the control of the first level of the input signal and the second level of the clock signal, the second level of the clock signal is provided to the first node; and under the control of the potential of the first node, the first power supply voltage is provided to the output end as an output signal.

[0021] According to an embodiment of the present disclosure, in the fourth stage, under the control of the second level of the input signal and the first level of the clock signal, the potential of the first node is controlled to be maintained at the second level; and under the control of the potential of the first node, the first power supply voltage is provided to the output end as an output signal.

[0022] According to an embodiment of the present disclosure, in the fifth stage, under the control of the second level of the input signal and the second level of the clock signal, the first power supply voltage is provided to the first node; and under the control of the potential of the first node, the second power supply voltage is provided to the output end as an output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1A is a schematic diagram of the structure of an exemplary shift register;

[0024] FIG1B is a signal timing diagram of an exemplary shift register;

[0025] FIG2 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

[0026] FIG3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0027] FIG4A is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0028] FIG4B is a schematic diagram of a simulation of voltages in a shift register according to an embodiment of the present disclosure;

[0029] FIG5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0030] FIG6 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0031] FIG7 is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0032] FIG8A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0033] FIG8B is a signal timing diagram of a driving circuit according to an embodiment of the present disclosure;

[0034] FIG9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure; and

[0035] FIG10 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0037] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0038] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0039] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain are interchangeable. In the embodiments of the present disclosure, based on their functions, the gate can be referred to as the control electrode, one of the source and drain can be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0040] Furthermore, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are used solely to distinguish between the different amplitudes of the two power supply voltages. For example, the following description uses the example of a relatively high voltage as the "first power supply voltage" and relatively low voltages as the "second power supply voltage" and "third power supply voltage." Those skilled in the art will appreciate that the present disclosure is not limited to this example.

[0041] It should be noted that in the description of the embodiments of the present disclosure, INPUT can represent both an input signal terminal and an input signal provided by the input signal terminal. Similarly, the symbol CK can represent both a clock terminal and a clock signal provided by the clock terminal, OUT can represent both an output signal terminal and an output signal output by the output signal terminal, and VGH, VGL1, and VGL2 can represent both a power supply terminal and a power supply voltage provided by the power supply terminal. For example, the power supply VGH can provide a high-level voltage, and the power supplies VGL1 and VGL2 can provide a low-level voltage. The following embodiments are the same and will not be repeated here.

[0042] Fig. 1A is a schematic diagram of the structure of an example shift register. Fig. 1B is a signal timing diagram of the example shift register shown in Fig. 1A.

[0043] Fig. 1A shows a shift register 100. As shown in Fig. 1A, the shift register 100 includes 16 TFT transistors and 3 capacitors.

[0044] FIG1B shows the timing change process of each signal of the shift register 100 in FIG1A.

[0045] As shown in FIG1A , the shift register 100 includes 16 P-type transistors and 3 capacitors.

[0046] In the first stage S1, ESTV is at a high level, ECK is at a low level, and ECB is at a high level. Under the control of the low level of ECK and the power supply voltage VGL, the high level signal of ESTV is written to the control electrode of the second transistor M2 through the conductive first transistor M1, and then written to the control electrodes of the tenth transistor M10 and the eighth transistor M8 through the twelfth transistor M12, causing the second transistor M2, the eighth transistor M8, and the tenth transistor M10 to be turned off. The power supply voltage VGL controls the conduction of the sixth transistor M6 through the conductive third transistor M3 and the eleventh transistor M11. The high level signal of ECB turns off the seventh transistor M7. At this time, the ninth transistor M9 maintains the state of the previous stage, and the output terminal Eout is in a floating state. At this time, the output terminal Eout maintains the low level signal output of the previous stage.

[0047] In the second phase S2, ECB goes low and ECK goes high. Under the control of ECB's low level, the ECB low signal passes through the sixth transistor M6 and the seventh transistor M7, turning on the ninth transistor M9, causing the output terminal Eout to output a high level. When ECB goes high and ECK goes low, the voltage stored in capacitor C3 keeps the ninth transistor M9 turned on, causing the output terminal Eout to output a high level.

[0048] In the third phase S3, ESTV is at a low level and ECK is at a low level. Under the control of the low level of ECK and the power supply voltage VGL, the power supply voltage VGL controls the sixth transistor M6 to turn on through the turned-on third transistor M3 and the eleventh transistor M11. The low-level signal of ESTV is written into the control electrode of the eighth transistor M8 through the turned-on first transistor M1, turning on the eighth transistor M8. The power supply voltage VGH can control the ninth transistor M9 to turn off through the eighth transistor M8, causing the output terminal Eout to output a low level.

[0049] In the fourth phase S4, ESTV is at a low level, ECB is at a low level, and ECK is at a high level. Under the control of the high level of ECK, the first transistor M1 and the twelfth transistor M12 are turned off, and the ESTV signal cannot be written. The tenth transistor M10 and the eighth transistor M8 remain in the on state of the previous phase. The power supply voltage VGH controls the ninth transistor M9 to be turned off through the eighth transistor M8, causing the output terminal Eout to output a low level.

[0050] Since the tenth transistor M10 is a P-type transistor, the P-type transistor has a weak conduction capability for low levels, which causes the voltage output by the output terminal Eout in the third stage S3 to slowly change from a high level to a low level, resulting in a step phenomenon in the falling edge of the output voltage Eout, as shown in Figure 1B.

[0051] In the shift register 100, the step phenomenon on the falling edge of the output voltage Eout is affected by the TFT characteristic parameter Vth of the first transistor M1, the tenth transistor M10, and the twelfth transistor M12. Because the driving circuit includes multiple cascaded shift registers, there are differences between the transistors in different shift registers, and the step state exhibited by the falling edge of the output voltage Eout output by different stages of the shift registers is different. Because the waveform of the output voltage Eout outputted by each different stage of the shift register changes from a high level to a low level is different, this can cause horizontal stripes to appear on a display screen driven by a driving circuit including multiple cascaded shift registers 100.

[0052] Since the step state of the falling edge of the output voltage Eout will lead to a poor display image, it is necessary to eliminate the step phenomenon in the output voltage Eout so that the falling edge of the output voltage Eout output by each stage of the shift register can quickly jump from a high level to a low level, so that the waveform of the output voltage Eout output by each different stage of the shift register is the same, thereby improving the display image.

[0053] To address the above issues, the present disclosure provides a shift register that uses P-type TFT transistors as pull-up transistors to output a high level, and N-type TFT transistors as pull-down transistors to output a low level. The output circuit uses a combination of P-type and N-type transistors, which are directly controlled by input signals and clock signals to achieve shifted output and pulse-width modulation of high-level signals.

[0054] FIG2 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.

[0055] As shown in FIG. 2 , the shift register 200 includes an input circuit 210 , a control circuit 220 , and an output circuit 230 .

[0056] In the embodiment of the present disclosure, the input circuit 210 is electrically connected to the clock terminal CK, and the input circuit 210 is electrically connected to the input terminal INPUT. The control circuit 220 is electrically connected to the first power supply VGH, the control circuit 220 is electrically connected to the clock terminal CK, and the control circuit 220 is electrically connected to the input terminal INPUT. The output circuit 230 is electrically connected to the input terminal INPUT, the output circuit 230 is electrically connected to the first power supply VGH, the output circuit 230 is electrically connected to the second power supply VGL1, and the output circuit 230 is electrically connected to the output terminal OUT.

[0057] The input circuit 210 , the control circuit 220 , and the output circuit 230 are electrically connected to the first node N1 .

[0058] In the embodiment of the present disclosure, the input circuit 210 is configured to provide a clock signal CK from a clock terminal CK to a first node N1 under the control of an input signal INPUT from an input terminal INPUT. The control circuit 220 is configured to provide a first power supply voltage VGH of a first power supply VGH to the first node N1 under the control of the input signal INPUT and the clock signal CK. The output circuit 230 is configured to provide the first power supply voltage VGH or the second power supply voltage VGL1 of a second power supply VGL1 to an output terminal OUT as an output signal OUT under the control of the potential of the first node N1 and the input signal INPUT.

[0059] In the embodiment of the present disclosure, the first level can be a high level, and the second level can be a low level. When the input signal INPUT is at a high level, if the clock signal CK jumps from a high level to a low level, the input circuit 210 can provide the low level of the clock signal CK to the first node N1, and the control circuit 220 cannot provide the first power supply voltage VGH to the first node N1. Under the control of the clock signal CK, the input circuit 210 pulls down the potential of the first node N1, causing the output circuit 230 to output a high-level signal.

[0060] When the input signal INPUT is at a high level and the clock signal CK is at a high level, the input circuit 210 and the control circuit 220 are unable to provide a voltage signal to the first node N1. At this time, the first node N1 maintains the low level state of the previous stage, and the control output circuit 230 outputs a high level. When the input signal INPUT is at a low level and the clock signal CK is at a high level, the input circuit 210 and the control circuit 220 are still unable to provide a voltage signal to the first node N1. The first node N1 maintains the low level state of the previous stage, and the control output circuit 230 outputs a high level signal.

[0061] The input circuit 210 is also electrically connected to a first power supply voltage VGH. When both the input signal INPUT and the clock signal CK are at a low level, under the control of the first power supply voltage VGH, the input circuit 210 cannot provide the low level of the clock signal CK to the first node N1. In this case, the control circuit 220 can provide the first power supply voltage VGH to the first node N1, thereby raising the potential of the first node N1 and causing the output circuit 230 to output a low-level signal.

[0062] According to an embodiment of the present disclosure, the shift register 200 changes the potential of the first node N1 under the control of the input signal INPUT and the clock signal CK, so that the output circuit 230 outputs a high-level signal or a low-level signal.

[0063] The shift register 200 outputs a high-level signal under the control of the clock signal CK, and can quickly pull down the output signal OUT when it changes from a high level to a low level, thereby avoiding voltage instability when the output signal voltage is pulled down.

[0064] According to an embodiment of the present disclosure, under the control of a low level of the first node N1, the output circuit 230 provides the first power supply voltage VGH to the output terminal OUT as the output signal OUT. Under the control of a high level of the first node N1 and a low level of the input signal INPUT, the second power supply voltage VGL1 is provided to the output terminal OUT as the output signal OUT.

[0065] Under the control of the potential of the first node N1 and the input signal, the output circuit 230 provides the first power voltage VGH and the second power voltage VGL1 to the output terminal OUT as output signals, thereby outputting a high-level signal.

[0066] According to an embodiment of the present disclosure, under the control of the first level of the input signal INPUT, when the clock signal CK switches from the first level to the second level, the input circuit 210 provides the second level of the clock signal CK to the first node N1.

[0067] In an embodiment of the present disclosure, when the input signal INPUT is at a high level, when the clock signal CK changes from a high level to a low level, the low level of the clock signal CK can be provided to the first node N1 by the input circuit 210, thereby lowering the potential of the first node N1. Since the potential of the first node N1 can control the potential of the output signal OUT, the input circuit 210 can change the potential of the first node N1 under the control of the input signal INPUT and the clock signal CK, thereby indirectly controlling the potential of the output signal.

[0068] According to an embodiment of the present disclosure, under the control of the second level of the clock signal CK and the second level of the input signal INPUT, the control circuit 220 provides the first power supply voltage VGH to the first node N1, controlling the potential of the first node N1 to be the first level. Under the control of the second level of the clock signal CK and the first level of the input signal INPUT, the potential of the first node N1 is controlled to be maintained at the second level.

[0069] In an embodiment of the present disclosure, when the clock signal CK and the input signal INPUT are at a low level, the control circuit 220 provides the first power supply voltage VGH to the first node N1, thereby raising the potential of the first node N1. Because the potential of the first node N1 can control the potential of the output signal, the control circuit 220 can change the potential of the first node N1 under the control of the input signal and the clock signal CK, thereby indirectly controlling the potential of the output signal.

[0070] FIG3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0071] As shown in FIG. 3 , the shift register 300 includes an input circuit 310 , a control circuit 320 , and an output circuit 330 .

[0072] In the embodiment of the present disclosure, the input circuit 310 , the control circuit 320 and the output circuit 330 are respectively similar to the input circuit 210 , the control circuit 220 and the output circuit 230 described above, and are not described again for the sake of brevity.

[0073] In the disclosed embodiment, the output circuit 330 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1. The input circuit 310 includes a fifth transistor T5, a sixth transistor T6, and a second capacitor C2. The control circuit 320 includes a seventh transistor T7, an eighth transistor T8, and a third capacitor C3. The first transistor T1 and the second transistor T2 are different types of transistors. The first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors, while the second transistor T2 and the fourth transistor T4 are N-type transistors.

[0074] In the embodiment of the present disclosure, the control electrode of the first transistor T1 is electrically connected to the first node N1 , the first electrode of the first transistor T1 is electrically connected to the first power supply VGH, and the second electrode of the first transistor T1 is electrically connected to the output terminal OUT.

[0075] A control electrode of the second transistor T2 is electrically connected to the second node N2 , a first electrode of the second transistor T2 is electrically connected to the output terminal OUT, and a second electrode of the second transistor T2 is electrically connected to the second power supply VGL1 .

[0076] A control electrode of the third transistor T3 is electrically connected to the input terminal INPUT, a first electrode of the third transistor T3 is electrically connected to the first node N1, and a second electrode of the third transistor T3 is electrically connected to the second node N2.

[0077] A control electrode of the fourth transistor T4 is electrically connected to the input terminal INPUT, a first electrode of the fourth transistor T4 is electrically connected to the second node N2 , and a second electrode of the fourth transistor T4 is electrically connected to the second power supply VGL1 .

[0078] A first end of the first capacitor C1 is electrically connected to a first power source VGH, and a second end of the first capacitor C1 is electrically connected to a first node N1.

[0079] A control electrode of the sixth transistor T6 is electrically connected to the input terminal INPUT, a first electrode of the sixth transistor T6 is electrically connected to the first power supply VGH, and a second electrode of the sixth transistor T6 is electrically connected to the third node N3.

[0080] A control electrode of the fifth transistor T5 is electrically connected to the third node N3 , a first electrode of the fifth transistor T5 is electrically connected to the clock terminal CK, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1 .

[0081] A first terminal of the second capacitor C2 is electrically connected to the third node N3 , and a second terminal of the second capacitor C2 is electrically connected to the clock terminal CK.

[0082] A control electrode of the seventh transistor T7 is electrically connected to the clock terminal CK, a first electrode of the seventh transistor T7 is electrically connected to the input terminal INPUT, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0083] A control electrode of the eighth transistor T8 is electrically connected to the fourth node N4 , a first electrode of the eighth transistor T8 is electrically connected to the first node N1 , and a second electrode of the eighth transistor T8 is electrically connected to the first power supply VGH.

[0084] A first end of the third capacitor C3 is electrically connected to the fourth node N4 , and a second end of the third capacitor C3 is electrically connected to the first power source VGH.

[0085] In the embodiment of the present disclosure, the first transistor T1 and the second transistor T2 are of different types. The first transistor T1 is a P-type transistor for pulling up the potential of the output signal, and the second transistor T2 is an N-type transistor for pulling down the potential of the output signal.

[0086] It should be noted that the N-type TFT transistors in the present disclosure may be LTPS process transistors, oxide process transistors, or other process transistors. The present disclosure does not limit the process type of the transistors.

[0087] FIG4A is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0088] The following describes the operation process of the shift register provided by the embodiment of the present disclosure, taking the structure of the shift register 300 shown in Figure 3 as an example and combining it with the signal timing diagram shown in Figure 4A. The operation process of the shift register 300 is divided into five stages.

[0089] Before the first phase S1, the input signal INPUT is at a high level. Under the control of the input signal INPUT, the fourth transistor T4 is turned on, and the third transistor T3 and the sixth transistor T6 are turned off. The second power supply voltage VGL1 is provided to the second node N2 via the fourth transistor T4, the second transistor T2 is turned off, and the output signal output by the output terminal OUT remains at the level of the previous phase.

[0090] In the first phase S1 , the input signal INPUT is kept at a high level, and the clock signal CK changes from a high level to a low level.

[0091] Since the sixth transistor T6 is turned off before the clock signal CK changes from high to low, the third node N3 is in a floating state when the clock signal CK changes from high to low. The low level of the clock signal CK is coupled to the third node N3 through the second capacitor C2, causing the third node N3 to be low.

[0092] Under the control of the low level of the third node N3, the fifth transistor T5 is turned on, and the low level of the clock signal CK is provided to the first node N1 through the fifth transistor T5, pulling down the first node N1 to a low level.

[0093] Under the control of the low level of the clock signal CK, the seventh transistor T7 is turned on, so that the high level of the input signal INPUT is provided to the fourth node N4 through the seventh transistor T7, and the eighth transistor T8 is turned off. The input signal INPUT charges the third capacitor C3, so that the third capacitor C3 stores a high level.

[0094] The low level of the clock signal CK is stored in the first capacitor C1 after pulling down the potential of the first node N1. Meanwhile, the first transistor T1 is turned on, and the first power supply voltage VGH is provided to the output terminal OUT through the first transistor T1, outputting a high level output signal OUT.

[0095] Under the control of the high level of the input signal INPUT, the third transistor T3 is turned off and the fourth transistor T4 is turned on. The low level of the second power supply voltage VGL1 pulls down the second node N2 through the fourth transistor T4, and the second transistor T2 is turned off. The low voltage of the second power supply voltage VGL1 cannot be provided to the output terminal OUT through the turned-off second transistor T2.

[0096] In the second phase S2 , the input signal INPUT is at a high level, and the clock signal CK changes from a low level to a high level.

[0097] Under the control of the high level of the input signal INPUT and the clock signal CK, the sixth transistor T6 and the seventh transistor T7 are turned off. The high level stored in the third capacitor C3 keeps the fourth node N4 at a high level, and the eighth transistor T8 is turned off.

[0098] When the clock signal CK transitions from a low level to a high level, the third node N3 is pulled high via coupling through the second capacitor C2, thereby turning off the fifth transistor T5. At this point, the first node N1 remains low, and the states of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 remain the same as in the first stage S1. The first transistor T1 and the fourth transistor T4 are turned on, while the second transistor T2 and the third transistor T3 are turned off. The output signal OUT at the output terminal OUT remains high.

[0099] In the third phase S3, the input signal INPUT is at a high level, and the clock signal CK changes from a high level to a low level. The timing changes of the signals in the shift register in the third phase S3 are similar to those in the first phase S1. Therefore, the on-off states of the components in the circuit are similar. The first node N1 is at a low level, and the output signal OUT at the output terminal OUT remains at a high level.

[0100] In the fourth phase S4 , the input signal INPUT is at a low level, and the clock signal CK changes from a low level to a high level.

[0101] Under the control of the high level of the clock signal CK, the seventh transistor is turned off, the low level of the input signal INPUT cannot be provided to the fourth node N4, the fourth node N4 maintains a high level, and the eighth transistor T8 is turned off.

[0102] Under the control of the low level of the input signal INPUT, the third transistor T3 and the sixth transistor T6 are turned on, and the fourth transistor T4 is turned off. The first power supply voltage VGH is supplied to the third node N3 via the sixth transistor T6, causing the third node N3 to be at a high level. Under the control of the high level of the third node N3, the fifth transistor T5 is turned off. The first node N1 remains at a low level, and the first transistor T1 is turned on. The low level of the first node N1 is supplied to the second node N2 via the third transistor T3, and the second transistor T2 is turned off. The output signal OUT outputted by the output terminal OUT remains at a high level.

[0103] In the fifth stage S5 , the input signal INPUT is at a low level, and the clock signal CK changes from a high level to a low level.

[0104] When the input signal INPUT is at a low level, the third transistor T3 and the sixth transistor T6 are turned on, and the fourth transistor T4 is turned off. The first power supply voltage VGH is supplied to the third node N3 via the sixth transistor T6, causing the third node N3 to be at a high level. The fifth transistor T5 is turned off, preventing the clock signal CK from being supplied to the first node N1 via the fifth transistor T5.

[0105] Under the control of the low level of the clock signal CK, the seventh transistor T7 is turned on. The low level of the input signal INPUT is provided to the fourth node N4 through the seventh transistor T7, so that the eighth transistor T8 is turned on.

[0106] When the eighth transistor T8 is turned on, the first power voltage VGH is provided to the first node N1 through the eighth transistor T8 , and the potential of the first node N1 is pulled up to a high level.

[0107] Under the control of the high level of the first node N1, the first transistor T1 is turned off. The high level of the first node N1 is provided to the second node N2 via the third transistor T3. The second node N2 is pulled high, turning on the N-type transistor second transistor T2. The second power supply voltage VGL1 is provided to the output terminal via the second transistor T2. At this time, the output signal OUT at the output terminal OUT is low. Furthermore, the output signal OUT at the output terminal OUT remains low until the input signal INPUT becomes high.

[0108] During stage S5, the second transistor T2 employed in the disclosed embodiment is an N-type TFT transistor with a strong pull-down capability, easily pulling the voltage at the output terminal OUT down to the low level of VGL1. Under the action of the second transistor T2, the voltage at the output terminal OUT can quickly drop to a low level, and the potential of the output signal is more stable. Furthermore, the shift register 300 has a simple circuit connection relationship, a small number of transistors and capacitors, and a small footprint, which facilitates narrowing the display panel frame.

[0109] FIG4B is a schematic diagram of a simulation of voltages in a shift register according to an embodiment of the present disclosure.

[0110] As shown in FIG4B , the simulation waveforms of the INPUT, CK, and OUT potentials of the shift register provided in each stage according to the embodiment of the present disclosure refer to the timing waveforms described in FIG4A , which will not be repeated for the sake of brevity.

[0111] With reference to the structure of the shift register 300 in FIG3 , potential changes of the first node N1 , the second node N2 , the third node N3 , and the fourth node N4 are described.

[0112] When the input signal INPUT is at a high level, when the clock signal CK drops from a high level to a low level, the potential of the first node N1 becomes a low level, and when the input signal INPUT remains at a high level, the potential of the first node N1 always remains at a low level, so that the first transistor T1 is turned on and the output terminal OUT outputs a high level.

[0113] Under the control of the high level of the input signal INPUT, the third transistor T3 is turned off and the fourth transistor T4 remains on, so that the second power voltage VGL1 is provided to the second node N2 through the fourth transistor T4. When the input signal INPUT is high, the second node N2 always remains low.

[0114] Under the control of the high level of the input signal INPUT, the sixth transistor T6 is turned off and the control electrode of the fifth transistor T5 is in a floating state. The clock signal CK couples the potential of the third node N3 through the second capacitor C2, so the potential change of the third node N3 is consistent with the clock signal CK.

[0115] When the input signal INPUT is at a high level and the clock signal CK changes from a high level to a low level, the seventh transistor T7 is turned on, so that the input signal INPUT is provided to the fourth node N4 through the seventh transistor T7, and the fourth node N4 is at a high level. The input signal INPUT charges the third capacitor C3, causing the third capacitor C3 to store a high level. When the clock signal CK changes from a low level to a high level, the seventh transistor T7 is turned off, and the high level stored in the third capacitor C3 causes the potential of the fourth node N4 to remain at a high level.

[0116] In one example, the low level of the clock signal CK provided in the present disclosure can be less than or equal to the second power supply voltage VGL1. When the low level of the clock signal CK is less than the second power supply voltage VGL1, the conduction effect of the seventh transistor T7 is improved, which facilitates the level of the input signal INPUT being written to the fourth node N4 via the seventh transistor T7, thereby correspondingly improving the conduction effect of the eighth transistor T8. This also facilitates the first power supply voltage VGH being written to the first node N1 via the eighth transistor T8 in the fifth stage S5, thereby ensuring that the first transistor T1 is completely cut off and improving the output effect of the shift register. It will be understood that the present disclosure does not limit the voltage relationship between the low level of the clock signal CK and the second power supply voltage VGL1.

[0117] FIG5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0118] As shown in FIG. 5 , the shift register 500 includes an input circuit 510 , a control circuit 520 , and an output circuit 530 .

[0119] In the embodiment of the present disclosure, the input circuit 510 and the control circuit 520 have similar structures to the input circuit 310 and the control circuit 320 described above, and are not described again for the sake of brevity.

[0120] In the disclosed embodiment, the output circuit 530 is further electrically connected to a third power supply VGL2, where the third power supply voltage VGL2 is lower than the second power supply voltage VGL1. The control electrodes of the second transistor T2 and the fourth transistor T4 in the output circuit 530 include a first control electrode and a second control electrode. The first control electrode and the second control electrode serve as the top gate and bottom gate of the transistor, respectively. The third power supply voltage VGL2 being lower than the second power supply voltage VGL1 ensures that the threshold voltage Vth of the second transistor T2 and the fourth transistor T4 undergoes a positive shift.

[0121] The first control electrode of the second transistor T2 is electrically connected to the second node N2, and the second control electrode of the second transistor T2 is electrically connected to the third power supply VGL2. The first control electrode of the fourth transistor T4 is electrically connected to the input terminal INPUT, and the second control electrode of the fourth transistor T4 is electrically connected to the third power supply VGL2.

[0122] In an embodiment of the present disclosure, the bottom gates of the second transistor T2 and the fourth transistor T4 are each electrically connected to a third power supply voltage VGL2. Since the third power supply voltage VGL2 applied to the bottom gate is lower than the second power supply voltage VGL1 applied to the top gate, the voltage of the bottom gate is lower than the voltage of the source of the transistor. This results in an increase in the amount of positive charge fixed in the semiconductor layer near the bottom gate, but the charge on the top gate remains unchanged. The increase in the bottom space charge near the bottom gate leads to a decrease in the movable charge in the channel, which reduces the conductivity level of the transistor, thereby causing the threshold voltage Vth of the second transistor T2 and the fourth transistor T4 to shift positively, preventing the TFT transistor from being unable to turn off due to a negative shift.

[0123] The timing changes of the signals of the shift register 500 during operation are similar to the timing changes of the signals of the shift register 300 described above, and are not described again for the sake of brevity.

[0124] FIG6 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0125] As shown in FIG. 6 , the shift register 600 includes an input circuit 610 , a control circuit 620 , and an output circuit 630 .

[0126] Compared to the shift register 300 described above, the second transistor T2 and the transistor T4 in the shift register 600 are replaced from N-type transistors to P-type transistors, and the first transistor T1, the third transistor T3, and the fifth transistor T5 through the eighth transistor T8 are replaced from P-type transistors to N-type transistors. The voltages output by the input signal INPUT and the clock signal CK are in opposite phases.

[0127] In an embodiment of the present disclosure, a first electrode of a first transistor T1 is electrically connected to a second power supply VGL1. A second electrode of a second transistor T2 is electrically connected to the first power supply VGH. A second electrode of a fourth transistor T4 is electrically connected to the first power supply VGH. A first end of a first capacitor C1 is electrically connected to the second power supply VGL1. A first electrode of a sixth transistor T6 is electrically connected to the second power supply VGL1. A second electrode of an eighth transistor T8 is electrically connected to the second power supply VGL1.

[0128] Since the types of transistors in the circuit are interchanged between P-type and N-type, the voltages of the corresponding input signal INPUT and the clock signal CK are completely inverted. Therefore, the working process of the circuit and the potential of the output signal are similar to those of the shift register 300 and will not be repeated for simplicity.

[0129] In the embodiment of the present disclosure, the first transistor T1 and the second transistor T2 are of different types. The first transistor T1 is an N-type transistor for pulling down the potential of the output signal, and the second transistor T2 is a P-type transistor for pulling up the potential of the output signal.

[0130] When the level of the output light-emission control signal changes in the opposite direction, the type of transistor connected to the EM signal in the corresponding pixel circuit also changes. In the disclosed embodiment, after swapping the P-type transistor with the N-type transistor, the first transistor T1 acts as a pull-down transistor to pull down the output voltage. Since the first transistor T1 is replaced with an N-type transistor, it also has the ability to quickly pull down the potential, making the output signal potential more stable. The circuit connection is simple and the space occupied is small, which helps to narrow the display panel frame.

[0131] FIG. 7 is a signal timing diagram of a shift register according to another embodiment of the present disclosure.

[0132] As shown in FIG. 7 , FIG. 7 shows the timing waveforms of various signals at each stage during the operation of the shift register 600 .

[0133] The timing waveforms of the signals at each stage during the operation of the shift register 600 shown in FIG7 are inversely proportional to the timing waveforms of the signals at each stage during the operation of the shift register 300 shown in FIG4A .

[0134] As shown in FIG7 , the input signal INPIUT is at a low level from the first stage S1 to the third stage S3 , and the output signal OUT remains at a low level from the first stage S1 to the fourth stage S4 .

[0135] Compared to shift register 300, shift register 600 only changes the transistor types and swaps the connection locations of the first power supply VGH and the second power supply VGL1. Therefore, after completely inverting the input signal INPUT and the clock signal CK, the potential changes at each node and the transistor states in shift register 600 are similar to the timing changes described above, and for the sake of simplicity, they are not further described.

[0136] FIG8A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0137] As shown in FIG. 8A , the driving circuit 800 a includes M cascaded shift registers, where M is a positive integer greater than 1.

[0138] In the embodiment of the present disclosure, the shift register may be any one of the shift register 200, the shift register 300, the shift register 500, and the shift register 600 described above. For example, the M shift registers are all shift register 300. For example, the M shift registers are all shift register 500. Detailed description is omitted here.

[0139] In an embodiment of the present disclosure, in M cascaded shift registers, the input signal INPUT of the input terminal INPUT of the first-stage shift register GOA1 is the start signal STV, and the input terminal INPUT of the m-th stage shift register is electrically connected to the output terminal OUT(m - 1) of the (m - 1)-th stage shift register. The input terminal INPUT of the (m + 1)-th stage shift register is electrically connected to the output terminal OUT(m) of the m-th stage shift register, where 1 < m ≤ M - 1 and m is an integer.

[0140] For example, the input terminal INPUT(m) of the m-th stage shift register GOAm is electrically connected to the output terminal OUT(m - 1) of the (m - 1)-th stage shift register GOAm - 1, and the output terminal OUT(m) of the m-th stage shift register GOAm is electrically connected to the input terminal INPUT(m + 1) of the (m + 1)-th stage shift register GOAm + 1.

[0141] In an embodiment of the present disclosure, the driving circuit includes a first clock signal line and a second clock signal line. The clock signal CK provided by the first clock signal line and the clock signal CB provided by the second clock signal line are not both at an effective level at the same time.

[0142] For example, the high level is the effective level. When the clock signal CK is at a high level, the clock signal CB is at a low level. When the clock signal CB is at a high level, the clock signal CK is at a low level.

[0143] For example, the low level is the effective level. When the clock signal CK is at a low level, the clock signal CB is at a high level. When the clock signal CB is at a low level, the clock signal CK is at a high level. In the driving circuit 800a, the m-th register is electrically connected to the first clock signal line, and the (m + 1)-th register is electrically connected to the second clock signal line.

[0144] FIG. 8B is a signal timing diagram of the driving circuit according to an embodiment of the present disclosure.

[0145] As shown in FIG. 8B, the timing waveforms of each signal in each stage during the operation of the m-th shift register and the (m + 1)-th shift register in the driving circuit 800a. The m-th shift register and the (m + 1)-th shift register are the shift registers 300 described above.

[0146] The m-th shift register is electrically connected to the clock terminal CK, and the input signal INPUT(m) is the output signal of the (m - 1)-th shift register. The (m + 1)-th shift register is electrically connected to the clock terminal CB, and the input signal INPUT(m + 1) is the output signal OUT(m) of the m-th shift register.

[0147] In the embodiment of the present disclosure, for the shift register 300 described above, a low level is an effective level. When the clock signal CK is at a low level, the clock signal CB is at a high level. When the clock signal CB is at a low level, the clock signal CK is at a high level.

[0148] In the S0 phase, INPUT(m) is at a high level. In the S1 phase, the clock signal CK drops from a high level to a low level, INPUT(m) remains at a high level, and the output signal OUT(m) of the m-th shift register becomes a high level. Since the input signal INPUT(m+1) of the m+1-th shift register is the output signal OUT(m) of the m-th shift register, the input signal INPUT(m+1) of the m+1-th shift register also becomes a high level.

[0149] In the S1-S5 phase, the changes in the waveforms of the signals of the m-th stage shift register during operation refer to the changes in the waveforms of the signals of the shift register 300 in the S1-S5 phase described above, which will not be repeated for the sake of brevity.

[0150] In the S2-S6 phase, the signal waveform changes of the m+1th stage shift register during operation refer to the signal waveform changes of the shift register 300 in the S1-S5 phase described above, which will not be repeated for the sake of simplicity.

[0151] FIG9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0152] As shown in FIG. 9 , a display device 900 may include a driving circuit 910 .

[0153] In the embodiment of the present disclosure, the driving circuit 910 may be the driving circuit 800 described above, which will not be described in detail here.

[0154] FIG10 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0155] As shown in FIG. 10 , the driving method may include operations S1010 to S1050 .

[0156] In operation S1010 , in a first phase, the input signal is at a first level and the clock signal is at a second level.

[0157] In operation S1020 , in the second phase, the input signal is at the first level, and the clock signal is at the first level.

[0158] In operation S1030 , a third stage, the input signal is at a first level and the clock signal is at a second level.

[0159] In operation S1040 , a fourth stage, the input signal is at the second level, and the clock signal is at the first level.

[0160] In operation S1050 , a fifth stage, the input signal is at the second level, and the clock signal is at the second level.

[0161] In the embodiment of the present disclosure, operations S1010 to S1050 are similar to the operations performed by the shift register 300 described above, and are not described again herein.

[0162] In the embodiment of the present disclosure, the first stage is similar to the operation of the first stage S1 shown in FIG4A , the second stage includes the operation of the second stage S2 shown in FIG4A , the third stage is similar to the operation of the third stage S3 shown in FIG4A , the fourth stage is similar to the operation of the fourth stage S4 shown in FIG4A , and the fifth stage is similar to the operation of the fifth stage S5 shown in FIG4A . For the sake of brevity, the same parts of the present disclosure are not repeated here.

[0163] In the embodiment of the present disclosure, the first level is a high level and the second level is a low level. Those skilled in the art may also set the first level to a low level and the second level to a high level according to the type of transistors in the shift register.

[0164] According to an embodiment of the present disclosure, in a first phase, under the control of a first level of an input signal and a second level of a clock signal, the second level of the clock signal is provided to a first node, and under the control of the potential of the first node, a first power supply voltage is provided to an output terminal as an output signal.

[0165] According to an embodiment of the present disclosure, in the second phase, under the control of the first level of the input signal and the first level of the clock signal, the potential of the first node is controlled to be maintained at the second level. Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as the output signal.

[0166] According to an embodiment of the present disclosure, in the third phase, under the control of the first level of the input signal and the second level of the clock signal, the second level of the clock signal is provided to the first node. Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as the output signal.

[0167] According to an embodiment of the present disclosure, in the fourth stage, under the control of the second level of the input signal and the first level of the clock signal, the potential of the first node is controlled to be maintained at the second level. Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as the output signal.

[0168] According to an embodiment of the present disclosure, in the fifth stage, under the control of the second level of the input signal and the second level of the clock signal, the first power supply voltage is provided to the first node. Under the control of the potential of the first node, the second power supply voltage is provided to the output terminal as an output signal.

[0169] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0170] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0171] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register comprising: an input circuit configured to provide a clock signal from a clock terminal to the first node under control of an input signal from an input terminal; a control circuit configured to provide a first power supply voltage of a first power supply to the first node under control of the input signal and the clock signal; as well as The output circuit is configured to provide the first power supply voltage or the second power supply voltage of the second power supply to an output terminal as an output signal under the control of the potential of the first node and the input signal.

2. The shift register according to claim 1, wherein: The output circuit is configured to provide the first power supply voltage or the second power supply voltage of the second power supply to an output terminal as an output signal under the control of the potential of the first node and the input signal, including: Under the control of the potential of the first node, providing the first power supply voltage to the output terminal as the output signal; and Under the control of the potential of the first node and the input signal, the second power supply voltage is provided to the output terminal as the output signal.

3. The shift register according to claim 1 or 2, wherein: The output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; wherein the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the output terminal; The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the output terminal, and the second electrode of the second transistor is electrically connected to the second power supply; The control electrode of the third transistor is electrically connected to the input terminal, and the first electrode of the third transistor is electrically connected to the first node; The control electrode of the fourth transistor is electrically connected to the input terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply; A first terminal of the first capacitor is electrically connected to the first power source, and a second terminal of the first capacitor is electrically connected to the first node.

4. The shift register according to claim 3, wherein: The first transistor and the second transistor are different types of transistors.

5. The shift register according to claim 3, wherein: The control electrode of the second transistor includes a first control electrode and a second control electrode, the first control electrode of the second transistor is electrically connected to the second node, and the second control electrode of the second transistor is electrically connected to a third power supply; The control electrode of the fourth transistor includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor is electrically connected to the input terminal, and the second control electrode of the fourth transistor is electrically connected to a third power supply; The third power supply voltage is lower than the second power supply voltage. The shift register according to claim 1 , wherein: The input circuit is configured to provide a clock signal from a clock terminal to a first node under the control of an input signal from an input terminal, and includes: Under the control of the first level of the input signal, when the clock signal switches from the first level to the second level, the second level of the clock signal is provided to the first node.

7. The shift register according to claim 1 or 6, wherein: The input circuit includes a fifth transistor, a sixth transistor and a second capacitor; wherein the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the clock terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the input terminal, the first electrode of the sixth transistor is electrically connected to the first power supply, and the second electrode of the sixth transistor is electrically connected to the third node; A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to the clock terminal.

8. The shift register according to claim 1, wherein: The control circuit is configured to provide a first power supply voltage of a first power supply to the first node under the control of the input signal and the clock signal, including: Under the control of the second level of the clock signal and the second level of the input signal, supplying the first power supply voltage to the first node to control the potential of the first node to be a first level; and Under the control of the second level of the clock signal and the first level of the input signal, the potential of the first node is controlled to be maintained at the first level.

9. The shift register according to claim 1 or 8, wherein: The control circuit includes a seventh transistor, an eighth transistor and a third capacitor; wherein the control electrode of the seventh transistor is electrically connected to the clock terminal, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node; The control electrode of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the first power supply; A first terminal of the third capacitor is electrically connected to the fourth node, and a second terminal of the third capacitor is electrically connected to the first power source.

10. A driving circuit comprising M cascaded shift registers, wherein the input end of the m-th shift register is electrically connected to the output end of the m-1-th shift register, 1<m≤M, m is an integer, and M is an integer greater than 1.

11. The driving circuit according to claim 10, further comprising: a first clock signal line and a second clock signal line; The m-th stage shift register is electrically connected to the first clock signal line, and the m+1-th stage shift register is electrically connected to the second clock signal line.

12. A display device comprising the driving circuit according to claim 10 or 11.

13. A driving method, applied to the shift register according to any one of claims 1 to 9, comprising: In the first stage, the input signal is at a first level, and the clock signal is at a second level; In the second stage, the input signal is at the first level, and the clock signal is at the first level; In the third stage, the input signal is at the first level, and the clock signal is at the second level; In the fourth stage, the input signal is at the second level, and the clock signal is at the first level; as well as In the fifth stage, the input signal is at the second level, and the clock signal is at the second level.

14. The driving method according to claim 13, wherein: In the first stage, under the control of the first level of the input signal and the second level of the clock signal, the second level of the clock signal is provided to the first node; as well as Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as an output signal.

15. The driving method according to claim 13, wherein: In the second stage, under the control of the first level of the input signal and the first level of the clock signal, the potential of the first node is controlled to be maintained at a second level; as well as Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as an output signal.

16. The driving method according to claim 13, wherein: In the third stage, under the control of the first level of the input signal and the second level of the clock signal, the second level of the clock signal is provided to the first node; as well as Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as an output signal.

17. The driving method according to claim 13, wherein: In the fourth stage, under the control of the second level of the input signal and the first level of the clock signal, the potential of the first node is controlled to be maintained at a second level; as well as Under the control of the potential of the first node, the first power supply voltage is provided to the output terminal as an output signal.

18. The driving method according to claim 13, wherein: In the fifth stage, under the control of the second level of the input signal and the second level of the clock signal, the first power supply voltage is provided to the first node; as well as Under the control of the potential of the first node, the second power supply voltage is provided to the output terminal as an output signal.

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