Hash filter based selective row refresh in memory devices

Abstract

This disclosure provides systems, methods, and devices for a memory system that supports row selective self-refresh operations when a host processor is in a sleep mode. In a first aspect, a method of operating a memory system by a memory controller includes receiving a hash filter indicating a first subset of rows in a memory array from a host device over a channel; and refreshing, by the memory controller, a second subset of the rows in the memory array based on the hash filter. The hash filter may be a Bloom filter, a Cuckoo filter, a linear detection filter, or an XOR filter. Other aspects and features are also claimed and described.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 321,535, filed May 22, 2023, entitled “HASH FILTER-BASED SELECTIVE-ROWREFRESH IN MEMORY DEVICE,” which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates generally to computer information systems, and more specifically to memory systems for storing data. Some features can be implemented by using hash-filter-based selective row flushing of memory cells in the memory system and providing improved memory capabilities for lower power operation. Background Technology

[0004] Computing devices (e.g., laptops, mobile phones, etc.) may include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions. A memory system is a crucial component of a computing device. The processor may be coupled to the memory system to perform the aforementioned computing functions. For example, the processor may fetch instructions from the memory system to perform computing functions and / or store temporary data involved in performing these computing functions within the memory system.

[0005] Memory systems can utilize memory cells that are inherently volatile. Volatile memory cells retain information for short periods of time (such as fractions of a second). Refresh operations can be performed on volatile memory cells to maintain information for longer periods of time. In an example volatile memory cell that stores information as electrical charge, the charge decays within fractions of a second. The memory cell can be refreshed to extend the time the memory cell retains information before the charge decays beyond the point at which the information is lost. In some cases, refresh operations can be performed repeatedly to extend the storage period of information indefinitely, or simply as long as the circuitry is powered. This refresh operation consumes power, which affects the operation of devices that operate from finite power sources (such as mobile devices that operate on battery power).

[0006] A common technique for reducing power consumption is Partial Array Self-Refresh (PASR), a low-power refresh mode in which some memory banks in a memory system are refreshed while others are turned off to save power. Unrefreshed memory banks will lose the information stored within them. Summary of the Invention

[0007] The following summary outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This summary is not an exhaustive overview of all the intended features of this disclosure, nor is it intended to identify key or essential elements of all aspects of this disclosure, nor to define the scope of any or all aspects of this disclosure. The sole purpose of this summary is to present, in a general form, some concepts of one or more aspects of this disclosure as a prelude to the more detailed description that follows.

[0008] In some aspects, selective row refresh techniques are described for memory systems that allow refresh operations to maintain information in specific rows stored in memory cells. Selective refresh techniques can reduce refresh cycle time and power consumption by activating only a subset of identified rows for refresh. In various embodiments, the rows to be refreshed can be selected by a hash filter, including, for example, a Bloom filter, a Cuckoo filter, a linear probe, and / or an XOR filter. A filter value can be determined by identifying rows with the information to be retained. The refresh operation can be performed based on this filter value to identify addresses corresponding to the sequence of rows to be refreshed during the refresh cycle, while omitting the generation of addresses not identified by the hash filter value during the refresh operation. Therefore, redundant refresh operations can be skipped for empty rows.

[0009] In some implementations, the hash filter value may be determined by a processor (e.g., an application processor) or other logical device storing information in a memory system by tracking the addresses of where the processor stores the information in the memory system (e.g., a double data rate (DDR) memory system). The processor may output the hash filter value to the memory system. The memory system then determines a set of row addresses to be flushed based on the hash filter value.

[0010] In some implementations, selective row refresh based on hash filter values ​​can be performed during a sleep mode of the processor or other logic device. The processor may enter sleep mode when a user presses the power button or when the user does not interact with the device for a predefined period of time. Before entering sleep mode, the processor may determine a hash filter value corresponding to the location of information stored in the memory system and expected to be available when the processor wakes up to perform further processing functions. The processor outputs the hash filter value to the memory system, which may store the hash filter value in registers and / or memory cells of the memory array. The processor then instructs the memory system to enter a self-refresh mode, during which the memory system performs a refresh operation without input from the processor. The processor then enters sleep mode, during which the processor's power consumption is reduced. Example sleep states may include sleep states such as C0 (active), C1 (auto-stop), C2 (stop clock), C3 (deep sleep), and C4 (deeper sleep). Different sleep states may correspond to states in which different parts or combinations of the processor are turned off or have reduced power.

[0011] These aspects can be implemented as a sequence of commands sent from the host to the memory system. Commands sent by the host may include commands for reading capabilities from the memory system, setting configurations in the memory system, reading data from one or more specified addresses in the memory system, and / or writing data from one or more specified addresses to the memory system. For example, the host device may include a processor and may be coupled to the memory system. Based on instructions from the processor, the host device may issue a command for setting a hash filter value in the memory system and subsequently issue a command for initiating a self-refresh operating mode of the memory system, during which the memory system refreshes rows based on the hash filter value without further instructions from the processor. The processor may wake up from sleep at a later time and issue a command for exiting the self-refresh operating mode.

[0012] An apparatus according to at least one embodiment includes a memory system configured to communicate with a host. The memory system includes a memory array configured to store data. The memory system may include a memory controller configured to provide data stored in the memory array to the host for further processing by a processor or other components of the host. The memory controller may also be configured to receive data from the host for storage in the memory array. In some embodiments, the memory array may be a plurality of volatile memory cells organized in rows and columns, such as in dynamic random access memory (DRAM) or static random access memory (SRAM). In other embodiments, the memory array may be a plurality of non-volatile memory cells or a mixture of volatile and non-volatile memory cells.

[0013] The apparatus according to at least one other embodiment includes a host device having a memory controller configured to communicate with a memory system to receive data stored in a memory array and / or store data in the memory array. The host device may be, for example, a user equipment (UE) device, such as a cellular phone, tablet computing device, personal computer, server, smartwatch, or Internet of Things (IoT) device.

[0014] In one aspect of this disclosure, a method for refreshing a memory array includes: obtaining, by a memory controller, a hash filter indicating a first subset of rows in the memory array from a host device via a first channel; and refreshing a second subset of rows in the memory array by the memory controller based on the hash filter.

[0015] In an additional aspect of this disclosure, an apparatus includes a memory controller coupled to a memory array via a first bus and configured to access data stored in the memory array via the first bus, the memory controller being coupled to a host device via a channel and configured to perform operations including: obtaining a hash filter from the host device via the first channel indicating a first subset of rows in the memory array; and refreshing a second subset of rows in the memory array based on the hash filter.

[0016] In an additional aspect of this disclosure, an apparatus includes: components for obtaining, by a memory controller from a host device via a first channel, a hash filter indicating a first subset of rows in a memory array; and components for refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter.

[0017] In another aspect of this disclosure, an apparatus includes: at least one processor; and a memory controller coupled to the at least one processor and a memory system via a channel and configured to communicate with the memory system via the channel. The at least one processor is configured to perform operations including: saving data to a first subset of rows in a memory array of the memory system via the memory controller; determining a hash filter corresponding to the first subset of rows; and copying the hash filter to the memory system via the memory controller.

[0018] In another aspect of this disclosure, a method for configuring a memory device includes: at least one processor of a host device coupled to the memory system via a channel through a memory controller saving data to a first subset of rows in a memory array of the memory system through the memory controller; determining a hash filter corresponding to the first subset of rows by the at least one processor; and copying the hash filter to the memory system by the at least one processor through the memory controller.

[0019] In another aspect of this disclosure, an apparatus includes: components for storing data by at least one processor of a host device coupled to the memory system via a channel through a memory controller into a first subset of rows in a memory array of the memory system; components for determining a hash filter corresponding to the first subset of rows by the at least one processor; and components for copying the hash filter by the at least one processor to the memory system via the memory controller.

[0020] In an additional aspect of this disclosure, an apparatus (such as a wireless device) includes at least one processor and memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory system via a memory controller coupled to a channel that couples the processor to the memory system. The processor may be a processor, controller, or other logic circuitry in a host computer.

[0021] In an additional aspect of this disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein with respect to various aspects of this disclosure.

[0022] The memory system of this disclosure can be embedded within a processor on a semiconductor die or as part of a different semiconductor die. The memory system can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash memory, or NOR flash memory, etc.

[0023] The methods and apparatuses presented in this disclosure are given as non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, LPDDR memory operates according to the LPDDR specification issued by the Joint Electron Device Engineering Committee (JEDEC). One such LPDDR specification could be LPDDR5. Another such LPDDR specification could be LPDDR6.

[0024] Other aspects, features, and specific embodiments will become apparent to those skilled in the art when they review the following description of particular exemplary aspects in conjunction with the accompanying drawings. Although features may be discussed hereinafter with reference to certain aspects and drawings, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed having certain advantageous features, one or more such features may also be used depending on the various aspects. Similarly, although exemplary aspects may be discussed hereinafter as aspects of an apparatus, system, or method, exemplary aspects can be implemented in various apparatuses, systems, and methods.

[0025] This method can be embedded as computer program code in a computer-readable medium, the computer program code including instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including: a first network adapter configured to transmit data, such as recorded images or videos or streaming data, via a first network connection among a plurality of network connections. The processor may be coupled to the first network adapter and memory for storing data to support processing and communication operations performed by the processor. The network adapter may support communication on a wireless communication network such as a 5G NR communication network. The processor may cause data stored in the memory to be transmitted via the wireless communication network.

[0026] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose of this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and operation) and their associated advantages will be better understood in conjunction with the accompanying drawings, based on the following description. Each figure in the accompanying drawings is provided for illustrative and descriptive purposes and not as a definition of limitation of the claims.

[0027] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or devices may be implemented via integrated chip implementations and other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to a use case or application, applicability to various types of the described innovations is possible. The scope of implementations ranges from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily involve multiple components (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.) for analog and digital purposes. The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0028] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numerals and a second reference numeral for differentiation between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numerals.

[0029] Figure 1 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0030] Figure 2 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0031] Figure 3A and Figure 3BA waveform illustrating data transfer via an example channel during a write operation, according to certain aspects of this disclosure, is shown.

[0032] Figure 4A and Figure 4B A waveform illustrating data transfer via an example channel during a read operation according to certain aspects of this disclosure is shown.

[0033] Figure 5 This is a block diagram illustrating various aspects of a selective refresh operation according to some embodiments of this disclosure.

[0034] Figure 6 This is an example flowchart illustrating selective row refresh in sleep mode according to some embodiments of this disclosure.

[0035] Figure 7 This is a block diagram illustrating the generation of row selection signals to perform selective row refresh according to some embodiments of this disclosure.

[0036] Figure 8 This is a flowchart illustrating a row-selective refresh operation performed by a memory system according to some embodiments of the present disclosure.

[0037] Figure 9 This is a flowchart illustrating a host device operating a memory system to perform line-selective self-refresh according to one or more aspects of this disclosure.

[0038] The same reference numerals and names in different figures denote the same elements. Detailed Implementation

[0039] The specific embodiments described below with reference to the accompanying drawings are intended as descriptions of various configurations and are not intended to limit the scope of this disclosure. Rather, the specific embodiments include specific details for providing a thorough understanding of the subject matter of the invention. It will be apparent to those skilled in the art that these specific details are not necessary in every situation, and in some cases, well-known structures and components are shown in block diagram form for clarity of presentation.

[0040] This disclosure provides systems, apparatus, methods, and computer-readable media supporting data processing, including techniques for selective row refresh, which allow refresh operations to maintain information in specific rows stored in memory cells. Selective refresh techniques can reduce refresh cycle time and power consumption by activating only a subset of identified rows for refresh. In various embodiments, the rows to be refreshed can be selected by a hash filter, including, for example, a Bloom filter, a Cuckoo filter, a linear probe, and / or an XOR filter. A filter value can be determined by identifying rows with information to be retained. A refresh operation can be performed based on this filter value to identify addresses corresponding to the sequence of rows to be refreshed during the refresh cycle, while omitting the generation of addresses not identified by the hash filter value during the refresh operation. Therefore, redundant refresh operations can be skipped for empty rows.

[0041] Specific embodiments of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides reduced power consumption, such as compared to all-bank refresh operations or per-bank refresh operations, by performing refresh operations on a selective row-based basis. As the number of rows to be refreshed in a refresh cycle decreases, refresh overhead time can be reduced by up to or more than 90%. In some embodiments, the selector hardware circuitry in the memory system can offload up to 90% of the counter operations, which reduces row selection latency. The frequency of refresh operations can be increased at higher operating temperatures. In such operating modes, higher operating temperatures may result in increased power consumption due to more frequent refresh cycles, which can be offset by selective row-based refresh using hash filter values. The reduced refresh operations resulting from selective row-based refresh using, for example, hash filter values ​​can also increase the lifetime of the memory array.

[0042] The benefits of lower power consumption can be greater when less memory is used so that fewer valid rows are refreshed during row-selective self-refresh operations. Table 1 compares the power P consumed by the memory bank at various temperatures for conventional LPDDR4 memory and memory utilizing row-selective self-refresh operations with various memory utilization rates. bank (in milliwatts) The current I consumed by the storage device at certain temperatures. bank (in milliamperes), a comparison of the time and cost of performing a refresh.

[0043]

[0044] Table 1. Example performance evaluation of automatic selective row refresh.

[0045] Figure 1The illustration shows an example memory device that can incorporate aspects of this disclosure, including selective row-based refresh based on hash filter values. Figure 1 An apparatus 100 is illustrated, comprising a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150. The apparatus 100 may be a device in, for example, a computing system (e.g., a server, data center, desktop computer), a mobile computing device (e.g., a laptop computer, a cellular phone, a vehicle, etc.), an Internet of Things (IoT) device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital video camera, a camera-equipped wireless communication device such as a mobile phone, a cellular or satellite radio phone, a personal digital assistant (PDA), a panel or tablet computer, a gaming device, a computing device such as a webcam, a video surveillance camera, or other devices with digital imaging or video capabilities), and / or a multimedia system (e.g., a television, an optical disc player, a streaming device).

[0046] Host 110 may include at least one processor, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), multimedia engine, and / or neural processing unit (NPU). Host 110 may be configured to couple and communicate with memory 150 (e.g., memory 150-1 to 150-4) via channel 190 (e.g., channels 190-1 to 190-4) to perform computing functions (such as data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc.). For example, memory 150-1 to 150-4 may store instructions or data for host to perform computing functions.

[0047] Host 110 may include memory controller 130, which may include controller PHY modules 134-1 to 134-4. Each of controller PHY modules 134-1 to 134-4 may be coupled to a corresponding memory 150-1 to 150-4 via a corresponding channel 190-1 to 190-4. For ease of reference, read and write are referred to from the perspective of host 110. For example, in a read operation, host 110 may receive stored data from one or more memories 150-1 to 150-4 via one or more channels 190-1 to 190-4. In a write operation, host 110 may provide data to be written to one or more memories 150-1 to 150-4 for storage via one or more channels 190-1 to 190-4. Memory controller 130 may be configured to control various aspects of communication to and from memories 150-1 to 150-4, such as the logic layer. The controller PHY modules 134-1 to 134-4 can be configured to control the electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) of signals provided or received on channels 190-1 to 190-4 respectively.

[0048] In some examples, memories 150-1 to 150-4 may be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, memories 150-1 to 150-4 may be different types of memory, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM, respectively. Host 110, memories 150-1 to 150-4, and / or channels 190-1 to 190-4 may operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of channels 190-1 to 190-4 may include 16 data bits (e.g., 16 DQs). In some examples, each of channels 190-1 to 190-4 may operate on 32 data bits (e.g., 32 DQs). Figure 1 The diagram shows four channels; however, the device 100 may include more or fewer channels, such as eight or sixteen channels.

[0049] exist Figure 2 Additional details are shown of one aspect of an embodiment of a device 100 for providing access to a memory system, such as one of memories 150-1 to 150-4 including logic and control circuitry. Figure 2 The configuration of host 110, memory system 250 and channel 190 according to some aspects of this disclosure is illustrated with greater specificity. Figure 2 Examples Figure 1Another representation of the apparatus 100 having a host 110, a memory system 250, and a channel 190. The channel 190 between the host 110 and the memory system 250 may include multiple connections, some carrying data (e.g., user data or application data), and some carrying non-data (e.g., address and other signaling information). For example, non-data connections in the channel 190 may include a data clock (e.g., WCK) used on a per-byte basis when providing data to the corresponding memory system 250 and a read data strobe (e.g., RDQS) used when receiving data from the corresponding memory system 250. The channel 190 may also include data masking (e.g., DM for indicating multiple functions performed by the signaling connection, sometimes referred to as Data Mask Inversion DMI) signaling for masking certain portions of data during write operations. The channel 190 may also include commands and addresses (e.g., CA[0:n]) and associated CA clocks to provide commands (e.g., read or write commands) to the memory system 250.

[0050] Host 110 may include at least one processor 120, which may include a CPU 122, a GPU 123, and / or an NPU 124. Host 110 may also include a memory controller 130 having a controller PHY module 134. Memory controller 130 may be coupled to at least one processor 120 via a bus system 115 to perform various computing functions. The term "bus system" may specify that the elements coupled to the "bus system" can exchange information directly or indirectly between them. In different embodiments, "bus system" may encompass multiple physical connections and intermediate levels such as buffers, latches, registers, etc. Modules may be implemented in hardware, software, or a combination of hardware and software.

[0051] Memory controller 130 can transfer and / or receive data blocks to and / or from other modules, such as at least one processor 120 and / or memory system 250. Memory system 250 may include memory controller 180 having a memory I / O module (e.g., PHY layer 160) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on the connection of channel 190. For example, PHY layer 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Figure 3A , Figure 3B , Figure 4A and Figure 4BThe example illustrates an example technique for communication over channel 190 between PHY layer 160 and memory controller 130. Memory controller 180 may also include data registers 182A-K configured to store data to be transmitted between host 110 and memory array 175 and / or storage configuration settings or other data. Memory controller 180 may also include additional logic circuitry 162 for controlling operations within memory system 250. For example, logic circuitry 162 may coordinate refresh operations of memory array 175.

[0052] The memory system 250 may also include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) for storing values. The host 110 can read data stored in the memory array 175 and write data to the memory array 175 via channel 190 and PHY layer 160. The memory array 175 may be divided into multiple memory banks, where each memory bank is organized into multiple pages.

[0053] Application or user data may be processed by processor 120, which instructs memory controller 130 to store such data and / or retrieve such data from memory system 250. For example, data may be generated during the execution of an application, such as a spreadsheet program that calculates values ​​based on other data. As another example, data may be generated during the execution of an application by receiving user input to, for example, a spreadsheet program. As yet another example, data may be generated during the execution of a game application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0054] Host 110 is coupled to memory system 250 via channel 190, exemplified for data bytes, DQ[0:7]. Channel 190 and signaling between host 110 and memory system 250 may be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As illustrated, channel 190 includes signaling connections for DQ, read data strobe (RDQS), data mask (DM), data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). Host 110 may use the read data strobe (RDQS) during a read operation to strobe data (e.g., time the data) to receive data on DQ. Memory system 250 may use the data mask (DM) during a write operation to mask certain portions of data from being written. Memory system 250 may use the data clock (WCK) to sample data on DQ for write operations. Memory system 250 may use the command and address clock (CK) to time CA (e.g., receive CA). Signal connections for each of the signaling components may include pins at host 110, pins at memory system 250, and one or more conductive traces for electrical connection pins. One or more conductive traces may be part of a single integrated circuit (IC) on a silicon chip containing processor 120 and memory system 250, part of a stacked package (PoP) containing processor 120 and memory system 250, or part of a printed circuit board (PCB) coupled to both processor 120 and memory system 250.

[0055] The memory system 250 may include a PHY layer 160 (e.g., a memory I / O module) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on channel 190. For example, the PHY layer 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Information transmitted across channel 190 may be stored in registers within the PHY layer 160 of the memory system 250 as a temporary or short-term storage location before long-term storage in memory array 175.

[0056] The memory system 250 may also include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells) for storing information. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via channel 190. In addition, the memory array 175 may be configured to store metadata associated with the stored data, such as ECC (e.g., system or array ECC).

[0057] According to some embodiments of this disclosure, operations for storing information and retrieving information from the memory array 175 can be performed via signals on a separate line of the control channel 190. (See reference...) Figure 3A and Figure 3B An example implementation of signaling for write operations is shown and described. References Figure 4A and Figure 4B An example implementation of the signaling used for the read operation is shown and described.

[0058] Figure 3A and Figure 3B A waveform illustrating data transfer via an example channel during a write operation according to certain aspects of this disclosure is shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_t and the falling edge of CK_c), a CAS command for a write operation to the memory system 250 can be provided by the host 110. At T1, the host 110 can provide a write command to the memory system 250.

[0059] After the write time interval (WL), host 110 may switch data clocks WCK0_t and WCK0_c to provide memory system 250 with a clock for receiving data to be written on the DQ signal connection. At Tc0 through Tc2, memory system 250 may serially receive 16 bytes of data on each of the DQ[0:7] signal connections, timed by data clocks WCK0_t and WCK0_c. Memory system 250 may serially (e.g., based on data clocks WCK0_t and WCK0_c) receive a 16-bit data mask DM0 to mask certain portions of the received data from write operations. In some examples, 16 bytes of data and a 16-bit data mask DM0 may be received by memory system 250, where each bit of the data mask DM0 masks the corresponding byte of the received data. At Tc0 through Tc2, the RDQS_t signal connection may be in Hi-Z condition. During a read operation, the RDQS_t signal connection can be configured to provide the read data strobe (RDQS) from the memory system 250 to the host 110.

[0060] Figure 4A and Figure 4BA waveform illustrating data transfer via an example channel during a read operation according to certain aspects of this disclosure is shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_t and the falling edge of CK_c), a CAS command for a read operation on the memory system 250 can be provided by the host 110. At T1, the host 110 can provide a read command to the memory system 250.

[0061] After the time period read delay (RL), memory system 250 can switch the read data strobe RDQS to provide host 110 with a clock for receiving data for read operations on the DQ signal connections. At Tc0 to Tc2, host 110 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, timed by read data strobes RDQS_t and RDQS_c. Thus, in this example, 16 bytes of data are received by host 110.

[0062] At Tc0 to Tc2, the data mask DM0 signal connection can be in Hi-Z mode. During a write operation, the DM signal connection can be configured to provide the data mask from the host 110 to the memory system 250, which can be timed by WCK0_t and WCK0_c.

[0063] exist Figure 5 An example refresh operation of a memory array 175 for a memory system 250 according to an embodiment of the present disclosure is shown. Figure 5 This is a block diagram illustrating various aspects of a row-selective refresh operation according to some embodiments of the present disclosure. The memory array 175 of the memory system 250 may be organized with multiple rows, each row having a corresponding address. Each row may have multiple memory cells, each memory cell being assigned to a separate column. The memory controller 180 may be configured to perform a refresh operation on the memory array 175 on a row-by-row basis. Conventionally, this involves cycling through each of the multiple rows and refreshing the information stored in that row. The memory array 175 may not be completely filled with data. Therefore, refreshing each row may result in unnecessarily refreshing rows that do not store information and thus wasting power.

[0064] The memory controller 180 may include a refresh unit 520 configured to perform at least some refresh operations on the memory array 175. For example, the refresh unit 520 may be configured to perform selective row refresh within the memory array 175. Selective refresh may be based on a table 522 stored in the memory controller 180. The table 522 may indicate row addresses and corresponding indicators regarding whether a row stores valid data (active row) or does not store valid data (inactive row). The table 522 may be populated by obtaining hash filters, such as by receiving hash filters from the host 110 and / or accessing the memory location corresponding to the hash filters. In some embodiments, no table is stored in the refresh unit 520; instead, the hash filters are stored in the refresh unit 520 and decoded to perform refresh operations.

[0065] The CPU 122 of host 110 can execute a sleep manager 510 that tracks a count of the number of active rows in memory, the starting address corresponding to the first active row in memory, and a hash filter indicating the active rows in memory. In some embodiments, the sleep manager 510 can be executed as a kernel-level process in an operating system executing on CPU 122. In some embodiments, the sleep manager 510 can be executed as firmware on hardware circuitry within host 110.

[0066] One or more hash filters may be stored by the sleep manager 510, where each hash filter indicates an active row for a different portion of the memory array 175. For example, hash filters may be stored for each bank of memory in the memory array 175, but other organization is also possible. Example hash filters for tracking active rows in the memory array 175 include Bloom filters, Cuckoo filters, Linear Probe filters, and XOR filters.

[0067] An example of a hash filter used to track active rows is a Bloom filter, a spatially efficient probabilistic data structure used to test whether an element (e.g., a particular row) is a member of a set (e.g., a subset of active rows in memory array 175). Tracking active rows in memory array 175 may include starting with an empty Bloom filter, which is an m-bit array where all bits are set to zero. A number of hash functions, h1(x), h2(x), h3(x), h4(x), h5(x), h6(x), h7(x), h8(x), h9(x), h1 ... 2(x) ...h k The bit at (x) is used to add the index as an item in the filter, where the hash function h is used. kThe index is calculated using row values ​​as input. A Bloom filter can be provided to the memory system 250 by the host 110. The memory controller 180 can execute a set of reverse operations applied to determine the active row based on the Bloom filter. For example, for each row value, an index can be calculated using h1, h2, ... h... k The hash is then used to check the hash filter to determine if all corresponding indices in the Bloom filter are set to "1" in the bit array. h1, h2, ... h k Example hash functions include cluster, FNV series, and Jenkins hash.

[0068] In some implementations using hash filters, the filter index is filled with row addresses (i.e., encoded addresses, not the entire address). The row addresses used for refreshing can be assigned count values ​​indicating the sequence of row addresses to be refreshed during the memory's self-refresh operation. In some implementations, the hash filter is constructed such that row addresses corresponding to active rows with stored data are ordered sequentially and each row address is assigned a sequential count value (e.g., row address 02 is assigned count 0, row address 07 is assigned count 1, and row address 1A is assigned count 2). The count values ​​are used to avoid needing to test the hash filter for every row address in the memory array during selective row refresh. If 40 row addresses out of 512 need to be refreshed, count values ​​0-39 are assigned to the 40 row addresses, allowing the counter in the memory system to step through 0 to 39 to sequentially activate the 40 row addresses (without disabling the row selection enable signal) and end the self-refresh operation after refreshing the 40 rows. Count value indications can be appended to the row addresses. For example, if the row address is 0xAh (binary 1010) and the count is 2 (decimal) or (binary 10), the hash filter index for that row will hold the binary value 101010. During a refresh operation on the memory device, the first four bits carrying the row address information are added to the starting address, and the last two bits are compared with the counter value to determine the row refresh.

[0069] Another example of a hash filter used to track active rows is the XOR filter. The XOR filter operates similarly to the Bloom filter described above, but the bits are grouped together into an L-bit sequence.

[0070] Another example of a hash filter used to track active rows is the cuckoo filter, which is a minimal hash table that uses cuckoo hashing to resolve collisions. The cuckoo filter can operate similarly to the XOR and Bloom filters described above to track active rows stored as fingerprints in a set of bits. The cuckoo filter may have a bucket array, where buckets are assigned to track different portions of the memory array 175.

[0071] Another example of a hash filter used to track active rows is a linear probing filter. With linear probing, each cell of the hash table stores a single key-value pair. In one implementation of linear probing, row address information (e.g., the difference between the starting row address and the current row address) is appended to a count value and stored linearly.

[0072] CPU 122 can be configured to detect a trigger event for activating a selective line refresh memory mode. The trigger event may be based on a counter that determines the host 110 has been in a low-power mode (e.g., sleep mode) for a predetermined amount of time. The trigger event may be based on the host 110 being in a location indicating that the host 110 can remain in sleep mode for an extended period. For example, when the host 110 is a car, such a location could be a parking lot at an airport. The trigger event may be user input where the user instructs the host 110 to enter sleep mode, such as by pressing a power button.

[0073] For example, if host 110 is integrated into a vehicle, CPU 122 can determine from location data that host 110 is located in a parking lot or car rental area, indicating that host 110 will not be used during the extended period. Therefore, once CPU 122 determines that host 110 is in a parking lot or car rental area, CPU 122 can send a hash filter to memory system 250 and cause memory system 250 to enter selective row refresh memory mode.

[0074] The memory system 250 can be configured to perform selective row refresh operations by the processor based on the processor's power state. Figure 6 This is an example flowchart illustrating selective row refresh in sleep mode according to some embodiments of this disclosure. Method 600 begins at block 602 with the sleep manager receiving a request. At block 604, it is determined whether the request is a sleep request or another request. If the request is not for sleep mode, method 600 keeps the device in the currently active state at block 606 and continues processing the request at block 602.

[0075] When a request is identified as a sleep request, method 600 proceeds to block 608 to notify subsystems of the computing device (such as other user-level and kernel-level applications or other hardware management circuitry) of the sleep request, enabling other processes to save the context to memory. When the context is written to memory, the sleep manager tracks the location of the data in memory based on the address of the write command used to save the context data to memory. At block 610, the sleep manager may compute a hash table based on the location of the context data. For example, the sleep manager may compute a hash of the address corresponding to each segment of the context data written to memory, and the output of this hash is used to construct a hash filter (such as a Bloom filter). After certain criteria for entering sleep mode have been met, method 600 may proceed to block 612 to copy the hash filter to the memory system. Criteria may be, for example, a predetermined amount of time has elapsed since the notification of block 608, the receipt of the request of block 602, or the receipt of acknowledgments that the context data from all processes has been written to memory.

[0076] After the hash filter is copied to the memory system, the processor may enter a sleep mode at block 614. When entering sleep mode, instructions may be sent to the memory controller to enter a refresh mode applicable during sleep mode. For example, a self-refresh command may be sent to the memory system. In some embodiments, the instructions may include an indication that row-selective refresh should be performed based on the hash filter sent at block 612. In some embodiments, the instructions may be specific to a row-selective self-refresh mode. While in sleep mode, the memory controller issues a refresh command at block 616 to the memory array of the memory system to maintain the contents of the memory (e.g., context data). The refresh command may originate from a memory controller on a host device or a memory controller on the memory system. The refresh command at block 618 causes the row selector circuitry to select a subset of rows in the memory array for refresh based on the contents of the hash filter. At block 620, the rows selected at block 618 are refreshed.

[0077] exist Figure 7 The example row selective refresh operation is shown in the figure. Figure 7This is a block diagram illustrating the generation of row selection signals to perform selective row refresh according to some embodiments of the present disclosure. One or more hash filters 702 and 704 may store indications corresponding to valid rows of the memory array. For example, hash filter 702 may include an empty cell corresponding to array location 0 and an entry corresponding to a valid row to be refreshed at array location 1. Array location 1 may include the value "1" and the value "f1", which indicates that the row at address "f1" should be refreshed when the refresh counter is at value 1. Other example values ​​from hash filter 702 are shown, such as an indication that the row at address "f7" should be refreshed when the refresh counter is at value 2. Rows for refresh may be indicated across multiple hash filters (e.g., hash filter 702 and hash filter 704). In some embodiments, different hash filters may correspond to different segments, banks, or dies in the memory array 175.

[0078] A counter can be used to generate row signals for refreshing individual rows of the memory array based on hash filter 702. The counter increments a count value from 1 to the number of elements in the hash filter. As the counter value progresses from the value "1" to subsequent values ​​up to the number of elements, a row address is retrieved from hash filter 702 and used to refresh the row of the memory array corresponding to the row address indicated by the entry in hash filter 702. Logic circuits (such as in...) Figure 7 In the example implementation, it can be used to generate a row selection signal. Each of the adders 713 generates an address value by adding the row address of hash filter 702 to a predetermined starting address. Thus, each of the adders 713 continuously outputs the row address corresponding to the row that should be refreshed. Gate 714 compares the count from counter 712 with the count value of each entry in hash filters 702 and 704. The operation of gates 714 and 716 is to select one of the row addresses output from adder 713 for refresh. As the count value increments, the next row address output from adder 713 is selected for refresh. Gate 714 performs an AND operation to select the hash filter 702 entry index value that matches a specific count value. Gate 716 performs an AND operation to select the row address with the count value corresponding to the output of counter 712. Multiplexer 718 performs an OR operation to combine the output of the selected row address with the unselected row address, such that the selected row address is passed to the memory array for refresh. Multiplexer 720 performs an OR operation to combine the output of the AND operation of the count values ​​in gate 714, causing an enable signal to be passed to the memory array for refresh, thereby indicating when a valid row address matches the count value in hash filter 702.

[0079] Now describing Figure 7A more specific example of operation is shown below. The generation of row signals from hash filters 702 and 704 is illustrated using logic including adder 713, gate 714, gate 716, multiplexer 718, and multiplexer 720. Counter 712 outputs sequential values ​​from zero to, for example, the maximum count value determined by sleep manager 510 and stored in a count register of memory system 250. The count values, as the sequential output of counter 712, are output to gate 714, which compares the count with the count value of each entry in hash filters 702 and 704. When a match occurs, a signal is output from the corresponding gate to gate 716. Activating one of the corresponding gates in 716 passes the output of adder 713, which combines the starting address with the memory address of the corresponding location from hash filter 702 or hash filter 704. The address is then passed to refresh control logic via multiplexer 718 to perform a refresh on the indicated row. The output of multiplexer 720 combines the output of gate 714 such that if at least one of the signals from gate 714 indicates a match between the counter value and hash filter 702 or hash filter 704, the enable signal SEL_EN is triggered, thereby instructing the refresh control logic to continue the refresh operation. When there is no match between the counter value and hash filter 702 or hash filter 704, the enable signal SEL_EN is turned off to indicate that a refresh operation should not be performed on that counter value. Normally, the enable signal during row-selective refresh operations remains active while the selected row is being refreshed and then deactivated until a new refresh cycle begins.

[0080] exist Figure 8 Example methods are shown in the figure. Figure 8 This is a flowchart illustrating a row-selective refresh operation performed by a memory system according to some embodiments of the present disclosure. Method 800 begins at block 802, wherein a hash filter indicating a valid row in the memory array is obtained (e.g., by receiving) from a host device. The hash filter may be received by the memory controller 180 of the memory system 250 from the memory controller 130 of the host 110 via channel 190. The hash filter may be received as part of a command transmitted on the command and address CA bus of channel 190. Alternatively, the hash filter may be received as part of data transmitted on the DQ bus of channel 190.

[0081] At box 804, the memory system receives an indication that the host device is entering a sleep mode. This indication causes the memory controller 180 to assume responsibility for refreshing the memory array 175 without further input from the host 110 until a new instruction to change the refresh mode is received. The indication that the host 110 is entering a sleep mode may be in the format of an instruction that allows the memory system 250 to enter a specific sleep mode that permits the host 110 to enter sleep mode.

[0082] In some implementations, the operations of blocks 802 and 804 can be performed by a single operation. For example, a command to initiate a row-selective self-refresh operation may include a hash filter. As another example, an indication that host 110 is entering sleep mode may include a hash filter. Using a single command that delivers the self-refresh instruction and the hash filter can help reduce the clock cycles of channel 190 occupied by overhead information.

[0083] At block 806, the memory system performs selective row refresh of the memory array based on a hash filter. The refresh can be performed by logic circuitry 162 in memory controller 180, such as generating... Figure 7 The described control signals (e.g., row selection and enable signals) Figure 5 The refresh unit is 520.

[0084] The host device can be configured with a memory system for execution. Figure 8 The self-refresh operation. Figure 9 This is a flowchart illustrating a host device operating a memory system to perform line-selective self-refresh according to one or more aspects of this disclosure. Method 900 begins at block 902, where the host processor receives an indication to enter a sleep mode. The indication may be triggered by information such as the location of the host device, the processing queue of the host device, user input specifying a low-power mode for the host device, and / or no user input to the host device within a predetermined time period. Although some examples of sleep modes are described, a sleep mode may refer to any low-power operating state during which the memory system will not be accessed by the host device for a certain period of time.

[0085] At box 904, the host processor saves context data to a subset of rows in the memory array of the memory system. Context data may include application data indicating the current state of processing performed by the host device, user data, register values ​​from the processor core, etc.

[0086] At block 906, the host processor determines a hash filter corresponding to a subset of the rows of data stored at block 904. In some embodiments, a table or other data structure of valid location may be maintained while the context data is stored at block 904, and the hash filter may be constructed based on the table or other data structure after the context data is stored. In some embodiments, the hash filter is updated as the context data is stored in the memory array. For example, first context data may be stored from a first application executing on the host processor at a first row address in the memory system. The first row address is then hashed, as described above with respect to Bloom filters or Cuckoo filters, and the hash filter is updated based on the hash value. Subsequently, second context data may be stored from a second application executing on the host processor at a second row address in the memory system. The second row address is then hashed, and the hash filter is updated based on the hash value. The process may be repeated for additional context data from additional applications until all context data has been stored in the memory system.

[0087] At block 908, the host processor copies the hash filter to the memory system. Copying may include storing the hash filter at a specific location in memory or appending the hash filter as a data value to a command transmitted to the memory system, such as a command for updating configuration registers or changing the mode of the memory system. In some embodiments, block 908 may involve the host processor sending a self-refresh command with the hash filter attached or a row-selective self-refresh command with the hash filter attached. In some embodiments, block 908 may involve the host processor sending a self-refresh command with an address in the memory array to the hash filter for use during a self-refresh operation.

[0088] At box 910, the host processor enters sleep mode. During sleep mode, the host processor can rely on the memory system to perform self-refresh operations without input from the host processor. While in sleep mode, power consumption by the host device is reduced by lowering the host processor's operating system to a lower voltage, lower frequency, deeper sleep state, and / or partially or fully power-gated the host processor. The host processor may later receive a trigger to exit sleep mode. Upon exiting sleep mode, the host processor may send a command to the memory system to exit the line-selective self-refresh operation mode so that the host processor can resume handling refresh operations.

[0089] Wireless communication devices may include at least Figure 1 and Figure 2The memory system illustrated herein is configured to receive and output data from a memory array and to perform refresh operations on the memory array. Memory systems according to any of the aspects disclosed herein can be configured or integrated into any processor-based device. Examples, without limitation, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, or avionics systems.

[0090] In one or more aspects, the techniques for memory storage and retrieval may include additional aspects, such as any single aspect or any combination of aspects described below or in conjunction with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations may include an apparatus comprising a memory controller coupled to a memory array via a first bus and configured to access data stored in the memory array via the first bus, the memory controller being configured to be coupled to a host device via a channel. Such the memory controller may be configured to receive, for example, a hash filter indicating a first subset of rows in the memory array from the host device via the channel; and to refresh a second subset of rows in the memory array by the memory controller based on the hash filter.

[0091] Additionally, the device may perform or operate according to one or more aspects described below. In some embodiments, the device includes a wireless device, such as a UE. In some embodiments, the device includes a remote server (such as a cloud-based computing solution) that receives image data, processes it, and determines output image frames. In some embodiments, the device may include at least one processor and memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the device. In some other embodiments, the device may include a non-transitory computer-readable medium having program code recorded thereon, and the program code may be executable by a computer to cause the computer to perform the operations described herein with reference to the device. In some embodiments, the device may include one or more components configured to perform the operations described herein. In some embodiments, a method of wireless communication may include one or more operations described herein with reference to the device.

[0092] In a second aspect, in conjunction with the first aspect, the hash filter indicates the valid rows of the memory array as the first subset of rows. In some aspects, the refresh is performed based on the hash filter only on the first subset of rows in the memory array, such that the second subset of rows is the first subset of rows.

[0093] In a third aspect, in conjunction with one or more of the first or second aspects, the hash filter includes at least one of a Bloom filter, a Cuckoo filter, a Linear Probe filter, or an XOR filter.

[0094] In a fourth aspect, in conjunction with one or more of the first to third aspects, the device is further configured to receive an instruction from the host device to enter a self-refresh mode, wherein upon receiving the instruction to enter the self-refresh mode, the memory controller performs a refresh of the second subset of rows based on the hash filter.

[0095] In the fifth aspect, in conjunction with one or more of the first to fourth aspects, the hash filter is received as part of the instruction to enter the self-refresh mode.

[0096] In a sixth aspect, in conjunction with one or more of the first to fifth aspects, receiving the instruction to enter the self-refresh mode includes receiving an instruction for the host device to enter a sleep mode.

[0097] In the seventh aspect, in conjunction with one or more of the first to sixth aspects, the second subset of refreshing rows includes the first subset of refreshing only rows in the memory array.

[0098] In the eighth aspect, in conjunction with one or more of the first to seventh aspects, the second subset of refreshing rows based on the hash filter includes: incrementing a counter from a starting value to a count value; and for each value of the counter: determining the row address corresponding to the counter value based on the hash filter; and refreshing the memory array at that row address.

[0099] In the ninth aspect, in conjunction with one or more of the first to eighth aspects, determining the row address includes adding the value from the hash filter to the starting address, and the row address and the count value are received from the host device.

[0100] In the tenth aspect, in conjunction with one or more of the first to ninth aspects, the memory controller is configured to communicate with a memory module including a low-power double data rate (LPDDR) memory module.

[0101] In an eleventh aspect, a method includes: receiving, by a memory controller, a hash filter indicating a first subset of rows in a memory array from a host device via a first channel; and refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter.

[0102] In the twelfth aspect, in conjunction with one or more of the eleventh aspects, the hash filter indicates the valid rows of the memory array as the first subset of rows.

[0103] In the thirteenth aspect, in combination with one or more of the eleventh to twelfth aspects, the hash filter includes at least one of a Bloom filter, a Cuckoo filter, a linear probe filter, or an XOR filter.

[0104] In a fourteenth aspect, in conjunction with one or more of the first to thirteenth aspects, the method further includes receiving an instruction from the host device to enter a self-refresh mode, wherein upon receiving the instruction to enter the self-refresh mode, the memory controller performs a refresh of the second subset of rows based on the hash filter.

[0105] In the fifteenth aspect, in conjunction with one or more of aspects eleven to fourteen, the hash filter is received as part of the instruction to enter the self-refresh mode.

[0106] In the sixteenth aspect, in combination with one or more of aspects eleven to fifteen, receiving the instruction to enter the self-refresh mode includes receiving an instruction for the host device to enter a sleep mode.

[0107] In the seventeenth aspect, in conjunction with one or more of aspects eleven to sixteen, the second subset of refreshing rows includes the first subset of refreshing only rows in the memory array.

[0108] In the eighteenth aspect, in conjunction with one or more of aspects eleven to seventeen, and in conjunction with one or more of aspects one to eighteen, the second subset of refreshing rows based on the hash filter includes: incrementing a counter from a starting value to a count value; and for each value of the counter: determining the row address corresponding to the counter value based on the hash filter; and refreshing the memory array at that row address.

[0109] In the nineteenth aspect, in conjunction with one or more of aspects eleven to nineteen, determining the row address includes adding the value from the hash filter to the starting address, and the row address and the count value are received from the host device.

[0110] In the twentieth aspect, in conjunction with one or more of the eleventh to twentieth aspects, the memory controller is configured to communicate with a memory module including a low-power double data rate (LPDDR) memory module.

[0111] In a twenty-first aspect, an apparatus includes: at least one processor; and a memory controller coupled to the at least one processor and a memory system via a channel and configured to communicate with the memory system via the channel, wherein the at least one processor is configured to perform operations including: saving data to a first subset of rows in a memory array of the memory system via the memory controller; determining a hash filter corresponding to the first subset of rows; and copying the hash filter to the memory system via the memory controller.

[0112] In a twentieth aspect, in combination with one or more of aspects twenty-one to twenty-two, the at least one processor is configured to perform further operations including: receiving an instruction to enter a sleep mode, wherein saving the data is performed after receiving the instruction to enter the sleep mode; after receiving the instruction to enter the sleep mode, sending an instruction to enter a self-refresh mode to the memory system via the memory controller; and entering the sleep mode after copying the hash filter to the memory system.

[0113] In the twenty-third aspect, in combination with one or more of the twenty-first to twenty-third aspects, the data includes context data corresponding to at least some applications executing on the at least one processor when the instruction to enter the sleep mode is received.

[0114] In the twenty-fourth aspect, in combination with one or more of the twenty-first to twenty-fourth aspects, the hash filter includes at least one of a Bloom filter, a Cuckoo filter, a Linear Probe filter, or an XOR filter.

[0115] In the twenty-fifth aspect, in combination with one or more of the twenty-first to twenty-fifth aspects, the memory controller is configured to communicate with a double data rate (DDR) memory system.

[0116] In a twenty-sixth aspect, in combination with one or more of aspects twenty-one to twenty-six, a method for operating a memory system (such as a processor coupled to the memory system via a memory controller) includes: at least one processor of a host device coupled to the memory system via a channel through the memory controller saving data to a first subset of rows in a memory array of the memory system; the at least one processor determining a hash filter corresponding to the first subset of rows; and the at least one processor copying the hash filter to the memory system via the memory controller.

[0117] In a twenty-seventh aspect, in combination with one or more of aspects twenty-one to twenty-seven, the method includes: receiving an instruction to enter a sleep mode, wherein saving the data is performed after receiving the instruction to enter the sleep mode; after receiving the instruction to enter the sleep mode, the at least one processor sends an instruction to enter a self-refresh mode to the memory system via the memory controller; and entering the sleep mode after copying the hash filter to the memory system.

[0118] In the twenty-eighth aspect, in combination with one or more of the twenty-first to twenty-eighth aspects, the data includes context data corresponding to at least some applications executing on the at least one processor when the instruction to enter the sleep mode is received.

[0119] In the twenty-ninth aspect, in combination with one or more of the twenty-first to twenty-ninth aspects, the hash filter includes at least one of a Bloom filter, a Cuckoo filter, a Linear Probe filter, or an XOR filter.

[0120] In the thirtieth aspect, in conjunction with one or more of the twenty-first to thirtieth aspects, the device is a wireless device, such as user equipment or a base station.

[0121] In the description of the embodiments herein, numerous specific details (such as examples of specific components, circuits, and processes) are set forth to provide a thorough understanding of this disclosure. As used herein, the term "coupled" means a direct connection or a connection via one or more intermediate components or circuits. Additionally, specific terminology is set forth in the following description and for purposes of explanation in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that practicing the teachings disclosed herein may not require these specific details. In other instances, known circuits and devices are illustrated in block diagram form to avoid obscuring the teachings of this disclosure.

[0122] Certain portions of the following detailed description are presented using other symbolic representations of procedures, logic blocks, processes, and data bit operations within computer memory. In this disclosure, procedures, logic blocks, processes, etc., are conceived as a self-consistent sequence of steps or instructions that lead to a desired result. These steps are those that require physical manipulation of physical quantities. Although not strictly necessary, these physical quantities typically take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated within a computer system.

[0123] In the accompanying drawings, a single block can be described as performing one or more functions. The one or more functions performed by this block can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps are described below in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Moreover, the example device may include components other than those shown, including well-known components such as processors, memory, etc.

[0124] Unless otherwise specifically stated, it will be apparent from the following discussion that, throughout this application, the use of terms such as “access,” “receive,” “transmit,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” “set,” “generate,” etc., refers to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system.

[0125] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some parts of this disclosure. Although the description and examples herein use the term "device" to describe various aspects of this disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or part of a device for performing the described operations.

[0126] Certain components in a device or apparatus described as “parts for access,” “parts for receiving,” “parts for transmitting,” “parts for using,” “parts for selecting,” “parts for determining,” “parts for normalizing,” “parts for multiplying,” or other similarly named terms referring to one or more operations on data (such as image data) may refer to processing circuitry (e.g., application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the described functions by means of hardware, software, or a combination of hardware configured by software.

[0127] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0128] This article is about Figures 1 to 2 The components, functional blocks, and modules described include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, and so on, or any combination thereof. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other terms. Furthermore, the features discussed herein can be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0129] Those skilled in the art will understand that one or more blocks (or operations) described with reference to the accompanying drawings included with this specification can be combined with one or more blocks (or operations) described in another drawing with reference to the accompanying drawings. For example, one or more blocks (or operations) of FIG3 can be combined with... Figure 1 or Figure 2A combination of one or more boxes (or operations).

[0130] Those skilled in the art will also recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein are merely examples, and that components, methods, or interactions of various aspects of this disclosure may be combined or performed in ways other than those illustrated and described herein.

[0131] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the specific implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0132] Hardware and data processing means for implementing the various exemplary logic units, logic blocks, modules, and circuits described herein can be implemented or executed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic units, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some embodiments, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processes and methods may be performed by circuitry specific to a given function.

[0133] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware, including the structures disclosed in this specification and their structural equivalents or any combination thereof. Specific implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0134] If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that can reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any medium that can be implemented to transfer a computer program from one location to another. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible to a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operation of a method or algorithm may reside as a set of code and instructions or any combination of code and instructions on a machine-readable medium and a computer-readable medium that may be incorporated into a computer program product.

[0135] Various modifications to the specific embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles disclosed herein, and the novel features thereof.

[0136] Additionally, those skilled in the art will readily recognize that, for the convenience of describing the accompanying drawings, contrasting terms such as “upper” and “lower” or “front” and “back” or “top” and “bottom” or “forward” and “backward” are sometimes used, indicating relative positions on a correctly oriented page corresponding to the orientation of the drawings, and may not reflect the correct orientation of any device as implemented.

[0137] As used herein, the term "coupled to," in various tenses of the verb "couple," can mean that element A is directly connected to element B, or that other elements can be connected between elements A and B (i.e., element A and element B are indirectly connected) to perform certain intended functions. In the context of electrical components, the term "coupled to" can also be used herein to mean that conductors, traces, or other conductive materials are used to electrically connect elements A and B (and any components electrically connected between them). In some examples, the term "coupled to" means the transfer of electrical energy between elements A and B to perform certain intended functions.

[0138] In some examples, the term "electrical connection" means having current or being configured to have current flowing between components A and B. For example, in addition to wires, traces, or other conductive materials and components, components A and B may also be connected via resistors, transistors, or inductors. Furthermore, for radio frequency functions, components A and B may be "electrically connected" via capacitors.

[0139] Certain features described in this specification in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even originally claimed in this way, one or more features from the claimed combination may be removed from that combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0140] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring such operations to be performed in the indicated specific order or sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the figures may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be combined with the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any illustrated operation. In some contexts, multitasking and parallel processing are advantageous. Moreover, the separation of the various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, several other embodiments also fall within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result.

[0141] As used herein (including the claims), the term "or" in a list of two or more items means that any one of the listed items may be used alone, or any combination of two or more listed items may be used. For example, if a composition is described as containing component A, B, or C, the composition may contain A alone; B alone; C alone; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein (including the claims), "or" in a list of items beginning with "at least one of" indicates a separate list, such that a list such as "at least one of A, B, or C" refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination of any of these items.

[0142] The term “substantially” is defined as being largely but not necessarily entirely what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by one of ordinary skill in the art. In any specific implementation of the disclosure, the term “substantially” may be used in place of the “[percentage]” of the specified content, where the percentage includes 0.1%, 1%, 5%, or 10%.

[0143] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: a memory controller coupled to a memory array by a first bus and configured to access data stored in the memory array through the first bus, the memory controller configured to be coupled to a host device through a channel and configured to perform operations comprising: obtaining, from the host device through the channel, a hash filter indicating a first subset of rows in the memory array; and refreshing, by the memory controller based on the hash filter, a second subset of rows in the memory array.

2. The apparatus of claim 1, wherein the hash filter indicates active rows of the memory array as the first subset of rows.

3. The apparatus of claim 1, wherein the hash filter comprises at least one of a Bloom filter, a cuckoo filter, a linear probe filter, or an XOR filter.

4. The apparatus of claim 1, wherein the memory controller is configured to perform further operations comprising: receiving, from the host device, an indication to enter a self-refresh mode, wherein after receiving the indication to enter the self-refresh mode, the memory controller performs a refresh of the second subset of rows based on the hash filter.

5. The apparatus of claim 4, wherein the hash filter is received as part of the indication to enter the self-refresh mode.

6. The apparatus of claim 4, wherein receiving the indication to enter the self-refresh mode comprises receiving an indication that the host device is entering a sleep mode.

7. The apparatus of claim 1, wherein refreshing the second subset of rows comprises refreshing only the first subset of rows in the memory array.

8. The apparatus of claim 1, wherein refreshing the second subset of rows based on the hash filter comprises: incrementing a counter from a start value to a count value; and for each value of the counter: determining a row address corresponding to the counter value based on the hash filter; and refreshing the memory array at the row address.

9. The apparatus of claim 8, wherein: determining the row address comprises adding a value from the hash filter to a start address, and the row address and the count value are received from the host device.

10. The apparatus of claim 1, wherein the memory controller is configured to communicate with a memory module comprising a low-power double data rate (LPDDR) memory module.

11. A method comprising: obtaining, by a memory controller from a host device through a first channel, a hash filter indicating a first subset of rows in a memory array; and refreshing, by the memory controller based on the hash filter, a second subset of rows in the memory array.

12. The method of claim 11, wherein the hash filter indicates active rows of the memory array as the first subset of rows.

13. The method of claim 11, wherein the hash filter comprises at least one of a Bloom filter, a cuckoo filter, a linear probe filter, or an XOR filter.

14. The method of claim 11, further comprising: receiving, from the host device, an indication to enter a self-refresh mode, wherein refreshing the second subset of rows based on the hash filter is performed by the memory controller after receiving the indication to enter the self-refresh mode.

15. The method of claim 14, wherein the hash filter is received as part of the indication to enter the self-refresh mode.

16. The method of claim 14, wherein receiving the indication to enter the self-refresh mode comprises receiving an indication that the host device is entering a sleep mode.

17. The method of claim 11, wherein refreshing the second subset of rows comprises refreshing only the first subset of rows in the memory array.

18. The method of claim 11, wherein refreshing the second subset of rows based on the hash filter comprises: incrementing a counter from a start value to a count value; and for each value of the counter: determining a row address corresponding to the counter value based on the hash filter; and refreshing the memory array at the row address.

19. The method of claim 18, wherein: determining the row address comprises adding a value from the hash filter to a start address, and the row address and the count value are received from the host device.

20. The method of claim 11, wherein the memory controller is configured to communicate with a memory module comprising a low power double data rate (LPDDR) memory module.

21. An apparatus comprising: at least one processor; and a memory controller coupled to the at least one processor and a memory system by a channel and configured to communicate with the memory system over the channel, wherein the at least one processor is configured to perform operations comprising: saving, by the memory controller, data to a first subset of rows in a memory array of the memory system; determining a hash filter corresponding to the first subset of rows; and copying, by the memory controller, the hash filter to the memory system.

22. The apparatus of claim 21, wherein the at least one processor is configured to perform further operations comprising: receiving an indication to enter a sleep mode, wherein saving the data is performed after receiving the indication to enter the sleep mode; after receiving the indication to enter the sleep mode, sending, by the at least one processor, an indication to enter a self-refresh mode to the memory system by the memory controller; and entering the sleep mode after copying the hash filter to the memory system. ​ ​ 23. The apparatus of claim 22, wherein the data comprises context data corresponding to at least some applications executing on the at least one processor when the indication to enter the sleep mode is received.

24. The apparatus of claim 22, wherein the hash filter comprises at least one of a Bloom filter, a cuckoo filter, a linear probe filter, or an XOR filter.

25. The apparatus of claim 21, wherein the memory controller is configured to communicate with a double data rate (DDR) memory system.

26. A method comprising: saving, by at least one processor of a host device coupled to a memory system via a memory controller over a channel, data to a first subset of rows in a memory array of the memory system by the memory controller; determining, by the at least one processor, a hash filter corresponding to the first subset of rows; and copying, by the at least one processor, the hash filter to the memory system by the memory controller.

27. The method of claim 26, further comprising: receiving an indication to enter a sleep mode, wherein saving the data is performed after receiving the indication to enter the sleep mode; sending, by the at least one processor, an indication to enter a self-refresh mode to the memory system by the memory controller after receiving the indication to enter the sleep mode; and entering the sleep mode after copying the hash filter to the memory system.

28. The method of claim 27, wherein the data comprises context data corresponding to at least some applications executing on the at least one processor when the indication to enter the sleep mode is received.

29. The method of claim 27, wherein the hash filter comprises at least one of a Bloom filter, a cuckoo filter, a linear probe filter, or an XOR filter.

30. The method of claim 26, wherein the memory controller is configured to communicate with a double data rate (DDR) memory system. ​ ​

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