Ideal diode bridge controller

Abstract

An ideal diode bridge controller is provided that includes a gate driver for connection to transistors of a bridge rectifier, where the transistors are arranged as high-side transistors and low-side transistors. The gate driver alternately switches the transistors such that the bridge rectifier converts an input voltage of any one of the two polarities to an output voltage of one of the two polarities. The gate drivers include low-side gate drivers for the low-side transistors, and respective ones of the low-side gate drivers include a linear drive circuit and a digital drive circuit. The linear driving circuits drive the respective low-side transistors to turn on and off based on forward currents through the respective low-side transistors. The digital drive circuit detects a reverse current through the respective low-side transistor and turns off the respective low-side transistor in response to the reverse current.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to diode bridges, and in particular to ideal diode bridge controllers. BACKGROUND

[0002] Power over Ethernet (PoE) is a technology that allows the transmission of both power and data over standard Ethernet network cables. It eliminates the need for separate power cables, enabling devices to receive power and achieve network connectivity through a single Ethernet cable.

[0003] With PoE, devices such as IP cameras, wireless access points, VoIP phones, and other networked devices can be powered directly through the Ethernet infrastructure. This simplifies the installation and deployment of these devices, especially in situations where power outlets can not be readily available.

[0004] PoE operates by using the wires in an Ethernet cable to carry power along with data signals. This is accomplished by injecting power into the cable at a Power Sourcing Equipment (PSE), which can be a PoE-enabled switch or a PoE injector, which can also be referred to as a midspan device. Power is then extracted at a Powered Device (PD), which is the device that receives both power and data.

[0005] There are different versions of PoE. The original PoE standard, also known as IEEE 802.3af, can deliver up to 15.4 watts of power per port. A newer PoE standard, known as IEEE 802.3at, provides higher power delivery of up to 30 watts per port. Another PoE standard, known as IEEE 802.3bt, can deliver even higher power levels, up to 90 watts per port. SUMMARY

[0006] Different versions of PoE do not guarantee the voltage polarity at the Power Interface (PI) of the Ethernet cable; and thus, PoE systems typically include a diode bridge to ensure the correct polarity at the PD input. Newer versions of PoE have achieved higher power delivery by increasing the current, but this has resulted in greater power loss in the diode bridge. An ideal diode bridge can be utilized to reduce power loss, which includes an ideal diode bridge controller connected to a bridge rectifier. In an ideal diode bridge, the diodes of the diode bridge are replaced by transistors that are alternately turned on and off by the ideal diode bridge controller to emulate the diode bridge. However, many conventional ideal diode bridge controllers are insufficient for use in PoE systems.

[0007] Example implementations of the present disclosure relate to diode bridges, and in particular to ideal diode bridge controllers. The present disclosure includes, but is not limited to, the following example implementations.

[0008] Some example implementations provide an ideal diode bridge controller comprising a gate driver for connection to transistors of a bridge rectifier, wherein the transistors are arranged as high-side transistors and low-side transistors, the gate driver for alternately turning on and off the transistors in pairs to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities, the gate driver comprising high-side gate drivers for the high-side transistors and low-side gate drivers for the low-side transistors, a respective one of the low-side gate drivers comprising a linear drive circuit for driving a respective one of the low-side transistors on and off based on a forward current through the respective one of the low-side transistors, and a digital drive circuit for detecting a reverse current through the respective one of the low-side transistors and causing the respective one of the low-side transistors to turn off in response to the reverse current.

[0009] Some example implementations provide a method comprising alternately turning on and off transistors of a bridge rectifier in pairs to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities, the transistors arranged as high-side transistors turned on and off by high-side gate drivers and low-side transistors turned on and off by low-side gate drivers, a respective one of the low-side gate drivers comprising a linear drive circuit and a digital drive circuit; driving, by the linear drive circuit, a respective one of the low-side transistors on and off based on a forward current through the respective one of the low-side transistors; and at the digital drive circuit, detecting a reverse current through the respective one of the low-side transistors; and causing the respective one of the low-side transistors to turn off in response to the reverse current.

[0010] It will be appreciated that this Summary is provided merely for purposes of summarizing some example implementations so as to provide a basic understanding of some aspects of the disclosure. Accordingly, it will be appreciated that the above-described example implementations are merely examples and should not be construed as limiting the scope or spirit of the disclosure in any way. Other example implementations, aspects and advantages will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of some of the described example implementations. BRIEF DESCRIPTION OF DRAWINGS

[0011] Having generally described an example implementation of the present disclosure, a specific example implementation will now be described with reference to the following drawings, which are not necessarily drawn to scale, and wherein:

[0012] Figure 1 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure;

[0013] Figure 2 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure that is similar to Figure 1 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure that is similar to

[0014] Figure 3 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure that can correspond to Figure 2 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure that can correspond to

[0015] Figure 4 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure that includes two bridge rectifiers;

[0016] Figure 5 A block diagram of a Power over Ethernet (PoE) system is illustrated in accordance with some example implementations of the disclosure that includes Figure 4 An ideal diode bridge controller is illustrated in accordance with some example implementations of the disclosure that includes

[0017] Figure 6 Various operations in a method of operating an ideal diode bridge controller are illustrated in accordance with some example implementations of the disclosure;

[0018] Figure 7 Plots of various currents and voltages during simulation of an ideal diode bridge controller are illustrated in accordance with some example implementations of the disclosure; Figure 3

[0019] Figure 8A Figure 8B Figure 8C Figure 8D Figure 8E Figure 8F Figure 8G Figure 8H Figure 8I 8J are flow diagrams illustrating various steps in a method in accordance with various example implementations. DETAILED DESCRIPTION

[0020] Some implementations of the disclosure will now be described more fully with reference to the accompanying drawings, in which some, but not all, implementations of the disclosure are illustrated. Indeed, the various implementations of the disclosure can be embodied in many different forms and should not be construed as limited to the specific implementations set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.​​​​​​​​​​

[0021] Unless otherwise specified or clear from the context, references to first, second, etc., should not be construed as implying a particular order. A feature described as above another feature (unless otherwise specified or clear from the context) may alternatively be below, and vice versa; and similarly, a feature described as to the left of another feature may alternatively be to the right, and vice versa. Furthermore, while references may be made herein to quantitative measurements, values, geometric relationships, etc., any one or more (if not all) of these quantitative measurements, values, geometric relationships, etc., may be approximate to account for acceptable variations that may occur, such as variations due to engineering tolerances, etc., unless otherwise stated.

[0022] As used herein, unless otherwise specified or clearly indicated from the context, an "OR" of a set of operands is an "inclusive OR," and thus the "OR" is true if and only if one or more of the operands are true, as opposed to an "exclusive OR," which is false when all operands are true. Therefore, for example, "[A] OR [B]" is true if [A] is true, or if [B] is true, or if both [A] and [B] are true. Furthermore, unless otherwise specified or clearly indicated from the context, the article "a" means "one or more." Additionally, it should be understood that, unless otherwise specified, the terms "data," "content," "digital content," "information," and similar terms are sometimes used interchangeably.

[0023] This disclosure relates to exemplary embodiments of diode bridges, and more specifically to an ideal diode bridge controller for Power over Ethernet (PoE). The features, aspects, and advantages of this disclosure will be apparent from the following detailed description and the accompanying drawings, which are briefly described below. This disclosure includes any combination of two, three, four, or more features or elements set forth in this disclosure, whether or not such features or elements are expressly combined or otherwise described in the particular exemplary embodiments described herein. This disclosure is intended to be read holistically such that, unless the context of this disclosure clearly specifies otherwise, any separable feature or element of this disclosure should be considered composable in all its aspects and in any aspect and exemplary embodiment.

[0024] Figure 1An ideal diode bridge 100 is illustrated according to some examples of implementations of this disclosure. As shown, the ideal diode bridge 100 includes an ideal diode bridge controller 102 connected to a bridge rectifier 104. The bridge rectifier includes transistors Q1, Q2, Q3, and Q4 arranged in two branches bridged by a pair of inputs IN1A and IN1B. As shown, in some examples, the transistors are field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs). The transistors include high-side transistors Q2 and Q3 and low-side transistors Q1 and Q4. In some examples, the bridge rectifier includes a pair of outputs VOUTP and VOUTN, to which an output voltage is provided; in some of these examples, the high-side transistors Q2 and Q3 are connected between the positive output (i.e., VOUTP) of the pair of outputs and the corresponding inputs of the pair of inputs IN1A and IN1B, respectively, and the low-side transistors Q1 and Q4 are connected between the corresponding inputs of the pair of inputs IN1A and IN1B and the negative output (i.e., VOUTN), respectively.

[0025] The ideal diode bridge controller 102 includes gate drivers 106 connected to the pair of inputs IN1A, IN1B and transistors Q1, Q2, Q3, Q4 to alternately turn the transistors on and off in pairs (Q2, Q4) and (Q3, Q1), so that the bridge rectifier simulates a diode bridge for the input voltage at the pair of inputs. In some examples, the gate drivers can cause the bridge rectifier 102 to convert an input voltage of either polarity to an output voltage of one polarity. Gate drivers 106 include a high-side gate driver 108 for the high-side transistors Q2, Q3 and a low-side gate driver 110 for the low-side transistors Q1, Q4.

[0026] For example Figure 1 As shown, the corresponding low-side gate driver in low-side gate driver 110 includes a linear drive circuit 112 and a digital drive circuit 114. The linear drive circuit 112 (sometimes referred to as a linear driver or linear driver circuit) is an electronic circuit that provides a proportional and continuous output in response to a changing input signal. The digital drive circuit (sometimes referred to as a digital driver or digital driver circuit) is an electronic circuit that provides a discrete output (e.g., logic high or logic low) in response to an input signal.

[0027] According to some example implementations of the present disclosure, the linear drive circuit 112 can drive a respective one of the low-side transistors Q1 / Q4 to turn on and off based on a forward current passing through the respective one of the low-side transistors. The digital drive circuit 114 can detect a reverse current passing through the respective one of the low-side transistors Q1 / Q4 and turn off the respective one of the low-side transistors in response to the reverse current.

[0028] In the ideal diode bridge controller 102, the forward current is the current flowing from IN1A / IN1B (depending on the polarity) to VOUTP; and thus, the forward current flows from the source to the drain of the pair of transistors that are turned on (Q2, Q4) or (Q3, Q1) (as shown, the source and drain are labeled as “S” and “D,” respectively). The reverse current is the current flowing from VOUTP to IN1 / IN2; and thus, the reverse current flows from the drain to the source of the pair of transistors that are turned on.

[0029] Figure 2 An ideal diode bridge 100 is illustrated according to some example implementations, which includes an ideal diode bridge controller 202 similar to the ideal diode bridge controller 102 and includes a control circuit 204. In some of these example implementations, the control circuit 204 is to selectively enable and disable the gate drivers 106, which can include the linear drive circuit 112 and the digital drive circuit 114 of a respective one of the low-side gate drivers 110. In some examples, the control circuit 204 can enable and disable the gate drivers 106 in pairs alternately corresponding to the pairs of transistors that are turned on and off alternately (Q2, Q4), (Q3, Q1). In some examples, the control circuit 204 can receive a signal from the digital drive circuit 114 indicating that a reverse current is detected and disable the gate drivers 106 in response to the signal. As also shown, the control circuit 204 can include an under-voltage lockout (UVLO) circuit 206 to disable the gate drivers 106 when the input voltage is below a threshold voltage and to enable the gate drivers 106 when the input voltage is greater than the threshold voltage. Hysteresis can be supplied by the UVLO circuit 206.

[0030] As indicated above, the ideal diode bridge 100 of some example implementations can be designed for Power over Ethernet (PoE). Then, in some examples, the ideal diode bridge controller 202 can be capable of connecting to a powered device (PD) of a PoE system or constituent components of the powered device (PD), and the ideal diode bridge controller 202 and the PD can be capable of connecting to an external power source, such as a wall adapter (WA). In some of these examples, the control circuit 204 can detect that the PD is connected to the external power source, and disable the gate driver 106 when the ideal diode bridge controller 202 and the PD are connected to the external power source.

[0031] Also as Figure 2 indicated and explained in greater detail below, in some examples, a respective one of the high-side gate drivers 108 can include a digital drive circuit 208 for driving a respective one of the high-side transistors Q2 / Q3 on and off based on a forward current through the respective one of the high-side transistors.

[0032] Figure 3 An ideal diode bridge 100 according to some example implementations is illustrated, including an ideal diode bridge controller 302 that can correspond to the ideal diode bridge controller 202. As shown, the digital drive circuit 208 of a respective one of the high-side gate drivers 108 can include a comparator U2 / U3 for comparing a source voltage V S and a drain voltage V D (shown as source voltage V S-Q2 / Q3 and drain voltage V D-Q2 / Q3 ) of a respective one of the high-side transistors Q2 / Q3, and outputting a switch signal to turn the respective one of the high-side transistors Q2 / Q3 on when the source voltage V S is greater than the drain voltage V D , which indicates that current is flowing through the MOSFET body diode of the respective one of the high-side transistors Q2 / Q3. Also as shown, in some examples, the comparator U2 / U3 can drive a respective one of the low-side transistors Q2 / Q3 through a respective buffer U13 / U14. The respective buffer U13 / U14 can be a tri-state buffer with an enable / disable input supplied by the control circuit 204 that can be used to set the respective buffer U13 / U14 to a high impedance state to effectively disconnect the output of the respective buffer U13 / U14 from the gate of the respective transistor Q2 / Q3, and thereby disable the comparator U2 / U3 and the digital drive circuit 208.

[0033] In some examples, the digital drive circuit 208 includes a voltage offset V comp-on (implemented as a voltage source); and in some of these examples, the comparator U2 / U3 outputs a switching signal when the source voltage V S is at least the voltage offset (V D greater than the drain voltage V S >(V D +V comp-on ). The voltage offset and other voltage offsets described herein can be trimmable in that the voltage offset can be adjusted or tweaked to a particular value to improve the performance of the ideal diode bridge controller 300. Also as shown, in some examples, the digital drive circuit 208 includes a charge pump 304 connected to the comparator U2 / U3 and to the buffer U13 / U14, such that the switching signal output by the comparator U2 / U3 and buffered by the buffer U13 / U14 (if provided) is boosted to an appropriate voltage to drive the respective one of the high-side transistors Q2 / Q3. Also as shown, in some examples, the output of the respective comparator U2 / U3 is fed to the respective drive circuit U13 / U14, which drives the respective one of the high-side transistors Q2 / Q3.

[0034] Attention is now directed to the low-side gate driver 110. Again, a respective one of the low-side gate drivers includes a linear drive circuit 112 and a digital drive circuit 114. As Figure 3 shown, in some examples, the linear drive circuit 112 of a respective one of the low-side gate drivers 110 includes an operational amplifier U5 / U6 that includes a non-inverting input (+) and an inverting input (-) connected to the source and drain, respectively, of the respective one of the low-side transistors Q1 / Q4. Also as shown, in some examples, the operational amplifier U5 / U6 can drive the respective one of the low-side transistors Q1 / Q4 through a respective buffer U7 / U10. Like the buffer U13 / U14, the respective buffer U7 / U10 can be a tri-state buffer with an enable / disable input supplied by the control circuit 204 that can be used to set the respective buffer U7 / U10 to a high-impedance state to effectively disconnect the output of the respective buffer U7 / U10 from the gate of the respective transistor Q1 / Q4 and thereby disable the operational amplifier U5 / U6 and the linear drive circuit 112.

[0035] In some examples, the operational amplifier U5 / U6 can regulate the forward voltage of a respective one of the low-side transistors Q1 / Q4 based on the forward current. In the ideal diode bridge controller 302, the forward voltage of a respective one of the low-side transistors Q1 / Q4 is the positive voltage between the source and the drain of the respective one of the low-side transistors Q1 / Q4, i.e., the source is at a higher voltage than the drain. In some examples, the linear driver circuit 112 can include a voltage offset V opamp-reg (implemented as a voltage source) that sets the minimum voltage to which the operational amplifier U5 / U6 regulates the forward voltage in the linear mode of the respective one of the low-side transistors Q1 / Q4. The operational amplifier U5 / U6 can provide a gate-to-source voltage to regulate the forward voltage for the forward current up to a corresponding current for the voltage offset and the characteristic on-resistance R DS(on) of the respective one of the low-side transistors Q1 / Q4 in the saturation mode, i.e., forward current = V opamp-reg / R DS(on) . Then, when the forward current increases to be greater than V opamp-reg / R DS(on) , i.e., where the forward voltage is greater than V opamp-reg , i.e., in the saturation mode of the respective one of the low-side transistors Q1 / Q4, the forward voltage depends on the characteristic on-resistance R DS(on) and is not regulated by the operational amplifier U5 / U6.

[0036] In some examples, the digital drive circuit 114 of a respective one of the low-side gate drivers 110 includes a comparator U1 / U4 that includes a non-inverting input (+) and an inverting input (-) connected to the drain and the source of the respective one of the low-side transistors Q1 / Q4.

[0037] In some examples, the comparator U1 / U4 can compare the drain voltage V D and the source voltage V S (shown as the source voltage V S-Q1 / Q4 and the drain voltage V D-Q1 / Q4 ) of the respective one of the low-side transistors Q1 / Q4. When the drain voltage V D is greater than the source voltage V S , the comparator can output a signal to turn off the respective one of the low-side transistors, which indicates that a reverse current is detected. As shown, in some examples, the comparator U1 / U4 can drive the respective one of the low-side transistors Q1 / Q4 through a respective buffer U8 / U12.

[0038] In some further examples, the digital drive circuit 114 includes a voltage offset V comp-off ; and in some of these examples, the comparator U1 / U4 can output a signal when the drain voltage V D is at least the voltage offset greater than the source voltage V S ((V D -V comp-off )>V S ). The reverse current at this time can be V comp-off / R DS(on) , where R DS(on) is the characteristic on-resistance R DS(on) of the respective one of the low-side transistors Q1 / Q4.

[0039] As also shown, in some examples, the digital drive circuit 114 includes a switching transistor Q5 / Q6 connected to the respective one of the low-side transistors Q1 / Q4, such as in a low-side switching fashion. In this regard, a low-side switch is a switch positioned on the “low side” of a load of the ideal diode bridge controller 300 (i.e., the side of the load closer to VOUTN). In some of these examples, the signal output by the comparator U1 / U4 is a switching signal for driving the switching transistor Q5 / Q6 on, which pulls down the gate voltage of the respective one of the low-side transistors Q1 / Q4 to turn off the respective one of the low-side transistors.

[0040] In some further examples, the signal output by the comparator U1 / U4 is a first signal, and the control circuit 204 outputs a second signal to selectively enable the digital drive circuit 114. In these examples, the digital drive circuit 114 includes a logic OR gate U9 / U11 to turn off the respective one of the low-side transistors Q1 / Q4 in response to the first signal from the comparator or the second signal from the control circuit 204. In this regard, the logic OR gate can output a switching signal to drive the switching transistor Q5 / Q6 on and to pull down the gate voltage of the respective one of the low-side transistors Q1 / Q4 to turn off the respective one of the low-side transistors.

[0041] As also shown, in the context of an ideal diode bridge controller 300 connected to a PD of a POE system, the control circuit 204 can include an input WA_Enable that can indicate that the ideal diode bridge controller 300 and the PD are connected to an external power source. In these cases, the control circuit 204 can disable the gate driver 106. Disabling the gate driver 106 in these and other cases can involve the control circuit sending appropriate signals to the tri-state buffers U7, U10 of the linear driver circuit 112 of the low-side gate driver 110 to disable the linear driver circuit by setting the tri-state buffers U7, U10 of the linear driver circuit 112 to a high impedance state. The control circuit can likewise send appropriate signals to the tri-state buffers U13, U14 of the high-side gate driver 208 to disable the high-side gate driver by setting the tri-state buffers U13, U14 of the high-side gate driver 208 to a high impedance state. Still further, as described above, the control circuit can send appropriate (second) signals to the OR logic gates U9, U11 of the digital driver circuit 114 of the low-side gate driver 110 to drive the switch transistors Q5 / Q6 on and pull down the gate voltage of a respective one of the low-side transistors Q1 / Q4 to turn off the respective one of the low-side transistors.

[0042] In some examples, the ideal diode bridge controller 102, 202, 302 can be implemented in a dual bridge rectifier. Figure 4 An ideal diode bridge 400 is illustrated that includes at least one ideal diode bridge controller 402 and two bridge rectifiers 404, in accordance with some example implementations. In this regard, the ideal diode bridge 400 can include two ideal diode bridge controllers 402 for the two bridge rectifiers 404. As shown, one of the two bridge rectifiers 404 can be coupled to the inputs IN1A, IN2A, and the other of the two bridge rectifiers 404 can be coupled to the inputs IN1B, IN2B. Then, an input voltage can be provided at the pair of inputs of either of the two bridge rectifiers 404, which converts the input voltage to an output voltage that can be provided to a pair of outputs VOUTP, VOUTN connected to two of the two bridge rectifiers, and the output voltage is provided to the pair of outputs. As also shown, the high-side transistors Q2, Q3 of the respective two bridge rectifiers 404 are connected to the positive output in the pair of outputs VOUTP, and the low-side transistors Q1, Q4 of the respective two bridge rectifiers 404 are connected to the negative output in the pair of outputs VOUTN. Although in the example shown the two bridge rectifiers 404 are connected to the same pair of outputs VOUTP, VOUTN, in other examples the two bridge rectifiers 404 can be connected to different pairs of outputs. Figure 4The diode bridge controller 402 is not shown separately, but the diode bridge controller 402 can include a control circuit 204 for a respective one of the two bridge rectifiers 404, or the diode bridge controller 402 can include a single control circuit for both of the two bridge rectifiers 404.

[0043] Figure 5 is a block diagram of a Power over Ethernet (PoE) system 500 including the ideal diode bridge 400 in accordance with some example implementations. Again, the PoE system can include an Ethernet cable 502 to carry power along with data signals. Power can be injected into the Ethernet cable 502 at a Power Sourcing Equipment (PSE). Power can then be extracted at a Powered Device (PD) 504, which is a device that receives power and data over the Ethernet cable 502. In this regard, the PD 504 can accept power carried over the Ethernet cable 502 (through which data is carried) and the ideal diode bridge 400 can provide polarity correction for the power carried over the Ethernet cable. As shown, the PD 504 can accept power from a Power Interface (PI) 506 (such as an Ethernet (e.g., RJ-45) connector) of the Ethernet cable, from which the PD 504 receives power from the ideal diode bridge converter 400.

[0044] In the PoE system 500, when a PD is connected to a PSE over the Ethernet cable 502, the PD 504 and the PSE can perform a handshake procedure. When the PD 504 is connected to the PSE over the Ethernet cable 502, the PSE performs a detection operation to determine whether the PD 504 is PoE compliant and a classification operation to determine power requirements of the PD 504. In the PoE system 500 of the example implementations of the present disclosure, the ideal diode bridge controller 402 of the ideal diode bridge 400 can include an enable input to enable or disable the ideal diode bridge controller and thereby the ideal diode bridge. In some examples, the PD 504 can then provide a logic high voltage to the enable input to disable the ideal diode bridge controller 402 during the detection and classification operations to reduce the effect of the ideal diode bridge 400 drawing current on the detection and classification currents.

[0045] The linear drive circuit 112 and the digital drive circuit 114 of the respective low-side gate driver in the low-side gate driver 110 can cooperate to enable the low-side gate driver 110 in response to the linear drive circuit 112 to turn on the transistor Q1 / Q4 in a controlled and smooth manner and in response to the digital drive circuit 114 to turn off the transistor Q1 / Q4 quickly (e.g., within less than 100 nanoseconds). In this context, “quickly” and similar terms refer to a time shorter than the rise time of a surge waveform, as specified by the International Telecommunication Union (ITU) Recommendation ITU-T K.21, Resistibility of Telecommunication Equipment Installed in Customer Premises to Overvoltages and Overcurrents (2022). In one example, the transistor Q1 / Q4 can be turned off quickly when the ideal diode bridge 400 and the PD 504 are connected to the external power source 508, where the external power source 508 provides a voltage greater than the input voltage. In another example, in the case of a negative current lightning surge, the transistor Q1 / Q4 can be turned off quickly in response to the digital drive circuit 114 to prevent a short circuit between the PSE and the lightning surge voltage.

[0046] The linear drive circuit 112 placed at the low-side gate driver 110 can also provide benefits over the high-side gate driver 108. In this regard, the linear drive circuit can avoid the need for a charge pump 304 of a relatively large high-side gate driver 108, where operational amplifiers U5, U6 provide sufficient current on the low side. When the ideal diode bridge controller 102 is implemented in an integrated circuit (IC), placing the linear drive circuit 110 at the low-side gate driver can thus reduce the footprint of the ideal diode bridge controller 102, 202, or 302 and lower the cost of the IC.

[0047] To further illustrate example implementations of the present disclosure, Figure 6 Various operations in a method of operating an ideal diode bridge controller 102, 202, or 302 are illustrated in accordance with some example implementations. As shown at blocks 602, 604, and 606, the control circuit 204 can enable the ideal diode bridge controller when the input voltage is greater than an under-voltage lockout (UVLO) voltage and the ideal diode bridge controller is not connected to an external power source (e.g., as indicated by a logic low voltage at an enable input of the ideal diode bridge controller).

[0048] When the forward source-to-drain current flows through a pair of transistors (Q2, Q4) but not through another pair of transistors (Q3, Q1), the gate driver 106 turns on the pair of transistors (Q2, Q4), as shown in boxes 608, 610, and 612. Figure 3 As shown, for example, control circuit 204 can receive an input indicating the current flowing through transistors Q1, Q2, Q3, and Q4 from the outputs of comparators U1, U2, U3, and U4. To turn on the pair of transistors (Q2, Q4), the control circuit can send an appropriate signal to the buffers (U13, U10) to enable the corresponding gate drivers in the high-side gate driver 108 and low-side gate driver 110. Alternatively, the gate drivers turn on another pair of transistors (Q3, Q1) when the positive source-to-drain current flows through the other pair of transistors (Q3, Q1) but not through the pair of transistors (Q2, Q4), as shown in boxes 614, 616, and 618. Similarly, as... Figure 3 As shown, for example, control circuit 204 can send appropriate signals to buffers (U14, U7) to enable the corresponding gate drivers in high-side gate driver 108 and low-side gate driver 110 to turn on another pair of transistors (Q3, Q1).

[0049] When the pair of transistors (Q2, Q4) is turned on and a reverse drain-to-source current is detected through the pair of transistors (Q2, Q4), control circuitry 204 disables gate driver 106, and in particular digital drive circuitry 114, 208, to quickly turn off the pair of transistors (Q2, Q4), as shown in boxes 620 and 622. Specifically, for example, control circuitry may send appropriate signals to buffer U13 and logic OR gate U11 to disable the corresponding digital drive circuitry in digital drive circuitry 114, 208 for the pair of transistors (Q2, Q4). Similarly, when another pair of transistors (Q3, Q1) is turned on and a reverse drain-to-source current is detected through the other pair of transistors (Q3, Q1), control circuitry disables gate driver 106 to quickly turn off the other pair of transistors (Q3, Q1), as shown in boxes 624 and 626. When the control circuit detects that the ideal diode bridge controller is connected to an external power supply (as indicated by a logic high voltage at the enable input of the ideal diode bridge controller), the control circuit can also quickly turn off the pair of transistors (Q2, Q4), (Q3, Q1) or another pair of transistors, as shown in boxes 628 and 630.

[0050] Figure 7Graphs illustrating various currents and voltages over time during simulation of an ideal diode bridge controller 302 are exemplified in accordance with some example implementations. In the exemplified example, the low-side transistors Q1, Q4 have a 2.5V threshold voltage and a 5V saturation voltage, but in other examples, the low-side transistors Q1, Q4 can have other characteristic voltages. As shown, current initially flows through the body diode of the respective one of the low-side transistors Q1 / Q4, as indicated by the gate-to-source voltage being zero. This can also be indicated by the source-to-drain voltage of the respective one of the low-side transistors Q1 / Q4 increasing to about 375mV, which is the forward voltage drop across the body diode when current is flowing through the body diode.

[0051] When the voltage across the body diode becomes greater than V opamp-reg (plus op-amp internal offset), the op-amp U5 / U6 begins to regulate the forward voltage of Q1 / Q4 source-to-drain to V opamp-reg , until the load current is V opamp-reg / R DS(on) , where R DS(on) is the on-resistance of Q1 / Q4. This can be seen in the figures, where the gate-to-source voltage is above the 2.5V threshold voltage of the respective one of the low-side transistors Q1 / Q4, but less than the 5V saturation voltage, indicating that the respective one of the low-side transistors Q1 / Q4 is not fully on.

[0052] For load currents greater than V opamp-reg / R DS(on) , the forward voltage depends on R RD(on) . That is, when the forward voltage of the respective one of the low-side transistors Q1 / Q4 is greater than V opamp-reg , the op-amp U5 / U6 can regulate the forward voltage. Although Figure 7 is not shown, if V opamp-reg = 20mV and R RD(on) = 50mOhm, for example, then the op-amp U5 / U6 can regulate the forward voltage of Q1 / Q4 to current = 20mV / 50mOhm = 400mA. For load currents greater than 400mA, Q1 / Q4 can be fully enhanced and the forward voltage increases based on the load current until it reaches the saturation voltage of Q1 / Q4, which in this example is 5V.

[0053] In the ideal diode bridge controller 302, forward current flows from the source to the drain of one of the transistor pairs (Q2, Q4) or (Q3, Q1). When an external power supply is connected to the ideal diode bridge controller 302 and PD, and the voltage of the external power supply is greater than the input voltage of the ideal diode bridge controller 302, current from the external power supply can flow from the drain to the source, damaging the PSE. Therefore, the comparators U1 / U4 of the digital drive circuit 114 can monitor the reverse current from the drain-to-source voltage and respond to the reverse current, such as when the reverse current reaches V... comp-off / R DS(on) When the value is set to a certain value, the corresponding low-side transistor in Q1 / Q4 is turned off very quickly. The gate driver 106 for the transistor can also be disabled by the control circuit 204.

[0054] Figures 8A to 8J This is a flowchart illustrating various steps in a method 800 implemented according to various examples. The method includes alternately turning transistors of a bridge rectifier on and off in pairs, such that the bridge rectifier converts an input voltage of either polarity into an output voltage of one polarity, as shown below. Figure 8A As shown in block 802, the transistors are arranged as high-side transistors turned on and off by high-side gate drivers, and low-side transistors turned on and off by low-side gate drivers, each low-side gate driver including a linear drive circuit and a digital drive circuit. The method includes driving the corresponding low-side transistor to turn on and off by the linear drive circuit based on a forward current flowing through it, as shown in block 804. The method includes detecting a reverse current flowing through the corresponding low-side transistor at the digital drive circuit, as shown in block 806. And the method includes turning off the corresponding low-side transistor via the digital drive circuit in response to the reverse current, as shown in block 808.

[0055] In some examples, method 800 includes selectively enabling and disabling high-side gate drivers and low-side gate drivers, including selectively enabling and disabling linear drive circuitry and digital drive circuitry for the respective low-side gate drivers, such as... Figure 8B As shown in box 810.

[0056] In some examples, method 800 includes alternately enabling and disabling pairs of high-side gate drivers and low-side gate drivers corresponding to pairs in which transistors are alternately turned on and off, such as Figure 8C As shown in box 812.

[0057] In some examples, the method 800 includes receiving, from the digital drive circuit, a signal indicating detection of a reverse current, as shown at block 814. In some of these examples, the method includes disabling the high-side gate driver and the low-side gate driver in response to the signal from the digital drive circuit indicating detection of the reverse current, as shown at block 816. Figure 8D

[0058] In some examples, the method 800 includes disabling the high-side gate driver and the low-side gate driver when the input voltage is less than a threshold voltage, as shown at block 818. Figure 8E

[0059] In some examples, the method 800 includes adjusting, by the linear drive circuit, a forward voltage of a respective one of the low-side transistors for a forward current up to a corresponding current for a voltage offset and a characteristic on-resistance of the respective one of the low-side transistors in a saturation mode, as shown at block 820. Figure 8F

[0060] In some examples, the method 800 includes comparing, at the digital drive circuit, a drain voltage and a source voltage of a respective one of the low-side transistors, as shown at block 822. In some of these examples, the method includes outputting, from the digital drive circuit, a signal to turn off the respective one of the low-side transistors when the drain voltage is greater than the source voltage, which indicates detection of a reverse current, as shown at block 824. Figure 8G

[0061] In some examples, the method 800 includes comparing, at the digital drive circuit, a drain voltage and a source voltage of a respective one of the low-side transistors, as shown at block 826. In some of these examples, the method includes outputting, from the digital drive circuit, a signal to turn off the respective one of the low-side transistors when the drain voltage is greater than the source voltage by at least a voltage offset, as shown at block 828. Figure 8H

[0062] In some examples, a respective one of the high-side gate drivers includes the digital drive circuit, and the method 800 includes driving, by the digital drive circuit, a respective one of the high-side transistors on and off based on a forward current through the respective one of the high-side transistors, as shown at block 830 of FIG. 81.

[0063] In some examples, the method 800 includes comparing, at the digital drive circuit, a source voltage and a drain voltage of a respective one of the high-side transistors, as shown at block 832. In some of these examples, the method includes outputting, from the digital drive circuit, a signal to turn off the respective one of the high-side transistors when the source voltage is greater than the drain voltage, which indicates detection of a reverse current, as shown at block 834. Figure 8J ​​​​​as shown at block 832. In some of these examples, the method includes outputting, from the digital drive circuit, a switch signal to turn on a respective one of the high-side transistors when the source voltage is greater than the drain voltage, outputting the switch signal when the source voltage is at least a voltage offset greater than the drain voltage, as shown at block 834.

[0064] As explained above and reiterated below, the present disclosure includes, without limitation, the following example implementations.

[0065] Clause 1. An ideal diode bridge controller, comprising: gate drivers for connection to transistors of a bridge rectifier, wherein the transistors are arranged as high-side transistors and low-side transistors, the gate drivers for alternately turning on and off the transistors in pairs to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities, the gate drivers including high-side gate drivers for the high-side transistors and low-side gate drivers for the low-side transistors, a respective one of the low-side gate drivers including: a linear drive circuit for driving a respective one of the low-side transistors to turn on and off based on a forward current through the respective one of the low-side transistors; and a digital drive circuit for detecting a reverse current through the respective one of the low-side transistors and causing the respective one of the low-side transistors to turn off in response to the reverse current.

[0066] Clause 2. The ideal diode bridge controller of clause 1, comprising control circuitry for selectively enabling and disabling the gate drivers, including the control circuitry for selectively enabling and disabling the linear drive circuit and the digital drive circuit of the respective ones of the low-side gate drivers.

[0067] Clause 3. The ideal diode bridge controller of clause 1 or clause 2, comprising control circuitry for alternately enabling and disabling the gate drivers corresponding to the pairs in which the transistors are alternately turned on and off.

[0068] Clause 4. The ideal diode bridge controller of any of clauses 1-3, comprising control circuitry for receiving a signal from the digital drive circuit indicating detection of the reverse current and disabling the gate drivers in response to the signal.

[0069] Clause 5. The ideal diode bridge controller of any one of clauses 1-4, comprising a control circuit including an under-voltage lockout (UVLO) circuit to disable the gate drivers when the input voltage is less than a threshold voltage.

[0070] Clause 6. The ideal diode bridge controller of any one of clauses 1-5, wherein the linear drive circuit includes an operational amplifier to adjust a forward voltage of the respective one of the low-side transistors based on the forward current, and wherein the linear drive circuit includes a voltage offset that sets a minimum voltage to which the operational amplifier adjusts the forward voltage in linear mode of the respective one of the transistors, and the operational amplifier adjusts the forward voltage for the forward current up to a corresponding current for the voltage offset and a characteristic on-resistance of the respective one of the low-side transistors in saturation mode.

[0071] Clause 7. The ideal diode bridge controller of any one of clauses 1-6, wherein the digital drive circuit includes a comparator to compare a drain voltage and a source voltage of the respective one of the low-side transistors, and output a signal to turn off the respective one of the low-side transistors when the drain voltage is greater than the source voltage, which indicates detection of the reverse current.

[0072] Clause 8. The ideal diode bridge controller of any one of clauses 1-7, wherein the digital drive circuit includes a voltage offset that sets a minimum voltage difference, and a comparator to compare a drain voltage and a source voltage of the respective one of the low-side transistors, and output a signal to turn off the respective one of the low-side transistors when the drain voltage is at least the voltage offset greater than the source voltage.

[0073] Clause 9. The ideal diode bridge controller of any one of clauses 1-8, wherein a respective one of the high-side gate drivers includes a digital drive circuit to drive a respective one of the high-side transistors on and off based on a forward current through the respective one of the high-side transistors.

[0074] Clause 10. The ideal diode bridge controller of clause 9, wherein the digital drive circuit includes a comparator to compare a source voltage and a drain voltage of the respective one of the high-side transistors and to output a switch signal to turn on the respective one of the high-side transistors when the source voltage is greater than the drain voltage, and wherein the digital drive circuit includes a voltage offset that sets a minimum voltage difference, and the comparator outputs the switch signal when the source voltage is at least the voltage offset greater than the drain voltage.

[0075] Clause 11. A method comprising: alternately turning on and off pairs of transistors of a bridge rectifier to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities, the transistors arranged as high-side transistors turned on and off by high-side gate drivers and low-side transistors turned on and off by low-side gate drivers, a respective one of the low-side gate drivers including a linear drive circuit and a digital drive circuit; driving, by the linear drive circuit, a respective one of the low-side transistors to turn on and off based on forward current through the respective one of the low-side transistors; and at the digital drive circuit, detecting reverse current through the respective one of the low-side transistors; and turning off the respective one of the low-side transistors in response to the reverse current.

[0076] Clause 12. The method of clause 11, comprising selectively enabling and disabling the high-side gate drivers and the low-side gate drivers, including selectively enabling and disabling the linear drive circuit and the digital drive circuit of the respective one of the low-side gate drivers.

[0077] Clause 13. The method of clause 11 or clause 12, comprising alternately enabling and disabling the high-side gate drivers and the low-side gate drivers corresponding to the pairs in which the transistors are alternately turned on and off.

[0078] Clause 14. The method of any of clauses 11-13, comprising: receiving, from the digital drive circuit, a signal indicating detection of the reverse current; and disabling the high-side gate drivers and the low-side gate drivers in response to the signal from the digital drive circuit indicating detection of the reverse current.

[0079] Clause 15. The method of any one of clauses 11-14, the method comprising disabling the high-side gate driver and the low-side gate driver when the input voltage is less than a threshold voltage.

[0080] Clause 16. The method of any one of clauses 11-15, the method comprising adjusting, by the linear drive circuit, a forward voltage of the respective one of the low-side transistors, the forward voltage being adjusted for the forward current until a corresponding current for a voltage offset and a characteristic on-resistance of the respective one of the low-side transistors in saturation mode.

[0081] Clause 17. The method of any one of clauses 11-16, the method comprising comparing, at the digital drive circuit, a drain voltage and a source voltage of the respective one of the low-side transistors, and outputting a signal from the digital drive circuit to turn off the respective one of the low-side transistors when the drain voltage is greater than the source voltage, which indicates that the reverse current is detected.

[0082] Clause 18. The method of any one of clauses 11-17, the method comprising comparing, at the digital drive circuit, a drain voltage and a source voltage of the respective one of the low-side transistors, and outputting a signal from the digital drive circuit to turn off the respective one of the low-side transistors when the drain voltage is at least a voltage offset greater than the source voltage.

[0083] Clause 19. The method of any one of clauses 11-18, wherein a respective one of the high-side gate drivers comprises a digital drive circuit, and the method comprises driving, by the digital drive circuit, the respective one of the high-side transistors on and off based on a forward current through the respective one of the high-side transistors.

[0084] Clause 20. The method of clause 19, the method comprising comparing, at the digital drive circuit, a source voltage and a drain voltage of the respective one of the high-side transistors, and outputting a switch signal from the digital drive circuit to turn on the respective one of the high-side transistors when the source voltage is greater than the drain voltage, the switch signal being output when the source voltage is at least a voltage offset greater than the drain voltage.

[0085] Many modifications and other specific embodiments of the present disclosure set forth herein will be apparent to those of ordinary skill in the art upon benefiting from the teachings presented in the foregoing descriptions and the associated drawings. Accordingly, the present disclosure is not limited to the specific embodiments set forth for purposes of exemplification alone, and it is therefore understood that the scope of the present disclosure is not limited to the specific examples described and techniques presented and / or components and described herein. Further, it should be understood that the specific embodiments set forth in the foregoing description and illustrated in the associated drawings are not intended to be limiting of the present disclosure, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing description has been described in the context of particular examples, it should be appreciated that the description set forth herein is a description of example embodiments and is not intended to limit the claims. Also, for example, where an element or component is said to be included in even one of multiple embodiments or configurations, such element or component would also, where possible and practicable, be included in and / or perform the functions of the other embodiments and configurations. Additionally, it should be understood that where the foregoing description has described one or more example embodiments, the description has not identified either expressly or implicitly all of the embodiments that would be relied upon to support the patentability of the present disclosure.

Claims

1. An ideal diode bridge controller, comprising: gate drivers for connection to transistors of a bridge rectifier, wherein the transistors are arranged as high-side transistors and low-side transistors, the gate drivers for alternately turning on and off the transistors in pairs to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities, the gate drivers including high-side gate drivers for the high-side transistors and low-side gate drivers for the low-side transistors, a respective one of the low-side gate drivers including: a linear drive circuit for driving a respective one of the low-side transistors to turn on and off based on a forward current through the respective one of the low-side transistors; and a digital drive circuit for detecting a reverse current through the respective one of the low-side transistors and causing the respective one of the low-side transistors to turn off in response to the reverse current.

2. The ideal diode bridge controller of claim 1, including control circuitry for selectively enabling and disabling the gate drivers, including the control circuitry for selectively enabling and disabling the linear drive circuit and the digital drive circuit of the respective ones of the low-side gate drivers.

3. The ideal diode bridge controller of claim 1, including control circuitry for alternately enabling and disabling the gate drivers in pairs corresponding to the pairs in which the transistors are alternately turned on and off.

4. The ideal diode bridge controller of claim 1, including control circuitry for receiving a signal from the digital drive circuit indicating detection of the reverse current and disabling the gate drivers in response to the signal.

5. The ideal diode bridge controller of claim 1, including control circuitry including an under-voltage lockout (UVLO) circuit to disable the gate drivers when the input voltage is less than a threshold voltage.

6. The ideal diode bridge controller of claim 1, wherein the linear drive circuit includes an operational amplifier for regulating a forward voltage of the respective one of the low-side transistors based on the forward current, and wherein the linear drive circuit includes a voltage offset that sets a minimum voltage to which the operational amplifier adjusts the forward voltage in the linear mode of the respective one of the transistors, and the operational amplifier adjusts the forward voltage for the forward current until a corresponding current for the voltage offset and a characteristic on-resistance of the respective one of the low-side transistors in saturation mode.

7. The ideal diode bridge controller of claim 1, wherein the digital drive circuit includes a comparator to compare a drain voltage and a source voltage of the respective one of the low-side transistors and output a signal to turn off the respective one of the low-side transistors when the drain voltage is greater than the source voltage, which indicates detection of the reverse current.

8. The ideal diode bridge controller of claim 1, wherein the digital drive circuit includes: a voltage offset that sets a minimum voltage difference; and a comparator to compare a drain voltage and a source voltage of the respective one of the low-side transistors and output a signal to turn off the respective one of the low-side transistors when the drain voltage is at least the voltage offset greater than the source voltage.

9. The ideal diode bridge controller of claim 1, wherein a respective one of the high-side gate drivers includes a digital drive circuit to drive a respective one of the high-side transistors on and off based on a forward current through the respective one of the high-side transistors.

10. The ideal diode bridge controller of claim 9, wherein the digital drive circuit includes a comparator to compare a source voltage and a drain voltage of the respective one of the high-side transistors and output a switch signal to turn on the respective one of the high-side transistors when the source voltage is greater than the drain voltage, and wherein the digital drive circuit includes a voltage offset that sets a minimum voltage difference, and the comparator outputs the switch signal when the source voltage is at least the voltage offset greater than the drain voltage.

11. A method comprising: alternately turning on and off pairs of transistors of a bridge rectifier to cause the bridge rectifier to convert an input voltage of either of two polarities to an output voltage of one of the two polarities, the transistors arranged as high-side transistors turned on and off by high-side gate drivers, and low-side transistors turned on and off by low-side gate drivers, a respective one of the low-side gate drivers including a linear drive circuit and a digital drive circuit; driving, by the linear drive circuit, a respective one of the low-side transistors on and off based on a forward current through the respective one of the low-side transistors; and at the digital drive circuit; ​ detecting a reverse current through the respective one of the low-side transistors; and turning off the respective one of the low-side transistors in response to the reverse current.

12. The method of claim 11, the method comprising selectively enabling and disabling the high-side gate drivers and the low-side gate drivers, including selectively enabling and disabling the linear drive circuit and the digital drive circuit in the respective low-side gate driver.

13. The method of claim 11, the method comprising enabling and disabling the high-side gate drivers and the low-side gate drivers in pairs alternately corresponding to the pairs in which the transistors are alternately turned on and off.

14. The method of claim 11, the method comprising: receiving a signal from the digital drive circuit indicating detection of the reverse current; and disabling the high-side gate drivers and the low-side gate drivers in response to the signal from the digital drive circuit indicating detection of the reverse current.

15. The method of claim 11, the method comprising disabling the high-side gate drivers and the low-side gate drivers when the input voltage is less than a threshold voltage.

16. The method of claim 11, the method comprising adjusting a forward voltage of the respective one of the low-side transistors by the linear drive circuit, the forward voltage being adjusted for the forward current until a corresponding current for a voltage offset and a characteristic on-resistance of the respective one of the low-side transistors in saturation mode.

17. The method of claim 11, the method comprising: comparing, at the digital drive circuit, a drain voltage and a source voltage of the respective one of the low-side transistors; and outputting a signal from the digital drive circuit to turn off the respective one of the low-side transistors when the drain voltage is greater than the source voltage, indicating detection of the reverse current.

18. The method of claim 11, the method comprising: comparing, at the digital drive circuit, a drain voltage and a source voltage of the respective one of the low-side transistors; and outputting a signal from the digital drive circuit to turn off the respective one of the low-side transistors when the drain voltage is at least a voltage offset greater than the source voltage.

19. The method of claim 11, wherein a respective one of the high-side gate drivers comprises a digital drive circuit, and the method comprises driving, by the digital drive circuit, the respective one of the high-side transistors to turn on and off based on a forward current through the respective one of the high-side transistors.

20. The method of claim 19, the method comprising: comparing, at the digital drive circuit, a source voltage and a drain voltage of the respective one of the high-side transistors; and When the source voltage is greater than the drain voltage, a switch signal is output from the digital driver circuit to turn on the respective one of the high-side transistors, the switch signal being output when the source voltage is at least a voltage offset greater than the drain voltage.

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