Multifunctional anti-riot device

Abstract

The embodiment of the invention relates to the field of circuit structures, and provides a multifunctional anti-riot device which comprises an anti-riot device body driving circuit, a magazine module driving circuit and an anti-riot device battery module, the anti-riot device body driving circuit is connected with the magazine module driving circuit and the anti-riot device battery module, and the magazine module driving circuit is connected with the anti-riot device battery module. The anti-riot device battery module supplies power to the anti-riot device body driving circuit and the magazine module driving circuit, after the processor detects trigger key input through the key input module, if it is detected that a magazine is installed, on-off control is conducted on the high-voltage module according to the type of the magazine, and the flexibility of the multifunctional anti-riot device is improved.

Description

Technical Field

[0001] This application relates to the field of circuit structure technology, specifically to a multi-functional riot control device. Background Technology

[0002] The electric blasting magazine contains an ignition circuit and an identification circuit, which are combined in an overlapping manner. The resistance formed by the combined ignition and identification circuits is compared with the voltage value generated by the resistors on the mainboard to determine whether the magazine is loaded or unloaded, and whether it has been fired or not. The overlapping combination of the ignition and identification circuits makes the manufacturing process complex.

[0003] The existing technology has the following drawbacks: Limited functionality: It can only identify whether the magazine is loaded or unloaded, and whether it is fired or not. Missing information: Unable to identify inherent information such as magazine type, magazine code, and magazine production date; Insufficient traceability: After firing, firing-related information, such as riot control device code, firing date, and time, cannot be recorded and stored; Process limitations: The cross-combination of ignition and identification circuits leads to complex manufacturing processes and insufficient flexibility. Summary of the Invention

[0004] This application provides a multi-functional riot control device. After the processor detects trigger button input through the button input module, if magazine installation is detected, the processor controls the switching of the high-voltage module according to the magazine type, thereby improving the flexibility of the multi-functional riot control device.

[0005] A first aspect of this application provides a multi-functional riot control device, which includes: a riot control device main body drive circuit, a magazine module drive circuit, and a riot control device battery module, wherein the riot control device main body drive circuit is connected to the magazine module drive circuit and the riot control device battery module, and the riot control device battery module supplies power to the riot control device main body drive circuit and the magazine module drive circuit; The main drive circuit of the riot control device includes a high-voltage module, a processor, a key input module, an OLED display module, a laser aiming module, and an illumination module. The battery module of the riot control device includes a battery module, a clock module, a data storage module, and a data upload module. The processor is connected to the high-voltage module, key input module, OLED display module, laser aiming module, lighting module, magazine module drive circuit, and battery module. The battery module is connected to the clock module, the data storage module, and the data upload module; The button input module is used to detect trigger button input and power button input; After the processor detects trigger button input through the button input module, if it detects magazine installation, it controls the switching of the high-voltage module according to the magazine type.

[0006] In one possible implementation, the magazine module drive circuit includes a first sub-drive circuit and a second sub-drive circuit, the first sub-drive circuit and the second sub-drive circuit are connected to the processor, and the second sub-drive circuit has the same circuit structure as the first sub-drive circuit. The first sub-driving circuit includes capacitor EC10, forty-fourth resistor R44, ninth MOSFET Q9, seventeenth interface J17, eighteenth interface J18, nineteenth interface J19, twentieth interface J20, fifth memory chip U5, and ignition wire DS1. The control terminal of the ninth MOSFET Q9 is connected to the MCU_DJ_CTL port of the processor and grounded through the parallel forty-fourth resistor R44. The first terminal of the ninth MOSFET Q9 is grounded, the second terminal of the ninth MOSFET Q9 is connected to the first terminal of the eighteenth interface J18, the second terminal of the eighteenth interface J18 is connected to the power interface and grounded through the parallel capacitor EC10. The seventeenth interface J17 is connected to the eighteenth interface J18, and the nineteenth interface J19 and the twentieth interface J20 are connected. The first and second ends of the seventeenth interface J17 are connected in series with the ignition wire DS1. The first end of the nineteenth interface J19 is grounded, and the second end of the nineteenth interface J19 is connected to the fifth memory chip U5. The grounding port of the fifth memory chip U5 is grounded.

[0007] In one possible implementation, the key input module includes a first key module and a second key module, the auxiliary key J2 and a first capacitor C1, and the second key module includes a trigger key J8 and a second capacitor C2. The first end of the auxiliary button J2 is connected to the processor and grounded through the first capacitor C1 connected in parallel; the second end of the auxiliary button J2 is grounded. The first end of trigger button J8 is connected to the processor and grounded through the second capacitor C2 connected in parallel. The second end of trigger button J8 is grounded.

[0008] In one possible implementation, the laser aiming module includes a first sub-laser aiming module and a second sub-laser aiming module. The first sub-laser aiming module includes a first laser module interface J16, a forty-second resistor R42, a forty-third resistor R43, a twelfth resistor R12, and an eighth transistor Q8. The control terminal of the eighth transistor Q8 is connected to the processor in series with the forty-second resistor R42, and the control terminal of the eighth transistor Q8 is connected to the forty-third resistor R43 and then grounded. The first terminal of the eighth transistor Q8 is connected in series with the twelfth resistor R12 and then connected to the first terminal of the first laser module interface J16. The second terminal of the eighth transistor Q8 is grounded, and the second terminal of the first laser module interface J16 is connected to the battery module. The second sub-laser aiming module includes a second resistor R2, a seventh resistor R7, an eighth resistor R8, a sixth transistor Q6, and a second laser module interface J14, wherein... The control terminal of the sixth transistor Q6 is connected to the processor via a series connection of the seventh resistor R7, and the control terminal of the sixth transistor Q6 is connected to the processor via an eighth resistor R8 and then grounded. The first terminal of the sixth transistor Q6 is connected in series with the second resistor R2 and then connected to the first terminal of the second laser module interface J14. The second terminal of the sixth transistor Q6 is grounded, and the second terminal of the second laser module interface J14 is connected to the battery module. In one possible implementation, the high-voltage module includes a third diode Q3, a fifteenth resistor R15, a thirty-third resistor R33, a thirteenth resistor R13, a seventh transistor Q7, and a high-voltage pack connection interface J7. The control port of the seventh transistor Q7 is connected to the processor via a series connection with the thirty-third resistor R33. The control port of the seventh transistor Q7 and the thirty-third resistor R33 are connected to ground via a series connection with the thirteenth resistor R13. The first terminal of the seventh transistor Q7 is connected to the first terminal of the fifteenth resistor R15 and the gate of the third diode Q3. The second terminal of the seventh transistor Q7 is grounded. The first and second terminals of the third diode Q3, and the second terminal of the fifteenth resistor R15, are connected to the battery module and the first terminal of the high-voltage pack connection interface J7. The second terminal of the high-voltage pack connection interface J7 is grounded.

[0009] In one possible implementation, the battery module includes a sub-battery module, a battery charging circuit, and a battery-to-motherboard interface. The sub-battery module includes a battery interface J100, a first capacitor C100, a capacitor EC100, a capacitor EC101, and a chip U100. The first end of the battery interface J100 is connected to the third end of the chip U100. A capacitor EC101 is connected between the first end of the battery interface J100 and the third end of the chip U100, and then grounded. A first power output interface is provided between the first end of the battery interface J100 and the third end of the chip U100. The first end of the chip U100 is grounded. The second end of the chip U100 is connected in series with the first capacitor C100 and then grounded. A capacitor EC100 is connected between the second end of the chip U100 and the first capacitor C100, and then grounded. A second power output interface is provided between the second end of the chip U100 and the first capacitor C100. The battery charging circuit includes an inductor L100 (100th), a resistor R100 (100th), a resistor R101 (101st), a capacitor C103 (103rd), a capacitor C105 (105th), a resistor R110 (110th), a capacitor C106 (106th), a capacitor C104 (104th), a capacitor C101 (101st), a capacitor C102 (102nd), and a chip U101. The eighth terminal of chip U101 is connected to the seventh terminal via capacitor C104, and is also connected to the first terminals of resistors R100, R101, and C103 via inductor L100. A charging unit connector is connected between inductor L100 and resistor R100. The second end of the 100th resistor R100 is connected to the sixth end of the chip U101. After the second end of the 100th resistor R100 is connected to the sixth end of the chip U101, the 105th capacitor C105 is connected between the second end of the 101st resistor R101 and the second end of the 103rd capacitor C103 is grounded. The ninth end of the chip U101 is grounded. The fourth end of the chip U101 is grounded through the 110th resistor R110 in series. The second end of the chip U101 is grounded through the 106th capacitor C106 in series. The second end of the chip U101 is connected to the 106th capacitor C106. The first power output interface is connected between the second end of the chip U101 and the 106th capacitor C106. The first end of the chip U101 is grounded through the 101st capacitor C101 and the 102nd capacitor C102 connected in parallel. The battery and motherboard interface includes a battery and motherboard connection interface J101, a power interface T100, and a ground interface T101. The first end of the battery and motherboard connection interface J101 provides a power interface for the processor, the second end of the battery and motherboard connection interface J101 is connected to the processor's SCL interface, and the third interface of the battery and motherboard connection interface J101 is connected to the processor's SDA interface.

[0010] In one possible implementation, the clock module includes: a clock chip U104, a 106th resistor R106, a 111th capacitor C111, a 112th capacitor C112, a capacitor EC104, and a crystal oscillator Y101. The first terminal of the clock chip U104 is connected to the first terminal of the crystal oscillator Y101 and the first terminal of the 111th capacitor C111. The second terminal of the 111th capacitor C111 is grounded. The second terminal of the crystal oscillator Y101 is connected to the first terminal of the 112th capacitor C112 and the second terminal of the clock chip U104. The second terminal of the 112th capacitor C112 is grounded. The third terminal of the clock chip U104 is connected in series with the 106th resistor R106 and then connected to the power port, the eighth terminal of the clock chip U104, and the first terminal of the capacitor EC104. The second terminal of the capacitor EC104 is grounded, and the fourth terminal of the clock chip U104 is grounded.

[0011] In one possible implementation, the data storage module includes a chip U105, a first 108 resistor R108, a first 109 resistor R109, and a first 114 capacitor C114. The first, second, third, and fourth terminals of the chip U105 are connected to the first terminal of the first 114 capacitor C114 and then grounded. The second terminal of the first 114 capacitor C114 is connected to the eighth terminal of the chip U105, the first terminal of the first 108 resistor R108, and the first terminal of the first 109 resistor R109. The second terminal of the first 108 resistor R108 is connected to the fifth terminal of the chip U105, and the second terminal of the first 109 resistor R109 is connected to the sixth terminal of the chip U105.

[0012] A second aspect of this application provides a multi-functional riot control device, the multi-functional riot control device including a circuit board and a multi-functional riot control device as described in any one of the first aspects, the multi-functional riot control device being disposed on the circuit board.

[0013] A third aspect of this application provides a multi-functional riot control device, which includes a housing and a multi-functional riot control device as described in the second aspect, wherein the multi-functional riot control device is disposed within the housing.

[0014] Implementing the embodiments of this application has at least the following beneficial effects: A multi-functional riot control device includes a main drive circuit, a magazine module drive circuit, and a battery module. The main drive circuit is connected to the magazine module drive circuit and the battery module. The battery module supplies power to the main drive circuit and the magazine module drive circuit. The main drive circuit includes a high-voltage module, a processor, a key input module, an OLED display module, a laser aiming module, and an illumination module. The battery module includes a battery module, a clock module, a data storage module, and a data upload module. The processor is connected to the high-voltage module and the key input module. The device is connected to an OLED display module, a laser aiming module, an illumination module, a magazine module drive circuit, and a battery module. The battery module is connected to a clock module, a data storage module, and a data upload module. A button input module is used to detect trigger button input and power button input. After the processor detects trigger button input through the button input module, if a magazine is detected being installed, it controls the high-voltage module to switch on and off according to the magazine type. Therefore, the processor controls the high-voltage module to switch on and off according to the magazine type after detecting trigger button input through the button input module, thus improving the flexibility of the multi-functional riot control device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of a multi-functional riot control device is provided for an embodiment of this application; Figure 2 A schematic diagram of a magazine module drive circuit is provided for an embodiment of this application; Figure 3 A schematic diagram of a second sub-driving circuit is provided for an embodiment of this application; Figure 4 A schematic diagram of a processor is provided for an embodiment of this application; Figure 5 This application provides a schematic diagram of the peripheral circuitry of a processor. Figure 6 A schematic diagram of a processor voltage control output circuit is provided for an embodiment of this application; Figure 7 A schematic diagram of a key input module provided in an embodiment of this application; Figure 8 A schematic diagram of a laser aiming module is provided for an embodiment of this application; Figure 9 A schematic diagram of a lighting module is provided as an embodiment of this application; Figure 10 A schematic diagram of a high-voltage module is provided for an embodiment of this application; Figure 11 A schematic diagram of a display module is provided for an embodiment of this application; Figure 12 This application provides a schematic diagram of a processor and battery interface. Figure 13 A schematic diagram of a battery module is provided for an embodiment of this application; Figure 14 This application provides a schematic diagram of an IIC isolation chip as an embodiment; Figure 15 This application provides a schematic diagram of a battery and processor module interface isolation chip as an embodiment of the present application; Figure 16 A schematic diagram of a clock module is provided for an embodiment of this application; Figure 17 This application provides a schematic diagram of a data storage module as an embodiment; Figure 18 This is a schematic diagram of a data upload module provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0019] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0020] Please see Figure 1 , Figure 1 This application provides a schematic diagram of a multifunctional riot control device. Figure 1 As shown, the multi-functional riot control device includes: a riot control device main body drive circuit, a magazine module drive circuit, and a riot control device battery module. The riot control device main body drive circuit is connected to the magazine module drive circuit and the riot control device battery module, and the riot control device battery module supplies power to the riot control device main body drive circuit and the magazine module drive circuit. The main drive circuit of the riot control device includes a high voltage module 1, a processor 2, a key input module 3, an OLED display module 4, a laser aiming module 5, and an illumination module 6. The battery module of the riot control device includes a battery module 7, a clock module 8, a data storage module 9, and a data upload module 10. The processor is connected to the high-voltage module 1, the key input module 3, the OLED display module 4, the laser aiming module 5, the lighting module 6, the magazine module drive circuit 11, and the battery module 7. The battery module 7 is connected to the clock module 8, the data storage module 9, and the data upload module 10; Key input module 3 is used to detect trigger key input and power key input; After the processor 2 detects the trigger button input through the button input module 3, if it detects that the magazine is being installed, it controls the high-voltage module 1 to switch on or off according to the magazine type.

[0021] The button input module includes a first button module and a second button module. The first button module includes an auxiliary button J2 and a first capacitor C1, and the second button module includes a trigger button J8 and a second capacitor C2. The auxiliary button J2 is used for power button activation.

[0022] When the battery is installed, the system detects a power button input to exit sleep mode, turns on the display, lights, and laser aiming, and checks if the magazine is installed. When the magazine status (magazine type, whether it is installed, and firing status) is detected, the magazine status is simultaneously displayed on the OLED display module.

[0023] When trigger button input is detected, if no magazine is installed, the high-voltage module is activated to output high voltage. The high voltage stops after 5 seconds or when the trigger is pressed again. The clock module time and the high-voltage output duration data are read and stored together in the data storage module.

[0024] Upon detecting trigger button input, when magazine installation is detected, depending on the magazine type, whether high voltage needs to be activated (e.g., tear gas magazines, strap-on magazines, etc. do not require high voltage output; stun magazines do require high voltage output), if high voltage output is present, the high voltage will stop after 5 seconds or stop the high voltage when the trigger is pressed again. The clock module time and high voltage output duration data are read, and the magazine type data is stored together in the data storage module.

[0025] In one possible implementation, such as Figure 2 As shown, the magazine module drive circuit includes a first sub-drive circuit and a second sub-drive circuit. The first sub-drive circuit and the second sub-drive circuit are connected to the processor 2. The second sub-drive circuit has the same circuit structure as the first sub-drive circuit. The first sub-driving circuit includes capacitor EC10, forty-fourth resistor R44, ninth MOSFET Q9, seventeenth interface J17, eighteenth interface J18, nineteenth interface J19, twentieth interface J20, fifth memory chip U5, and ignition wire DS1. The control terminal of the ninth MOSFET Q9 is connected to the MCU_DJ_CTL port of the processor and grounded through the parallel forty-fourth resistor R44. The first terminal of the ninth MOSFET Q9 is grounded, the second terminal of the ninth MOSFET Q9 is connected to the first terminal of the eighteenth interface J18, the second terminal of the eighteenth interface J18 is connected to the power interface and grounded through the parallel capacitor EC10. The seventeenth interface J17 is connected to the eighteenth interface J18, and the nineteenth interface J19 and the twentieth interface J20 are connected. The first and second ends of the seventeenth interface J17 are connected in series with the ignition wire DS1. The first end of the nineteenth interface J19 is grounded, and the second end of the nineteenth interface J19 is connected to the fifth memory chip U5. The grounding port of the fifth memory chip U5 is grounded.

[0026] EC10 is the source capacitor, storing energy for ignition. V_SYS is the battery output voltage controlled by the processor module. J17 and J19 are interfaces on the magazines. J18 connects to J17, J20, and J19 after the magazines are installed.

[0027] DS1 is the ignition wire. When not fired, its resistance is about 2 ohms. After firing, it is disconnected, and the resistance becomes infinite.

[0028] Q9 and R44 form the ignition circuit, which is controlled by the MCU_L_CTL from the main control module.

[0029] U5 is a single-bus memory chip. It is connected to the processor module via the MCU_L_DATA line. The selected chip is the GX2431 single-bus memory chip. Its 1KB data capacity is sufficient to store the required information and offers a high level of security. R46 is a pull-up resistor required for single-bus communication.

[0030] Figure 3 The second sub-drive circuit is shown. EC2 is the power supply capacitor, storing energy for ignition. V_SYS is the battery output voltage controlled by the processor module.

[0031] J3 and J5 are the interfaces on the magazine. J4 connects to J3, J6, and J5 after the magazine is installed.

[0032] DS2 is the ignition wire. When not fired, its resistance is about 2 ohms. After firing and disconnection, the resistance becomes infinite.

[0033] Q2 and R5 form the ignition circuit, which is controlled by the MCU_R_CTL from the main control module.

[0034] U1 is a single-bus memory chip. The selected chip is the GX2431 single-bus memory chip. Its 1KB data capacity is sufficient to store the required information, and it offers a high level of security. R6 is a pull-up resistor required for single-bus communication.

[0035] like Figure 4 As shown, Figure 4 A schematic diagram of a processor is shown. The main control chip selected for the processor is the GD32F303. It has enough pins and a clock speed of 120MHz, which is sufficient to meet the requirements of the task.

[0036] Figure 5 This diagram illustrates a peripheral circuit for a processor. D3 is a diode to prevent voltage fluctuations in the output stage after shutdown. U3 is an LDO that converts the battery voltage to the voltage required by the main control chip, typically 3.3V. MCU_VCC is the operating voltage of the main control chip. EC5 and EC6 are energy storage capacitors. MCU_VDDA is the voltage detection voltage for the main control chip. It is connected to MCU_VCC via R24. R24 helps stabilize MCU_VDDA. C26, C14, C15, C24, and C25 are coupling capacitors.

[0037] Figure 6 This diagram illustrates a voltage control output circuit for a processor. V_BAT represents the battery voltage. V_SYS is the output voltage after control, supplied to other modules. EC1 is an energy storage capacitor to prevent voltage fluctuations. R11 is a pull-up resistor to prevent Q4 from accidentally turning on when the output is not enabled. Q4 is a P-MOS transistor, which can be controlled to turn on and off by the main control chip. Q1 and R36 form a control circuit. When MCU_SYS_CTL is high, Q4 is on, and the V_SYS output is connected to V_BAT. When MCU_SYS_CTL is low, Q4 is off, and V_SYS has no voltage output. R3, R4, C3, and R49 form a voltage detection circuit, connected to the main control chip via MCU_BAT_VOL. This circuit detects the V_SYS voltage and calculates the battery voltage value.

[0038] In one possible implementation, such as Figure 7 As shown, Figure 7 A schematic diagram of a key input module is shown. The key input module 3 includes a first key module and a second key module, an auxiliary key J2 and a first capacitor C1, and the second key module includes a trigger key J8 and a second capacitor C2. The first end of the auxiliary button J2 is connected to the processor 2 and grounded through the first capacitor C1 connected in parallel; the second end of the auxiliary button J2 is grounded. The first end of the trigger button J8 is connected to the processor 2 and grounded through the second capacitor C2 connected in parallel. The second end of the trigger button J8 is grounded.

[0039] J2 is an auxiliary button. C1 is a debounce capacitor. Both are connected to the main control chip via MCU_ACC_Key_IN. J8 is a trigger button. C2 is a debounce capacitor. Both are connected to the main control chip via MCU_DJ_Key_IN.

[0040] In one possible implementation Figure 8 A schematic diagram of a laser aiming module is shown. (For example...) Figure 8 As shown, the laser aiming module 5 includes a first sub-laser aiming module and a second sub-laser aiming module. The first sub-laser aiming module includes a first laser module interface J16, a forty-second resistor R42, a forty-third resistor R43, a twelfth resistor R12, and an eighth transistor Q8. The control terminal of the eighth transistor Q8 is connected to the processor 2 after being connected in series with the forty-second resistor R42. The control terminal of the eighth transistor Q8 is connected to the forty-third resistor R43 after being connected between the forty-third resistor R43 and grounded. The first terminal of the eighth transistor Q8 is connected in series with the twelfth resistor R12 and then connected to the first terminal of the first laser module interface J16. The second terminal of the eighth transistor Q8 is grounded, and the second terminal of the first laser module interface J16 is connected to the battery module 7. The second sub-laser aiming module includes a second resistor R2, a seventh resistor R7, an eighth resistor R8, a sixth transistor Q6, and a second laser module interface J14, wherein... The control terminal of the sixth transistor Q6 is connected in series with the seventh resistor R7 and then connected to the processor 2. The control terminal of the sixth transistor Q6 and the seventh resistor R7 are connected to the eighth resistor R8 and then grounded. The first end of the sixth transistor Q6 is connected in series with the second resistor R2 and then connected to the first end of the second laser module interface J14. The second end of the sixth transistor Q6 is grounded, and the second end of the second laser module interface J14 is connected to the battery module 7.

[0041] Specifically, R2 and R12 are current-limiting resistors. R42, R43, and Q8 form the aiming control circuit on the laser aiming module, controlled by the MCU_LASER1_CTL of the main control chip. R7, R8, and Q6 form the aiming control circuit on the laser aiming module, controlled by the MCU_LASER1_CTL of the main control chip. Power is provided by V_SYS.

[0042] like Figure 9The diagram illustrates a lighting module. Specifically, J15 is the LED chip connection interface. U4 is the LED driver chip. L3 is the inductor in the driver chip's peripheral circuit. EC3 is the energy storage capacitor. R9 is the LED current sensing resistor. U4 controls the SW pin to stabilize the LED current output based on the current value fed back from R9. R14 and R10 form the control circuit, which is connected to the main control chip via MCU_LED_CTL.

[0043] In one possible implementation Figure 10 A schematic diagram of a high-voltage module is provided. (For example...) Figure 10 As shown, the high-voltage module 1 includes a third diode Q3, a fifteenth resistor R15, a thirty-third resistor R33, a thirteenth resistor R13, a seventh transistor Q7, and a high-voltage pack connection interface J7. The control port of the seventh transistor Q7 is connected to the processor 2 via a series connection of the thirty-third resistor R33. The control port of the seventh transistor Q7 and the thirty-third resistor R33 are connected to ground via a series connection of the thirteenth resistor R13. The first end of the seventh transistor Q7 is connected to the first end of the fifteenth resistor R15 and the gate of the third diode Q3. The second end of the seventh transistor Q7 is grounded. The first and second ends of the third diode Q3, and the second end of the fifteenth resistor R15, are connected to the battery module 7 and the first end of the high-voltage pack connection interface J7. The second end of the high-voltage pack connection interface J7 is grounded.

[0044] Q3 is a P-MOSFET, controlled by MCU_DJ_CTL for on / off switching. When on, the high-voltage transformer outputs high voltage. When off, the high-voltage transformer has no output. R15 is a pull-up resistor. It prevents Q4 from accidentally turning on when the output is not enabled. R33, R13, and Q7 form the control circuit, controlled by the MCU_DJ_CTL of the main control circuit.

[0045] Figure 11 A schematic diagram of a display module is provided. CON8 is the interface for the OLED display. The backlight voltage is provided by V_SYS. R30 is an isolation resistor. Voltage is provided to the OLED display by MCU_VCC. The OLED display is connected to the main control chip via SPI communication. MCU_OLED_CS is the chip select signal pin. MCU_OLED_RES is the reset signal pin. MCU_OLED_DC is the command signal pin. MCU_OLED_CLK is the clock signal pin. MCU_OLED_SI is the data signal pin.

[0046] Figure 12A processor-battery interface is provided. J13, T4, and T6 are the battery interface pins, typically connected to the battery via battery contacts or pogo pin probes; V-BAT is connected to the battery positive terminal; GND is connected to the battery negative terminal; MCU_VCC provides a connection signal to the battery via R45. This pin is used to determine if the battery is connected correctly; EEP_I2C_SDA and EEP_I2C_SCL are the I2C interfaces for communication with the battery. Switch S1 is the power switch; the system starts when S1 is closed and shuts down when S1 is open.

[0047] In one possible implementation Figure 13 A schematic diagram of a battery module is provided. (Example) Figure 13 As shown, the battery module 7 includes a sub-battery module, a battery charging circuit, and a battery-to-motherboard interface. The sub-battery module includes a battery interface J100, a first capacitor C100, a capacitor EC100, a capacitor EC101, and a chip U100. The first end of the battery interface J100 is connected to the third end of the chip U100. A capacitor EC101 is connected between the first end of the battery interface J100 and the third end of the chip U100, and then grounded. A first power output interface is provided between the first end of the battery interface J100 and the third end of the chip U100. The first end of the chip U100 is grounded. The second end of the chip U100 is connected in series with the first capacitor C100 and then grounded. A capacitor EC100 is connected between the second end of the chip U100 and the first capacitor C100, and then grounded. A second power output interface is provided between the second end of the chip U100 and the first capacitor C100. The battery charging circuit includes an inductor L100 (100th), a resistor R100 (100th), a resistor R101 (101st), a capacitor C103 (103rd), a capacitor C105 (105th), a resistor R110 (110th), a capacitor C106 (106th), a capacitor C104 (104th), a capacitor C101 (101st), a capacitor C102 (102nd), and a chip U101. The eighth terminal of chip U101 is connected to the seventh terminal via capacitor C104, and is also connected to the first terminals of resistors R100, R101, and C103 via inductor L100. A charging unit connector is connected between inductor L100 and resistor R100. The second end of the 100th resistor R100 is connected to the sixth end of the chip U101. After the second end of the 100th resistor R100 is connected to the sixth end of the chip U101, the 105th capacitor C105 is connected between the second end of the 101st resistor R101 and the second end of the 103rd capacitor C103 is grounded. The ninth end of the chip U101 is grounded. The fourth end of the chip U101 is grounded through the 110th resistor R110 in series. The second end of the chip U101 is grounded through the 106th capacitor C106 in series. The second end of the chip U101 is connected to the 106th capacitor C106. The first power output interface is connected between the second end of the chip U101 and the 106th capacitor C106. The first end of the chip U101 is grounded through the 101st capacitor C101 and the 102nd capacitor C102 connected in parallel. The battery and motherboard interface includes a battery and motherboard connection interface J101, a power interface T100, and a ground interface T101. The first end of the battery and motherboard connection interface J101 provides a power interface for the processor 2. The second end of the battery and motherboard connection interface J101 is connected to the SCL interface of the processor 2. The third interface of the battery and motherboard connection interface J101 is connected to the SDA interface of the processor 2.

[0048] V33_MCU is the control signal; MCU_SCL and MCU_SDA are IIC communication signal pins; J100 is the battery interface. The battery uses two lithium batteries connected in series; EC101, U100, EC100, and C100 form an LDO circuit; V33 power supply is provided to the memory module and clock module; U101, C101, C102, C106, C105, C104, C103, L100, R100, R101, and R110 constitute the battery charging circuit. The charging power is provided by V5V, which comes from the Type-C interface.

[0049] Figure 14 A schematic diagram of the IIC isolation chip is provided. Figure 15 A schematic diagram of the battery and processor module interface isolation chip is provided. Figure 16A schematic diagram of the clock module is shown. Figure 17 A schematic diagram of the data storage module is shown.

[0050] The clock module 8 includes: a clock chip U104, a 106th resistor R106, a 111th capacitor C111, a 112th capacitor C112, a capacitor EC104, and a crystal oscillator Y101. The first terminal of the clock chip U104 is connected to the first terminal of the crystal oscillator Y101 and the first terminal of the 111th capacitor C111. The second terminal of the 111th capacitor C111 is grounded. The second terminal of the crystal oscillator Y101 is connected to the first terminal of the 112th capacitor C112 and the second terminal of the clock chip U104. The second terminal of the 112th capacitor C112 is grounded. The third terminal of the clock chip U104 is connected in series with the 106th resistor R106 and then connected to the power port, the eighth terminal of the clock chip U104, and the first terminal of the capacitor EC104. The second terminal of the capacitor EC104 is grounded, and the fourth terminal of the clock chip U104 is grounded.

[0051] The data storage module 9 includes a chip U105, a first 108 resistor R108, a first 109 resistor R109, and a first 114 capacitor C114. The first, second, third, and fourth terminals of the chip U105 are connected to the first terminal of the first 114 capacitor C114 and then grounded. The second terminal of the first 114 capacitor C114 is connected to the eighth terminal of the chip U105, the first terminal of the first 108 resistor R108, and the first terminal of the first 109 resistor R109. The second terminal of the first 108 resistor R108 is connected to the fifth terminal of the chip U105. The second terminal of the first 109 resistor R109 is connected to the sixth terminal of the chip U105.

[0052] Specifically, U103 and U106 are IIC isolation chips. They isolate the IIC communication circuit between the data upload chip and the main control chip to prevent mutual interference. C110 and C113 are decoupling capacitors. R105 and R107 are turn-on resistors, connected to MCU_VCC (the processor module's battery connection signal) and V5V (the power signal when connected to the Type-C interface), respectively. U104 is a clock chip. It stores the real-time clock and is battery powered. It connects to the main control chip via I2C_SCL, I2C_SDA, and an isolation chip. Y101, C111, and C112 are the crystal oscillator circuits for the clock chip; EC104 is an energy storage capacitor; R106 is the interrupt pull-up resistor for the clock chip.

[0053] U105 is a memory chip, typically an AT24C512, capable of storing 64KB of data. It connects to the main control chip via I2C_SCL, I2C_SDA, and an isolation chip; C114 is a decoupling capacitor; R108 and R109 are pull-up resistors for IIC communication.

[0054] Figure 18 A schematic diagram of a data upload module is shown. J103 is a Type-C interface. V5V is the voltage provided when the interface is connected; this voltage can charge the battery.

[0055] R102 and R103 are the CC signals of the TYPE C interface; U102 is a data upload chip, typically CH331A. When connected to a computer via a Type-C interface, the data storage chip can be recognized as a USB flash drive, allowing desktop software to read its internal data. It connects to the Type-C interface via D+ and D-. CH331_SCL and CH331_SDA are connected to the IIC communication pins of the data storage chip via an isolation chip; EC103 is an energy storage capacitor; C107 is a decoupling capacitor; R104 is a write-disable pull-down resistor, preventing the desktop software from modifying the data storage chip's data; Y100, C108, and C109 form the crystal oscillator circuit for U102.

[0056] Therefore, the technical solution of this application embodiment has the following effects: 1. Functional expansion: It enables the identification of inherent information such as magazine type, code, and production date, meeting the needs of refined management.

[0057] 2. Information traceability: After firing, firing-related information can be automatically recorded and stored for easy subsequent traceability and management.

[0058] 3. Simplified process: The ignition circuit and the identification circuit are designed independently, which simplifies the production process and improves production flexibility.

[0059] 4. Enhanced Security: An authentication unit prevents the use of unauthorized magazines, improving device security. The magazine contains a memory chip that identifies whether it is an authorized magazine.

[0060] 5. Easy maintenance: The independent design facilitates circuit fault diagnosis, maintenance, and replacement.

[0061] 6. Data Management: The EEPROM memory enables long-term storage and reading / writing of information, providing the possibility for data statistics and analysis.

[0062] This application provides a multi-functional riot control device, which includes a circuit board and a multi-functional riot control device as described in any of the foregoing embodiments, wherein the multi-functional riot control device is disposed on the circuit board.

[0063] This application provides a multi-functional riot control device, which includes a housing and a multi-functional riot control device as described in the foregoing embodiments, wherein the multi-functional riot control device is disposed within the housing.

[0064] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0065] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0067] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A multi-functional riot suppressor, characterized in that, The multi-functional riot control device includes: a riot control device main body drive circuit, a magazine module drive circuit, and a riot control device battery module. The riot control device main body drive circuit is connected to the magazine module drive circuit and the riot control device battery module, and the riot control device battery module supplies power to the riot control device main body drive circuit and the magazine module drive circuit. The main drive circuit of the riot control device includes a high-voltage module, a processor, a key input module, an OLED display module, a laser aiming module, and an illumination module. The battery module of the riot control device includes a battery module, a clock module, a data storage module, and a data upload module. The processor is connected to the high-voltage module, key input module, OLED display module, laser aiming module, lighting module, magazine module drive circuit, and battery module. The battery module is connected to the clock module, the data storage module, and the data upload module; The button input module is used to detect trigger button input and power button input; After the processor detects trigger button input through the button input module, if it detects magazine installation, it controls the switching of the high-voltage module according to the magazine type.

2. The multi-functional riot control device according to claim 1, characterized in that, The magazine module drive circuit includes a first sub-drive circuit and a second sub-drive circuit. The first sub-drive circuit and the second sub-drive circuit are connected to the processor. The second sub-drive circuit has the same circuit structure as the first sub-drive circuit. The first sub-driving circuit includes capacitor EC10, forty-fourth resistor R44, ninth MOSFET Q9, seventeenth interface J17, eighteenth interface J18, nineteenth interface J19, twentieth interface J20, fifth memory chip U5, and ignition wire DS1. The control terminal of the ninth MOSFET Q9 is connected to the MCU_DJ_CTL port of the processor and grounded through the parallel forty-fourth resistor R44. The first terminal of the ninth MOSFET Q9 is grounded, the second terminal of the ninth MOSFET Q9 is connected to the first terminal of the eighteenth interface J18, the second terminal of the eighteenth interface J18 is connected to the power interface and grounded through the parallel capacitor EC10. The seventeenth interface J17 is connected to the eighteenth interface J18, and the nineteenth interface J19 and the twentieth interface J20 are connected. The first and second ends of the seventeenth interface J17 are connected in series with the ignition wire DS1. The first end of the nineteenth interface J19 is grounded, and the second end of the nineteenth interface J19 is connected to the fifth memory chip U5. The grounding port of the fifth memory chip U5 is grounded.

3. The multi-functional riot control device according to claim 2, characterized in that, The key input module includes a first key module and a second key module. The first key module includes an auxiliary key J2 and a first capacitor C1. The second key module includes a trigger key J8 and a second capacitor C2. The first end of the auxiliary button J2 is connected to the processor and grounded through the first capacitor C1 connected in parallel; the second end of the auxiliary button J2 is grounded. The first end of trigger button J8 is connected to the processor and grounded through the second capacitor C2 connected in parallel. The second end of trigger button J8 is grounded.

4. The multi-functional riot control device according to any one of claims 1-3, characterized in that, The laser aiming module includes a first sub-laser aiming module and a second sub-laser aiming module. The first sub-laser aiming module includes a first laser module interface J16, a forty-second resistor R42, a forty-third resistor R43, a twelfth resistor R12, and an eighth transistor Q8. The control terminal of the eighth transistor Q8 is connected to the processor after being connected in series with the forty-second resistor R42. The control terminal of the eighth transistor Q8 and the forty-second resistor R42 are connected to the forty-third resistor R43 and then grounded. The first terminal of the eighth transistor Q8 is connected in series with the twelfth resistor R12 and then connected to the first terminal of the first laser module interface J16. The second terminal of the eighth transistor Q8 is grounded, and the second terminal of the first laser module interface J16 is connected to the battery module. The second sub-laser aiming module includes a second resistor R2, a seventh resistor R7, an eighth resistor R8, a sixth transistor Q6, and a second laser module interface J14, wherein... The control terminal of the sixth transistor Q6 is connected to the processor via a series connection of the seventh resistor R7, and the control terminal of the sixth transistor Q6 is connected to the processor via an eighth resistor R8 and then grounded. The first terminal of the sixth transistor Q6 is connected in series with the second resistor R2 and then connected to the first terminal of the second laser module interface J14. The second terminal of the sixth transistor Q6 is grounded, and the second terminal of the second laser module interface J14 is connected to the battery module.

5. The multi-functional riot control device according to claim 4, characterized in that, The high-voltage module includes a third diode Q3, a fifteenth resistor R15, a thirty-third resistor R33, a thirteenth resistor R13, a seventh transistor Q7, and a high-voltage pack connection interface J7. The control port of the seventh transistor Q7 is connected to the processor via a series connection with the thirty-third resistor R33. The control port of the seventh transistor Q7 and the thirty-third resistor R33 are connected to ground via a series connection with the thirteenth resistor R13. The first terminal of the seventh transistor Q7 is connected to the first terminal of the fifteenth resistor R15 and the gate of the third diode Q3. The second terminal of the seventh transistor Q7 is grounded. The first and second terminals of the third diode Q3, and the second terminal of the fifteenth resistor R15, are connected to the battery module and the first terminal of the high-voltage pack connection interface J7. The second terminal of the high-voltage pack connection interface J7 is grounded.

6. The multi-functional riot control device according to claim 5, characterized in that, The battery module includes a sub-battery module, a battery charging circuit, and a battery-to-motherboard interface. The sub-battery module includes a battery interface J100, a first-hundredth capacitor C100, a capacitor EC100, a capacitor EC101, and a chip U100. The first end of the battery interface J100 is connected to the third end of the chip U100. A capacitor EC101 is connected between the first end of the battery interface J100 and the third end of the chip U100, and then grounded. A first power output interface is provided between the first end of the battery interface J100 and the third end of the chip U100. The first end of the chip U100 is grounded. The second end of the chip U100 is connected in series with the first-hundredth capacitor C100 and then grounded. A capacitor EC100 is connected between the second end of the chip U100 and the first-hundredth capacitor C100, and then grounded. A second power output interface is provided between the second end of the chip U100 and the first-hundredth capacitor C100. The battery charging circuit includes an inductor L100 (100th), a resistor R100 (100th), a resistor R101 (101st), a capacitor C103 (103rd), a capacitor C105 (105th), a resistor R110 (110th), a capacitor C106 (106th), a capacitor C104 (104th), a capacitor C101 (101st), a capacitor C102 (102nd), and a chip U101. The eighth terminal of chip U101 is connected to the seventh terminal via capacitor C104, and is also connected to the first terminals of resistors R100, R101, and C103 via inductor L100. A charging unit connector is connected between inductor L100 and resistor R100. The second end of the 100th resistor R100 is connected to the sixth end of the chip U101. After the second end of the 100th resistor R100 is connected to the sixth end of the chip U101, the 105th capacitor C105 is connected between the second end of the 101st resistor R101 and the second end of the 103rd capacitor C103 is grounded. The ninth end of the chip U101 is grounded. The fourth end of the chip U101 is grounded through the 110th resistor R110 in series. The second end of the chip U101 is grounded through the 106th capacitor C106 in series. The second end of the chip U101 is connected to the 106th capacitor C106. The first power output interface is connected between the second end of the chip U101 and the 106th capacitor C106. The first end of the chip U101 is grounded through the 101st capacitor C101 and the 102nd capacitor C102 connected in parallel. The battery and motherboard interface includes a battery and motherboard connection interface J101, a power interface T100, and a ground interface T101. The first end of the battery and motherboard connection interface J101 provides a power interface for the processor, the second end of the battery and motherboard connection interface J101 is connected to the processor's SCL interface, and the third interface of the battery and motherboard connection interface J101 is connected to the processor's SDA interface.

7. The multi-functional riot control device according to claim 6, characterized in that, The clock module includes: a clock chip U104, a 106th resistor R106, a 111th capacitor C111, a 112th capacitor C112, a capacitor EC104, and a crystal oscillator Y101. The first terminal of the clock chip U104 is connected to the first terminal of the crystal oscillator Y101 and the first terminal of the 111th capacitor C111. The second terminal of the 111th capacitor C111 is grounded. The second terminal of the crystal oscillator Y101 is connected to the first terminal of the 112th capacitor C112 and the second terminal of the clock chip U104. The second terminal of the 112th capacitor C112 is grounded. The third terminal of the clock chip U104 is connected in series with the 106th resistor R106 and then connected to the power port, the eighth terminal of the clock chip U104, and the first terminal of the capacitor EC104. The second terminal of the capacitor EC104 is grounded, and the fourth terminal of the clock chip U104 is grounded.

8. The multi-functional riot control device according to claim 7, characterized in that, The data storage module includes a chip U105, a 108th resistor R108, a 109th resistor R109, and a 114th capacitor C114. The first, second, third, and fourth terminals of the chip U105 are connected to the first terminal of the 114th capacitor C114 and then grounded. The second terminal of the 114th capacitor C114 is connected to the eighth terminal of the chip U105, the first terminal of the 108th resistor R108, and the first terminal of the 109th resistor R109. The second terminal of the 108th resistor R108 is connected to the fifth terminal of the chip U105, and the second terminal of the 109th resistor R109 is connected to the sixth terminal of the chip U105.

9. A multi-functional riot control device, characterized in that, The multi-functional riot control device includes a circuit board and a multi-functional riot control device as described in any one of claims 1-8, wherein the multi-functional riot control device is disposed on the circuit board.

10. A multi-functional riot control device, characterized in that, The multi-functional riot control device includes a housing and a multi-functional riot control device as described in claim 9, wherein the multi-functional riot control device is disposed within the housing.

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