High-precision low-jitter clock recovery method

Abstract

The invention discloses a high-precision low-jitter clock recovery method, relates to the field of digital signal processing, and solves the problem of inaccuracy during clock jitter deviation recovery. Preprocessing the original clock signal and generating a corresponding square wave diagram based on the preprocessed processing clock signal; the clock fluctuation period of the processing clock signal is analyzed based on the square wave diagram, and the existence condition of the jitter deviation corresponding to the processing clock signal is judged; calculating the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period in combination with the square wave diagram; inputting a processing clock signal into the ultrafast clock fan-out buffer, and performing comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period; and calculating the proportion of the processing clock signal output by the ultrafast clock fan-out buffer, and judging the validity of the ultrafast clock fan-out buffer. The method and the device provided by the invention realize accurate identification and recovery of the clock jitter deviation.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing technology, specifically a high-precision, low-jitter clock recovery method. Background Technology

[0002] In recent years, due to the rapid development of semiconductor technology, digital signal processing technology, and communication technology, A / D and D / A converters have also shown a high-speed development trend. With the development of high-speed and high-precision A / D converters, especially the market availability of high-resolution data converters that can directly perform intermediate frequency sampling, the demand for stable sampling clocks has become increasingly urgent. In order to ensure the data acquisition, control feedback, and digital processing capabilities and performance of electronic systems, modern military electronic systems have increasingly higher requirements for A / D converters. To ensure the performance of high-speed and high-precision A / D converters, it is essential to first ensure that the sampling encoding clock has a suitable duty cycle and very low jitter.

[0003] However, when dealing with high-precision, low-jitter clocks, existing methods cannot accurately identify clock jitter deviations because the values ​​of clock jitter deviations are low, resulting in inaccurate jitter recovery.

[0004] Therefore, this invention proposes a high-precision, low-jitter clock recovery method. Summary of the Invention

[0005] The purpose of this invention is to propose a high-precision, low-jitter clock recovery method to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A high-precision, low-jitter clock recovery method, the method comprising:

[0008] Step S1: Acquire the original clock signal during the data interaction process of the electronic system, preprocess the original clock signal, and generate the corresponding square wave diagram based on the preprocessed clock signal.

[0009] Step S2: Analyze the clock fluctuation period of the processing clock signal based on the square wave diagram to determine the existence of jitter deviation corresponding to the processing clock signal.

[0010] Step S3: Analyze the processing clock signal based on the square wave diagram, and calculate the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period based on the square wave diagram.

[0011] Step S4: Input the processing clock signal into the ultrafast clock fan-out buffer to perform comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period;

[0012] Step S5: Receive the directly output processing clock signal or the processing clock signal output from the ultrafast clock fan-out buffer, calculate the proportion of the processing clock signal output from the ultrafast clock fan-out buffer, and determine the effectiveness of the ultrafast clock fan-out buffer.

[0013] Further, step S1 includes the following sub-steps:

[0014] Step S101: Obtain the original clock signal of the electronic system during the data interaction process;

[0015] Step S102: The original clock signal of the electronic system during the data interaction process is passed into a low-pass filter to filter the high-frequency signal and obtain the processing clock signal.

[0016] Step S103: Compare the processing clock signal with a preset threshold. If the processing clock signal is greater than or equal to the preset threshold, record the value in the square wave diagram as 1. If the processing clock signal is less than the preset threshold, record the value in the square wave diagram as 0, thus obtaining the square wave diagram of the processing clock signal.

[0017] Further, step S2 includes the following sub-steps:

[0018] Step S201: Obtain the square wave diagram corresponding to the processing clock signal of the corresponding electronic system during the data interaction process;

[0019] Step S202: The duration between one rising edge and the next rising edge in the square wave diagram is recorded as the clock fluctuation period; thus, z clock fluctuation periods of the square wave diagram corresponding to the processing clock signal are obtained.

[0020] Step S203: Select t clock fluctuation periods from z clock fluctuation periods and denot them as selected fluctuation periods ZQi, where i is the number of the selected fluctuation period. Traverse all selected fluctuation periods and identify the peak fluctuation period in the selected fluctuation periods. Then, add the t selected fluctuation periods together and take the average value to obtain the average selected fluctuation period.

[0021] Step S204: Calculate the standard deviation BZ of the fluctuation period corresponding to t selected fluctuation periods using the formula as follows:

[0022] In the formula, JZQ represents the average selected fluctuation period.

[0023] Furthermore, step S2 also includes the following sub-steps:

[0024] Step S205: Select t fluctuation periods again from z clock fluctuation periods, and calculate the peak fluctuation period, average selected fluctuation period, and fluctuation period standard deviation again based on the calculation process described in steps S203-S204; iterate multiple times to obtain n sets of peak fluctuation periods, n sets of average selected fluctuation periods, and n sets of fluctuation period standard deviations.

[0025] Step S206: Compare the n sets of peak fluctuation periods with the standard peak fluctuation period. If any set of peak fluctuation periods is greater than or equal to the standard peak fluctuation period, it is determined that the corresponding processing clock signal has jitter, and step S3 is executed directly.

[0026] Step S207: If all peak fluctuation periods are less than the standard peak fluctuation period, the average value of the selected fluctuation period is calculated by averaging the selected fluctuation periods of n groups, and the average value of the standard deviation of the fluctuation period is calculated by averaging the selected fluctuation periods of n groups.

[0027] Furthermore, step S2 also includes the following sub-steps:

[0028] Step S208: By selecting the mean of the fluctuation period plus the mean of three times the standard deviation of the fluctuation period as the right endpoint, and by selecting the mean of the fluctuation period minus the mean of three times the standard deviation of the fluctuation period as the left endpoint, the processing distribution interval corresponding to the clock fluctuation period is obtained based on the left endpoint and the right endpoint.

[0029] Step S209: Count the number of clock fluctuation cycles within the processing distribution interval, and obtain the distribution rate of the processing distribution interval by dividing the number of clock fluctuation cycles within the processing distribution interval by the total number of processing distribution intervals.

[0030] Step S210: The probability corresponding to three times sigma is regarded as the standard distribution probability. The distribution rate of the processing distribution interval is compared with the standard distribution probability. If the distribution rate of the processing distribution interval is greater than or equal to the standard distribution probability, it is determined that the processing clock signal does not have clock jitter in the corresponding clock fluctuation period, and the subsequent steps are not performed.

[0031] Step S211: If the distribution rate of the processing distribution interval is less than the standard distribution probability, it is determined that the processing clock signal has clock jitter in the corresponding clock fluctuation period, and step S3 is executed.

[0032] Further, step S3 includes the following sub-steps:

[0033] Step S301: Obtain the square wave diagram corresponding to the processing clock signal, and identify multiple clock fluctuation cycles based on the square wave diagram; randomly select a local square wave diagram of a fixed length on the square wave diagram corresponding to the processing clock signal, and identify multiple clock fluctuation cycles corresponding to the local square wave diagram.

[0034] Step S302: Sum the clock fluctuation periods corresponding to the local square wave diagrams and take the mean to obtain the mean of the corresponding clock period; calculate the corresponding standard deviation based on the mean of the clock period and multiple clock fluctuation periods; traverse all clock fluctuation periods and identify the mode of the clock fluctuation period.

[0035] Step S303: Select a local square wave of fixed length at any position on the square wave of the processing clock signal, repeat steps S301 to S302 and iterate multiple times to obtain m sets of clock cycle mean, m sets of standard deviation and m sets of mode.

[0036] Furthermore, step S3 also includes the following sub-steps:

[0037] Step S304: Sum the clock cycle mean values ​​and take the average to obtain the mean of the clock cycle mean values. Similarly, obtain the mean of the standard deviation and the mean of the mode.

[0038] If the sum of the mean corresponding to the clock cycle mean and the mean corresponding to the standard deviation is less than the mean of the mode, and the difference between the mean corresponding to the clock cycle mean and the mean corresponding to the standard deviation is greater than or equal to the mean of the mode, then the mean of the mode is recorded as the standard clock cycle.

[0039] Conversely, the average of the clock cycle averages is recorded as the standard clock cycle.

[0040] Furthermore, step S3 also includes the following sub-steps:

[0041] Step S305: Draw a standard square wave diagram corresponding to the standard clock cycle based on the number of clock fluctuation periods corresponding to the processing clock signal and the number of standard clock cycles;

[0042] Step S306: Align the left endpoint of the standard square wave diagram with the square wave diagram corresponding to the processing clock signal; within the same clock fluctuation period, subtract the time of the rising edge in the square wave diagram corresponding to the rising edge in the standard square wave diagram from the time of the rising edge in the square wave diagram corresponding to the processing clock signal and take the absolute value to obtain the rising jitter deviation.

[0043] The falling edge jitter deviation is obtained by subtracting the falling edge time of the processing clock signal from the falling edge time of the standard square wave diagram and taking the absolute value. The falling edge jitter deviation plus the rising edge jitter deviation is used to obtain the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period.

[0044] Further, step S4 includes the following sub-steps:

[0045] Step S401: Obtain the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period;

[0046] Step S402: Obtain the chip output jitter of the chip corresponding to the ultrafast clock fan-out buffer, and obtain the additional jitter caused by the power supply noise being added to the processing clock signal; calculate the sum of the squares of the chip output jitter and the additional jitter caused by the power supply noise being added to the processing clock signal, and then take the square root to obtain the total jitter of the pin corresponding to the ultrafast clock fan-out buffer.

[0047] Read the jitter contributed by the ultrafast clock fanout buffer itself, calculate the square root of the sum of the squares of the jitter contributed by the ultrafast clock fanout buffer itself and the total jitter of the corresponding pin of the ultrafast clock fanout buffer, and then obtain the total output jitter corresponding to the ultrafast clock fanout buffer.

[0048] Furthermore, step S3 also includes the following sub-steps:

[0049] Step S403: Sum the clock jitter deviations of the clock fluctuation period in the processing clock signal to obtain the total jitter deviation of the processing clock signal;

[0050] Step S404: Compare the total jitter deviation value with the total output jitter corresponding to the ultrafast clock fan-out buffer. If the total jitter deviation value is greater than or equal to the total output jitter corresponding to the ultrafast clock fan-out buffer, then perform clock jitter deviation recovery on the processing clock signal cycle by cycle based on the clock jitter deviation of the clock fluctuation period in the processing clock signal, and output it through the LVPECL output stage after the recovery is completed.

[0051] Step S405: If the total jitter deviation is less than the total output jitter corresponding to the ultrafast clock fanout buffer, then no operation is performed on the processing clock signal, and it is directly output through the LVPECL output stage.

[0052] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0053] 1. This invention first acquires the original clock signal during the data interaction process of the electronic system, preprocesses the original clock signal, and generates a corresponding square wave diagram based on the preprocessed processing clock signal; then, it analyzes the clock fluctuation period of the processing clock signal based on the square wave diagram to determine the existence of jitter deviation corresponding to the processing clock signal. This invention realizes the determination of the existence of jitter deviation of the processing clock signal.

[0054] 2. This invention analyzes the processing clock signal based on a square wave diagram, calculates the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period using the square wave diagram, and then inputs the processing clock signal into an ultra-fast clock fan-out buffer to comprehensively recover the clock jitter deviation in the clock fluctuation period. Finally, it receives the directly output processing clock signal or the processing clock signal output from the ultra-fast clock fan-out buffer, calculates the proportion of the processing clock signal output from the ultra-fast clock fan-out buffer, and judges the effectiveness of the ultra-fast clock fan-out buffer, thereby achieving accurate identification and recovery of clock jitter deviation. Attached Figure Description

[0055] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0056] Figure 1 This is a flowchart of the method of the present invention;

[0057] Figure 2 This is a square wave diagram of the processing clock signal in this invention;

[0058] Figure 3 This is a square wave diagram corresponding to the standard clock cycle in this invention;

[0059] Figure 4 This is a functional block diagram of the ultrafast clock fanout buffer in this invention;

[0060] Figure 5 This is a chip pinout diagram of the chip corresponding to the ultrafast clock fanout buffer in this invention;

[0061] Figure 6 This is a schematic diagram of the LVPECL output stage in this invention;

[0062] Figure 7 This is a schematic diagram of the electronic device in this invention. Detailed Implementation

[0063] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Example 1: Please refer to Figures 1-6As shown, the technical solution provided by the present invention is: a high-precision low-jitter clock recovery method, which acquires and processes clock signals, then draws a square wave diagram corresponding to the processing clock signal, analyzes the processing clock signal based on the square wave diagram, determines the existence of jitter in the processing clock signal, calculates the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period, and recovers the hour hand jitter deviation of the processing clock signal based on the clock jitter deviation combined with an ultra-fast clock fan-out buffer;

[0065] The aforementioned clock jitter refers to the short-term, non-cumulative deviation in time of the edge (rising edge or falling edge) of the clock signal relative to its ideal position, as measured by measurement.

[0066] In this invention, the clock recovery method is specifically as follows:

[0067] Step S1: Acquire the original clock signal during the data interaction process of the electronic system, preprocess the original clock signal, and generate the corresponding square wave diagram based on the preprocessed clock signal.

[0068] In this invention, step S1 includes the following sub-steps:

[0069] Step S101: Obtain the original clock signal of the electronic system during the data interaction process;

[0070] Step S102: The original clock signal of the electronic system during the data interaction process is passed into a low-pass filter to filter the high-frequency signal and obtain the processing clock signal.

[0071] Step S103, as follows Figure 2 As shown, the processing clock signal is compared with a preset threshold. If the processing clock signal is greater than or equal to the preset threshold, the value in the square wave diagram is recorded as 1. If the processing clock signal is less than the preset threshold, the value in the square wave diagram is recorded as 0, thus obtaining the square wave diagram of the processing clock signal.

[0072] Step S2: Analyze the clock fluctuation period of the processing clock signal based on the square wave diagram to determine the existence of jitter deviation corresponding to the processing clock signal.

[0073] In this invention, step S2 includes the following sub-steps:

[0074] Step S201: Obtain the square wave diagram corresponding to the processing clock signal of the corresponding electronic system during the data interaction process;

[0075] Step S202: The duration between one rising edge and the next rising edge in the square wave diagram is recorded as the clock fluctuation period; thus, z clock fluctuation periods of the square wave diagram corresponding to the processing clock signal are obtained.

[0076] Step S203: Select t clock fluctuation periods from z clock fluctuation periods and denot them as selected fluctuation periods ZQi, where i is the number of the selected fluctuation period. Traverse all selected fluctuation periods and identify the peak fluctuation period in the selected fluctuation periods. Then, add the t selected fluctuation periods together and take the average value to obtain the average selected fluctuation period.

[0077] It should be noted that the selection rule for the fluctuation period is random, and the number of selected fluctuation periods is greater than or equal to one-third of the number of clock fluctuation periods, while the number of selected fluctuation periods is less than one-half of the number of clock fluctuation periods.

[0078] Step S204: Calculate the standard deviation BZ of the fluctuation period corresponding to t selected fluctuation periods using the formula as follows:

[0079] In the formula, JZQ is the average selected fluctuation period;

[0080] Step S205: Select t fluctuation periods again from z clock fluctuation periods, and calculate the peak fluctuation period, average selected fluctuation period, and fluctuation period standard deviation again based on the calculation process described in steps S203-S204; iterate multiple times to obtain n sets of peak fluctuation periods, n sets of average selected fluctuation periods, and n sets of fluctuation period standard deviations.

[0081] Step S206: Compare the n sets of peak fluctuation periods with the standard peak fluctuation period. If any set of peak fluctuation periods is greater than or equal to the standard peak fluctuation period, it is determined that the corresponding processing clock signal has jitter, and step S3 is executed directly.

[0082] Step S207: If all peak fluctuation periods are less than the standard peak fluctuation period, the average value of the selected fluctuation period is calculated by averaging the selected fluctuation periods of n groups, and the average value of the standard deviation of the fluctuation period is calculated by averaging the standard deviations of the selected fluctuation periods of n groups.

[0083] Step S208: By selecting the mean of the fluctuation period plus the mean of three times the standard deviation of the fluctuation period as the right endpoint, and by selecting the mean of the fluctuation period minus the mean of three times the standard deviation of the fluctuation period as the left endpoint, the processing distribution interval corresponding to the clock fluctuation period is obtained based on the left endpoint and the right endpoint.

[0084] Step S209: Count the number of clock fluctuation cycles within the processing distribution interval, and obtain the distribution rate of the processing distribution interval by dividing the number of clock fluctuation cycles within the processing distribution interval by the total number of processing distribution intervals.

[0085] It should be noted that since the clock's periodic jitter is essentially a random quantity with a Gaussian distribution, it is assumed that the clock's fluctuation period follows a Gaussian probability density function, that is, the clock's fluctuation period follows the law of Gaussian normal distribution; therefore, the clock's fluctuation period satisfies the three sigma rule of normal distribution.

[0086] Step S210: The probability corresponding to three times sigma is regarded as the standard distribution probability. The distribution rate of the processing distribution interval is compared with the standard distribution probability. If the distribution rate of the processing distribution interval is greater than or equal to the standard distribution probability, it is determined that the processing clock signal does not have clock jitter in the corresponding clock fluctuation period, and the subsequent steps are not performed.

[0087] Step S211: If the distribution rate of the processing distribution interval is less than the standard distribution probability, it is determined that the processing clock signal has clock jitter in the corresponding clock fluctuation period, and step S3 is executed.

[0088] Step S3: Analyze the processing clock signal based on the square wave diagram, and calculate the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period based on the square wave diagram.

[0089] In this invention, step S3 includes the following sub-steps:

[0090] Step S301: Obtain the square wave diagram corresponding to the processing clock signal, and identify multiple clock fluctuation cycles based on the square wave diagram; randomly select a local square wave diagram of a fixed length on the square wave diagram corresponding to the processing clock signal, and identify multiple clock fluctuation cycles corresponding to the local square wave diagram; specifically, the fixed length can be one thousand unit durations.

[0091] Step S302: Sum the clock fluctuation periods corresponding to the local square wave diagrams and take the mean to obtain the mean of the corresponding clock period; calculate the corresponding standard deviation based on the mean of the clock period and multiple clock fluctuation periods; traverse all clock fluctuation periods and identify the mode of the clock fluctuation period.

[0092] Step S303: Select a local square wave of fixed length at any position on the square wave of the processing clock signal, repeat steps S301 to S302 and iterate multiple times to obtain m sets of clock cycle mean, m sets of standard deviation and m sets of mode.

[0093] Step S304: Sum the clock cycle mean values ​​and take the average to obtain the mean of the clock cycle mean values. Similarly, obtain the mean of the standard deviation and the mean of the mode. If the sum of the mean of the clock cycle mean and the mean of the standard deviation is less than the mean of the mode, and the difference between the mean of the clock cycle mean and the mean of the standard deviation is greater than or equal to the mean of the mode, then the mean of the mode is recorded as the standard clock cycle. Otherwise, the mean of the clock cycle mean values ​​is recorded as the standard clock cycle.

[0094] Step S305: Draw a standard square wave diagram corresponding to the standard clock cycle based on the number of clock fluctuation periods corresponding to the processing clock signal and the number of standard clock cycles;

[0095] Step S306, as follows Figure 3 As shown, the left endpoints of the standard square wave diagram and the corresponding square wave diagram of the processing clock signal are aligned. Within the same clock fluctuation period, the rising jitter deviation is obtained by subtracting the rising time of the corresponding square wave diagram of the processing clock signal from the rising time of the rising edge of the standard square wave diagram and taking the absolute value. The falling jitter deviation is obtained by subtracting the falling time of the corresponding square wave diagram of the processing clock signal from the falling time of the standard square wave diagram and taking the absolute value. The falling jitter deviation plus the rising jitter deviation gives the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period.

[0096] Step S4: Input the processing clock signal into the ultrafast clock fan-out buffer to perform comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period;

[0097] In this invention, step S4 includes the following sub-steps:

[0098] Step S401: Obtain the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period;

[0099] It should be noted that since the ultrafast clock fanout buffer itself will output jitter, it is necessary to calculate the jitter output by the ultrafast clock fanout buffer.

[0100] Step S402: Obtain the chip output jitter of the chip corresponding to the ultrafast clock fan-out buffer, and obtain the additional jitter caused by the power supply noise added to the processing clock signal; calculate the square root of the sum of the squares of the chip output jitter and the additional jitter caused by the power supply noise added to the processing clock signal to obtain the total jitter of the pin corresponding to the ultrafast clock fan-out buffer; read the jitter contributed by the ultrafast clock fan-out buffer itself from the datasheet, calculate the square root of the sum of the squares of the jitter contributed by the ultrafast clock fan-out buffer itself and the total jitter of the pin corresponding to the ultrafast clock fan-out buffer to obtain the total output jitter corresponding to the ultrafast clock fan-out buffer;

[0101] Step S403: Sum the clock jitter deviations of the clock fluctuation period in the processing clock signal to obtain the total jitter deviation of the processing clock signal;

[0102] Step S404: Compare the total jitter deviation value with the total output jitter corresponding to the ultrafast clock fan-out buffer. If the total jitter deviation value is greater than or equal to the total output jitter corresponding to the ultrafast clock fan-out buffer, then perform clock jitter deviation recovery on the processing clock signal cycle by cycle based on the clock jitter deviation of the clock fluctuation period in the processing clock signal, and output it through the LVPECL output stage after the recovery is completed.

[0103] Step S405: If the total jitter deviation is less than the total output jitter corresponding to the ultrafast clock fan-out buffer, then no operation is performed on the processing clock signal, and it is directly output through the LVPECL output stage; it should be noted that this situation only exists in a very small number of cases.

[0104] Among them, the LVPECL output stage is a differential output circuit structure used for high-speed digital signal transmission, such as... Figure 6 This is a simplified schematic diagram of an LVPECL output stage;

[0105] Please see Figure 4 The following is a pin function table for the chip package pins:

[0106]

[0107]

[0108] Step S5: Receive the directly output processing clock signal or the processing clock signal output from the ultrafast clock fan-out buffer, calculate the proportion of the processing clock signal output from the ultrafast clock fan-out buffer, and determine the effectiveness of the ultrafast clock fan-out buffer.

[0109] Example 2: This embodiment of the invention also provides an electronic device for running the aforementioned high-precision, low-jitter clock recovery method; see [link to previous example]. Figure 7 The schematic diagram of an electronic device provided by the embodiment of the present invention shown above includes a memory and a processor. The memory is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor to realize the above-mentioned high-precision low-jitter clock recovery method.

[0110] Furthermore, Figure 7 The electronic device shown also includes a communication bus and a communication interface, with the processor, communication interface and memory connected via the communication bus;

[0111] The memory may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk drive. Communication between this system network element and at least one other network element is achieved through at least one communication interface (wired or wireless), which can use the Internet, wide area network, local area network, metropolitan area network, etc. The communication bus can be an ISA bus, PCI bus, or EISA bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The symbol is represented by only one double-headed arrow, but this does not mean that there is only one communication bus or one type of communication bus.

[0112] The processor may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above methods can be completed by integrated logic circuits in the processor's hardware or by software instructions. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0113] Example 3: This embodiment of the invention also provides a computer storage medium that stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned high-precision low-jitter clock recovery method. For specific implementation, please refer to the method embodiment, which will not be repeated here.

[0114] The computer program product of the high-precision low-jitter clock recovery method provided in this embodiment of the invention includes a computer storage medium storing program code. The instructions included in the program code can be used to execute the methods in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0115] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and / or device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0116] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0117] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-precision, low-jitter clock recovery method, characterized in that, The methods include: Step S1: Acquire the original clock signal during the data interaction process of the electronic system, preprocess the original clock signal, and generate the corresponding square wave diagram based on the preprocessed clock signal. Step S2: Analyze the clock fluctuation period of the processing clock signal based on the square wave diagram to determine the existence of jitter deviation corresponding to the processing clock signal. Step S3: Analyze the processing clock signal based on the square wave diagram, and calculate the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period based on the square wave diagram. Step S4: Input the processing clock signal into the ultrafast clock fan-out buffer to perform comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period; Step S5: Receive the directly output processing clock signal or the processing clock signal output from the ultrafast clock fan-out buffer, calculate the proportion of the processing clock signal output from the ultrafast clock fan-out buffer, and determine the effectiveness of the ultrafast clock fan-out buffer.

2. The high-precision, low-jitter clock recovery method according to claim 1, characterized in that, Step S1 includes the following sub-steps: Step S101: Obtain the original clock signal of the electronic system during the data interaction process; Step S102: The original clock signal of the electronic system during the data interaction process is passed into a low-pass filter to filter the high-frequency signal and obtain the processing clock signal. Step S103: Compare the processing clock signal with a preset threshold. If the processing clock signal is greater than or equal to the preset threshold, record the value in the square wave diagram as 1. If the processing clock signal is less than the preset threshold, record the value in the square wave diagram as 0, thus obtaining the square wave diagram of the processing clock signal.

3. The high-precision, low-jitter clock recovery method according to claim 1, characterized in that, Step S2 includes the following sub-steps: Step S201: Obtain the square wave diagram corresponding to the processing clock signal of the corresponding electronic system during the data interaction process; Step S202: The duration between one rising edge and the next rising edge in the square wave diagram is recorded as the clock fluctuation period; thus, z clock fluctuation periods of the square wave diagram corresponding to the processing clock signal are obtained. Step S203: Select t clock fluctuation periods from z clock fluctuation periods and denot them as selected fluctuation periods ZQi, where i is the number of the selected fluctuation period. Traverse all selected fluctuation periods and identify the peak fluctuation period in the selected fluctuation periods. Then, add the t selected fluctuation periods together and take the average value to obtain the average selected fluctuation period. Step S204: Calculate the standard deviation BZ of the fluctuation period corresponding to t selected fluctuation periods using the formula as follows: In the formula, JZQ represents the average selected fluctuation period.

4. The high-precision, low-jitter clock recovery method according to claim 3, characterized in that, Step S2 further includes the following sub-steps: Step S205: Select t selected fluctuation periods again from z clock fluctuation periods, and calculate the peak fluctuation period, average selected fluctuation period and fluctuation period standard deviation again based on the calculation process described in steps S203-S204. After multiple iterations, n sets of peak fluctuation periods, n sets of average selected fluctuation periods, and n sets of fluctuation period standard deviations are obtained. Step S206: Compare the n sets of peak fluctuation periods with the standard peak fluctuation period. If any set of peak fluctuation periods is greater than or equal to the standard peak fluctuation period, it is determined that the corresponding processing clock signal has jitter, and step S3 is executed directly. Step S207: If all peak fluctuation periods are less than the standard peak fluctuation period, the average value of the selected fluctuation period is calculated by averaging the selected fluctuation periods of n groups, and the average value of the standard deviation of the fluctuation period is calculated by averaging the selected fluctuation periods of n groups.

5. The high-precision, low-jitter clock recovery method according to claim 4, characterized in that, Step S2 further includes the following sub-steps: Step S208: By selecting the mean of the fluctuation period plus the mean of three times the standard deviation of the fluctuation period as the right endpoint, and by selecting the mean of the fluctuation period minus the mean of three times the standard deviation of the fluctuation period as the left endpoint, the processing distribution interval corresponding to the clock fluctuation period is obtained based on the left endpoint and the right endpoint. Step S209: Count the number of clock fluctuation cycles within the processing distribution interval, and obtain the distribution rate of the processing distribution interval by dividing the number of clock fluctuation cycles within the processing distribution interval by the total number of processing distribution intervals. Step S210: The probability corresponding to three times sigma is regarded as the standard distribution probability. The distribution rate of the processing distribution interval is compared with the standard distribution probability. If the distribution rate of the processing distribution interval is greater than or equal to the standard distribution probability, it is determined that the processing clock signal does not have clock jitter in the corresponding clock fluctuation period, and the subsequent steps are not performed. Step S211: If the distribution rate of the processing distribution interval is less than the standard distribution probability, it is determined that the processing clock signal has clock jitter in the corresponding clock fluctuation period, and step S3 is executed.

6. The high-precision, low-jitter clock recovery method according to claim 1, characterized in that, Step S3 includes the following sub-steps: Step S301: Obtain the square wave diagram corresponding to the processing clock signal, and identify multiple clock fluctuation cycles based on the square wave diagram; randomly select a local square wave diagram of a fixed length on the square wave diagram corresponding to the processing clock signal, and identify multiple clock fluctuation cycles corresponding to the local square wave diagram. Step S302: Add the clock fluctuation periods corresponding to the local square wave diagrams, sum them up, and take the average value to obtain the average value of the corresponding clock periods; The standard deviation is calculated based on the mean of the clock cycle and multiple clock fluctuation cycles; the mode of the clock fluctuation cycle is identified by traversing all clock fluctuation cycles. Step S303: Select a local square wave of fixed length at any position on the square wave of the processing clock signal, repeat steps S301 to S302 and iterate multiple times to obtain m sets of clock cycle mean, m sets of standard deviation and m sets of mode.

7. The high-precision, low-jitter clock recovery method according to claim 6, characterized in that, Step S3 further includes the following sub-steps: Step S304: Sum the clock cycle mean values ​​and take the average to obtain the mean of the clock cycle mean values. Similarly, obtain the mean of the standard deviation and the mean of the mode. If the sum of the mean corresponding to the clock cycle mean and the mean corresponding to the standard deviation is less than the mean of the mode, and the difference between the mean corresponding to the clock cycle mean and the mean corresponding to the standard deviation is greater than or equal to the mean of the mode, then the mean of the mode is recorded as the standard clock cycle. Conversely, the average of the clock cycle averages is recorded as the standard clock cycle.

8. The high-precision, low-jitter clock recovery method according to claim 7, characterized in that, Step S3 further includes the following sub-steps: Step S305: Draw a standard square wave diagram corresponding to the standard clock cycle based on the number of clock fluctuation periods corresponding to the processing clock signal and the number of standard clock cycles; Step S306: Align the left endpoint of the standard square wave diagram with the square wave diagram corresponding to the processing clock signal; within the same clock fluctuation period, subtract the time of the rising edge in the square wave diagram corresponding to the rising edge in the standard square wave diagram from the time of the rising edge in the square wave diagram corresponding to the processing clock signal and take the absolute value to obtain the rising jitter deviation. Subtract the time of the falling edge in the square wave corresponding to the processing clock signal from the time of the falling edge in the standard square wave plot and take the absolute value to obtain the falling jitter deviation. The clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period is obtained by adding the falling jitter deviation to the rising jitter deviation.

9. The high-precision, low-jitter clock recovery method according to claim 1, characterized in that, Step S4 includes the following sub-steps: Step S401: Obtain the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period; Step S402: Obtain the chip output jitter of the chip corresponding to the ultrafast clock fan-out buffer, and obtain the additional jitter caused by the power supply noise being added to the processing clock signal; calculate the sum of the squares of the chip output jitter and the additional jitter caused by the power supply noise being added to the processing clock signal, and then take the square root to obtain the total jitter of the pin corresponding to the ultrafast clock fan-out buffer. Read the jitter contributed by the ultrafast clock fanout buffer itself, calculate the square root of the sum of the squares of the jitter contributed by the ultrafast clock fanout buffer itself and the total jitter of the corresponding pin of the ultrafast clock fanout buffer, and then obtain the total output jitter corresponding to the ultrafast clock fanout buffer.

10. A high-precision, low-jitter clock recovery method according to claim 9, characterized in that, Step S3 further includes the following sub-steps: Step S403: Sum the clock jitter deviations of the clock fluctuation period in the processing clock signal to obtain the total jitter deviation of the processing clock signal; Step S404: Compare the total jitter deviation value with the total output jitter corresponding to the ultrafast clock fan-out buffer. If the total jitter deviation value is greater than or equal to the total output jitter corresponding to the ultrafast clock fan-out buffer, then perform clock jitter deviation recovery on the processing clock signal cycle by cycle based on the clock jitter deviation of the clock fluctuation period in the processing clock signal, and output it through the LVPECL output stage after the recovery is completed. Step S405: If the total jitter deviation is less than the total output jitter corresponding to the ultrafast clock fanout buffer, then no operation is performed on the processing clock signal, and it is directly output through the LVPECL output stage.

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