Server mainboard, communication method and system, DPU card, device, medium and product

Abstract

The invention provides a server mainboard, a communication method and system, a DPU card, equipment, a medium and a product, and the server mainboard comprises a mainboard substrate management controller (Host-BMC) which is used for communicating with external equipment and managing a gating unit to transmit a serial port signal; the main board central processing unit Host-CPU is connected to the gating unit and is used for transmitting a Host-CPU serial port signal to the gating unit; the gating unit is connected with the DPU card, the Host-BMC (Baseboard Management Controller) and the Host-CPU (Central Processing Unit); the Host-BMC is used for receiving a first serial port signal and transmitting the first serial port signal to the Host-BMC based on the management of the Host-BMC; the first serial port signal is a Host-CPU serial port signal or a DPU card serial port signal. In conclusion, different serial port signals can be selected by using the unified gating logic and channel selection mechanism of the server mainboard. Therefore, the risk problem of DPU card information exposure is greatly reduced, meanwhile, the complexity of management interaction can be simplified, resource occupation can be reduced, and actual objective requirements can be met.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, and in particular to a server motherboard, a communication method and system, a DPU card, an apparatus, a medium and a product. BACKGROUND

[0002] At present, when the existing external device obtains a Data Processing Unit (DPU) serial signal or a Central Processing Unit (CPU) serial signal, it needs to be connected with the out-of-band management module of the DPU or the out-of-band management module of the CPU respectively and independently to obtain the signal. In this way, the DPU card must have the capability of independent out-of-band management network, which greatly increases the exposure risk of DPU card information, and also makes the management interaction process complex and cumbersome, increases resource occupation, and is difficult to meet the actual objective needs. SUMMARY

[0003] The present disclosure provides a server motherboard, a communication method and system, a DPU card, an apparatus, a medium and a product, which can solve the problems of DPU card information exposure, complex and cumbersome management interaction process, increased resource occupation, and difficulty in meeting the actual objective needs to some extent.

[0004] According to an aspect of the present disclosure, a server motherboard is provided, comprising: a motherboard baseboard management controller Host-BMC, configured to communicate with an external device and manage a gating unit to transmit a serial signal; a motherboard central processing unit Host-CPU, connected to the gating unit, configured to transmit a Host-CPU serial signal to the gating unit; and the gating unit, connected to a DPU card, the Host-BMC and the Host-CPU, configured to receive a first serial signal and transmit the first serial signal to the Host-BMC based on the management of the Host-BMC; the first serial signal is the Host-CPU serial signal or the DPU card serial signal.

[0005] In addition, according to the server motherboard of the present disclosure, the Host-BMC communicates with the external device through the out-of-band management network port; and the external device comprises a hardware management platform.

[0006] In addition, according to the server motherboard of the present disclosure, the Host-BMC manages the gating unit through a control signal; and the control signal is used to indicate the connection of the transmission channel of each first serial signal.

[0007] In addition, according to the server motherboard of the present disclosure, the server motherboard further comprises: a first connector connected to a second connector through a cable; and the second connector is arranged in the DPU card.

[0008] Furthermore, according to one aspect of the server motherboard disclosed herein, when an external device requests a Host-CPU serial port signal, the first serial port signal is a Host-CPU serial port signal, and a first channel is connected between the Host-BMC, the gating unit, and the Host-CPU; or, when an external device requests a DPU card serial port signal, the first serial port signal is a DPU card serial port signal, and a second channel is connected between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card.

[0009] Furthermore, according to one aspect of this disclosure, the server motherboard further includes: a host-CPLD (Host Complex Programmable Device), wherein a gating unit is disposed in the host-CPLD.

[0010] According to another aspect of this disclosure, a communication method is provided, applied to a server motherboard as described in any of the above claims; the method includes: the Host-BMC sending a control signal to a gating unit; the gating unit controlling the connection between the Host-BMC and a first serial port signal transmission channel based on the control signal; the first serial port signal including at least one of the following: a Host-CPU serial port signal and a DPU card serial port signal; the Host-BMC sending the first serial port signal.

[0011] Furthermore, according to another aspect of the method of this disclosure, before the Host-BMC sends a control signal to the gating unit, the method further includes: based on first information sent by an external device, the Host-BMC sends a control signal to the gating unit; the control signal is used to indicate the connection of the transmission channels of each first serial port signal.

[0012] Furthermore, according to another aspect of the method of this disclosure, the gating unit controls the connection between the Host-BMC and the first serial port signal transmission channel based on a control signal, including: when the control signal indicates that the first channel is connected, the gating unit controls the first channel to be connected; the first channel is a transmission channel between the Host-BMC, the gating unit, and the Host-CPU; or, when the control signal indicates that the second channel is connected, the gating unit controls the second channel to be connected; the second channel is a transmission channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card.

[0013] According to another aspect of this disclosure, a DPU card is provided, including: a DPU processor and a gating unit connected to a server motherboard for transmitting DPU card serial port signals to the gating unit.

[0014] Furthermore, according to another aspect of this disclosure, the DPU card also includes: a second connector connected to the first connector via a cable, the first connector being disposed in the server motherboard.

[0015] Furthermore, according to another aspect of the present disclosure, the DPU card serial port signal includes at least one of the following: a universal asynchronous transceiver (UART) transmit signal and a UART receive signal.

[0016] According to another aspect of this disclosure, a communication system is provided, comprising: a server motherboard for implementing the server motherboard as described in any of the above claims; and a DPU card for implementing the DPU card as described in any of the above claims.

[0017] According to another aspect of this disclosure, an electronic device is provided, comprising: a memory for storing computer-readable instructions; and a processor for executing the computer-readable instructions, causing the electronic device to perform the method as described in any embodiment of one aspect.

[0018] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided for storing computer-readable instructions that, when executed by a processor, cause the processor to perform the method as described in any embodiment of one aspect.

[0019] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method as described in any embodiment of one aspect.

[0020] This disclosure provides a server motherboard, a communication method and system, a DPU card, a device, a medium, and a product. The server motherboard of this disclosure includes: a Host Baseboard Management Controller (Host-BMC) for communicating with external devices and managing the gating unit to transmit serial port signals; a Host Central Processing Unit (Host-CPU) connected to the gating unit for transmitting Host-CPU serial port signals to the gating unit; and a gating unit connected to the DPU card, Host-BMC, and Host-CPU for receiving a first serial port signal and transmitting the first serial port signal to it based on the management of the Host-BMC; the first serial port signal is either a Host-CPU serial port signal or a DPU card serial port signal. In summary, the technical solution provided by this disclosure can centrally manage and control the gating unit to transmit different serial port signals through the Host-BMC of the server motherboard. Compared to existing methods that acquire signals independently, this disclosure can utilize the unified gating logic and channel selection mechanism of the server motherboard to select different serial port signals. This significantly reduces the risk of DPU card information exposure, while simplifying management and interaction complexity, reducing resource consumption, and meeting actual objective needs.

[0021] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0022] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to offer a further understanding of the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0023] Figure 1 This is a schematic diagram of the existing structure for acquiring different serial port signals;

[0024] Figure 2 This is a schematic diagram illustrating the structure for acquiring different serial port signals provided in an embodiment of this disclosure;

[0025] Figure 3 A hardware block diagram of an electronic device provided in an embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this disclosure more apparent, exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments of this disclosure. It should be understood that this disclosure is not limited to the exemplary embodiments described herein.

[0028] Currently, existing external devices need to connect independently to the out-of-band management module of the DPU or CPU to obtain serial port signals from the data processing unit (DPU) or central processing unit (CPU). For example, Figure 1 This is a schematic diagram of an existing structure for acquiring different serial port signals. For example... Figure 1 As shown, from Figure 1As can be seen, when the CPU's serial port signal needs to be obtained, the hardware management platform needs to send a signal to the server motherboard's out-of-band management network port, and the server motherboard's Host-BMC will directly obtain the CPU's serial port signal from the Host-CPU. Similarly, when the DPU card's serial port signal needs to be obtained, the hardware management platform needs to send a signal to the DPU card's out-of-band management network port, and the DPU's out-of-band management module obtains the DPU card's serial port signal from the DPU processor. It should also be noted that... Figure 1 The Peripheral Component Interconnect Express SLot (PCIeSLot), as a channel conforming to the high-speed interconnect protocol standard, will not support the transmission of serial port information by the DPU card.

[0029] In summary, using existing technology, to obtain the serial port information of a DPU card, the DPU card must have independent out-of-band management network capabilities to communicate independently with external devices. This significantly increases the risk of exposing DPU card information, makes the management interaction process complex and cumbersome, increases resource consumption, and makes it difficult to meet actual objective needs.

[0030] Therefore, this application proposes a server motherboard that can centrally manage and control the transmission of different serial port signals through the Host-BMC (Host-Block Controller) of the server motherboard. Please refer to... Figure 2 , Figure 2 This is a schematic diagram illustrating the structure for acquiring different serial port signals provided in embodiments of this disclosure, such as... Figure 2 As shown: The service motherboard includes:

[0031] The motherboard baseboard management controller (Host-BMC) is used to communicate with external devices and manage the gating unit to transmit serial port signals.

[0032] The motherboard's central processing unit (Host-CPU) is connected to the gating unit and is used to transmit Host-CPU serial port signals to the gating unit.

[0033] The gating unit is connected to the DPU card, Host-BMC, and Host-CPU; it is used to receive the first serial port signal and transmit the first serial port signal to the Host-BMC based on the management of the Host-BMC; the first serial port signal is either the Host-CPU serial port signal or the DPU card serial port signal.

[0034] In this disclosure, the server motherboard features a newly added gating unit. This gating unit can connect to the Host-BMC, Host-CPU, and DPU card, enabling the gating and transmission of the first serial port signal. The Host-BMC can connect to external devices and serves as the control center of the entire server motherboard, controlling the gating transmission of the gating unit. The Host-CPU is connected to the gating unit and transmits its CPU serial port signal to the gating unit when necessary. The first serial port signal in this disclosure includes, but is not limited to, the Host-CPU serial port signal or the DPU card serial port signal. Specifically, the Host-CPU serial port signal can be understood as being used to monitor and manage the status of the Host-CPU. The DPU card serial port signal can be understood as being used to monitor and manage the status of the DPU card. The specific form of the DPU card serial port signal can include, but is not limited to, at least one of the following: Universal Asynchronous Receiver / Transmitter Transmit (UART_TX) and Universal Asynchronous Receiver / Transmitter Receive (UART_RX), without specific limitations.

[0035] In this way, when external devices require specific serial port signals or the server needs to perform internal processing, the Host-BMC can manage the gating unit according to the actual situation and select the appropriate first serial port signal for transmission. If the Host-CPU's serial port signal needs to be transmitted, the Host-CPU will send its signal to the gating unit, which will then transmit the signal under the management of the Host-BMC. Similarly, if it is a serial port signal from the DPU card, the DPU card's signal can also be transmitted through the gating unit under the control of the Host-BMC.

[0036] In summary, the newly added gating unit enhances the signal management capabilities of the server motherboard. Different serial port signals can be transmitted through the gating unit, which can be centrally managed and controlled via the server motherboard's Host-BMC. Compared to the existing method of acquiring signals independently, this disclosure utilizes the server motherboard's unified gating logic and channel selection mechanism to select different serial port signals. This significantly reduces the risk of DPU card information exposure, simplifies management interaction, reduces resource consumption, and meets practical needs.

[0037] The following details the main functions of each unit on the server motherboard when acquiring serial port signals.

[0038] In this disclosure, the Host-BMC primarily performs two functions: communicating with external devices and managing the signal transmission of the gating unit. The details are explained below:

[0039] The primary function of the Host-BMC is to communicate with external devices via its out-of-band management port. Specifically, the out-of-band management port can be understood as an independent network path through which communication with external devices can be achieved. It's important to note that the out-of-band management port is unaffected by the server's operating system; even if the server's operating system experiences problems, communication with external devices can still be maintained through the out-of-band management port.

[0040] The external devices include at least a hardware management platform. This hardware management platform can be used for remote management and monitoring of server hardware. It can be a physical device or virtualized management software; there are no specific limitations.

[0041] The second function of the Host-BMC is to manage the gating unit via control signals. These control signals, generated by the Host-BMC, primarily indicate the connectivity of transmission channels for each first serial port signal. Specifically, when the Host-BMC needs to transmit a specific first serial port signal, it generates a corresponding control signal. This control signal is then sent to the gating unit. Upon receiving the control signal, the gating unit determines which transmission channels are connected based on its indication. For example, if the control signal indicates that the Host-CPU's serial port signal should be transmitted, the gating unit will connect the channel connected to the Host-CPU as well as the channels connected to external devices or other parts that need to receive the signal, thereby enabling the transmission of the Host-CPU's serial port signal.

[0042] The specific form of the control signal may include, but is not limited to, at least one of the following: general-purpose input / output (GPIO) signals and inter-integrated circuit (I2C) signals, without any specific restrictions.

[0043] This logical design allows the Host-BMC to flexibly control the transmission paths of different serial port signals and dynamically adjust them according to actual needs, thereby improving the unified management efficiency of the server motherboard.

[0044] In this disclosure, in addition to the Host-BMC, Host-CPU, and strobe unit, the server motherboard may also include a first connector, the main purpose of which is to connect the DPU card. Specifically, the first connector can be connected to a second connector located on the DPU card via a cable, thereby realizing the connection between the server motherboard and the DPU card.

[0045] Both the first connector and / or the second connector can be sideband signal connectors. A sideband signal connector can be understood as a connection channel outside the main transmission channel, capable of signal transmission independently of the server's main transmission channel, thus unaffected by its influence. Furthermore, there are no specific restrictions on the cable material and construction; different materials and constructions can be selected based on actual needs and application scenarios. For example, cables with good shielding performance can be chosen to reduce external interference, or flexible and bendable cables can be selected for ease of wiring and installation, or specially customized cables can be chosen. Cable materials can include copper, optical fiber, etc., and constructions can be single-core, multi-core, shielded, etc., to meet different signal transmission requirements and environmental conditions.

[0046] For example, as shown above Figure 2 It can be seen that the server motherboard can use the sideband signal connector (equivalent to the first connector) and the custom cable (equivalent to the cable) to achieve the connection and communication between the server motherboard and the DPU card.

[0047] In this disclosure, the gating unit of the server motherboard can be implemented in various ways.

[0048] In one exemplary embodiment, the server motherboard further includes a Host Complex Programmable Logic Device (Host-CPLD), and the gating unit is disposed within the Host-CPLD. The Host-CPLD is a programmable logic device with high flexibility and configurability. By placing the gating unit within the Host-CPLD, the programmable characteristics of the CPLD can be utilized to implement the gating and transmission functions of different serial port signals. Specifically, the Host-CPLD can be programmed and configured according to control signals from the Host-BMC to determine which serial port signal transmission channels are connected.

[0049] In another exemplary embodiment, the server motherboard may further include a Field Programmable Gate Array (FPGA) and the gating unit is located within the FPGA. The FPGA, with its high programmability and flexibility, allows the gating unit's functionality to be implemented through programming. Specifically, a serial port signal is connected to the FPGA's input pins, and logic circuitry is designed within the FPGA to select and output a specific signal based on control signals from the Host-BMC.

[0050] The following section will elaborate on the use of a server motherboard to transmit different serial port signals:

[0051] In the first scenario: when an external device requests a Host-CPU serial port signal, the first serial port signal is the Host-CPU serial port signal, and the first channel between the Host-BMC, the strobe unit, and the Host-CPU is connected.

[0052] In this disclosure, when an external device requests a Host-CPU serial port signal, the first internal serial port signal that the server motherboard needs to transmit is the Host-CPU serial port signal. Upon receiving the request signal from the external device, the Host-BMC generates a corresponding control command and sends it to the gating unit. Based on the control command, the gating unit connects the first channel between the Host-BMC, the gating unit, and the Host-CPU, enabling the Host-CPU's serial port signal to be successfully transmitted through the gating unit to the Host-BMC, which then transmits the signal to the external device. For example, as described above... Figure 2 When the Host-BMC receives a request from the CPU serial port signal of the hardware management platform (equivalent to an external device), it controls the gating unit to connect the CPU serial port signal channel, so that the serial port signal of the Host-CPU can be successfully transmitted to the Host-BMC through the gating unit, and then the Host-BMC transmits the signal to the hardware management platform.

[0053] Second scenario: When an external device requests a DPU card serial port signal, the first serial port signal is the DPU card serial port signal, and the second channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card is connected.

[0054] In this disclosure, when an external device requests a serial port signal from the DPU card, the first internal serial port signal that the server motherboard needs to transmit is the DPU card serial port signal. At this time, the Host-BMC receives the request signal from the external device, analyzes it to determine that the required serial port signal comes from the DPU card, and generates a corresponding control command. Based on this control command, the gating unit connects the second channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card. Thus, the DPU card's serial port signal can be transmitted sequentially through the second connector, the first connector, and the gating unit to the Host-BMC, and finally, the Host-BMC transmits the signal to the external device. For example, as described above... Figure 2 When the Host-BMC receives a request from the hardware management platform (equivalent to an external device) for a serial port signal from the DPU card, it controls the gating unit to connect the DPU serial port signal channel, so that the serial port signal of the DPU card can be successfully transmitted to the Host-BMC through the second connector, the first connector, and the gating unit. Finally, the Host-BMC transmits the signal to the hardware management platform.

[0055] This disclosure also provides a communication method for use on a server motherboard, including:

[0056] The Host-BMC sends control signals to the gating unit;

[0057] The gating unit controls the connection between the Host-BMC and the first serial port signal transmission channel based on the control signal; the first serial port signal includes at least one of the following: Host-CPU serial port signal, DPU card serial port signal;

[0058] The Host-BMC sends the first serial port signal.

[0059] In this disclosure, the Host-BMC sends a control signal to the gating unit, which instructs the gating unit to perform gating operations on different first serial port signals. Upon receiving the control signal, the gating unit controls the connection between the Host-BMC and the first serial port signal transmission channel based on the control signal. The first serial port signal includes at least one type, which can be a Host-CPU serial port signal, a DPU card serial port signal, or both signals at different time periods. Once the gating unit determines the first serial port signal to be transmitted based on the control signal, it connects the corresponding transmission channel, enabling the first serial port signal to be transmitted from the signal source (Host-CPU or DPU card) to the Host-BMC. Finally, the Host-BMC sends the received first serial port signal to an external device or performs other processing operations. In this way, the server motherboard can achieve unified management of different serial port signals, greatly reducing the risk of DPU card information exposure.

[0060] The following section details how the Host-BMC determines the control signals to be sent.

[0061] In one exemplary embodiment, the Host-BMC can determine to send a control signal (i.e., passive triggering) based on a request from an external device. The method then includes:

[0062] Based on the first information sent by the external device, the Host-BMC sends a control signal to the gating unit; the control signal is used to indicate the connection of the transmission channels of each first serial port signal.

[0063] In this disclosure, when an external device has a specific serial port signal requirement, it sends a first message to the server motherboard. After receiving the first message from the external device, the Host-BMC analyzes the message to determine the type of serial port signal requested by the external device. Then, based on the request from the external device, the Host-BMC determines to send the corresponding control signal to the selection unit.

[0064] This design allows the server motherboard to dynamically adjust the serial port signal transmission channel according to the requests of external devices, improving the flexibility and adaptability of the interaction between the server motherboard and external devices.

[0065] In another exemplary embodiment, the Host-BMC can proactively send control signals (i.e., proactively trigger them). Specifically, the Host-BMC can proactively send control signals when preset conditions are met. These preset conditions may include, but are not limited to, at least one of the following: periodic automatic sending, autonomous detection, and system patrol. This proactive control signal sending method can improve the intelligence and autonomous management capabilities of the server motherboard, enabling the system to operate more stably and efficiently.

[0066] The following details how the gating unit communicates based on control signals sent by the Host-BMC. The method includes:

[0067] When the control signal indicates that the first channel is connected, the gating unit controls the first channel to be connected; the first channel is the transmission channel between Host-BMC, gating unit, and Host-CPU.

[0068] Alternatively, when the control signal indicates that the second channel is connected, the gating unit controls the second channel to be connected; the second channel is the transmission channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card.

[0069] In this disclosure, the gating unit can precisely control the connectivity status of different channels based on control signals sent by the Host-BMC. When the control signal indicates that the first channel is connected, the gating unit immediately adjusts its internal connection status, ensuring smooth connectivity of the first channel—the transmission channel between the Host-BMC, the gating unit, and the Host-CPU. The first channel can be understood as the channel for transmitting CPU serial port signals. This ensures that when Host-CPU serial port signals need to be transmitted, the signals can be transmitted quickly and accurately on this channel.

[0070] When the control signal indicates that the second channel is connected, the gating unit can also respond quickly and control the connection of the second channel. The second channel is the transmission channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card. Specifically, the second channel can be understood as the transmission channel of the DPU card; its connection enables the effective transmission of the DPU card's serial port signals under certain conditions.

[0071] This design, which flexibly switches between different channel connection states based on control signals, provides high manageability and adaptability for the serial port signal transmission of the server motherboard, and can meet the transmission requirements of different serial port signals in different application scenarios.

[0072] This disclosure also provides a DPU card, including:

[0073] The DPU processor, connected to the gating unit on the server motherboard, is used to transmit DPU card serial port signals to the gating unit.

[0074] In this disclosure, the gating unit can be directly connected to the DPU processor of the DPU card, realizing the connection between the server motherboard and the DPU card. For example, as described above... Figure 2 This shows that the DPU processor of the DPU card is connected to the strobe unit of the server motherboard.

[0075] The DPU card disclosed herein also includes: a second connector that connects to the first connector via a cable, the first connector being disposed in the server motherboard.

[0076] In this disclosure, the specific connection between the server motherboard and the DPU card can be achieved by connecting the corresponding connectors on both sides using cables, as detailed above.

[0077] This disclosure also provides a communication system, including:

[0078] The server motherboard can be used to implement a server motherboard as described in any of the above embodiments;

[0079] The DPU card can be used to implement the DPU card as described in any of the above embodiments.

[0080] Figure 3 This is a hardware block diagram of an electronic device provided according to an embodiment of the present disclosure. The electronic device 300 according to an embodiment of the present disclosure includes at least a processor; and a memory for storing computer-readable instructions. When the computer-readable instructions are loaded and executed by the processor, the processor performs the communication method described in any of the preceding embodiments of the present disclosure.

[0081] Figure 3 The illustrated electronic device 300 specifically includes a central processing unit (CPU) 301, a graphics processing unit (GPU) 302, and a memory 303. These units are interconnected via a bus 304. The CPU 301 and / or GPU 302 can function as the aforementioned processor, and the memory 303 can function as the aforementioned memory storing computer-readable instructions. Furthermore, the electronic device 300 may also include a communication unit 305, a storage unit 306, an output unit 307, an input unit 308, and an external device 309, all of which are also connected to the bus 304.

[0082] Figure 4 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure. (As shown...) Figure 4As shown, a computer-readable storage medium 400 according to an embodiment of the present disclosure stores computer-readable instructions 401 thereon. When the computer-readable instructions 401 are executed by a processor, the communication method described above with reference to any embodiment of the present disclosure is performed. The computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0083] This disclosure further provides a computer program product, including a computer program that, when executed by a processor, implements the communication method described in any of the preceding embodiments of this disclosure.

[0084] The present disclosure provides a server motherboard, a communication method and system, a DPU card, a device, a medium, and a product. The server motherboard of this disclosure includes: a Host Baseboard Management Controller (Host-BMC) for communicating with external devices and managing the gating unit to transmit serial port signals; a Host Central Processing Unit (Host-CPU) connected to the gating unit for transmitting Host-CPU serial port signals to the gating unit; and a gating unit connected to the DPU card, Host-BMC, and Host-CPU for receiving a first serial port signal and transmitting the first serial port signal to it based on the management of the Host-BMC; the first serial port signal is either a Host-CPU serial port signal or a DPU card serial port signal. In summary, the technical solution provided by this disclosure can centrally manage and control the gating unit to transmit different serial port signals through the Host-BMC of the server motherboard. Compared to existing methods that acquire signals independently, this disclosure can utilize the unified gating logic and channel selection mechanism of the server motherboard to select different serial port signals. This significantly reduces the risk of DPU card information exposure, while simplifying management and interaction complexity, reducing resource consumption, and meeting actual objective needs.

[0085] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0086] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0087] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0088] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0089] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0090] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0091] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0092] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A server motherboard, characterized in that, include: The motherboard baseboard management controller (Host-BMC) is used to communicate with external devices and manage the gating unit to transmit serial port signals. The motherboard central processing unit (Host-CPU) is connected to the gating unit and is used to transmit the Host-CPU serial port signal to the gating unit. The gating unit is connected to the DPU card, the Host-BMC, and the Host-CPU; it is used to receive a first serial port signal and transmit the first serial port signal to the Host-BMC based on the management of the Host-BMC; the first serial port signal is either a Host-CPU serial port signal or a DPU card serial port signal.

2. The server motherboard according to claim 1, characterized in that, The Host-BMC communicates with the external device via an out-of-band management network port. The external device includes a hardware management platform.

3. The server motherboard according to claim 1, characterized in that, The Host-BMC manages the gating unit through control signals; The control signal is used to indicate the connection of the transmission channels of each first serial port signal.

4. The server motherboard according to claim 1, characterized in that, The server motherboard also includes: The first connector is connected to the second connector via a cable; the second connector is located in the DPU card.

5. The server motherboard according to any one of claims 1-4, characterized in that, When an external device requests a Host-CPU serial port signal, the first serial port signal is the Host-CPU serial port signal, and the first channel between the Host-BMC, the gating unit, and the Host-CPU is connected; Alternatively, when an external device requests a DPU card serial port signal, the first serial port signal is the DPU card serial port signal, and the second channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card is connected.

6. The server motherboard according to any one of claims 1-5, characterized in that, The server motherboard also includes: The host-CPLD is a complex programmable device on the motherboard, and the gating unit is disposed in the host-CPLD.

7. A communication method, applied to a server motherboard as described in any one of claims 1-6; characterized in that, The method includes: The Host-BMC sends a control signal to the gating unit; The gating unit controls the connection between the Host-BMC and the first serial port signal transmission channel based on the control signal; the first serial port signal includes at least one of the following: the Host-CPU serial port signal and the DPU card serial port signal; The Host-BMC sends the first serial port signal.

8. The method according to claim 7, characterized in that, Before the Host-BMC sends a control signal to the gating unit, the method further includes: Based on the first information sent by the external device, the Host-BMC sends the control signal to the gating unit; the control signal is used to indicate the connection of the transmission channels of each first serial port signal.

9. The method according to claim 7, characterized in that, The gating unit controls the connection between the Host-BMC and the first serial port signal transmission channel based on the control signal, including: When the control signal indicates that the first channel is connected, the gating unit controls the first channel to be connected; the first channel is the transmission channel between the Host-BMC, the gating unit, and the Host-CPU; Alternatively, when the control signal indicates that the second channel is connected, the gating unit controls the second channel to be connected; the second channel is the transmission channel between the Host-BMC, the gating unit, the first connector, the second connector, and the DPU card.

10. A DPU card, characterized in that, include: The DPU processor, connected to the gating unit on the server motherboard, is used to transmit DPU card serial port signals to the gating unit.

11. The DPU card according to claim 10, characterized in that, Also includes: The second connector connects to the first connector via a cable, and the first connector is located in the server motherboard.

12. The DPU card according to claim 10, characterized in that, The DPU card serial port signal includes at least one of the following: a universal asynchronous transceiver (UART) transmit signal and a universal asynchronous transceiver (UART) receive signal.

13. A communication system, characterized in that, include: Server motherboard, including the apparatus as claimed in any one of claims 1-6; DPU card, including the apparatus as claimed in any one of claims 10-12.

14. An electronic device, characterized in that, include: Memory, used to store computer-readable instructions; as well as A processor for executing the computer-readable instructions, causing the electronic device to perform the method as described in any one of claims 7-9.

15. A non-transitory computer-readable storage medium for storing computer-readable instructions, characterized in that, When the computer-readable instructions are executed by a processor, the processor performs the method as described in any one of claims 7-9.

16. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method as described in any one of claims 7-9.

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