Memory device and data access method thereof
By applying a read voltage during the partially overlapping time interval between memory cell blocks, the problem of excessively long read voltage waiting time in the prior art is solved, and efficient data reading of the memory device is achieved.
Patent Information
- Application Number
- CN202410809676.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-13
- Filing Date
- 2024-06-21
- Publication Date
- 2025-12-16
AI Technical Summary
In continuous data reading operations across multiple memory cell blocks, existing technologies require repeated application of read voltage and pass voltage, resulting in excessively long waiting times and reduced operating efficiency of the memory device.
By applying a read voltage to the first storage cell block and reading data during the first time interval, and applying a read voltage to the second storage cell block during the second time interval, and reading data when the two time intervals partially overlap, the repeated waiting for the read voltage and the waiting through the voltage stabilization state are avoided.
This effectively reduces the waiting time for reading voltage and through voltage stabilization, thus improving the data reading efficiency of the storage unit.
Smart Images
Figure CN121148451A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a memory device and a data access method thereof, and particularly relates to a memory device capable of improving data read rate and a data access method thereof. BACKGROUND
[0002] In a non-NAND flash memory device, in the prior art, when a data read operation is performed on a memory cell block, a read voltage is applied to a read-selected word line in the memory cell block, and a pass voltage is applied to a non-selected word line in the memory cell block. After the read voltage and the pass voltage are stable, the stored data in the selected memory cell is read out by turning on the memory cell string. When the next data read operation is performed, the read voltage and the pass voltage need to be applied to the word line in the memory cell block to be read, and the stored data in the selected memory cell can be read out only after the read voltage and the pass voltage rise to the stable voltage value. That is, in the continuous data read operation of multiple memory cell blocks, a large amount of waiting time is consumed due to the repeated waiting operation of the stable state of the read voltage and the pass voltage, and the working efficiency of the memory device is reduced. SUMMARY
[0003] The present disclosure provides a memory device and a data access method thereof, which can improve the data read rate.
[0004] The data access method of the memory device of the present disclosure includes: applying a read voltage to a first read-selected word line of a first memory cell block in a first time interval; turning on at least one first memory cell string in the first memory cell block in a first data readout time interval in the first time interval; applying the read voltage to a second read-selected word line of a second memory cell block in a second time interval, wherein the first time interval and the second time interval partially overlap; and turning on at least one second memory cell string in the second memory cell block in a second data readout time interval in the second time interval, wherein the first data readout time interval and the second data readout time interval do not overlap with each other.
[0005] Another data access method of the memory device of the present disclosure includes: distinguishing a plurality of memory cell blocks corresponding to a plurality of word lines of a memory device; setting a first memory cell block and a second memory cell block in the memory cell blocks according to a reading order; performing a default operation on the word lines of the second memory cell block when at least one first memory cell string in the first memory cell block is turned on to perform a read operation; and turning on at least one second memory cell string in the second memory cell block after the read operation of the at least one first memory cell string in the first memory cell block is completed.
[0006] The memory device of the present disclosure comprises a plurality of memory cell blocks and a controller. The controller is coupled to the memory cell blocks and is configured to perform the data access method as described above.
[0007] Based on the above, the memory device and the data access method thereof can perform the default operation on the word line of the next memory cell block to be accessed, and continuously perform the data read operation on different memory cell blocks in the first time interval and the second time interval that partially overlap with each other. In this way, the first data read time interval and the second data read time interval corresponding to different memory cell blocks can be connected to be generated, effectively improving the data read efficiency of the memory cell. BRIEF DESCRIPTION OF DRAWINGS
[0008] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:
[0009] Figure 1 A flowchart of a data access method of a memory device according to an embodiment of the present disclosure is schematically shown;
[0010] Figure 2 A schematic diagram of a memory device according to an embodiment of the present disclosure is schematically shown;
[0011] Figure 3 An operation waveform diagram of a memory device according to an embodiment of the present disclosure is schematically shown;
[0012] REFERENCE SIGNS
[0013] 200: memory device
[0014] 210: controller
[0015] 221-22M: page buffer
[0016] B1-B3: memory cell block
[0017] BL0-BLM: bit line
[0018] GND: reference ground terminal
[0019] GS1: ground selection switch
[0020] GSL1-GSL3, SSL1-SSL3: control signal
[0021] MC: memory cell
[0022] MS1: memory cell string
[0023] S110-S140: step
[0024] SS1: storage unit string selection switch
[0025] TP1~TP3, tR1~tR3: time interval
[0026] Vpass: pass voltage
[0027] Vread: read voltage
[0028] WL10~WL3N: word line DETAILED DESCRIPTION
[0029] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to specific embodiments and drawings.
[0030] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present disclosure. The terms "include", "comprise" and the like used herein indicate the presence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.
[0031] Reference will now be made to the drawings, and specific embodiments will be described in detail in the following. Figure 1 , Figure 1 A flowchart of a data access method of a memory device according to an embodiment of the present disclosure is shown. In this embodiment, the memory device includes a plurality of memory cell blocks, each of which has one or more memory cell strings. A plurality of memory cells on each memory cell string can be respectively coupled to a plurality of word lines. In this embodiment, the memory device can be a NAND flash memory device.
[0032] In the flow of the data access method of this embodiment, in step S110, the controller of the memory device can apply a read voltage to a first read-selected word line of a first memory cell block in a plurality of memory cell blocks in a first time interval. Then, in step S120, the controller can turn on at least a first memory cell string in the first memory cell block in a first data readout time interval in the first time interval. Thus, the data stored in the memory cells corresponding to the first read-selected word line in the one or more first memory cell strings turned on in the first memory cell block can be read out in the first data readout time interval.
[0033] In addition, in step S130, the controller of the memory device can apply a read voltage to a second read-selected word line of a second memory cell block in the plurality of memory cell blocks in a second time interval. The second time interval can be different from the first time interval described above, and in detail, the second time interval can partially overlap with the first time interval described above, but not completely overlap.
[0034] Next, in step S140, the controller can turn on at least one second memory cell string in the second memory cell block in a second data readout time interval in the second time interval. By this, the data stored in the memory cells corresponding to the second read-selected word line in the turned-on one or more second memory cell strings in the first memory cell block can be read out in the second data readout time interval.
[0035] Notably, in the present embodiment, the first data readout time interval and the second data readout time interval do not overlap each other at all. The read-out data of the memory cells corresponding to the first read-selected word line in the first data readout time interval can be transferred out through the corresponding bit line. And the read-out data of the memory cells corresponding to the second read-selected word line in the first data readout time interval can also be transferred out through the corresponding bit line. In the present embodiment, the memory cells corresponding to the first read-selected word line and the memory cells corresponding to the second read-selected word line can correspond to the same bit line.
[0036] In the present embodiment, the controller of the memory device, when the data read operation of the first memory cell block has not been completed in the first time interval, can apply the read voltage to the second read-selected word line of the second memory cell block in advance in the time interval in which the second time interval overlaps with the first time interval. In this way, when the data read operation of the memory cells of the first memory cell block performed in the first data readout time interval in the first time interval is completed, the controller of the memory device can perform the data read operation of the memory cells of the second memory cell block in the second data readout time interval immediately after the first data readout time interval. In this way, the read efficiency of the stored data of the memory cells among the plurality of memory blocks can be effectively improved.
[0037] Please refer to Figure 2 , Figure 2 A schematic diagram of a memory device of an embodiment of the present disclosure is shown. The memory device 200 includes a plurality of memory cell blocks B1-B3 and a controller 210. The controller 210 is coupled to the memory cell blocks B1-B3. In the present embodiment, each memory cell block B1-B3 includes a plurality of memory cell strings (e.g., memory cell string MS1). The memory cell strings in each memory cell block B1-B3 are respectively coupled to a plurality of bit lines BL0-BLM. The bit lines BL0-BLM are respectively coupled to a plurality of page buffers (PB) 221-22M.
[0038] The plurality of memory cells in the memory cell block B1 are coupled to the word lines WL10~WL1N; the plurality of memory cells in the memory cell block B2 are coupled to the word lines WL20~WL2N; and the plurality of memory cells in the memory cell block B3 are coupled to the word lines WL30~WL3N. The plurality of memory cell strings in the memory cell blocks B1, B2, B3 correspond to each other respectively and are coupled to the bit lines BL0~BLM respectively. That is, the three memory cell strings corresponding to each other in position in the memory cell blocks B1, B2, B3 can be coupled to the same shared bit line.
[0039] As to the implementation details of the memory cell string MS1, the memory cell string MS1 has a plurality of memory cells MC connected in series with each other and a memory cell string selection switch SS1 and a ground selection switch GS1 coupled at both ends of the memory cell string MS1. The control terminals of the memory cells MC are coupled to the plurality of word lines WL10~WL1N respectively, the ground selection switch GS1 is coupled between the plurality of memory cells MC and the reference ground terminal GND, and the memory cell string selection switch SS1 is coupled between the memory cells MC and the corresponding bit line BL0. The ground selection switch GS1 is controlled by the control signal GSL1, and the memory cell string selection switch SS1 is controlled by the control signal SSL1.
[0040] In the embodiment, the controller 210 can be a processor with computing capability, or the controller 210 can be any form of digital circuit, or be designed by a hardware description language (HDL) or any other design method known to those skilled in the art, and be implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or a special application integrated circuit (ASIC).
[0041] As to the details of the data reading action of the memory device 200, reference can be made to Figure 2 and Figure 3 wherein Figure 3 The action waveform diagram of the memory device of the embodiment of the present disclosure is shown. In Figure 3In the embodiment, the controller 210 of the memory device 200 can first perform a data read operation on the memory cell block Bl. In the first time interval TP1, the controller 210 can apply a read voltage Vread to the read-selected word line selected for the data read operation in the memory cell block Bl, and apply a pass voltage Vpass to the unselected word lines other than the read-selected word line.
[0042] Next, in the first time interval TP1, when the read voltage Vread and the pass voltage Vpass have risen to the steady voltage values, the controller 210 can apply control signals SSL1 and GSL1 to the ground selection switches and the memory cell string selection switches in the memory cell strings in the memory cell block Bl, respectively, in the first read time interval tR1. The control signals SSL1 and GSL1 have relatively high voltage values, and thus the ground selection switches and the memory cell string selection switches in the memory cell strings in the memory cell block Bl are turned on, and the memory cell strings in the memory cell block Bl are opened.
[0043] In the embodiment, the pass voltage Vpass can be greater than the read voltage Vread. When the memory cell strings in the memory cell block Bl are opened, the memory cells (unselected memory cells) in the memory cell block Bl receiving the pass voltage Vpass are fully turned on without affecting the current on the corresponding bit lines. The memory cells (selected memory cells) receiving the read voltage Vread can generate the current on the bit lines according to the stored data. Thus, the memory device 200 can determine the stored data in the selected memory cells in the memory cell strings in the memory cell block Bl by sensing the current on the bit lines BL0- BLM.
[0044] It is worth mentioning that, in the embodiment, the second time interval TP2 partially overlaps with the first time interval TP1, and the second time interval TP2 can also partially overlap with the first read time interval tR1 in the first time interval TP1. That is, while the data read operation on the memory cell block Bl is being performed, the controller can apply the read voltage Vread to the read-selected word line selected for the data read operation in the memory cell block B2, and apply the pass voltage Vpass to the unselected word lines other than the read-selected word line in the second time interval TP2.
[0045] From Figure 3It can be known that the read voltage Vread and the pass voltage Vpass corresponding to the second memory cell block can be applied to the corresponding word lines in the memory cell block B2 in advance while the data read operation of the memory cell block B1 is performed, so as to perform the default operation for the word lines of the memory cell block B1. And before the first read time interval tR1 is completed, the read voltage Vread and the pass voltage Vpass on each word line in the memory cell block B2 can reach a steady state. In this way, after the first read time interval tR1 is completed, the controller 210 can make the ground selection switch and the memory cell string selection switch in the memory cell string in the memory cell block B2 be turned on by providing the control signals SSL2 and GSL2 with relatively high voltage values in the second read time interval tR2, and perform the data read operation of the memory cells in the memory cell block B2.
[0046] In the embodiment, the second read time interval tR2 can occur after the first read time interval tR1. The second read time interval tR2 can be adjacent to the first read time interval tR1.
[0047] It is worth noting that in the embodiments of the present disclosure, the controller 210 of the memory device 200 can continue to perform the data read operation of the memory cells in the memory cell block B3 after the data read operation of the memory cells in the memory cell block B2. Wherein, the controller 210 can provide the read voltage Vread and the pass voltage Vpass to each word line of the memory cell block B3 in advance in the third time interval TP3 partially overlapping with the second time interval TP2 and the second read time interval tR2. And in the third read time interval tR3 after the second read time interval tR2, the control signals SSL3 and GSL3 with relatively high voltage values are provided to make the ground selection switch and the memory cell string selection switch in the memory cell string in the memory cell block B3 be turned on, and perform the data read operation of the memory cells in the memory cell block B3.
[0048] From the above embodiments, it can be known that the memory device 200 of the embodiments of the present disclosure can quickly switch between different memory cell blocks B1-B3 to perform data read operations. And by providing the read voltage Vread and the pass voltage Vpass to the next memory cell block to be performed data read operation in advance before the data read operation of the previous block is completed, the waiting time for the read voltage Vread and the pass voltage Vpass to rise to a steady state can be effectively reduced, and the data read rate of the memory device 200 can be improved.
[0049] In Figure 3In the embodiment of the present disclosure, after the data read operation of the memory cell block B3, the controller 210 can successively perform the data read operation of the memory cell blocks B1, B2 or other memory cell blocks not shown. In the embodiment of the present disclosure, the controller 210 can successively perform the data read operation of any two different memory cell blocks, Figure 3 The embodiment of sequentially performing the data read operation of the memory cell blocks B1 to B3 is only an illustrative example and is not used to limit the scope of the present disclosure.
[0050] It is worth noting that the data read operation of the embodiment of the present disclosure can also be applied to other types of memory devices and is not limited to be applied to the NAND flash memory device.
[0051] In addition, in other embodiments of the present disclosure, a piece of demand data can be split into multiple data pages and sequentially stored in different memory cell blocks according to a set order. In this way, when the data read operation is performed on the demand data, the embodiment of the present disclosure can be applied to sequentially perform the fast data read operation on each memory cell block according to the storage order of the multiple data pages. In this way, the demand data can be quickly read out to improve the work efficiency of the system. Figure 3
[0052] In summary, the memory device and the data access method thereof of the present disclosure can apply the corresponding read voltage and pass voltage to the word line of the next memory cell block to be subjected to the data read operation when the data read operation of the current memory cell block is performed. In this way, the waiting time for the stabilization time of the read voltage and the pass voltage on the word line can be saved in the data read operation of the continuous memory cell blocks, and the data read efficiency of the memory cell is effectively improved.
[0053] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above-described specific embodiments are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A method for data access of a memory device, comprising: applying a read voltage to a first read-selected word line of a first memory cell block in a first time interval; turning on at least a first memory cell string in the first memory cell block in a first data sensing time interval in the first time interval; applying the read voltage to a second read-selected word line of a second memory cell block in a second time interval, wherein the first time interval partially overlaps with the second time interval; and turning on at least a second memory cell string in the second memory cell block in a second data sensing time interval in the second time interval, wherein the first data sensing time interval and the second data sensing time interval do not overlap with each other.
2. The method for data access of claim 1, wherein the first data sensing time interval is immediately adjacent to the second data sensing time interval.
3. The method for data access of claim 1, further comprising: applying a pass voltage to a plurality of first unselected word lines of the first memory cell block in the first time interval; and applying the pass voltage to a plurality of second unselected word lines of the second memory cell block in the second time interval.
4. The method for data access of claim 3, wherein the pass voltage is greater than the read voltage.
5. The method for data access of claim 1, wherein the step of turning on the at least the first memory cell string in the first memory cell block comprises: pulling up a first control signal and a second control signal in the first data sensing time interval to turn on a ground select switch and a memory cell string select switch of the at least the first memory cell string, respectively.
6. The method for data access of claim 1, wherein the step of turning on the at least the second memory cell string in the second memory cell block comprises: pulling up a first control signal and a second control signal in the second data sensing time interval to turn on a ground select switch and a memory cell string select switch of the at least the second memory cell string, respectively.
7. The method for data access of claim 1, further comprising: applying the read voltage to a third read-selected word line of a third memory cell block in a third time interval, wherein the second time interval partially overlaps with the third time interval; and turning on at least a third memory cell string in the third memory cell block in a third data sensing time interval in the third time interval, wherein the first data sensing time interval, the second data sensing time interval, and the third data sensing time interval do not overlap with each other.
8. A memory device, comprising: a plurality of memory cell blocks; and a controller coupled to the memory cell blocks, configured to: apply a read voltage to a first read-selected word line of a first memory cell block in a first time interval; turn on at least a first memory cell string in the first memory cell block in a first data sensing time interval in the first time interval; applying the read voltage to a second read-selected word line of a second memory cell block in a second time interval, wherein the first time interval partially overlaps with the second time interval; and turning on at least a second memory cell string in the second memory cell block in a second data readout time interval in the second time interval, wherein the first data readout time interval and the second data readout time interval do not overlap with each other.
9. The memory device of claim 8, wherein the first data readout time interval is immediately adjacent to the second data readout time interval.
10. The memory device of claim 8, wherein the controller is further configured to: apply a pass voltage to a plurality of first unselected word lines of the first memory cell block in the first time interval; and apply the pass voltage to a plurality of second unselected word lines of the second memory cell block in the second time interval.
11. The memory device of claim 10, wherein the pass voltage is greater than the read voltage.
12. The memory device of claim 8, wherein the at least a first memory cell string comprises a ground select switch and a memory cell string select switch, the controller is further configured to: pull up a first control signal and a second control signal to turn on the ground select switch and the memory cell string select switch of the at least a first memory cell string, respectively, in the first data readout time interval.
13. The memory device of claim 8, wherein the at least a second memory cell string comprises a ground select switch and a memory cell string select switch, the controller is further configured to: pull up a first control signal and a second control signal to turn on the ground select switch and the memory cell string select switch of the at least a second memory cell string, respectively, in the second data readout time interval.
14. The memory device of claim 8, wherein the controller is further configured to: apply the read voltage to a third read-selected word line of a third memory cell block in a third time interval, wherein the second time interval partially overlaps with the third time interval; and turn on at least a third memory cell string in the third memory cell block in a third data readout time interval in the third time interval, wherein the first readout time interval, the second data readout time interval, and the third data readout time interval do not overlap with each other.
15. The memory device of claim 8, wherein the at least a first memory cell string and the at least a second memory cell string are coupled to at least a first bit line and at least a second bit line, respectively.
16. The memory device of claim 8, wherein the at least a first memory cell string and the corresponding at least a second memory cell string share a same shared bit line.
17. The memory device of claim 16, further comprising: at least one page buffer coupled to the shared bit line.
18. A data access method of a memory device, comprising: distinguishing a plurality of memory cell blocks from a plurality of word lines of the memory device; According to a reading order to set a first memory cell block and a second memory cell block among the memory cell blocks; performing a default operation on word lines of the second memory cell block when at least one first memory cell string in the first memory cell block is turned on for a read operation; and after the read operation of the at least one first memory cell string in the first memory cell block is completed, turning on at least one second memory cell string in the second memory cell block.
19. The data access method of claim 18, further comprising: splitting the demand data into a plurality of data pages; and storing the data pages into the memory cell blocks in the memory device in sequence.
20. The data access method of claim 18, wherein performing a default operation on word lines of the second memory cell block comprises: applying a read voltage to a read selected word line in the second memory cell block; and applying a pass voltage to unselected word lines in the second memory cell block.