Chip damage detection structure and detection method
By introducing a sequence generator and receiver into the chip's functional area and using detection connection lines for signal sequence matching detection, the problem of chip edge damage detection under advanced packaging is solved, achieving efficient and simplified damage detection and improving chip reliability.
Patent Information
- Application Number
- CN202511162981.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-19
- Publication Date
- 2025-12-16
AI Technical Summary
Existing technologies lack efficient chip edge damage detection methods under advanced packaging methods, which affects chip reliability and requires the introduction of external equipment and PADs for detection, leading to increased complexity.
A sequence generator and a sequence receiver are introduced into the chip's functional area. The signal sequence is output from the sequence generator to the receiver through a detection connection line. Damage detection is performed using the chip's own structure without the need for additional PADs or external devices. The detection connection line can be set around or partially around the chip's functional area. Damage is determined by the matching of the detection signal sequence.
It enables efficient detection of chip edge damage without external equipment under advanced packaging conditions, simplifies the detection process, reduces design complexity and power consumption, and improves detection accuracy.
Smart Images
Figure CN121149129A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip design technology, and in particular to a chip damage detection structure and detection method. Background Technology
[0002] As chip sizes continue to shrink, the demand for advanced packaging methods is also growing stronger. Advanced packaging methods, such as wafer-level chip-scale packaging (WLCSP), are advanced packaging forms that complete packaging manufacturing before the silicon wafer is completely intact and individual chips have been cut. With its high integration, low power consumption and miniaturization, it is widely used in high-performance computing, mobile communications and other fields.
[0003] However, the semiconductor manufacturing process generates stress that can be detrimental to the chip, potentially causing cracks and affecting its normal function. After wafer packaging and testing, the chip undergoes dicing. Due to the internal stress of the wafer, dicing can also lead to severe cracking damage, which has a high probability of causing chip failure. As chip manufacturing processes continue to advance, the requirements for chip edge integrity are becoming increasingly stringent, necessitating more precise and reliable testing methods to improve chip yield.
[0004] Currently, some methods exist for edge detection of chips, such as measuring resistance. However, these methods generally require additional external inputs or external testing instruments. The introduction of additional testing equipment and procedures increases complexity. Furthermore, existing detection methods require leading out PADs from the edge detection structure and connecting them to external testing instruments, necessitating the addition of input and output PADs to the chip. These additional PADs are not needed for normal chip functionality and are therefore not designed for detection during packaging. Consequently, the chip cannot be tested using existing detection schemes after packaging, and this advanced packaging method cannot achieve post-diced chip inspection. Therefore, it is clear that current technologies lack efficient methods for inspecting diced chips, impacting chip reliability.
[0005] Therefore, providing an efficient chip damage detection structure and method that can effectively detect chip edge damage under advanced packaging conditions is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0006] To address the aforementioned technical problems, this disclosure provides a chip damage detection structure and method to solve the problem of the lack of efficient detection methods for diced chips in the prior art, which affects chip reliability.
[0007] This disclosure provides a chip damage detection structure, including a chip body and a detection structure. The chip body includes a chip functional area and a sealing ring. The sealing ring is disposed around the chip functional area and is located between the chip functional area and the chip edge.
[0008] The detection structure includes a sequence generator, a sequence receiver, and a detection connection line. The output terminal of the sequence generator is electrically connected to one end of the detection connection line, and the other end of the detection connection line is electrically connected to the input terminal of the sequence receiver.
[0009] Both the sequence generator and the sequence receiver are located in the chip functional area, and the detection connection line is located on the side of the chip functional area facing the chip edge. The detection connection line is at least partially arranged around the chip functional area.
[0010] Optionally, the detection connection line is arranged in a partially enclosed shape around the periphery of the chip's functional area.
[0011] Optionally, the test connection wires may reuse at least part of the sealing ring;
[0012] The sealing ring comprises multiple metal layers, and the detection connection line is disposed on at least one metal layer.
[0013] Further optionally, the sealing ring comprises N electrically insulating metal layers, each metal layer comprising a detection connection line; wherein N is a positive integer greater than or equal to 2;
[0014] The chip's functional area includes N sequence generators and N sequence receivers, with one detection connection line corresponding to one sequence generator and one sequence receiver.
[0015] Further optionally, the sealing ring comprises N electrically insulating metal layers, each metal layer comprising a detection connection line; wherein N is a positive integer greater than or equal to 2;
[0016] The chip's functional area includes a sequence generator and a sequence receiver;
[0017] The detection structure also includes a first gating switch and a second gating switch;
[0018] The input terminal of the first gating switch is electrically connected to the output terminal of the sequence generator. The first gating switch includes N first gating output terminals, and each of the N first gating output terminals is electrically connected to one end of N detection connection lines.
[0019] The output of the second gating switch is electrically connected to the input of the sequence receiver. The second gating switch includes N second gating inputs, and each of the N second gating inputs is electrically connected to the other end of one of the N detection connection lines.
[0020] Further optionally, the sealing ring includes at least a first metal layer, a second metal layer and a third metal layer, and the detection connection line includes at least a first segment, a second segment and a third segment, wherein the first segment is located in the first metal layer, the second segment is located in the second metal layer and the third segment is located in the third metal layer;
[0021] The first sub-segment is electrically connected to the second sub-segment through the first via, and the second sub-segment is electrically connected to the third sub-segment through the second via.
[0022] Optionally, the detection connection line is located between the sealing ring and the chip functional area.
[0023] Alternatively, the detection connection may include a metal ring arranged around the functional area of the chip.
[0024] Based on the same inventive concept, this disclosure also provides a chip damage detection method, including:
[0025] Turn on the sequence generator and sequence receiver located in the chip's functional area;
[0026] The sequence generator generates an initial signal sequence;
[0027] The initial signal sequence generated by the sequence generator is transmitted to the detection connection line via the output of the sequence generator; wherein the detection connection line is arranged at least partially around the functional area of the chip;
[0028] The sequence receiver receives the detection signal sequence after it has passed through the detection connection line;
[0029] Compare the detection signal sequence with the initial signal sequence;
[0030] If the detected signal sequence matches the initial signal sequence, the detection result is that the chip edge is undamaged.
[0031] If the detected signal sequence does not match the initial signal sequence, the detection result is chip edge damage.
[0032] Optionally, the initial signal sequence generated by the sequence generator is a logic signal sequence.
[0033] The technical solution provided in this disclosure has the following advantages compared with the prior art:
[0034] The chip damage detection structure disclosed herein introduces a sequence generator and a sequence receiver in the chip's functional area. The output of the sequence generator is electrically connected to one end of a detection connection line disposed on the inner side of the chip edge, and the other end of the detection connection line is electrically connected to the input of the sequence receiver. During damage detection, the output of the sequence generator outputs a specific signal sequence, which reaches the sequence receiver via the detection connection line. If chip edge damage causes damage to the detection connection line, the timing signal received by the sequence receiver will not match the standard signal sequence emitted by the sequence generator, indicating that there is damage at the chip edge. Conversely, if the timing signal received by the sequence receiver matches the standard signal sequence emitted by the sequence generator, it indicates that the chip edge is not damaged, thus completing the chip edge damage detection. The chip damage detection structure disclosed herein, compared to existing schemes that require separate PADs to be led out from the edge detection structure and connected to external testing equipment for detection, eliminates the need for external testing equipment and additional PADs on the chip for transmitting detection signals. This allows for effective detection of chip edge damage even under advanced packaging conditions, and the detection remains unaffected even after chip packaging and the absence of additional detection PADs. The chip damage detection structure primarily relies on the chip's integrated sequence generator to output a detection signal sequence and a sequence receiver to receive the detection signal sequence. Detection can be achieved without additional input / output ports or external testing equipment. This simplifies the process and, by transforming chip edge damage detection into the detection of changes in chip logic timing and function, facilitates efficient chip edge damage detection. The sequence generator and sequence receiver in the chip damage detection structure can be controlled to be turned on or off, enabling activation during detection and deactivation after detection, thus reducing chip power consumption. Attached Figure Description
[0035] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a schematic diagram of a chip damage detection structure provided in an embodiment of this disclosure;
[0038] Figure 2This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure;
[0039] Figure 3 This is a schematic diagram of an equivalent circuit structure used in the chip damage detection structure of this disclosure embodiment;
[0040] Figure 4 yes Figure 3 A schematic diagram illustrating an example of a signal sequence generated by a sequence generator and a signal sequence received by a sequence receiver;
[0041] Figure 5 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure;
[0042] Figure 6 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure;
[0043] Figure 7 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure;
[0044] Figure 8 yes Figure 5 A schematic diagram showing the relationship between the multiple metal layers of the central sealing ring and the detection structure;
[0045] Figure 9 yes Figure 5 Another schematic diagram showing the relationship between the multiple metal layers of the central sealing ring and the detection structure;
[0046] Figure 10 This is a schematic diagram of the electrical connections of the detection structure;
[0047] Figure 11 yes Figure 5 Another schematic diagram showing the relationship between the multiple metal layers of the central sealing ring and the detection structure;
[0048] Figure 12 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure;
[0049] Figure 13 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure;
[0050] Figure 14 This is a schematic flowchart of a chip damage detection method provided in an embodiment of this disclosure. Detailed Implementation
[0051] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0052] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0053] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a chip damage detection structure provided in an embodiment of the present disclosure. The chip damage detection structure provided in this embodiment includes a chip body 10 and a detection structure 20. The chip body 10 includes a chip functional area 10A and a sealing ring 10B. The sealing ring 10B is disposed around the chip functional area 10A and is located between the chip functional area 10A and the chip edge 10L.
[0054] The detection structure 20 includes a sequence generator 20A, a sequence receiver 20B, and a detection connection line 20C. The output terminal of the sequence generator 20A is electrically connected to one end of the detection connection line 20C, and the other end of the detection connection line 20C is electrically connected to the input terminal of the sequence receiver 20B.
[0055] The sequence generator 20A and the sequence receiver 20B are both located in the chip functional area 10A. The detection connection line 20C is located on the side of the chip functional area 10A facing the chip edge 10L. The detection connection line 20C is arranged at least partially around the chip functional area 10A.
[0056] Specifically, the chip damage detection structure provided in this embodiment can be used to detect edge damage of chips after wafer-level packaging and testing and after dicing. The chip damage detection structure of this embodiment includes a chip body 10 and a detection structure 20. The chip body 10 can be understood as the chip structure after packaging and dicing. The detection structure 20 is used to detect whether the edges of the chip body 10 are damaged. Specifically, the detection structure 20 can be integrated inside the chip body 10. The chip body 10 includes a chip functional area 10A and a sealing ring 10B. The sealing ring 10B surrounds the chip functional area 10A and is located between the chip functional area 10A and the chip edge 10L. The chip edge 10L can be understood as the dicing edge of the chip body 10, and the chip functional area 10A can be understood as the area where the actual circuitry is located within the chip body 10. The sealing ring 10B, also known as the seal ring, is a special structure located at the edge of a chip in integrated circuit manufacturing. It primarily surrounds the effective circuit area (i.e., the chip functional area 10A) of the chip body 10. The sealing ring 10B not only provides physical protection for the chip structure but also offers electrical isolation, prevents crack propagation, and protects against environmental pollution. From a process perspective, the sealing ring 10B is a structure consisting of a metal layer, an oxide layer, and a passivation layer, acting like a dam to protect the chip functional area 10A of the chip body 10. From a wafer perspective, the sealing ring 10B is a protective ring located between the functional area 10A of the chip body 10 and the chip edge 10L, i.e., the scribe line. It is understood that no circuit devices or other structures are typically placed between the chip functional area 10A and the sealing ring 10B of the chip body 10.
[0057] The detection structure 20 of this embodiment includes a sequence generator 20A, a sequence receiver 20B, and a detection connection line 20C. The output terminal of the sequence generator 20A is electrically connected to one end of the detection connection line 20C, and the other end of the detection connection line 20C is electrically connected to the input terminal of the sequence receiver 20B. The three components are electrically connected on the inner side of the chip edge 10L to form an edge damage detection structure. Both the sequence generator 20A and the sequence receiver 20B of the detection structure 20 are disposed in the chip functional region 10A; that is, the sequence generator 20A and the sequence receiver 20B can be circuit design structures and can be integrated into the various conductive film layer structures of the chip functional region 10A. The detection connection line 20C of the detection structure 20 is located on the side of the chip functional region 10A facing the chip edge 10L, and the detection connection line 20C is at least partially disposed around the chip functional region 10A. Optionally, the detection connection line 20C can be arranged in a partially enclosed shape around the periphery of the chip functional area 10A, with openings only at intervals between the sequence generator 20A and the sequence receiver 20B, so that the detection connection line 20C is in a partially enclosed shape around the chip functional area 10A, such as... Figure 1 As shown.
[0058] In some other alternative embodiments, please refer to Figure 2 , Figure 2 This is another schematic diagram of the chip damage detection structure provided in this embodiment. The detection connection line 20C can be set only around the chip functional area 10A in the critical area of the chip. The critical area of the chip can be understood as certain areas of the chip that are more prone to damage or will cause serious consequences after damage. The detection connection line 20C is set in this critical area to cooperate with the sequence generator 20A and the sequence receiver 20B to perform damage detection. That is, the detection connection line 20C does not have to be completely around the chip functional area 10A. A section of the detection connection line 20C can be set only in the outer part of the chip functional area 10A. The two ends of the detection connection line 20C are electrically connected to the sequence generator 20A and the sequence receiver 20B integrated in the chip functional area 10A, respectively, to form an edge damage detection structure.
[0059] The chip damage detection structure provided in this embodiment introduces a sequence generator 20A and a sequence receiver 20B into the chip functional area 10A. The output terminal of the sequence generator 20A is electrically connected to one end of a detection connection line 20C disposed on the inner side of the chip edge 10L, and the other end of the detection connection line 20C is electrically connected to the input terminal of the sequence receiver 20B. During damage detection, the output terminal of the sequence generator 20A outputs a specific signal sequence, which reaches the sequence receiver 20B through the detection connection line 20C. If chip edge damage causes the detection connection line 20C to be damaged, the timing signal received by the sequence receiver 20B will not match the standard signal sequence emitted by the sequence generator 20A, indicating that there is damage to the chip edge. Conversely, if the timing signal received by the sequence receiver 20B matches the standard signal sequence emitted by the sequence generator 20A, it indicates that the chip edge is not damaged, thereby completing the chip edge damage detection.
[0060] The chip damage detection structure provided in this embodiment, compared to existing solutions that require separate PADs to be led out from the edge detection structure and connected to external testing equipment for detection, eliminates the need for external testing equipment and additional PADs to be led out on the chip for transmitting detection signals. This allows for effective detection of chip edge damage even under advanced packaging conditions, and the detection remains unaffected even after chip packaging is complete and no additional detection PADs are led out. For different chips, if the chip itself has a sequence generator and sequence receiver, the sequence generator 20A and sequence receiver 20B of the detection structure 20 in this embodiment can be reused, effectively reducing design complexity and saving chip layout space. Even if the chip itself does not have a sequence generator and sequence receiver, only the sequence generator 20A and sequence receiver 20B need to be designed into the film layer structure of the chip functional area 10A during chip manufacturing, increasing only design complexity without increasing process complexity.
[0061] The chip damage detection structure provided in this embodiment has a detection connection line 20C that at least partially surrounds the chip functional area 10A. The detection connection line 20C can be arranged in a partially enclosed shape around the periphery of the chip functional area 10A, or it can be arranged only around the chip functional area 10A in the critical area of the chip. In specific implementation, edge damage detection can be performed on the entire chip or the critical part of the chip according to the actual circuit requirements. It can not only detect whether the chip edge is damaged, but also detect the specific damaged area. The detection structure is simple, the detection result processing is more convenient, and the control flexibility is high.
[0062] The chip damage detection structure provided in this embodiment mainly relies on the chip's own integrated sequence generator 20A to output the detection signal sequence and the sequence receiver 20B to receive the detection signal sequence. It can achieve detection without introducing additional input / output ports or external test equipment. The steps are simple, and by transforming chip edge damage into the detection of changes in chip logic timing and function, it is beneficial to achieve efficient detection of chip edge damage.
[0063] The sequence generator 20A and sequence receiver 20B of the chip damage detection structure provided in this embodiment can be turned on or off by control, so that they can be turned on during detection and turned off after detection is completed, which helps to reduce chip power consumption.
[0064] It is understandable that the detection structure 20 set in this embodiment is designed to ensure that the path through which the signal after passing through the detection connection line 20C is sampled and received by the sequence receiver 20B is a timing-critical path. Timing-critical means that after the signal is sent by the sequence generator 20A, transmitted through the detection connection line 20C, and then received and sampled by the sequence receiver 20B, the signal delay during this period needs to be precisely controlled. That is, the design ensures that there is no large margin in timing. In this way, when damage on the detection connection line 20C is reflected in the signal delay, it can be accurately detected by the signal sequence received and sampled by the sequence receiver 20B. This ensures that the physical damage changes at the chip edge caused by external force can be reflected in the electrical logic of the signal sequence.
[0065] It should be noted that in this embodiment... Figure 1 and Figure 2 In this diagram, the shape of the chip body 10 and the location and shape of the chip functional area 10A are only schematic. In actual implementation, they can be set according to the actual chip design. The detection structure 20 is set around the chip functional area 10A at least in part. The connection structure of the detection structure 20 is only schematic. In actual implementation, the detection connection line 20C may not be set straight around the chip functional area 10A. The sequence generator 20A and the sequence receiver 20B in the figure are only schematic diagrams. In actual implementation, the sequence generator 20A and the sequence receiver 20B can be circuit connection structures integrated into the conductive film layer of the chip body 10. This embodiment will not be described in detail here.
[0066] like Figure 3 and Figure 4 As shown, Figure 3 This is a schematic diagram of an equivalent circuit structure used in the chip damage detection structure of this disclosure embodiment. Figure 4 yes Figure 3 This is a schematic diagram illustrating an example of a signal sequence generated by a sequence generator and a signal sequence received by a sequence receiver. In this embodiment, the sequence generator 20A can be a pseudo-random sequence generator. In practice, the complexity of the sequence generator 20A and the sequence receiver 20B can be selected according to the design itself. For example, the output of a linear shift feedback register (LSFR) with different lengths based on different cost requirements can be used as the sequence generator 20A. Figure 3As shown, in this embodiment, the sequence generator 20A is abstractly understood as an output register S01, the sequence receiver 20B is abstractly understood as a sampling register S02, and the detection connection line 20C is abstractly understood as a delay unit S03. The delay unit S03 is not necessarily an actual logic gate circuit in the detection structure 20; it can be understood as the delay constituted by the wires of the detection connection line 20C itself. Because the detection connection line 20C itself has resistance, it will cause a delay in signal transmission. When designing the detection structure 20, the sampling time of the sequence receiver 20B is controlled according to the duration of this delay, which can ensure that the detection circuit can sample correctly. Furthermore, the design must also ensure that an increase or decrease in the delay caused by the detection connection line 20C itself will not cause an error in the sampling time of the sequence receiver 20B. Figure 4 As shown, Figure 4 In the diagram, CK represents the clock signal trigger timing, S04 represents the data timing generated by the sequence generator 20A, and S05 represents the data timing received by the sequence receiver 20B. The data timing generated by the sequence generator 20A can be understood as an output register S01 being generated under the trigger of the clock signal. When the clock signal of the output register S01 is triggered by the rising edge, a "1" pulse signal is sent out. When it is transmitted to the sequence receiver 20B through the detection connection line 20C, it becomes a narrow pulse. This narrow pulse is sampled and identified as "1" when the clock signal of the sequence receiver 20B is sampled at the rising edge. This indicates that the timing signal received by the sequence receiver 20B will match the standard signal sequence sent by the sequence generator 20A, indicating that the chip edge is not damaged.
[0067] In some alternative embodiments, please refer to the references. Figure 5 and Figure 6 , Figure 5 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure. Figure 6 This is another schematic diagram of the chip damage detection structure provided in this embodiment. In this embodiment, the detection connection line 20C reuses at least part of the sealing ring 10B; the sealing ring 10B includes multiple metal layers, and the detection connection line 20C is disposed on at least one metal layer.
[0068] This embodiment explains that the sealing ring 10B included in the chip body 10 is a special structure located at the edge of the chip in the field of integrated circuit manufacturing. It is generally a structure of metal layer, oxide layer, and passivation layer, similar to a dam, protecting the chip functional area 10A of the chip body 10. Therefore, the detection connection line 20C in the detection structure 20 can be made using at least a portion of the conductive metal layer in the sealing ring 10B. That is, the sealing ring 10B includes multiple metal layers, and the detection connection line 20C can be disposed in at least one metal layer. This satisfies the requirement that the detection connection line 20C is located on the side of the chip functional area 10A facing the chip edge 10L, and that the detection connection line 20C is at least partially disposed around the chip functional area 10A. Figure 5 The detection connection line 20C reuses all the sealing rings 10B and is arranged around the entire functional area 10A of the chip. Figure 5 The detection connection line 20C reuses only a portion of the sealing ring 10B (set around part of the chip functional area 10A in critical areas prone to damage). The metal layer in the sealing ring 10B can also be used to create the conductive structure of the detection connection line 20C for signal propagation. This avoids introducing additional size overhead to the chip and prevents the detection connection line 20C from occupying too much space around the chip functional area 10A, thus making the chip layout more rational, reducing the overall size of the chip, and reducing the process steps of the detection structure 20, which helps to improve manufacturing efficiency.
[0069] It is understandable that when the detection connection line 20C reuses all the sealing rings 10B and is set around the entire chip functional area 10A, the sealing rings 10B can be in a shape that is not completely closed around the entire chip functional area 10A, so that the detection connection line 20C forms a certain opening 20K at intervals at the sequence generator 20A and the sequence receiver 20B (e.g., Figure 5 As shown in the figure, the detection connection line 20C is not completely closed.
[0070] Further optional, such as Figure 5 and Figure 7 As shown, Figure 7 This is another schematic diagram of the chip damage detection structure provided in this embodiment. When the detection connection line 20C reuses all the sealing rings 10B, a sealing ring supplementary structure 10B0 can be further provided at the openings of the sequence generator 20A and the sequence receiver 20B to fill the opening positions of the sequence generator 20A and the sequence receiver 20B. The sealing ring supplementary structure 10B0 is electrically insulated from the sealing rings 10B reused as the detection connection line 20C, thereby ensuring both the overall protection effect of the sealing rings 10B and the sealing ring supplementary structure 10B0 on the chip functional area 10A and the detection effect of the detection structure 20.
[0071] Optional, such as Figure 5 and Figure 8 As shown, Figure 8 yes Figure 5 A schematic diagram illustrating the relationship between multiple metal layers of the sealing ring and the detection structure. The sealing ring 10B includes N electrically insulating metal layers 10B1, each metal layer 10B1 including a detection connection line 20C; where N is a positive integer greater than or equal to 2; for example... Figure 8 As shown, an example is given with N=3.
[0072] The chip functional area 10A includes N sequence generators 20A and N sequence receivers 20B. One detection connection line 20C is electrically connected to one sequence generator 20A and one sequence receiver 20B.
[0073] This embodiment explains that the sealing ring 10B generally includes multiple metal layers, such as three electrically insulating metal layers 10B1. To ensure that damage to each layer surrounding the chip functional area 10A can be detected individually, achieving a comprehensive detection effect and ensuring that damage to each layer can be detected, multiple sets of detection structures 20 can be set. Specifically, the sealing ring 10B includes N electrically insulating metal layers 10B1. Each metal layer 10B1 is independent of each other and is not connected through vias. Each metal layer 10B1 includes a detection connection line 20C, and a corresponding sequence generator 20A and sequence receiver 20B are set for the multiplexed detection connection line 20C of each metal layer 10B1 to achieve the effect of damage detection for each metal layer, which helps to improve the accuracy of chip damage detection.
[0074] Optional, such as Figure 5 and Figure 9 , Figure 10 As shown, Figure 9 yes Figure 5 Another schematic diagram showing the relationship between the multiple metal layers of the central sealing ring and the detection structure. Figure 10 This is a schematic diagram of the electrical connection relationship of the detection structure. In this embodiment, the sealing ring 10B includes N electrically insulating metal layers, each metal layer including a detection connection line; where N is a positive integer greater than or equal to 2, such as... Figure 9 As shown, an example is given with N=3.
[0075] Chip functional area 10A includes a sequence generator 20A and a sequence receiver 20B;
[0076] The detection structure 20 also includes a first gating switch 20D and a second gating switch 20E.
[0077] The input terminal of the first gating switch 20D is electrically connected to the output terminal of the sequence generator 20A. The first gating switch 20D includes N first gating output terminals, and each of the N first gating output terminals is electrically connected to one end of one of the N detection connection lines 20C.
[0078] The output of the second gating switch 20E is electrically connected to the input of the sequence receiver 20B. The second gating switch 20E includes N second gating inputs, and each of the N second gating inputs is electrically connected to the other end of one of the N detection connection lines 20C.
[0079] This embodiment explains that the sealing ring 10B generally includes multiple metal layers, such as three electrically insulating metal layers 10B1. To ensure that damage to each layer surrounding the chip functional area 10A can be detected individually, achieving a comprehensive detection effect and ensuring that damage to each layer can be detected, multiple detection structures 20 can be set. However, it is still possible to set only one sequence generator 20A and sequence receiver 20B. Specifically, the chip functional area 10A can be equipped with only one sequence generator 20A and one sequence receiver 20B. The detection structure 20 also includes a first gating switch 20D and a second gating switch 20E. Both the first gating switch 20D and the second gating switch 20E can be N-to-one (e.g., if N is 3, it is a three-to-one gating switch). Figure 10As shown, the input terminal of the first gating switch 20D is electrically connected to the output terminal of the sequence generator 20A. The first gating switch 20D includes three first gating output terminals, each corresponding to one end of one of the three detection connection lines 20C. The output terminal of the second gating switch 20E is electrically connected to the input terminal of the sequence receiver 20B. The second gating switch 20E includes three second gating input terminals, each corresponding to the other end of one of the three detection connection lines 20C. Thus, when the signal sequence generated by the sequence generator 20A is output from the input terminal of the first gating switch 20D and enters the detection connection line 20C multiplexed by a certain metal layer 10B1, only one of the three first gating output terminals of the first gating switch 20D is connected to the first... The input terminal of the gating switch 20D selects only one of the three metal layers 10B1. Before the signal sequence is received by the sequence receiver 20B at the output terminal of the second gating switch 20E, only one of the three second gating input terminals of the second gating switch 20E is connected to the output terminal of the second gating switch 20E. At this time, the sequence generator 20A and the sequence receiver 20B detect the detection connection line 20C multiplexed by one of the three metal layers 10B1. Then the first gating switch 20D and the second gating switch 20E select another metal layer, and the steps are repeated to realize the damage detection of different detection connection lines 20C set for different metal layers. This can save the setup cost and setup space of the sequence generator 20A and the sequence receiver 20B.
[0080] In some alternative embodiments, please refer to the references. Figure 5 and Figure 11 As shown, Figure 11 yes Figure 5 Another schematic diagram showing the relationship between the multiple metal layers of the sealing ring and the detection structure. In this embodiment, the sealing ring 10B includes, for example, three electrically insulating metal layers 10B1, that is, the sealing ring 10B includes at least a first metal layer 10B1-1, a second metal layer 10B1-2 and a third metal layer 10B1-3, and the detection connection line 20C includes at least a first segment 20C-1, a second segment 20C-2 and a third segment 20C-3. The first segment 20C-1 is located in the first metal layer 10B1-1, the second segment 20C-2 is located in the second metal layer 10B1-2, and the third segment 20C-3 is located in the third metal layer 10B1-3.
[0081] The first sub-segment 20C-1 is electrically connected to the second sub-segment 20C-2 through the first via K1, and the second sub-segment 20C-2 is electrically connected to the third sub-segment 20C-3 through the second via K2.
[0082] This embodiment explains that the sealing ring 10B generally includes multiple metal layers, such as three electrically insulating metal layers 10B1. To ensure that any potential damage to the periphery of the chip functional area 10A can be detected, a detection connection line 20C can be set to reuse the sealing ring 10B structure. If the sealing ring 10B includes a first metal layer 10B1-1, a second metal layer 10B1-2, and a third metal layer 10B1-3, then the detection connection line 20C should include at least a first segment 20C-1, a second segment 20C-2, and a third segment 20C-3. The first segment 20C-1 is located on the first metal layer 10B1-1. Layer 10B1-1, the second segment 20C-2 is located in the second metal layer 10B1-2, and the third segment 20C-3 is located in the third metal layer 10B1-3. The first segment 20C-1 is electrically connected to the second segment 20C-2 through the first via K1, and the second segment 20C-2 is electrically connected to the third segment 20C-3 through the second via K2. Sections of the detection connection lines 20C between each metal layer 10B1 are electrically connected through vias. A via can be understood as a through-hole passing through the insulating layer between two adjacent metal layers. This allows for the installation of only one set of sequence generator 20A and sequence receiver 20B. When affected by cutting or other external forces, a single via more easily reflects physical damage in terms of logic function and timing. Damage to the structure of any segment of the detection connection line 20C in any layer can be detected by the sequence receiver, which is beneficial for achieving efficient detection while simplifying the manufacturing process and saving costs.
[0083] In some alternative embodiments, please refer to the references. Figure 12 and Figure 13 , Figure 12 This is another schematic diagram of the chip damage detection structure provided in this embodiment of the disclosure. Figure 13 This is another schematic diagram of the chip damage detection structure provided in this embodiment. In this embodiment, the detection connection line 20C is located between the sealing ring 10B and the chip functional area 10A. Optionally, the detection connection line 20C includes a metal ring, which surrounds or only partially surrounds the chip functional area 10A.
[0084] This embodiment explains that the detection connection line 20C of the detection structure 20 can be set between the sealing ring 10B and the chip functional area 10A. That is, the detection connection line 20C can be a custom-added circuit structure between the sealing ring 10B and the chip functional area 10A, independent of the sealing ring 10B. This is because the metal layers in the sealing ring 10B are usually connected together. If the sealing ring 10B is to be reused as the detection connection line 20C, and each metal layer is detected individually, the metal layers need to be electrically insulated, which requires changing the design concept of the sealing ring 10B. Moreover, if the chip is partially damaged, it may not be able to block the signal propagation. Therefore, this embodiment makes reasonable use of the space between the sealing ring 10B and the chip functional area 10A (no circuit devices or other structures are usually set between the chip functional area 10A of the chip body 10 and the sealing ring 10B of the chip body 10) and introduces a custom circuit structure for the detection connection line 20C. That is, a metal ring is set at the corresponding position inside the sealing ring 10B to surround the chip functional area 10A. Figure 12 The detection connection cable 20C is arranged around the entire functional area 10A of the chip. Figure 13 The detection connection line 20C is only set around part of the chip functional area 10A in the critical area that is easily damaged, which helps to improve detection accuracy and ensure detection efficiency and accuracy.
[0085] Optionally, when the detection connection line 20C is positioned between the sealing ring 10B and the chip functional area 10A, different segments of the detection connection line 30C with a metal ring structure can be located in different metal layers. (See also...) Figure 11 As shown, different segments of the detection connection line 20C are located at least in the first metal layer 10B1-1, the second metal layer 10B1-2, and the third metal layer 10B1-3. The detection connection line 20C includes at least a first sub-segment 20C-1, a second sub-segment 20C-2, and a third sub-segment 20C-3. The first sub-segment 20C-1 is located in the first metal layer 10B1-1, the second sub-segment 20C-2 is located in the second metal layer 10B1-2, and the third sub-segment 20C-3 is located in the third metal layer 10B1-3. The first sub-segment 20C-1 is electrically connected to the second sub-segment 20C-2 through a first via K1, and the second sub-segment 20C-2 is electrically connected to the third sub-segment 20C-3 through a second via K2. Partial segments of the detection connection line 20C between each metal layer 10B1 are electrically connected through vias. A via can be understood as a through-hole passing through the insulating layer between two adjacent metal layers, thus requiring only one set of sequence generator 20A and sequence receiver 20B. When affected by cutting or other external forces, a single via is more likely to reflect physical damage in terms of logic function and timing. Damage to the sub-segment of the detection connection line 20C in any layer can be detected by the sequence receiver, which is conducive to achieving efficient detection effect, while also simplifying the process and saving costs.
[0086] In some alternative embodiments, please refer to the references. Figures 1-13 and Figure 14 , Figure 14 This is a schematic flowchart of a chip damage detection method provided in this embodiment. The chip damage detection method provided in this embodiment can be applied to the chip damage detection structure of any of the above embodiments to detect whether there is damage to the chip periphery. Specifically, the detection method includes:
[0087] J11: Turn on the sequence generator 20A and sequence receiver 20B located in the chip function area 10A;
[0088] J12: Sequence generator 20A generates an initial signal sequence; optionally, the initial signal sequence generated by sequence generator 20A is a logic signal sequence, such as... Figure 4 As shown;
[0089] J13: The initial signal sequence generated by the sequence generator 20A is transmitted to the detection connection line 20C via the output terminal of the sequence generator 20A; wherein, the detection connection line 20C is at least partially arranged around the chip functional area 10A, such as... Figure 1 and Figure 2 As shown;
[0090] J14: Sequence receiver 20B receives the detection signal sequence after it has been routed through detection connection line 20C, such as... Figure 4 As shown;
[0091] J15: Compare the detection signal sequence with the initial signal sequence, such as comparison Figure 4 The timing sequence S04 of the data generated by the sequence generator 20A and the timing sequence S05 of the data received by the sequence receiver 20B;
[0092] If the detected signal sequence matches the initial signal sequence, the detection result is that the chip edge is undamaged.
[0093] If the detected signal sequence does not match the initial signal sequence, the detection result is chip edge damage.
[0094] The chip damage detection method provided in this embodiment introduces a sequence generator 20A and a sequence receiver 20B into the chip functional area 10A when setting up the chip damage detection structure. The output terminal of the sequence generator 20A is electrically connected to one end of a detection connection line 20C disposed on the inner side of the chip edge 10L, and the other end of the detection connection line 20C is electrically connected to the input terminal of the sequence receiver 20B. During damage detection, the sequence generator 20A generates a specific initial signal sequence, which is output from the output terminal of the sequence generator 20A and transmitted to the output terminal of the detection connection line 20C, outputting a specific detection signal sequence. This sequence is then received by the sequence receiver 20B via the detection connection line 20C. The sequence receiver 20B then compares the detection signal sequence with the initial signal sequence. If the comparison fails... Figure 4 The data timing sequence S04 generated by the sequence generator 20A and the data timing sequence S05 received by the sequence receiver 20B are used to detect chip edge damage. If chip edge damage causes damage to the detection connection line 20C, the detection signal sequence received by the sequence receiver 20B will not match the standard initial signal sequence emitted by the sequence generator 20A, indicating chip edge damage. Conversely, if the detection signal sequence received by the sequence receiver 20B matches the standard initial signal sequence emitted by the sequence generator 20A, it indicates that the chip edge is not damaged, thus completing the chip edge damage detection. The chip damage detection method provided in this embodiment mainly relies on the detection signal sequence output by the sequence generator 20A integrated in the chip and the detection signal sequence received by the sequence receiver 20B. It can achieve detection without introducing additional input / output ports or external test equipment. The steps are simple, and by transforming chip edge damage into the detection of changes in chip logic timing and function, it is beneficial to achieve efficient chip edge damage detection.
[0095] Optionally, after chip damage detection is completed, the sequence generator 20A and sequence receiver 20B located in the chip functional area 10A can be turned off, so that they can be turned on during detection and turned off after detection is completed, which helps to reduce chip power consumption.
[0096] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0097] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A chip damage detection structure, characterized in that, The device includes a chip body and a detection structure. The chip body includes a chip functional area and a sealing ring. The sealing ring is disposed around the chip functional area and is located between the chip functional area and the chip edge. The detection structure includes a sequence generator, a sequence receiver, and a detection connection line. The output terminal of the sequence generator is electrically connected to one end of the detection connection line, and the other end of the detection connection line is electrically connected to the input terminal of the sequence receiver. The sequence generator and the sequence receiver are both located in the functional area of the chip, and the detection connection line is located on the side of the functional area of the chip facing the edge of the chip. The detection connection line is at least partially arranged around the functional area of the chip.
2. The chip damage detection structure according to claim 1, characterized in that, The detection connection line is arranged in a partially enclosed shape around the periphery of the chip's functional area.
3. The chip damage detection structure according to claim 1, characterized in that, The detection connection line reuses at least a portion of the sealing ring; The sealing ring comprises multiple metal layers, and the detection connection line is disposed on at least one of the metal layers.
4. The chip damage detection structure according to claim 3, characterized in that, The sealing ring comprises N electrically insulating metal layers, each metal layer comprising one detection connection line; wherein N is a positive integer greater than or equal to 2; The chip functional area includes N sequence generators and N sequence receivers, and one detection connection line is electrically connected to one sequence generator and one sequence receiver.
5. The chip damage detection structure according to claim 3, characterized in that, The sealing ring comprises N electrically insulating metal layers, each metal layer comprising one detection connection line; wherein N is a positive integer greater than or equal to 2; The chip functional area includes a sequence generator and a sequence receiver; The detection structure also includes a first gating switch and a second gating switch; The input terminal of the first gating switch is electrically connected to the output terminal of the sequence generator. The first gating switch includes N first gating output terminals, and each of the N first gating output terminals is electrically connected to one end of one of the N detection connection lines. The output terminal of the second gating switch is electrically connected to the input terminal of the sequence receiver. The second gating switch includes N second gating input terminals, and each of the N second gating input terminals is electrically connected to the other end of the N detection connection lines.
6. The chip damage detection structure according to claim 3, characterized in that, The sealing ring includes at least a first metal layer, a second metal layer, and a third metal layer, and the detection connection line includes at least a first segment, a second segment, and a third segment, wherein the first segment is located in the first metal layer, the second segment is located in the second metal layer, and the third segment is located in the third metal layer; The first sub-segment is electrically connected to the second sub-segment through a first via, and the second sub-segment is electrically connected to the third sub-segment through a second via.
7. The chip damage detection structure according to claim 1, characterized in that, The detection connection line is located between the sealing ring and the chip functional area.
8. The chip damage detection structure according to claim 7, characterized in that, The detection connection line includes a metal ring, which is arranged around the functional area of the chip. The detection connection line is located at least in a first metal layer, a second metal layer, and a third metal layer. The detection connection line includes at least a first segment, a second segment, and a third segment. The first segment is located in the first metal layer, the second segment is located in the second metal layer, and the third segment is located in the third metal layer. The first sub-segment is electrically connected to the second sub-segment through a first via, and the second sub-segment is electrically connected to the third sub-segment through a second via.
9. A chip damage detection method, characterized in that, include: Turn on the sequence generator and sequence receiver located in the chip's functional area; The sequence generator generates an initial signal sequence; The initial signal sequence generated by the sequence generator is transmitted to the detection connection line via the output terminal of the sequence generator; wherein the detection connection line is at least partially arranged around the functional area of the chip; The sequence receiver receives the detection signal sequence after it has passed through the detection connection line; Compare the detected signal sequence with the initial signal sequence; If the detected signal sequence matches the initial signal sequence, the detection result is that the chip edge is undamaged. If the detected signal sequence does not match the initial signal sequence, the detection result is chip edge damage.
10. The chip damage detection method according to claim 9, characterized in that, The initial signal sequence generated by the sequence generator is a logic signal sequence.