Charge pump circuit, touch display device, voltage calibration method and storage medium
By introducing a combination of a clock generation module, a charge pump module, a sampling module, and a feedback control module into the charge pump circuit, and by using a digital control unit to adjust the bit value of the drive control signal, the problems of large output ripple and slow response speed of the charge pump circuit are solved, achieving voltage stability and fast response.
Patent Information
- Application Number
- CN202511323460.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-12-16
AI Technical Summary
In the prior art, the charge pump circuit has a large output ripple and a slow response speed, which results in a large voltage difference and a slow response speed when the touch display device switches between different scanning modes.
The system employs a combination of a clock generation module, a charge pump module, a sampling module, and a feedback control module. During the calibration phase, the digital control unit adjusts and stores the preset bit values of the drive control signals corresponding to different scanning modes. During the operation phase, it quickly acquires the preset bit values of the corresponding drive control signals and controls the number of switching elements in the dynamic switching unit within the charge pump module to maintain the stability of the power supply voltage and the response speed.
The voltage difference at the charge pump output was reduced, improving the response speed of the touch display device and reducing the signal-to-noise ratio and capacitor squeal.
Smart Images
Figure CN121150480A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronics, and in particular, to a charge pump circuit, a touch display device, a voltage calibration method and a storage medium. BACKGROUND
[0002] In recent years, capacitive touch detection technology is widely used in various human-computer interaction electronic products, such as smart phones, tablet computers, and will be applied to large-size electronic products such as smart televisions in the future. The touch display device usually includes a touch panel and a touch controller. The touch controller can further include a receiving circuit, a scanning logic circuit, a driving circuit and a charge pump circuit. The receiving circuit receives a touch sensing signal. The scanning logic circuit sets the scanning mode of the touch display device. The driving circuit is used to provide an excitation signal to the touch panel. The charge pump circuit is used to output a power supply voltage to the driving circuit. In the prior art, the touch display device can contain different scanning modes. The current load of the charge pump driven is different for different scanning modes. When switching between different scanning modes, the voltage output by the charge pump is quite different and the response speed of the charge pump circuit is slow when the load corresponding to the driving circuit changes. SUMMARY
[0003] The main purpose of the present application is to provide a charge pump circuit, a touch display device, a voltage calibration method and a storage medium, which aims to solve the problem of large output ripple and slow response speed of the charge pump circuit in the prior art.
[0004] The present application will be described from different aspects below. It should be understood that the embodiments and advantages of the different aspects below can be referred to each other.
[0005] In a first aspect, the present application provides a charge pump circuit, comprising a clock generation module, a charge pump module, a sampling module and a feedback control module; the clock generation module is used to generate a clock control signal; the charge pump module is used to generate a power supply voltage; the charge pump module comprises at least one dynamic switching unit; the at least one dynamic switching unit comprises a plurality of switching elements; the sampling module is used to sample the power supply voltage and output a sampling voltage; the feedback control module comprises: an analog-to-digital conversion unit, electrically connected with the sampling module; the analog-to-digital conversion unit is used to generate a digital signal according to the sampling voltage; a digital control unit, electrically connected with the analog-to-digital conversion unit; the digital control unit is used to adjust and store the preset bit value of the driving control signal corresponding to the scanning mode according to the digital signal and the calibration parameter in the calibration stage, and to obtain the preset bit value of the corresponding driving control signal according to the set scanning mode in the working stage; and The drive control unit is electrically connected between the clock generation module and the charge pump module, and is electrically connected with the digital control unit; the drive control unit is used for setting the number of switch elements turned on in at least one dynamic switch unit according to the corresponding drive control signal when the clock control signal is valid.
[0006] In a second aspect, the application provides a touch display device, comprising a touch panel and a touch controller, the touch controller comprising a receiving circuit, a scanning logic circuit, a drive circuit and a charge pump circuit; the receiving circuit is used for receiving a touch sensing signal; the scanning logic circuit is used for setting a scanning mode of the receiving circuit; the charge pump circuit is used for outputting a supply voltage to the drive circuit; the drive circuit is used for generating an excitation signal to the touch panel according to the supply voltage in any one scanning mode; the charge pump circuit can be switched between multiple scanning modes; the charge pump circuit comprises a clock generation module, a charge pump module, a sampling module and a feedback control module; the clock generation module is used for generating a clock control signal; the charge pump module is used for generating a supply voltage; the charge pump module comprises at least one dynamic switch unit; the at least one dynamic switch unit comprises a plurality of switch elements; the sampling module is used for sampling the supply voltage and outputting a sampling voltage; the feedback control module comprises: an analog-to-digital conversion unit electrically connected with the sampling module; the analog-to-digital conversion unit is used for generating a digital signal according to the sampling voltage; a digital control unit electrically connected with the analog-to-digital conversion unit; the digital control unit is used for adjusting and storing preset bit values of the drive control signal corresponding to the scanning mode according to the digital signal and a calibration parameter in a calibration phase, and obtaining the preset bit values of the drive control signal corresponding to the set scanning mode in a working phase; and a drive control unit electrically connected between the clock generation module and the charge pump module, and electrically connected with the digital control unit; the drive control unit is used for setting the number of switch elements turned on in at least one dynamic switch unit according to the corresponding drive control signal when the clock control signal is valid.
[0007] In a third aspect, the application provides a voltage calibration method applied to a charge pump circuit; the charge pump circuit is switched between different scanning modes; the charge pump circuit comprises a clock generation module, a charge pump module, a sampling module and a feedback control module; the charge pump module comprises at least one dynamic switch unit; the at least one dynamic switch unit comprises a plurality of switch elements; the voltage calibration method comprises: in an initial phase, the feedback control module sets a calibration parameter; in a calibration phase, the feedback control module calibrates and stores preset bit values of the drive control signal corresponding to at least one scanning mode according to the calibration parameter; the feedback control module stores a corresponding relationship between different scanning modes and different preset bit values of the drive control signal; In the working stage, the feedback control module acquires the preset bit value of the driving control signal corresponding to the current scanning mode, and sets the number of switch elements turned on in the at least one dynamic switch unit according to the acquired preset bit value of the driving control signal when the clock control signal output by the clock generation module is effective.
[0008] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer executable instructions executable by at least one processor, and the computer executable instructions implement the following steps when executed by the at least one processor: In the initial stage, the feedback control module sets the calibration parameter; In the calibration stage, the feedback control module calibrates and stores the preset bit value of the driving control signal corresponding to at least one scanning mode according to the calibration parameter; the feedback control module stores the correspondence between different scanning modes and different preset bit values of the driving control signal; In the working stage, the feedback control module acquires the preset bit value of the driving control signal corresponding to the current scanning mode, and sets the number of switch elements turned on in the at least one dynamic switch unit according to the acquired preset bit value of the driving control signal when the clock control signal output by the clock generation module is effective.
[0009] Compared with the prior art, the present application has the following advantages: In the embodiments of the present application, the number of switch elements turned on in the dynamic switch unit in the charge pump module is set by the preset bit value of the driving control signal. Meanwhile, the correspondence between different scanning modes and different preset bit values of the driving control signal is stored, and when the scanning logic circuit switches the scanning mode, the digital control unit quickly acquires the preset bit value of the corresponding driving control signal, which can reduce the voltage difference of the charge pump output, and the fast response speed can reduce the signal-to-noise ratio and the capacitive howling in the touch display device. BRIEF DESCRIPTION OF DRAWINGS
[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without any creative effort.
[0011] Figure 1 FIG. 1 is a schematic diagram of a touch display device according to a preferred embodiment of the present application.
[0012] Figure 2 FIG. 2 is a schematic diagram of a module of the touch display device in FIG. 1. Figure 1 FIG. 3 is a schematic diagram of a module of the touch display device in FIG. 1.
[0013] Figure 3 for Figure 2 A schematic diagram of a medium charge pump circuit module.
[0014] Figure 4 for Figure 3 A schematic diagram of the feedback control module in the first embodiment.
[0015] Figure 5 for Figure 3 A schematic diagram of the feedback control module in the second embodiment.
[0016] Figure 6 for Figure 5 A partial circuit diagram of the charge pump module, sampling module, and feedback control module.
[0017] Figure 7 for Figure 6 The waveform diagrams of the input clock signal, the first sub-clock control signal, the second sub-clock control signal, the third sub-clock control signal, and the fourth sub-clock control signal are shown.
[0018] Figure 8 This is a flowchart of a charge pump voltage calibration method according to a preferred embodiment of this application.
[0019] Figure 9 for Figure 8 A detailed flowchart of step S82 in the first embodiment.
[0020] Figure 10 for Figure 8 A detailed flowchart of step S82 in the second embodiment.
[0021] Explanation of main component symbols The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0023] The terms "first," "second," and "third," etc., used in the specification and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising," and any variations thereof, are intended to cover non-exclusive inclusion.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0025] The specific implementation of the charge pump circuit, touch display device, voltage calibration method, and storage medium of this application will be described below with reference to the accompanying drawings.
[0026] Please see Figure 1 This is a perspective view of a preferred embodiment of the touch display device 100 provided in this application. In at least one embodiment of this application, the touch display device 100 can be a mobile device such as a personal computer, tablet computer, smartphone, personal digital assistant (PDA), game console, interactive network television (Internet Protocol Television, IPTV), smart wearable device, navigation device, etc., or a fixed device such as a desktop computer, server, digital television, etc. The touch display device 100 may further include one or more combinations of other functions such as fingerprint recognition and camera functions.
[0027] Please refer to the following: Figure 2 This is a schematic diagram of a preferred embodiment of the touch display device 100 of this application. The touch display device 100 includes a touch panel 10 and a touch controller 20.
[0028] The touch panel 10 is used to sense user touch operations. The touch panel 10 includes multiple drive lines 11, multiple sensing lines 12, a drive interface 13, and a sensing interface 14. The multiple drive lines 11 extend along a first direction X and are arranged parallel to each other. The multiple sensing lines 12 extend along a second direction Y and are arranged parallel to each other. The multiple drive lines 11 and multiple sensing lines 12 are insulated from each other and are arranged in a grid pattern. In at least one embodiment of this application, the first direction X and the second direction Y are perpendicular. In other embodiments, the first direction X and the second direction Y may intersect at other angles. A touch node 111 is present at the intersection of the drive lines 11 and the sensing lines 12. The drive lines 11 can receive excitation signals generated by the touch controller 20 through the drive interface 13. The sensing lines 12 can transmit the sensed touch signals to the touch controller 20 through the sensing interface 14. In at least one embodiment of this application, at least one touch electrode (not shown) is present at the touch node 111. The touch electrode can be configured in a mutual capacitance touch mode. In other embodiments, the touch electrode can be configured in a self capacitance or a combination of mutual capacitance and self capacitance.
[0029] In at least one embodiment of this application, the touch controller 20 includes a receiving circuit 21, a scanning logic circuit 22, a storage circuit 23, a driving circuit 24, and a charge pump circuit 25.
[0030] The receiving circuit 21 is electrically connected to the touch panel 10. The receiving circuit 21 is used to receive one or more touch signals generated by the touch node 111 through the sensing interface 14. In at least one embodiment of this application, the receiving circuit 21 may also receive sensing signals from other sensors.
[0031] The scanning logic circuit 22 is electrically connected to the receiving circuit 21. The scanning logic circuit 22 is used to access the storage circuit 23, autonomously read the touch signals from the receiving circuit 21, and control the touch panel 10 to operate in different scanning modes. In at least one embodiment of this application, the scanning mode can be one of several scanning modes, such as self-capacitance scanning mode, mutual capacitance scanning mode, and pen scanning mode. For example, in mutual capacitance scanning mode, the scanning logic circuit 22 is configured to sense the mutual capacitance between intersecting touch electrodes; in self-capacitance scanning mode, the scanning logic circuit 22 is configured to sense the self-capacitance of the touch electrodes relative to the ground terminal; in pen scanning mode, the scanning logic circuit 22 is configured to sense the capacitance between the touch electrodes and the stylus (not shown).
[0032] The driving circuit 24 is electrically connected to the scanning logic circuit 22, the charge pump circuit 25, and the touch panel 10. Under the control of the scanning logic circuit 22, the driving circuit 24 generates excitation signals of various frequencies and phases based on the supply voltage output by the charge pump circuit 25.
[0033] The charge pump circuit 25 is electrically connected to the receiving circuit 21 and the driving circuit 24. The charge pump circuit 25 provides a supply voltage to the receiving circuit 21 and the driving circuit 24. In at least one embodiment of this application, the charge pump circuit 25 can be a boost charge pump or a negative charge pump. The supply voltage output by the charge pump circuit 25 remains constant when switching between different scanning modes.
[0034] Please refer to the following: Figure 3 This is a schematic diagram of the charge pump circuit 25. The charge pump circuit 25 can operate in the initial stage, calibration stage, and operation stage. The charge pump circuit 25 includes a clock generation module 251, a charge pump module 252, a sampling module 253, and a feedback control module 254.
[0035] The clock generation module 251 is used to generate a non-overlapping clock control signal Clk based on the input clock signal.
[0036] The charge pump module 252 is electrically connected to the clock generation module 251, the sampling module 253, the feedback control module 254, and the touch panel 10. The charge pump module 252 includes a voltage input terminal P_in, a drive control terminal P_ctrl, and a voltage output terminal P_out. The voltage input terminal P_in receives the input voltage Vin. The drive control terminal P_ctrl is electrically connected to the feedback control module 254 and receives the drive control signal Dri_ctrl output by the feedback control module 254. The voltage output terminal P_out is electrically connected to the drive circuit 24 and outputs a supply voltage to the drive circuit 24. The charge pump module 252 generates a supply voltage for the drive circuit 24 based on the input voltage Vin and the drive control signal Dri_ctrl. When the scan logic circuit 22 switches between different scan modes, the charge pump module 252 maintains a constant output supply voltage according to the bit value of the corresponding drive control signal Dri_ctrl.
[0037] The charge pump module 252 is equipped with at least one dynamic switching unit 2521 / 2522 (e.g., Figure 6 (As shown). Each dynamic switching unit 2521 / 2522 includes multiple switching elements (not shown). In at least one embodiment of this application, the switching element is a transistor. The supply voltage output at the voltage output terminal P_out can be calculated according to the following formula.
[0038] Formula 1 in, The power supply voltage output by the charge pump module 252; It is the harmonic coefficient; The input voltage received by the charge pump module 252; This is the on-resistance of the charge pump module 252; This refers to the operating frequency of the charge pump module 252; For the capacitors within the charge pump module 252; This is the load current corresponding to charge pump module 252.
[0039] Therefore, it can be seen from formula one that, at the input voltage , Under fixed conditions, the supply voltage output by the charge pump module 252 is mainly determined by the on-resistance within the charge pump module 252. The decision is made based on the on-resistance. The change can be adjusted by altering the number of switched elements that are turned on within the dynamic switching unit 2521 / 2522. On-resistance The magnitude of the resistance is inversely proportional to the number of switched elements turned on within the dynamic switching unit 2521 / 2522. That is, the resistance at which the switching impedance is turned on is... The larger the value, the fewer the number of switched elements that are turned on within the dynamic switching unit 2521 / 2522; the higher the on-resistance... The smaller the value, the more switching elements are turned on in the dynamic switching unit 2521 / 2522.
[0040] In at least one embodiment of this application, the drive control signal Dri_ctrl varies within a preset range. The number of bits in the drive control signal Dri_ctrl is the same as the total number of switching elements in at least one dynamic switching unit 2521 / 2522, and the magnitude of the preset bit value of the drive control signal Dri_ctrl is proportional to the number of switching elements turned on in at least one dynamic switching unit 2521 / 2522. Taking a 6-bit drive control signal Dri_ctrl as an example, the preset range is 000000-111111, and the upper limit threshold is 111111.
[0041] The sampling module 253 is electrically connected between the voltage output terminal P_out of the charge pump module 252 and the feedback control module 254. The sampling module 253 samples the voltage at the voltage output terminal P_out of the charge pump module 252 to obtain a sampled voltage, and outputs the sampled voltage to the feedback control module 254. In at least one embodiment of this application, as... Figure 6 As shown, the sampling module 253 includes two voltage divider resistors R1 and R2 connected in series. One end of the first voltage divider resistor R1 is electrically connected to the voltage output terminal P_out, and the other end is grounded through the second voltage divider resistor R2.
[0042] The feedback control module 254 is electrically connected to the drive control terminal P_ctrl of the sampling module 253 and the charge pump module 252. In the initial stage, the feedback control module 254 sets calibration parameters. During the calibration stage, the feedback control module 254 calibrates the preset bit values of the drive control signal Dri_ctrl corresponding to different scan modes according to the calibration parameters. The preset bit values of the drive control signal Dri_ctrl can be the same or different under different scan modes. During the operating stage, the feedback control module 254 obtains the preset bit value of the corresponding drive control signal Dri_ctrl according to the scan mode set by the scan logic circuit 22, and provides the obtained preset bit value of the drive control signal Dri_ctrl to the charge pump module 252 when the clock control signal Clk is valid.
[0043] In at least one embodiment of this application, the scanning mode can be divided into a reference scanning mode and a normal scanning mode based on power consumption. The reference scanning mode is the scanning mode with the maximum power consumption. The calibration parameters may include a calibration voltage. The calibration voltage is the supply voltage output by the charge pump module 252 when the bit value of the drive control signal Dri_ctrl is at the upper limit threshold of a preset range in the reference scanning mode. In at least one embodiment of this application, during the calibration phase, the feedback control module 254 calibrates the preset bit value of the drive control signal Dri_ctrl corresponding to the normal scanning mode according to the calibration parameters. During the operation phase, when the scanning mode switches to the reference scanning mode, the feedback control module 254 acquires the upper limit threshold of the drive control signal Dri_ctrl and outputs the acquired upper limit threshold of the drive control signal Dri_ctrl to the charge pump module 252 when the clock control signal Clk is valid; when the scanning mode switches to the normal scanning mode, the feedback control module 254 acquires the preset bit value of the drive control signal Dri_ctrl corresponding to the normal scanning mode and outputs the acquired preset bit value of the drive control signal Dri_ctrl to the charge pump module 252 when the clock control signal Clk is valid.
[0044] The feedback control module 254 includes an analog-to-digital converter 2541, a digital control unit 2542, and a drive control unit 2543.
[0045] The analog-to-digital converter 2541 is electrically connected between the sampling module 253 and the digital control unit 2542. The analog-to-digital converter 2541 is used to convert the sampled voltage into a digital signal.
[0046] The digital control unit 2542 is electrically connected between the analog-to-digital converter 2541 and the drive control unit 2543. The digital control unit 2542 is used to set reference parameters according to the reference scan mode during the initial stage. The digital control unit 2542 is also used to set the preset bit value of the drive control signal Dri_ctrl corresponding to the scan mode according to the digital signal and calibration voltage during the calibration stage. The digital control unit 2542 is also used to directly acquire the preset bit value of the drive control signal Dri_ctrl corresponding to the scan mode set by the scan logic circuit 22 during the operation stage.
[0047] The drive control unit 2543 is electrically connected between the clock generation module 251 and the charge pump module 252, and is also electrically connected to the digital control unit 2542. The drive control unit 2543 is used to provide the acquired drive control signal Dri_ctrl to at least one corresponding dynamic switching unit 2521 / 2522 when the clock control signal Clk is valid during the initial phase, calibration phase, and operation phase, in order to set the number of switching elements turned on within at least one dynamic switching unit 2521 / 2522.
[0048] Implementation Method 1 Please refer to the following: Figure 4 This is a schematic diagram of the feedback control module 254A according to the first embodiment. The reference parameters of the feedback control module 254A include only the calibration voltage. The analog-to-digital converter unit 2541 is a comparator. During the calibration and operation phases, the analog-to-digital converter unit 2541 outputs a digital signal based on the comparison result between the sampled voltage and the calibration voltage. In this embodiment, the digital signal is a binary digital signal. When the sampled voltage is greater than the calibration voltage, the digital signal is 1; when the sampled voltage is less than the calibration voltage, the digital signal is 0.
[0049] During the calibration phase, when the digital signal is not 0, the digital control unit 2542 controls the bit value of the drive control signal Dri_ctrl to be gradually adjusted from the initial bit value in predetermined steps until the digital signal is 0, and stores the bit value of the drive control signal Dri_ctrl at this time as the preset bit value of the drive control signal Dri_ctrl corresponding to the normal scanning mode. During the operation phase, the digital control unit 2542 obtains the preset bit value of the drive control signal Dri_ctrl corresponding to the scanning mode set by the scanning logic circuit 22.
[0050] Implementation Method 2 Please refer to the following: Figure 5This is a schematic diagram of the feedback control module 254B according to the second embodiment. During the calibration and operation phases, the analog-to-digital converter 2541 directly converts the sampled voltage into a digital signal. In this embodiment, the digital signal is a multi-bit digital code value. That is, different sampled voltage values correspond to different digital code values. The reference parameters of the feedback control module 254B also include a calibration code value. The calibration code value is the digital code value obtained by directly converting the sampled voltage corresponding to the calibration voltage into a digital code value by the analog-to-digital converter 2541.
[0051] During the calibration phase, the digital control unit 2542 outputs the initial bit value of the drive control signal Dri_ctrl to the drive control unit 2543. When the clock control signal Clk is valid, the charge pump module 252 outputs the supply voltage to be calibrated according to the initial bit value of the drive control signal Dri_ctrl. The sampling module 253 samples the supply voltage to be calibrated and outputs the sampled voltage to be calibrated. The analog-to-digital converter 2541 converts the sampled voltage to be calibrated into a digital code value. The digital control unit 2542 compares the digital code value with the calibration code value, and when the digital code to be calibrated is not equal to the calibration code value, it controls the drive control signal Dri_ctrl to gradually adjust from the initial bit value with a preset step size until the digital code to be calibrated equals the calibration code value. The digital control unit 2542 stores the bit value of the drive control signal Dri_ctrl when the digital code value and the calibration code value are equal as the preset bit value of the drive control signal Dri_ctrl in the current scan mode. In at least one embodiment of this application, the digital control unit 2542 determines whether the digital code value and the calibration code value are equal. When the digital code value and the calibration code value are not equal, the digital control unit 2542 dynamically adjusts the value of the drive control signal Dri_ctrl until the digital code value and the calibration code value are equal, and stores the value of the drive control signal Dri_ctrl at this time as the preset bit value of the drive control signal Dri_ctrl in the current scanning mode. Specifically, the digital control unit 2542 can further determine whether the digital code value is greater than the calibration code value. When the digital code value is greater than the calibration code value, the drive control signal Dri_ctrl output by the digital control unit 2542 is gradually adjusted upward from the initial value with a predetermined step size. When the digital code value is less than the calibration code value, the drive control signal Dri_ctrl output by the digital control unit 2542 is gradually adjusted downward from the initial value with a predetermined step size. In at least one embodiment of this application, the initial value is an intermediate value within a preset range. Taking a 6-bit drive control signal Dri_ctrl as an example, the preset range is 000000-111111, and the initial value of the drive control signal Dri_ctrl is 100000. The predetermined step size is 1 bit. For example, when the digital code value is greater than the calibration code value, the value of the drive control signal Dri_ctrl output by the digital control unit 2542 is adjusted from 100000 to 100001. If the digital code value is still greater than the calibration code value, the value of the drive control signal Dri_ctrl output by the digital control unit 2542 is adjusted from 100001 to 100011. When the digital code value is less than the calibration code value, the value of the drive control signal Dri_ctrl output by the digital control unit 2542 is adjusted from 100000 to 011111. If the digital code value is still less than the calibration code value, the value of the drive control signal Dri_ctrl output by the digital control unit 2542 is adjusted from 011111 to 011110.
[0052] During the operation phase, the digital control unit 2542 acquires the preset bit value of the drive control signal Dri_ctrl corresponding to the scan mode set by the scan logic circuit 22.
[0053] Please refer to the following: Figure 6 and Figure 7 , Figure 6 for Figure 5 A partial circuit diagram of the neutralization charge pump module 252, the sampling module 253, and the feedback control module 254. Figure 7 This diagram illustrates the waveforms of the input clock signal Clk_in, the first sub-clock control signal Clk_1_1, the second sub-clock control signal Clk_1_2, the third sub-clock control signal Clk_2_1, and the fourth sub-clock control signal Clk_2_2. In the embodiments of this application, the clock generation module 251 outputs non-overlapping first clock control signal Clk_1 and second clock control signal Clk_2. The drive control unit 2543 outputs the first sub-clock control signal Clk_1_1 and the second sub-clock control signal Clk_1_2 based on the first clock control signal Clk_1, and outputs the third sub-clock control signal Clk_2_1 and the fourth sub-clock control signal Clk_2_2 based on the second clock control signal Clk_2.
[0054] The charge pump module 252 is a double charge pump. The charge pump module 252 includes two dynamic switching units 2521 / 2522, two static switching units 2523 / 2524, and a charge pump capacitor Cfly. In other embodiments, the static switching units 2523 / 2524 can also be dynamic switching units. Specifically, dynamic switching unit 2521 and static switching unit 2523 are connected in series between the voltage input terminal P_in and the voltage output terminal P_out; dynamic switching unit 2522 and static switching unit 2524 are connected in series between the voltage input terminal P_in and the voltage output terminal P_out; one end of the charge pump capacitor Cfly is electrically connected between dynamic switching unit 2521 and static switching unit 2523; and the other end of the charge pump capacitor Cfly is electrically connected between dynamic switching unit 2522 and static switching unit 2524. Among them, dynamic switch unit 2521 is controlled by the first sub-clock control signal Clk_1_1, static switch unit 2524 is controlled by the third sub-clock control signal Clk_2_1, dynamic switch unit 2522 is controlled by the fourth sub-clock control signal Clk_2_2, and static switch unit 2523 is controlled by the second sub-clock control signal Clk_1_2. Figure 7As shown, the waveforms of the first sub-clock control signal Clk_1_1 and the second sub-clock control signal Clk_1_2 are the same, and the waveforms of the third sub-clock control signal Clk_2_1 and the fourth sub-clock control signal Clk_2_2 are the same, but are interleaved with the waveforms of the first sub-clock control signal Clk_1_1 and the second sub-clock control signal Clk_1_2. When the first sub-clock control signal Clk_1_1 and the second sub-clock control signal Clk_1_2 are at a high level, the third sub-clock control signal Clk_2_1 and the fourth sub-clock control signal Clk_2_2 are at a low level. At this time, according to the preset bit value of the drive control signal Dri_ctrl, at least some of the switching elements in the dynamic switching unit 2521 are turned on, and all the switching elements in the static switching unit 2524 are turned on; all the switching elements in the dynamic switching unit 2522 and the static switching unit 2523 are turned off. When the third sub-clock control signal Clk_2_1 and the fourth sub-clock control signal Clk_2_2 are at a high level, the first sub-clock control signal Clk_1_1 and the second sub-clock control signal Clk_1_2 are at a low level. At this time, according to the preset bit value of the drive control signal Dri_ctrl, at least some of the switching elements in the dynamic switching unit 2522 are turned on, and all the switching elements in the static switching unit 2523 are turned on; all the switching elements in the dynamic switching unit 2521 and the static switching unit 2524 are turned off.
[0055] In calibration mode, under any scan mode, the digital control unit 2542 sets the preset bit value of the drive control signal Dri_ctrl according to the digital signal and the calibration voltage. Specifically, the clock generation module 251 outputs a non-overlapping first clock control signal Clk_1 and a second clock control signal Clk_2. The drive control signal Dri_ctrl output by the digital control unit 2542 is at its initial value. When the first sub-clock control signal Clk_1_1 and the second sub-clock control signal Clk_1_2 are at a high level, the drive control unit 2543 provides the drive control signal Dri_ctrl at its initial value to the dynamic switch unit 2521 and the static switch unit 2524. When the third sub-clock control signal Clk_2_1 and the fourth sub-clock control signal Clk_2_2 are at a low level, the drive control unit 2543 controls the dynamic switch unit 2522 and the static switch unit 2523 to be disconnected. At this time, the sampling module 253 samples the supply voltage of the voltage output terminal P_out and outputs the sampled voltage. The analog-to-digital converter unit 2541 directly converts the sampled voltage into a digital signal. The digital control unit 2542 acquires the corresponding digital code value based on the digital signal and compares the acquired digital code value with the calibration code value. When the acquired digital code value is lower than the calibration code value, the drive control unit 2543 controls the drive control signal Dri_ctrl to gradually adjust upward from its initial value in predetermined steps. According to the adjusted drive control signal Dri_ctrl, the number of switched elements turned on in the dynamic switching units 2521 / 2522 increases, the on-resistance of the charge pump module 252 decreases, and the supply voltage of the voltage output terminal P_out increases. Conversely, when the acquired digital code value is higher than the calibration code value, the drive control unit 2543 controls the drive control signal Dri_ctrl to gradually adjust downward from its initial value in predetermined steps. According to the adjusted drive control signal Dri_ctrl, the number of switched elements turned on in the dynamic switching units 2521 / 2522 increases, the on-resistance of the charge pump module 252 decreases, and the supply voltage of the voltage output terminal P_out decreases. When the acquired digital code value is equal to the calibration code value, the drive control unit 2543 uses the value of the current drive control signal Dri_ctrl as the preset bit value of the drive control signal Dri_ctrl corresponding to the normal scanning mode.
[0056] During the working phase, when the scanning logic circuit 22 switches between different scanning modes, the digital control unit 2542 obtains the preset bit value of the drive control signal Dri_ctrl corresponding to the scanning mode set by the scanning logic circuit 22. When the clock control signal Clk output by the clock generation module 251 is valid, the drive control unit 2543 provides the obtained drive control signal Dri_ctrl to the charge pump module 252. The charge pump module 252 sets the number of switching elements turned on in the dynamic switching unit 2521 / 2522 according to the drive control signal Dri_ctrl, so that the power supply voltage of the voltage output terminal P_out is maintained at the calibration voltage. In at least one embodiment of this application, when the scanning mode set by the scanning logic circuit 22 is the reference scanning mode, the digital control unit 2542 extracts the upper limit threshold of the drive control signal Dri_ctrl, and the drive control unit 2543 sets the number of switching elements turned on in the dynamic switching units 2521 / 2522 in the charge pump module 252 according to the clock control signal Clk output by the clock generation module 251 and the drive control signal Dri_ctrl output by the digital control unit 2542.
[0057] The aforementioned charge pump circuit 25 and touch display device 100 utilize the preset bit value of the drive control signal Dri_ctrl to set the number of switching elements turned on in the dynamic switching units 2521 / 2522 within the charge pump module 252. Simultaneously, they store the correspondence between different scanning modes and different preset bit values of the drive control signal Dri_ctrl. When the scanning logic circuit 22 switches scanning modes, the digital control unit 2542 quickly obtains the corresponding preset bit value of the drive control signal Dri_ctrl, which reduces the voltage difference output by the charge pump circuit 25. Furthermore, the fast response speed reduces the signal-to-noise ratio and capacitor howling in the touch display device 100.
[0058] Please see Figure 8 This is a flowchart of a voltage calibration method according to a preferred embodiment of this application. In at least one embodiment of this application, the voltage calibration method can be applied to a feedback control module 254A / 254B. The feedback control module 254A / 254B may include a ratio Figures 1 to 6 More or less hardware, or different component setups. Understandably, the implementation of voltage calibration methods is not limited to applications... Figures 1 to 6 The feedback control modules 254A / 254B shown are for illustrative purposes only and are illustrated with diagrams. The voltage calibration method includes the following steps: In step S81, during the initial stage, the feedback control module 254 sets the calibration parameters.
[0059] In such Figure 4The calibration parameters for the feedback control module 254A shown include the calibration voltage. (In, for example...) Figure 5 In the feedback control module 254B shown, the calibration parameters include a calibration voltage and a calibration code value. The calibration voltage is the supply voltage output at the voltage output terminal P_out in the reference scan mode when the bit value of the drive control signal Dri_ctrl is the upper threshold. The reference scan mode is the scan mode with maximum power consumption. In at least one embodiment of this application, taking the 6-bit drive control signal Dri_ctrl as an example, the preset range is 000000-111111, and the upper threshold is 111111. The calibration code value is the digital code value obtained by directly converting the sampled voltage corresponding to the calibration voltage into a digital code value by the analog-to-digital converter unit 2541.
[0060] In step S82, during the calibration phase, the feedback control module 254 calibrates and stores the preset bit value of the drive control signal Dri_ctrl corresponding to at least one scanning mode according to the calibration parameters.
[0061] In at least one embodiment of this application, the feedback control module 254 calibrates and stores the preset bit value of the drive control signal Dri_ctrl corresponding to the normal scanning mode according to calibration parameters. In other embodiments, the feedback control module 254 calibrates and stores the preset bit value of the drive control signal Dri_ctrl corresponding to each scanning mode according to calibration parameters.
[0062] Please see Figure 9 A detailed flowchart of step S82 is provided. In at least one embodiment of this application, when employing... Figure 5 When the feedback control module 254B structure is shown, step S82 may further include the following steps: In step S821, the feedback control module 254 sets one of the multiple scanning modes as the scanning mode to be calibrated.
[0063] In at least one embodiment of this application, the feedback control module 254 selects a conventional scanning mode as the scanning mode to be calibrated.
[0064] In step S822, under the calibration scan mode, the drive control unit 2543 outputs the initial bit value of the drive control signal Dri_ctrl to the charge pump module 252. When the clock control signal Clk is valid, the charge pump module 252 sets the number of switching elements turned on in at least one dynamic switching unit 2521 / 2522 according to the initial bit value of the drive control signal Dri_ctrl.
[0065] In step S823, the analog-to-digital conversion unit 2541 converts the sampling voltage to be calibrated output by the sampling module 253 into a digital code value.
[0066] In at least one embodiment of this application, the sampling voltage to be calibrated is the sampling voltage obtained by the sampling module 253 sampling the supply voltage output by the charge pump module 252 according to the initial bit value of the drive control signal Dri_ctrl when the clock control signal Clk is valid.
[0067] Step S824: Determine whether the digital code value is equal to the calibration code value.
[0068] Step S825: When the digital code value is not equal to the calibration code value, determine whether the digital code value is greater than the calibration code value.
[0069] In step S826, when the digital code value is greater than the calibration code value, the digital control unit 2542 controls the bit value of the drive control signal Dri_ctrl to be gradually adjusted upward from the initial bit value by a preset step size.
[0070] In step S827, when the digital code value is less than the calibration code value, the digital control unit 2542 controls the bit value of the drive control signal Dri_ctrl to be gradually adjusted downward from the initial bit value by a preset step size.
[0071] In step S828, when the digital code value is equal to the calibration code value, the digital control unit 2542 stores the bit value of the current drive control signal Dri_ctrl as the preset bit value of the drive control signal Dri_ctrl corresponding to the scan mode to be calibrated.
[0072] Please see Figure 10 This is a detailed flowchart of step S82 in another embodiment. When using... Figure 4 When the feedback control module 254B structure is shown, step S82 may further include the following steps: In step S821, the feedback control module 254 sets one of the multiple scanning modes as the scanning mode to be calibrated.
[0073] In at least one embodiment of this application, the feedback control module 254 selects a conventional scanning mode as the scanning mode to be calibrated.
[0074] In step S822, under the calibration scan mode, the drive control unit 2543 outputs the initial bit value of the drive control signal Dri_ctrl to the charge pump module 252. When the clock control signal Clk is valid, the charge pump module 252 sets the number of switching elements turned on in at least one dynamic switching unit 2521 / 2522 according to the initial bit value of the drive control signal Dri_ctrl.
[0075] In step S823, the analog-to-digital conversion unit 2541 determines whether the sampling voltage to be calibrated output by the sampling module 253 is equal to the calibration voltage.
[0076] In at least one embodiment of this application, the sampling voltage to be calibrated is the sampling voltage obtained by the sampling module 253 sampling the supply voltage output by the charge pump module 252 according to the initial bit value of the drive control signal Dri_ctrl when the clock control signal Clk is valid.
[0077] In step S824, when the sampling voltage to be calibrated is not equal to the calibration voltage, the analog-to-digital conversion unit 2541 determines whether the sampling voltage to be calibrated is greater than the calibration voltage.
[0078] In step S825, when the sampling voltage to be calibrated is greater than the calibration voltage, the digital control unit 2542 controls the bit value of the drive control signal Dri_ctrl to be gradually adjusted upward from the initial bit value by a preset step size.
[0079] In step S826, when the sampling voltage to be calibrated is less than the calibration voltage, the digital control unit 2542 controls the bit value of the drive control signal Dri_ctrl to be gradually adjusted downward from the initial bit value by a preset step size.
[0080] In step S827, when the sampling voltage to be calibrated is equal to the calibration voltage, the digital control unit 2542 stores the bit value of the current drive control signal Dri_ctrl as the preset bit value of the drive control signal Dri_ctrl corresponding to the scan mode to be calibrated.
[0081] The voltage calibration method described above uses the preset bit value of the drive control signal Dri_ctrl to set the number of switching elements turned on in the dynamic switching units 2521 / 2522 within the charge pump module 252. Simultaneously, it stores the correspondence between different scanning modes and different preset bit values of the drive control signal Dri_ctrl. When the scanning logic circuit 22 switches scanning modes, the digital control unit 2542 quickly obtains the corresponding preset bit value of the drive control signal Dri_ctrl, which can reduce the voltage difference output by the charge pump circuit 25. Furthermore, the fast response speed can reduce the signal-to-noise ratio and capacitor howling in the touch display device 100.
[0082] This application also provides a computer-readable storage medium. The computer-readable storage medium stores program instructions that, when executed on a computing device, cause the computing device to perform the voltage calibration method provided in the foregoing embodiments.
[0083] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, any appropriate changes and variations made to the above embodiments within the essential spirit and scope of this application should fall within the scope of protection claimed by this application.
Claims
1. A charge pump circuit, characterized in that: It can switch between multiple scanning modes; the charge pump circuit includes a clock generation module, a charge pump module, a sampling module, and a feedback control module; the clock generation module is used to generate a clock control signal; the charge pump module is used to generate a supply voltage; the charge pump module includes at least one dynamic switching unit; the at least one dynamic switching unit includes multiple switching elements; The sampling module is used to sample the power supply voltage and output the sampled voltage; The feedback control module includes: An analog-to-digital converter (ADC) is electrically connected to the sampling module; the ADC is used to generate a digital signal based on the sampling voltage. A digital control unit is electrically connected to the analog-to-digital conversion unit; the digital control unit is used to adjust and store preset bit values of the drive control signal corresponding to the scanning mode according to the digital signal and calibration parameters during the calibration phase, and to obtain the preset bit values of the drive control signal corresponding to the set scanning mode during the operation phase; and A drive control unit is electrically connected between the clock generation module and the charge pump module, and is also electrically connected to the digital control unit; the drive control unit is used to set the number of switching elements turned on in the at least one dynamic switching unit according to the corresponding drive control signal when the clock control signal is valid.
2. The charge pump circuit as described in claim 1, characterized in that, The number of bits in the drive control signal is the same as the total number of switching elements in the at least one dynamic switching unit; the preset bit value of the drive control signal is proportional to the number of switching elements that are turned on in the at least one dynamic switching unit.
3. The charge pump circuit as described in claim 2, characterized in that, When the charge pump circuit is operating in the initial stage, the digital control unit is also used to set calibration parameters; the calibration parameters include a calibration voltage; when the charge pump circuit is operating in the calibration stage, the analog-to-digital conversion unit outputs the comparison result of the sampled voltage and the calibration voltage as a digital signal, wherein the digital signal switches between 1 and 0; when the digital signal is 1, the digital control unit controls the bit value of the drive control signal to be gradually adjusted from the initial bit value in predetermined steps until the digital signal is 0; the digital control unit is also used to store the bit value corresponding to the digital signal being 0 as the preset bit value of the drive control signal corresponding to the scanning mode.
4. The charge pump circuit as described in claim 3, characterized in that, The scanning mode includes a reference scanning mode; the preset bit value of the drive control signal varies within a preset range; the initial bit value is the middle bit value within the preset range; The calibration voltage is the power supply voltage output by the charge pump module when the reference scan mode is in effect and the bit value of the drive control signal is the upper limit threshold of the preset range; the reference scan mode is the scan mode with the highest power consumption.
5. The charge pump circuit as described in claim 2, characterized in that, When the charge pump circuit is operating in the initial stage, the digital control unit is also used to set calibration parameters; the calibration parameters include calibration voltage and calibration code value; when the charge pump circuit is operating in the calibration stage, the analog-to-digital conversion unit directly converts the sampled voltage into an analog-to-digital signal and outputs the digital signal; the digital signal is a digital code value, and different sampled voltages correspond to different digital code values. The digital control unit compares the digital code value and the calibration code value, and when the digital code value is inconsistent with the calibration code value, controls the bit value of the drive control signal to be gradually adjusted from the initial bit value in a predetermined step size until the digital code value is equal to the calibration code value; the digital control unit is also used to store the bit value of the drive control signal as a preset bit value corresponding to the drive control signal in the scanning mode when the digital code value and the calibration code value are equal.
6. The charge pump circuit as described in claim 5, characterized in that, The scanning mode includes a reference scanning mode; the preset bit value of the drive control signal varies within a preset range; the initial bit value is an intermediate bit value within the preset range; the calibration voltage is the power supply voltage output by the charge pump module when the reference scanning mode is in effect and the drive control signal is at the upper limit threshold of the preset range; The calibration code value is obtained by directly converting the sampled voltage corresponding to the calibration voltage into a digital code value by the analog-to-digital conversion unit; the reference scanning mode is the scanning mode with the highest power consumption.
7. A touch display device, comprising a touch panel and a touch controller, the touch controller comprising a receiving circuit, a scanning logic circuit, a driving circuit, and a charge pump circuit; the receiving circuit is used to receive touch sensing signals; the scanning logic circuit is used to set a scanning mode of the receiving circuit; the charge pump circuit is used to output a power supply voltage to the driving circuit; the driving circuit is used to generate an excitation signal to the touch panel according to the power supply voltage in any of the scanning modes; characterized in that, The charge pump circuit adopts the charge pump circuit as described in any one of claims 1 to 6.
8. The touch display device as claimed in claim 7, characterized in that, The scanning mode is at least one of the following: self-capacitance scanning mode, mutual capacitance scanning mode, pen scanning mode, and sleep mode.
9. A voltage calibration method applied to a charge pump circuit; the charge pump circuit switches between different scanning modes; the charge pump circuit includes a clock generation module, a charge pump module, a sampling module, and a feedback control module; the charge pump module includes at least one dynamic switching unit; The at least one dynamic switching unit includes a plurality of switching elements; characterized in that... The voltage calibration method includes: In the initial stage, the feedback control module sets the calibration parameters; During the calibration phase, the feedback control module calibrates and stores the preset bit values of the drive control signal corresponding to at least one scanning mode according to the calibration parameters; the feedback control module stores the correspondence between different scanning modes and different preset bit values of the drive control signal. During the working phase, the feedback control module obtains the preset bit value of the corresponding drive control signal according to the current scanning mode, and when the clock control signal output by the clock generation module is valid, the feedback control module sets the number of the switching elements turned on in the at least one dynamic switching unit according to the preset bit value of the obtained drive control signal.
10. The voltage calibration method as described in claim 9, characterized in that, The preset bit value of the drive control signal varies within a preset range; the step of calibrating and storing the preset bit value of the drive control signal in the feedback control module in at least one scanning mode according to the calibration parameters further includes: One of the multiple scanning modes is selected as the scanning mode to be calibrated; In the calibration scan mode, the feedback control module outputs the initial bit value of the drive control signal to the charge pump module. When the clock control signal is valid, the charge pump module sets the number of switching elements turned on in the at least one dynamic switching unit according to the initial value of the drive control signal; the initial bit value is an intermediate bit value within the preset range. The feedback control module converts the sampling voltage to be calibrated output by the sampling module into a digital code value. Determine whether the digital code value is equal to the calibration code value; wherein, the calibration code value is the digital code value obtained by the feedback control module directly converting the sampling voltage corresponding to the calibration voltage; the calibration voltage is the power supply voltage output by the charge pump module when the bit value of the drive control signal is the upper limit threshold of the preset range in the reference scan mode; the reference scan mode is the scan mode with the highest power consumption; When the digital code value is not equal to the calibration code value, determine whether the digital code value is greater than the calibration code value; When the digital code value is greater than the calibration code value, the feedback control module controls the bit value of the drive control signal to be gradually adjusted upward from the initial bit value by a preset step size; When the digital code value is less than the calibration code value, the feedback control module controls the bit value of the drive control signal to be gradually adjusted downward from the initial bit value by a preset step size; When the digital code value is equal to the calibration code value, the feedback control module stores the current bit value of the drive control signal as the preset bit value of the drive control signal corresponding to the scan mode to be calibrated.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that can be executed by at least one processor, which, when executed by the at least one processor, implement the voltage calibration method as described in any one of claims 9 to 10.