FPGA (Field Programmable Gate Array) implementation method and system for channelized receiver of WOLA structure of non-radix-2-FFT (Fast Fourier Transform)

Abstract

The invention provides an FPGA (Field Programmable Gate Array) implementation method and system for a channelized receiver of a WOLA structure based on a non-radix-2-FFT (Fast Fourier Transform) in order to complete FPGA implementation of the channelized receiver of the WOLA structure, and belongs to the technical field of software radio. The method comprises the following steps: firstly, determining digital channelization parameters; then converting the single-path serial data into path parallel data through a two-stage serial-parallel conversion module and converting the single-path serial data into the path parallel data in a pipeline register mode; dividing the path parallel data and the inverted order filter coefficient into groups through an FIR grouping filtering module, then multiplying the corresponding data by the filter coefficient, and adding products in each group to obtain a path grouping filtering result; the point FFT is divided into levels for calculation through a parallel grouping multi-level FFT module; and finally, finishing the correction of the channelized data through an output correction module. The method is particularly suitable for FPGA implementation of a channelized receiver of a WOLA structure of the non-radix-2-FFT.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of software radio, and particularly relates to a field programmable gate array (FPGA) implementation method of a non-base-2-FFT (Fast Fourier Transform) weighted overlap-add (WOLA) channelized receiver. BACKGROUND

[0002] In the technical field of software radio, a digital channelized receiver has a high receiving sensitivity and a good frequency resolution, can effectively capture and detect signals in a frequency band, and has other advantages such as good adaptability and scalability, and has been a key research direction of software radio technology and has been widely applied in radar electronic warfare and wireless communication fields. The digital channelized receiver technology is to divide a received signal into each sub-channel, and then process the signals in each sub-channel, so as to form a parallel multi-channel architecture to realize high-speed signal capture and separation.

[0003] Common digital channelization structures can be divided into three types according to different principles: FFT-based digital channelization, multi-phase discrete Fourier transform (DFT)-based digital channelization, and WOLA structure digital channelization. Among the three types of digital channelization structures, the FFT-based digital channelization has a problem of inflexible channel division because the channel division is restricted by the FFT point number and the signal needs to be decomposed in the frequency domain by FFT; the multi-phase DFT-based digital channelization consumes less resources and is easy to implement in FPGA, but the extraction multiple and the channel number can only be a power of 2, and the two must be integer multiples of each other, which cannot meet special sub-channel bandwidth requirements. The WOLA structure digital channelization structure is more flexible, the extraction multiple and the channel number can not be a power of 2, and the two do not need to be integer multiples of each other, but the research on the non-base-2-FFT WOLA structure channelization has only been in the theoretical stage and has not been implemented in engineering.

[0004] Based on the above problems, the application provides a WOLA structure-based channelized receiver FPGA implementation method, in particular, a non-base-2-FFT WOLA structure channelized receiver FPGA implementation, which uses the flexibility of the WOLA structure to complete signal reception. SUMMARY

[0005] This invention aims to implement a channelized receiver based on the WOLA structure on an FPGA, particularly a WOLA channelized receiver with non-radix-2 FFT, and proposes an FPGA implementation method for a channelized receiver with a WOLA structure based on the WOLA structure.

[0006] To achieve the above objectives, the present invention provides the following solution: Firstly, the present invention provides an FPGA implementation method for a channelized receiver with a non-radix-2 FFT WOLA structure, the method comprising the following steps: Step 1: Determine the digital channelization parameters; Step 2: Construct a two-stage serial-to-parallel conversion module. The first-stage serial-to-parallel conversion is used to convert the sampling rate of the ADC output. Single-channel ADC data acquisition Convert to parallel data The second-level serial-to-parallel conversion is used to convert the output of the first-level serial-to-parallel conversion. parallel data Converted through a flow-through storage method parallel data ; Step 3: Construct an FIR group filtering module, used to first... parallel data With reverse order First-order filter coefficients Divided into Group the data, then multiply the corresponding data by the filter coefficients, and sum the products within each group to obtain the result. Path grouping filtering results ; Step 4: Construct a parallel grouped multi-level FFT module for use based on the... Path grouping filtering results ,Will Point FFT is divided into Calculations are performed at each level; Step 5: Construct an output correction module to input the I and Q signals from the parallel grouped multi-stage FFT outputs, along with the corresponding correction factors, into a complex multiplier to obtain... The I and Q data output by the channelization are used to complete the correction of the channelization data.

[0007] Furthermore, the aforementioned digital channelization parameters include the sampling rate. Extract multiple Number of channels filter order ; Filter order for and The least common multiple; and all data processing is performed within the clock. Completed.

[0008] Furthermore, the aforementioned number of channels Can be broken down into Factors that are not equal to 1 The product of.

[0009] Furthermore, based on the digital channelization parameter settings First-order filter coefficients .

[0010] Furthermore, the first-level serial-to-parallel conversion is performed using J204B serial-to-parallel conversion; the second-level serial-to-parallel conversion is performed using pipelined registers.

[0011] Furthermore, the above will Point FFT is divided into The specific calculation for each level is as follows: When performing the first-level FFT processing, first... Parallel FIR filtering data Divided into Groups, each group Data points, then parallel computation group Point FFT yields Road I and Q data; During the first Before performing FFT processing, first determine and Are they coprime? If and If the values ​​are not coprime, then the output of the previous stage needs to be multiplied by a rotation factor first. and If they are coprime, then there is no need to multiply by the rotation factor, and then... Road I and Q data are divided into Group, parallel computing group Point FFT yields Road I and Q data, ; After completion After FFT, we get FFT results .

[0012] Furthermore, the correction factor in the above-mentioned output correction module The real and imaginary parts are stored in registers respectively.

[0013] The second aspect, the FPGA implementation method of the channelization receiver of the non-base-2-FFT WOLA structure disclosed by the application can be implemented by using computer software, and therefore, the application further provides an FPGA implementation system of the channelization receiver of the non-base-2-FFT WOLA structure.

[0014] The third aspect, the application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is run by a processor to execute the FPGA implementation method of the channelization receiver of the non-base-2-FFT WOLA structure.

[0015] The fourth aspect, the application further provides a computer device, and the computer device comprises a memory and a processor, and the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes the FPGA implementation method of the channelization receiver of the non-base-2-FFT WOLA structure.

[0016] The application has the following beneficial effects: The application provides an FPGA implementation method of the channelization receiver of the non-base-2-FFT WOLA structure, and the method comprises the following steps: firstly, determining digital channelization parameters; then, building a two-stage serial-parallel conversion module, so that the first-stage serial-parallel conversion realizes serial-parallel conversion from high-speed single-channel serial data to low-speed multi-channel parallel data, and the second-stage serial-parallel conversion realizes the continuity of the parallel data in the time domain in a pipeline register mode; building an FIR grouping filter module, so that the continuous parallel data are subjected to grouping processing, each group of data is subjected to convolution operation by using a corresponding polyphase sub-filter group, and the required filtering and weighting of the WOLA structure are realized; building a parallel grouping multi-stage FFT module, so that the multi-channel parallel data filtered by the FIR grouping filter are input into a plurality of independent FFT modules in parallel for processing, the multi-stage decomposition FFT algorithm is used, the non-base-2-point fast Fourier transform is realized, and parallel calculation ensures the real-time performance of the channelization processing; and finally, completing correction of the channelized data by using an output correction module, so that the channelization receiver of the non-base-2-FFT WOLA structure is truly and effectively realized, and a great gap in engineering application of the non-base-2-FFT WOLA structure channelization is filled.

[0017] The application is suitable for FPGA implementation of the channelization receiver based on the WOLA structure, and in particular, for FPGA implementation of the non-base-2-FFT WOLA channelization receiver. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art of the present application, the drawings needed in the specific implementation or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without any creative effort.

[0019] Figure 1 is a flowchart of the FPGA implementation method of the non-base2-FFT WOLA channelization receiver described in the embodiments of the present application. Figure 2 is a flowchart of the FPGA implementation of the two-stage serial-parallel conversion described in the embodiments of the present application. Figure 3 is a flowchart of the FPGA implementation of the single-group FIR filtering described in the embodiments of the present application. Figure 4 is a flowchart of the FPGA implementation of the 20-point FFT described in the embodiments of the present application. Figure 5 is a flowchart of the FPGA implementation algorithm of the 5-point FFT described in the embodiments of the present application. Figure 6 is a test result chart of the FPGA implementation of the non-base2-FFT WOLA channelization receiver described in the embodiments of the present application. DETAILED DESCRIPTION

[0020] In the following description, the specific implementation details (such as experimental devices, operation processes, data processing steps, and example parameters) provided in the specification regarding "a FPGA implementation method of a channelization receiver with a non-base2-FFT WOLA structure" are fundamentally intended to be illustrative rather than limitative, and are intended to help those skilled in the art to thoroughly understand the principles and implementation of the present application; however, those skilled in the art should understand that these details only represent one of the possible embodiments, and the core concept of the present application can be implemented through other not-yet-described technical means or alternative schemes without departing from the spirit and essence thereof, and the omission of details of conventional experimental methods and devices in the specification is to avoid redundant information from interfering with the understanding of the innovative points, which does not mean that these well-known technologies are not needed in implementation, and those skilled in the art should be able to supplement and use them based on their professional knowledge.

[0021] The specific embodiments of the present application will be further described in detail below with reference to the accompanying drawings. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present application, and these changes and improvements are within the scope of protection of the present application.

[0022] Example 1, Combination Figure 1 This embodiment aims to implement a channelized receiver based on the WOLA structure on an FPGA, specifically a method for implementing a WOLA channelized receiver without radix-2 FFT on an FPGA. The method includes the following steps, the flow of which is as follows: Figure 1 As shown: Step 1: Determine the digital channelization parameters; Step 2: Construct a two-stage serial-to-parallel conversion module. The first-stage serial-to-parallel conversion is used to convert the sampling rate of the ADC output. Single-channel ADC data acquisition Convert to parallel data The second-level serial-to-parallel conversion is used to convert the output of the first-level serial-to-parallel conversion. parallel data Converted through a flow-through storage method parallel data ; Step 3: Construct an FIR group filtering module to convert... parallel data With reverse order First-order filter coefficients Divided into Group the data, then multiply the corresponding data by the filter coefficients, and sum the products within each group to obtain the result. Path grouping filtering results ; Step 4: Construct a parallel grouped multi-level FFT module for use based on the... Path grouping filtering results ,Will Point FFT is divided into Calculations are performed at each level; Step 5: Construct an output correction module to input the I and Q signals from the parallel grouped multi-stage FFT outputs, along with the corresponding correction factors, into a complex multiplier to obtain... The I and Q data output by the channelization are used to complete the correction of the channelization data.

[0023] Example 2: This example provides a detailed description of each step in the FPGA implementation method of a channelized receiver with a non-radix-2 FFT WOLA structure described in Example 1 above. Step 1: Determine the digital channelization parameters; Specifically: Based on the actual system requirements, determine the parameters for digital channelization, including the sampling rate. Extract multiple Number of channels ( It can be broken down into Factors that are not equal to 1 The product of, i.e. ), filter order ( for and If the least common multiples of the clock, then all data processing in the system occurs within the clock. Complete. Based on the digital channelization parameter settings. First-order filter coefficients .

[0024] Step 2: Construct a two-level serial-to-parallel conversion module; Specifically: The first-level serial-to-parallel conversion to J204B serial-to-parallel conversion is achieved by adjusting the sampling rate of the ADC output. Single-channel ADC data acquisition Convert to parallel data The second-level serial-to-parallel conversion is a pipelined register, which converts the J204B serial-to-parallel converter output... parallel data Converted through a flow-through storage method parallel data .

[0025] Step 3: Construct an FIR group filtering module, used to first... parallel data With reverse order First-order filter coefficients Divided into Group the data, then multiply the corresponding data by the filter coefficients, and sum the products within each group to obtain the result. Path grouping filtering results .

[0026] Step 4: Construct a parallel grouped multi-level FFT module for use based on the... Path grouping filtering results ,Will Point FFT is divided into Calculations are performed at each level; Specifically: Will Point FFT is divided into The calculation is performed at each level. When performing the first-level FFT processing, first... Parallel FIR filtering data Divided into Groups, each group Data points, then parallel computation group Point FFT yields Road I and Q data; During the first Before performing FFT processing, first determine and Are they coprime? If and If the values ​​are not coprime, then the output of the previous stage needs to be multiplied by a rotation factor first. and If they are coprime, then there is no need to multiply by the rotation factor, and then... Road I and Q data are divided into Group, parallel computing group Point FFT yields Road I and Q data, ; After completion After FFT, we get FFT results .

[0027] Step 5: Construct the output correction module; Specifically: Correction factor The real and imaginary parts are stored in registers respectively. Then, the I and Q signals output by the FFT, along with the corresponding correction factors, are input into a complex multiplier to finally obtain... The I and Q data output by the channelization are used to complete the correction of the channelization data.

[0028] Example 3, Combination Figures 2 to 5 This embodiment describes a specific implementation method for comprehensively explaining the FPGA implementation method of a channelized receiver with a non-radix-2 FFT WOLA structure as described in any of the above embodiments.

[0029] The core idea of ​​WOLA channelization is to divide a broadband signal into multiple narrow sub-band signals. for The coefficients of the prototype filter bank are uniformly distributed across the sub-channels, and the number of sub-channels is [number missing]. The extraction multiplier is Then the first The output of each sub-channel is shown in formula (1): (1) In the formula, It is the delay parameter of the time window, let ,but Right now Discrete Fourier Transform, In the above formula When the input signal changes, the window remains unchanged. The coefficients of the prototype filter are in reverse order, each Corresponding to Each output value, when In order to perform FFT operations, it is necessary to... Fold into The sequence of points, each Each point is grouped together, and the corresponding points in each group are summed up to form a new group, i.e.: (2) Therefore, we can conclude that: (3) The FFT algorithm uses a mixed basis algorithm. For simplicity, this section only introduces the two-level mixed basis FFT algorithm. First, let's consider the one-dimensional... Point FFT decomposes into two dimensions Point FFT. The formula for point FFT is as follows: (4) Redefining and : (5) Substituting equation (5) into equation (4), we get: (6) This transforms a one-dimensional FFT into a two-dimensional FFT. First, calculate... indivual The point-wise DFT is then performed, and the result is multiplied by the rotation factor. Finally, calculate indivual The point-wise DFT is used to ultimately obtain the FFT output. If , If the bases are coprime, the step of multiplying by the rotation factor can be omitted using the rules of the prime factorization algorithm. In this case, the mixed-basis FFT algorithm becomes: (7) Although the step of multiplying by the rotation factor can be omitted, The definition will also change accordingly: (8) like (or It can also be decomposed into the product of two or more numbers, and then the above process can be applied to... Point DFT (or The point DFT can be decomposed using mixed-base FFT.

[0030] The specific implementation method includes the following steps: Step 1: Determine the digital channelization parameters. To facilitate a detailed description of the FPGA design method, the sampling rate will be used below. Extraction multiplier Total number of channels and filter order Then all data processing in the system is done within the clock. The following steps are completed. The clock signal is generated by multiplying the 50MHz output from the crystal oscillator through the Digital Clock Manager (DCM). The passband of the 120th-order FIR filter is set to 25MHz and the stopband to 50MHz, resulting in the 120th-order filter coefficients. The parameters selected in this embodiment are merely for ease of description. Various parameters can be chosen, and those skilled in the art can make various corresponding changes and modifications based on this invention without departing from its spirit and essence. However, all such corresponding changes and modifications should fall within the protection scope of the appended claims.

[0031] Step 2: The two-stage serial-to-parallel conversion module, its FPGA implementation process is as follows: Figure 2 As shown. The first-stage serial-to-parallel conversion is performed using the J204B serial-to-parallel converter, which acquires data via a single 1GHz ADC. The J204B interface IP core handles data transmission from a single 1GHz serial stream to eight 125MHz parallel streams. The serial-to-parallel conversion is performed. The second-stage serial-to-parallel conversion pipelined register module converts the J204B serial-to-parallel conversion output into 8 parallel data streams. A reverse-order input pipeline register is used to ensure the continuity of parallel data in the time domain. After a 15-clock delay, 120 parallel data streams are obtained by reversing the order. .

[0032] Step 2: The FPGA implementation process of the FIR group filtering module is as follows: Figure 3 As shown. For 120 parallel data streams... and the reversed order of the 120th order filter coefficients Grouping is performed according to formula (9). After grouping, the branch filter coefficients at the corresponding positions of each group are multiplied by the parallel data input parallel multiplier. The outputs of the 6 multipliers in each group are summed to obtain 20 channels of FIR filter data. .

[0033] (9) Step 3: Parallel grouping multi-stage FFT module, FPGA implementation process as shown in Figure 4 The 20-way parallel FIR filtered data is divided into 4 groups according to formula (10).

[0034] (10) wherein, represents is the number of the th in the th group. After grouping, each group of data is input to a 5-point DFT module to obtain the 5-point DFT result of each group; since 4 and 5 are co-prime, no rotation factor needs to be multiplied here; then the same I, Q data in each group of 5-point DFT results is input to a 4-point DFT module, and the result of the 4-point DFT module is reordered according to formula (11) to obtain the I, Q data of the 20-point FFT output .

[0035] (11) Step 3.1: 5-point DFT module, FPGA implementation algorithm flowchart as shown in Figure 5 The implementation of 5-point DFT adopts Winograd circular convolution algorithm, which is shown in formula (12): (12) As can be seen from formula (12), the implementation of 5-point DFT mainly has three steps: data preprocessing, rotation factor multiplication, and data addition.

[0036] Data preprocessing: the first level operation is performed. Since no input data is used in the first level operation, and the second level operation needs input data , the is delayed by one clock cycle while is calculated; Rotation factor: store , , and in the register, then calculate the rotation factor multiplication result , and at the same time, delay and by one clock cycle for subsequent processing; Data addition: input to the adder to calculate according to the adder in formula (12), and delay and With Input adder, calculate 5-point FFT result.

[0037] Step 3.2: 4-point DFT module. The 4-point FFT also uses Winograd circular convolution algorithm, which is shown in formula (13): (13) As can be seen from formula (13), the processing flow of 4-point FFT is mainly the addition and subtraction of 4 numbers, and the input data is input into the adder for operation to obtain the result of 4-point DFT, that is, the I and Q data of 20-point FFT output.

[0038] Step 4: correction factor module. According to the set digital channelization parameters, the correction factor of the first road is , which is about the sub-channel and the time variable is 5 periods. The FFT is divided into 4 groups in order, and the correction factors of and are calculated and stored in the register; a cycle counter with a period of 5 clock cycles is set, and the I and Q data of the current time FFT and the corresponding correction factor are input into the complex multiplier according to the count, completing the correction of 20-channelized data, and finally obtaining the I and Q data of 20-channelized output.

[0039] Example four, combining Figure 6 to illustrate this embodiment, in order to verify the effectiveness of the present application, an experimental environment is built. The FPGA chip selected is XCVU13P, and the ADC model is AD9689, with a sampling frequency of 1GHz. The resource usage of this embodiment is shown in Table 1, and the total system delay is 24 clock cycles. The FPGA signal generator DSG3030 outputs a single-point frequency signal with a frequency of 205MHz, and the channelization result is shown in Figure 6 . As can be seen from Figure 6 , there is a signal in the 5th channel (175MHz-225MHz), which proves that the method described in the present application can complete the digital channelization reception of the measured signal.

[0040] Table 1

[0041] Example five, the channelization receiver FPGA implementation method of the non-base2-FFT WOLA structure described in any one of the above embodiments can be all implemented by computer software, therefore, corresponding, this embodiment provides a channelization receiver FPGA implementation system of the non-base2-FFT WOLA structure, the system comprises: Storage device for digital channelization parameter determination Storage device for constructing two-stage serial-parallel conversion module, the first stage serial-parallel conversion is used for converting the sampling rate of ADC output single-channel ADC collected data to parallel data , the second stage serial-parallel conversion is used for converting the parallel data of output by the first stage serial-parallel conversion to parallel data by means of pipeline register Storage device for constructing FIR grouping filter module, first, the parallel data of is divided into groups with the filter coefficients of order in reverse order , then the corresponding data is multiplied by the filter coefficients, and the products in each group are added to obtain the grouping filter result of Storage device for constructing parallel grouping multi-stage FFT module, according to the grouping filter result of , the point FFT is divided into stages for calculation Storage device for constructing output correction module, used for inputting the I, Q signals of parallel grouping multi-stage FFT output and the corresponding correction factors into a complex multiplier to obtain the I, Q data of channelization output, and complete the correction of channelization data

[0042] Embodiment six, the embodiment provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is run by a processor to execute the FPGA implementation method of the channelization receiver of the WOLA structure of non-base 2-FFT in any one of the above embodiments.

[0043] ​​​​​Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing the relevant hardware. The program can be stored in a computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid state drive (SSD), etc. The storage medium can also include a combination of the above-mentioned types of memories.

[0044] Embodiment seven, the embodiment provides a computer device, the device includes a memory and a processor, the memory stores a computer program, when the processor runs the computer program stored in the memory, the processor executes the channelization receiver FPGA implementation method of the non-base 2-FFT WOLA structure of any one of the above-mentioned embodiments.

[0045] The computer device provided by the embodiment, the hardware devices of this part are general models, which are not represented in the form of drawings. The system includes a processor and a memory, wherein the processor and the memory can be connected through a bus or other means. The memory is a non-transitory computer readable storage medium, which can be used to store non-transitory software programs, non-transitory computer executable programs and modules, and corresponding program instructions / modules. The processor executes various functions of the processor and data processing by running the non-transitory software programs, instructions and modules stored in the memory, so as to realize the channelization receiver FPGA implementation method and steps of the non-base 2-FFT WOLA structure.

[0046] The memory can include a program storage area and a data storage area. The program storage area can store an operating system and at least one application required by a function. The data storage area can store data created by the processor, etc. In addition, the memory can include a high-speed random access memory and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, an extranet, a mobile communication network, and a combination thereof.

[0047] One or more modules are stored in the memory, and when the processor executes, the method steps in the embodiments are executed, so that the inventive purpose of the present application can be achieved through the method and device, process of the present application. The above computer device specific details can be understood by referring to the corresponding description and effect in the embodiments, which will not be repeated here.

[0048] The above further describes the technical solutions provided by the present application through several specific embodiments, in order to highlight the advantages and benefits of the technical solutions provided by the present application. However, the above several specific embodiments are not used as a limitation of the present application, and any reasonable changes and improvements, reasonable combinations and equivalent replacements of the embodiments, etc. based on the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A non-base 2-FFT WOLA structure channelization receiver FPGA implementation method, characterized in that, Step 1: digital channelization parameter determination; Step 2: Constructing two-stage serial-parallel conversion module, the first stage serial-parallel conversion is used to convert the sampling rate of ADC output single-channel ADC collected data to parallel data , the second stage serial-parallel conversion is used to convert the parallel data output by the first stage serial-parallel conversion to parallel data by means of flow register; Step 3: Construct an FIR group filtering module, used to first... parallel data With reverse order First-order filter coefficients Divided into Group the data, then multiply the corresponding data by the filter coefficients, and sum the products within each group to obtain the result. Path grouping filtering results ; Step 4: Construct a parallel grouped multi-stage FFT module for calculating the result of the filtering according to the grouped filtering result , the point FFT is divided into stages for calculation; Step 5: Constructing an output correction module for inputting the I, Q signals of the parallel grouped multi-stage FFT output and the corresponding correction factors into a complex multiplier to obtain the I, Q data of the channelized output, completing the correction of the channelized data.

2. The channelized receiver FPGA implementation method of non-base 2-FFT WOLA structure according to claim 1, characterized in that, The digital channelization parameters include a sampling rate , a decimation factor , a number of channels , a filter order ; Filter order For With The common multiple; and data processing is all done under the clock under the clock 3. The method of claim 2, wherein the non-base 2-FFT WOLA structure channelized receiver FPGA implementation method is characterized by, Number of channels Resolvable into Factors other than 1 The product of.

4. The channelized receiver FPGA implementation method of non-base 2-FFT WOLA structure according to claim 2, wherein, Setting digital channelization parameters Filter coefficients .

5. The non-base 2-FFT WOLA structure channelization receiver FPGA implementation method according to claim 1, wherein the first-stage serial-parallel conversion is a J204B serial-parallel conversion, and the second-stage serial-parallel conversion is a pipeline register.

6. The channelized receiver FPGA implementation method of non-base 2-FFT WOLA structure according to claim 1, wherein, The FFT is divided into points FFT is divided into stages, and the calculation is specifically When the first-stage FFT processing is performed, the data are first divided into parallel FIR filtering data groups, and each group has data, and then the data of each group are calculated in parallel point FFT to obtain parallel I and Q data;​​ During the first Before performing FFT processing, first determine and Are they coprime? If and If the values ​​are not coprime, then the output of the previous stage needs to be multiplied by a rotation factor first. and If they are coprime, then there is no need to multiply by the rotation factor, and then... Road I and Q data are divided into Group, parallel computing group Point FFT yields Road I and Q data, ; After completing the level FFT, the result is the road FFT result .

7. The method of claim 1, wherein the non-base 2-FFT WOLA structure channelized receiver FPGA implementation method is characterized by, Correction factors in an output correction module The real and imaginary parts of the complex number are stored in registers, respectively.

8. A non-base 2-FFT WOLA structure channelized receiver FPGA implementation system, characterized in that, The system is implemented based on the non-base 2-FFT WOLA structure channelization receiver FPGA implementation method of any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a processor to perform the non-base 2-FFT WOLA structure channelization receiver FPGA implementation method of any one of claims 1-7.

10. A computer device, comprising: The device comprises a memory and a processor, and the memory stores a computer program, and when the processor executes the computer program stored in the memory, the processor executes the non-base 2-FFT WOLA structure channelization receiver FPGA implementation method of any one of claims 1-7.

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