Delay-tolerant reporting method, pcie switch and storage medium

Abstract

The embodiment of the application discloses a delay tolerance reporting method, a PCIe switch and a storage medium. The method comprises the following steps: a downlink port module generates a delay tolerance message based on a first delay tolerance message, transmits the delay tolerance message to an uplink port module in the same partition according to a standard TLP message routing mechanism, generates a second delay tolerance message based on a minimum delay tolerance value, and controls the uplink port module to report the second delay tolerance message to a root complex. The embodiment of the application generates a delay tolerance message based on a first delay tolerance message, transmits the delay tolerance message from a downlink port module to an uplink port module in the same partition according to a standard TLP message routing mechanism, does not need to set a complex hardware signal line, and only transmits the delay tolerance message to the uplink port module in a software mode. The uplink port module collects delay tolerance values transmitted by each downlink port module, and then finds a minimum delay tolerance value, thereby reducing the occupation of physical resources.

Description

Technical Field

[0001] This application relates to the field of PCIe switch technology, and in particular to a latency tolerance reporting method, a PCIe switch, and a storage medium. Background Technology

[0002] The Latency Tolerance Reporting (LTR) mechanism is an important link management mechanism that allows PCIe (Peripheral Component Interconnect Express) devices to report their maximum tolerable latency threshold to the root federation. In the PCIe protocol, PCIe switches support the LTR mechanism. When a PCIe switch connects to multiple port devices that support LTR, the PCIe switch needs to perform a global minimum aggregation operation: finding the minimum latency tolerance value among the latency tolerance values ​​reported by each port device and reporting this minimum latency tolerance value to the root federation. To achieve this, related technologies require establishing a large number of hardware signal lines inside the PCIe switch to report the latency tolerance values ​​of different port devices to the root federation. This consumes excessive physical resources within the PCIe switch, reducing its operating efficiency. Summary of the Invention

[0003] One objective of this application is to provide a latency tolerance reporting method, a PCIe switch, and a storage medium to improve the situation where related technologies require excessive physical resources when aggregating latency tolerance values ​​of various port devices.

[0004] In a first aspect, embodiments of this application provide a latency tolerance reporting method applied to a PCIe switch. The PCIe switch is configured with multiple port modules. The latency tolerance reporting method includes: responding to port configuration information sent by the root federation, performing port configuration operations on the multiple port modules to obtain uplink port modules and at least one downlink port module in different partitions; obtaining a first latency tolerance message transmitted by a port device received by the downlink port module; responding to the downlink port module detecting that the port device meets the latency change condition, controlling the downlink port module to generate a latency tolerance message based on the first latency tolerance message. The latency tolerance message carries a latency tolerance value after the latency change. The latency tolerance message belongs to the message message type in the TLP message specified by the PCIe protocol. According to the standard TLP message routing mechanism, the latency tolerance message is transmitted from the downlink port module to the uplink port module in the same partition. Controlling the uplink port module to find the minimum latency tolerance value based on the latency tolerance messages of each downlink port module in the same partition; responding to the uplink module detecting that the PCIe switch is in a latency tolerance reporting state, generating a second latency tolerance message based on the minimum latency tolerance value; and controlling the uplink port module to report the second latency tolerance message to the root federation.

[0005] Optionally, the control uplink port module finds the minimum latency tolerance value based on the latency tolerance messages of each downlink port module in the same partition, including: the control uplink port module extracts the latency tolerance value from the latency tolerance messages of the downlink modules in the same partition, the control uplink port module records each latency tolerance value in a preset latency statistics table, and finds the minimum latency tolerance value in the latency statistics table.

[0006] Optionally, in accordance with the standard TLP message routing mechanism, the delay-tolerant message is transmitted from the downlink port module to the uplink port module in the same partition, including: obtaining the delay-tolerant message transmitted by the downlink port module; in response to the delay-tolerant message being an abnormal message, notifying the downlink port module to retransmit the delay-tolerant message; and in response to the delay-tolerant message being a normal message, transmitting the delay-tolerant message to the uplink port module in the same partition in accordance with the standard TLP message routing mechanism.

[0007] Optionally, the delay tolerance message also carries a downlink port number. In response to the delay tolerance message being an abnormal message, the downlink port module is notified to retransmit the delay tolerance message, including: in response to the delay tolerance message being an abnormal message, extracting the downlink port number from the delay tolerance message, and notifying the downlink port module that matches the downlink port number to retransmit the delay tolerance message.

[0008] Optionally, in response to the uplink port module detecting that the PCIe switch is in a latency tolerance reporting state, a second latency tolerance message is generated based on the minimum latency tolerance value, including: in response to the uplink port module detecting that the PCIe switch is in a latency tolerance reporting state, subtracting a preset transmission delay value from the minimum latency tolerance value to obtain a final latency tolerance value, detecting whether the final latency tolerance value is greater than a preset latency threshold, if the final latency tolerance value is greater than the preset latency threshold, determining the preset latency threshold as the target latency threshold, and generating a second latency tolerance message based on the target latency threshold; if the final latency tolerance value is less than or equal to the preset latency threshold, determining the final latency tolerance value as the target latency threshold, and generating a second latency tolerance message based on the target latency threshold.

[0009] Optionally, controlling the uplink port module to report the second delay tolerance message to the root union includes: determining the past duration of the uplink port module sending the most recent delay tolerance information to the root union, and in response to the past duration being equal to a preset period, controlling the uplink port module to report the second delay tolerance message to the root union.

[0010] Optionally, in response to the downlink port module detecting a delay change condition, the downlink port module is controlled to generate a delay-tolerant message based on the first delay-tolerant message, including: in response to the downlink port module detecting a change in the delay requirement of the port device, the downlink port module is controlled to generate a delay-tolerant message; or, in response to the downlink port module detecting a change in the parameters of the SNOOP delay or the NO SNOOP delay, the downlink port module is controlled to generate a delay-tolerant message; or, in response to the downlink port module receiving a message retransmission information sent by the internal virtual bus of the PCIe switch, the downlink port module is controlled to retransmit the delay-tolerant message.

[0011] Optionally, the delay tolerance reporting method further includes: in response to the downlink port module detecting that the communication link between the port device and the PCIe switch is disconnected, controlling the downlink port module to send an invalid message to the uplink port module so that the uplink port module clears the delay tolerance data about the downlink port module; or, in response to the delay tolerance mechanism of the downlink port module being turned off, controlling the downlink port module to send an invalid message to the uplink port module so that the uplink port module clears the delay tolerance data about the downlink port module, wherein the invalid message belongs to the message type in the TLP message specified by the PCIe protocol.

[0012] Optionally, in response to the port configuration information sent by the root union, a port configuration operation is performed on multiple port modules, including: obtaining the port configuration information sent by the root union, the port configuration information being used to indicate that uplink port modules belonging to the same partition are configured as downlink port modules; in response to the port configuration information, clearing the latency tolerance data of the uplink port modules; and configuring the uplink port modules as downlink port modules.

[0013] Optionally, in response to port configuration information sent by the root union, port configuration operations are performed on multiple port modules, including: obtaining port configuration information sent by the root union, the port configuration information being used to indicate that downlink port modules belonging to the same partition are configured as uplink port modules, and in response to the port configuration information, configuring the downlink port modules as uplink port modules.

[0014] Optionally, in response to the port configuration information sent by the root union, a port configuration operation is performed on multiple port modules, including: obtaining the port configuration information sent by the root union, the port configuration information being used to indicate that the downlink port module of the initial partition is configured as the downlink port module or uplink port module of the specified partition; in response to the port configuration information, sending a first clear message to the uplink port module of the initial partition to clear the delay-tolerant data of the downlink port module of the initial partition, the first clear message being of the message type in the TLP message specified by the PCIe protocol, and configuring the downlink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

[0015] Optionally, in response to the port configuration information sent by the root union, a port configuration operation is performed on multiple port modules, including: obtaining the port configuration information sent by the root union, the port configuration information being used to indicate that the uplink port module of the initial partition is configured as a downlink port module or an uplink port module of the specified partition; in response to the port configuration information, sending a second clear message to the root union of the initial partition, so that the root union of the initial partition clears the delay-tolerant data about the uplink port module of the initial partition, the second clear message being a message message type in the TLP message specified by the PCIe protocol, and configuring the uplink port module of the initial partition as a downlink port module or an uplink port module of the specified partition.

[0016] In a second aspect, embodiments of this application provide a PCIe switch, including a memory and a processor. The memory is connected to the processor, and the processor is used to execute one or more computer programs stored in the memory. When the processor executes one or more computer programs, it causes the PCIe switch to implement the aforementioned latency tolerance reporting method.

[0017] In a third aspect, embodiments of this application provide a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the aforementioned latency tolerance reporting method.

[0018] The embodiments of this application can achieve the following technical effects: The embodiments of this application generate a delay tolerance message based on the first delay tolerance message, and then transmit the delay tolerance message from the downlink port module to the uplink port module in the same partition according to the standard TLP message routing mechanism. There is no need to set up complex hardware signal lines. The delay tolerance message can be transmitted to the uplink port module only through software, so that the uplink port module can aggregate the delay tolerance values ​​transmitted by each downlink port module, and finally find the minimum delay tolerance value, thereby reducing the occupation of physical resources. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a PCIe switch system architecture provided for related technologies;

[0021] Figure 2 A flowchart illustrating a delay tolerance reporting method provided in an embodiment of this application;

[0022] Figure 3 A schematic diagram of a PCIe switch provided in this application embodiment;

[0023] Figure 4 A schematic diagram illustrating the data format of a delay-tolerant message provided in an embodiment of this application;

[0024] Figure 5 A schematic diagram of a delay statistics table provided in an embodiment of this application;

[0025] Figure 6 A schematic diagram of a PCIe switch system architecture is provided for another embodiment of this application;

[0026] Figure 7 A schematic diagram of a PCIe switch provided in another embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of a delay tolerance reporting device provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of a PCIe switch provided in an embodiment of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0030] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0031] To address the bandwidth limitations of the traditional PCI protocol, an Intel-led working group and the PCI-SIG launched PCIe in 2002. PCIe is a high-speed serial computer expansion bus standard, featuring high-speed serial point-to-point dual-channel high-bandwidth transmission. Connected devices are allocated dedicated channel bandwidth and do not share bus bandwidth. It primarily supports active power management, error reporting, end-to-end reliable transmission, hot-plugging, and Quality of Service (QoS) features.

[0032] As a next-generation serial bus, PCIe employs a point-to-point topology and differential signal transmission, with each port device having its own dedicated bandwidth, completely eliminating the bottleneck of parallel shared buses. In PCIe version 1.0, the initial speed per channel reached 2.5GT / s. Subsequent iterations through protocol optimization (such as improved coding efficiency and upgraded modulation technology) are expected to achieve 128GT / s per channel in PCIe 7.0. PCIe not only boasts compatibility with PCI's software architecture but also, with its high bandwidth and low latency characteristics, has become the core standard for connecting high-speed devices such as CPUs, GPUs, and NVMe SSDs.

[0033] As the number of port devices supporting the PCIe protocol increases, devices such as graphics cards and NVMe solid-state drives are prone to resource contention due to their different latency sensitivities and bandwidth requirements. To address this, PCIe version 3.0 introduced the LTR mechanism. Port devices proactively report latency tolerance values ​​based on the LTR mechanism. In complex topologies, PCIe switches can also achieve end-to-end collaboration, enabling the system to shift from passive response to proactive demand awareness, ensuring latency-sensitive tasks and improving bandwidth utilization, thus laying the foundation for the interconnection of larger-scale devices in the future.

[0034] The root consortium, based on the LTR mechanism, can optimize data transmission scheduling strategies based on report information. For example, for latency-sensitive devices (such as GPUs), transmission resources are allocated preferentially to reduce latency; for devices with higher latency tolerance (such as some storage peripherals), transmission priorities can be adjusted appropriately. Therefore, the LTR mechanism improves the resource utilization of the PCIe bus and optimizes the overall system performance.

[0035] PCIe switches collect the LTR values ​​of each port device based on the LTR mechanism, select the minimum LTR value as the global LTR value of the PCIe switch, and send the minimum LTR value to the root federation using LTR messages.

[0036] Please see Figure 1 The PCIe switch 100 is configured with a first partition 10a and a second partition 10b. The first partition 10a is connected to the first root junction 11a, and the second partition 10b is connected to the second root junction 11b.

[0037] Both the first partition 10a and the second partition 10b are configured with multiple port modules. For example... Figure 1 As shown, the first partition 10a is configured with port module 11, port module 12, and port module 13. Port module 11 is configured as an uplink port module for communication with the first root union 11a. Port modules 12 and 13 are configured as downlink port modules for communication with port module 11. Port module 12 interfaces with port device 12a, and port module 13 interfaces with port device 12b.

[0038] The second partition 10b is configured with port modules 14, 15, and 16. Port module 14 is configured as an uplink port module for communication with the second root union 11b. Port modules 15 and 16 are configured as downlink port modules for communication with port module 14. Port module 15 interfaces with port device 13a, and port module 16 interfaces with port device 13b.

[0039] In related technologies, since the root union of each partition is different, each partition needs to independently determine the corresponding minimum LTR value and report the corresponding minimum LTR value to the corresponding root union.

[0040] To collect the latency tolerance values ​​sent by each downlink port module to the uplink port module, related technologies require establishing hardware signal lines between the uplink port module and each downlink port module, such as... Figure 1 As shown, port module 11 establishes hardware signal lines with port modules 12 and 13 respectively. However, this is the case when port module 11 is an uplink port module.

[0041] When port module 12 is configured as an uplink port module, and port modules 11 and 13 are downlink port modules, the relevant technologies still require establishing logical connections between port module 12 and port modules 11 and 13, respectively. Thus, the relevant technologies need to establish complex hardware signal lines within the same partition, and this situation only applies to the case of the same partition.

[0042] When different port modules are flexibly divided into different partitions, for example, port modules 11, 12, and 14 are divided into the first partition 10a, and port modules 13, 15, and 16 are divided into the second partition 10b, in order to achieve the aggregation of latency tolerance values ​​for each port module, the relevant technology still needs to establish hardware signal lines between port module 14 and port modules 11 and 12 respectively, and between port module 13 and port modules 15 and 16 respectively. Thus, the PCIe switch 100 needs to establish complex hardware signal lines between each port module, which consumes a lot of physical resources.

[0043] The following embodiment of this application provides a latency tolerance reporting method applied to a PCIe switch, wherein the PCIe switch is configured with multiple port modules. Please refer to... Figure 2 The embodiment of this application implements the delay tolerance reporting method through steps S21 to S27, as detailed below:

[0044] Step S21: In response to the port configuration information sent by the root union, perform port configuration operations on multiple port modules to obtain uplink port modules and at least one downlink port module under different partitions.

[0045] The Root Complex (RC) serves as a bridge connecting the PCIe bus domain with the processor and system memory, and can be integrated into the PCIe controller.

[0046] Port configuration information configures the operating mode of each port module in the PCIe switch. Port modules connect to their corresponding port devices and can be configured as uplink or downlink port modules. Uplink port modules are ports that point to the root union and communicate with it, used to transmit data or report status. In multi-zone PCIe switches, each zone has one uplink port module, connected to the root union of that zone. It aggregates the latency tolerance values ​​of all downstream port devices in that zone, finds the minimum latency tolerance value, and reports it to the corresponding root union. Downlink port modules are ports that point to port devices and are responsible for receiving commands from the uplink port modules or sending messages or data to them.

[0047] Please see Figure 3 The PCIe switch 300 is configured with a third partition 30a and a fourth partition 30b. The third partition 30a is connected to the third root union 31a, and the fourth partition 30b is connected to the fourth root union 31b.

[0048] Both the third partition 30a and the fourth partition 30b are configured with multiple port modules. For example... Figure 3 As shown, the third partition 30a is configured with port module 31, port module 32, and port module 33. Port module 31 is configured as an uplink port module for communication with the third root union 31a. Port modules 32 and 33 are configured as downlink port modules for communication with port module 31. Port module 32 interfaces with port device 32a, and port module 33 interfaces with port device 32b.

[0049] The fourth partition 30b is configured with port modules 34, 35, and 36. Port module 34 is configured as an uplink port module for communication with the fourth root union 31b. Port modules 35 and 36 are configured as downlink port modules for communication with port module 34. Port module 35 interfaces with port device 33a, and port module 36 interfaces with port device 33b.

[0050] Step S22: Obtain the first delay tolerance message transmitted by the downlink port module receiving port device.

[0051] The first delay-tolerance message is a message conforming to the LTR mechanism. The port device generates the first delay-tolerance message and sends it to the downlink port module. According to the requirements of the LTR mechanism, the LTR message is a locally terminated routing message, meaning the first delay-tolerance message is a locally terminated routing message.

[0052] "Local Termination Type" is a core concept describing the routing and processing scope of message packets (or transactions). Messages of this type are only received, processed, and terminated at the "local device / port level" and are not forwarded to other devices within the bus domain or to higher-level ports (such as uplink port modules). In short, the "lifecycle" of a locally terminated type routed message is limited to the port module that receives it and requires no further propagation. However, the port module receiving the locally terminated type routed message will still parse it, but will not forward it to the uplink port module. Therefore, when the downlink port module receives the first delay tolerance message transmitted by the port device, it parses the first delay tolerance message, extracts the delay tolerance value, but does not forward the first delay tolerance message to the uplink port module.

[0053] Step S23: In response to the downlink port module detecting that the port device meets the delay change condition, the downlink port module is controlled to generate a delay tolerance message based on the first delay tolerance message.

[0054] The delay tolerance message is a vendor-defined message (VDM), which belongs to the message type in the TLP message specified by the PCIe protocol. As mentioned above, the first delay tolerance message is a local termination type routing message. In order for the uplink port module to collect the delay tolerance values ​​of each downlink port module, this application embodiment needs to use the delay tolerance message as a carrier to carry the transmission of the delay tolerance value.

[0055] The delay tolerance message carries the delay tolerance value after the delay changes. Specifically, the downlink port module parses the delay tolerance value from the first delay tolerance message, encapsulates the delay tolerance value in a delay tolerance message according to the data format requirements of the TLP message specified in the PCIe protocol, so as to transmit the delay tolerance message to the root union.

[0056] Please see Figure 4 The message code field is used to distinguish message types. The Request ID includes the Bus, Device, and Function numbers of the downlink port module that sent the message. The Tag field stores the port number of the downlink port module that sent the message, so that the uplink port module can distinguish the source of the delay-tolerant message. Bytes 12-15 are used to record the delay tolerance value.

[0057] The conditions for delay changes are quite diverse. All embodiments of this application are able to detect different delay change conditions and control the downlink port module to generate a delay-tolerant message based on the first delay-tolerant message, as detailed below:

[0058] 1.1) The delayed demand has changed.

[0059] In this embodiment of the application, when the latency requirement changes, the downlink port module is controlled to generate a latency tolerance message based on the first latency tolerance message through step A, as follows: Step A, in response to the downlink port module detecting a change in the latency requirement of the port device, the downlink port module is controlled to generate a latency tolerance message.

[0060] For example, when a port device changes its core latency requirement type (such as "low latency priority" or "high throughput priority"), such as when a graphics card switches from 2D mode to 3D rendering mode, the graphics card's latency requirement changes significantly. The graphics card generates first latency change information and sends it to the downlink port module. The downlink port module detects the first latency change information and determines that the graphics card's latency requirement has changed, meaning the downlink port module has detected that the port device meets the latency change condition. As another example, when an SSD chip switches from "power-saving mode" (allowing higher latency) to "high-performance mode" (requiring low latency), the SSD chip generates second latency change information and sends it to the downlink port module. The downlink port module detects the second latency change information and determines that the SSD chip's latency requirement has changed.

[0061] 1.2) The value or scale of the SNOOP delay or NO SNOOP delay changes.

[0062] In this embodiment of the application, when the value or scale of the Snoop delay or the NO Snoop delay changes, the downlink port module is controlled to generate a delay-tolerant message based on the first delay-tolerant message through step B, as follows: Step B, in response to the downlink port module detecting that the parameter of the Snoop delay or the parameter of the NO Snoop delay has changed, the downlink port module is controlled to generate a delay-tolerant message.

[0063] SNOOP latency, or Cache Coherence Snooping Latency, refers to the time required for a transaction (such as CPU access to shared memory) that needs to trigger a cache consistency check to complete from the time the request is sent.

[0064] NO SNOOP latency, also known as non-cached-coherent latency or no-snoop latency, refers to the time required for a transaction that does not require a cache consistency check (such as a GPU directly accessing non-cacheable memory) to complete from the time the request is issued.

[0065] The parameters of the SNOOP delay include a value or a scale. When both the value and the scale change, the port device generates a third delay change information and sends the third delay change information to the downlink port module. The downlink port module detects the third delay change information and determines that the graphics card's latency requirement has changed, that is, the downlink port module detects that the port device meets the latency change condition.

[0066] 1.3) The PCIe switch’s internal virtual bus indicates that the delay-tolerant message (LTR VDM) was not delivered correctly.

[0067] In this embodiment of the application, when the internal virtual bus indication delay tolerance message (LTR VDM) of the PCIe switch is not delivered correctly, the downlink port module is controlled to generate a delay tolerance message based on the first delay tolerance message through step C, as follows: Step C, in response to the downlink port module receiving the message retransmission information sent by the internal virtual bus of the PCIe switch, the downlink port module is controlled to retransmit the delay tolerance message.

[0068] The Internal Virtual Bus is a set of logical channels within a PCIe switch used to connect multiple ports and achieve efficient data routing and resource scheduling. It can solve the problems of concurrent communication, transaction ordering and bandwidth allocation between multiple ports of a PCIe switch through a hardware logic or firmware-defined virtual connection architecture.

[0069] Delay-Tolerant Messages (LTR VDMs) are “unacknowledged messages” (no explicit ACK required). However, the PCIe internal virtual bus detects whether the delay-tolerant message has been successfully sent through hardware logic (e.g., TLP check error, routing failure). If the delay-tolerant message is detected to have failed to be sent, the downlink port module is triggered to retransmit the delay-tolerant message, thereby ensuring that the uplink port module can reliably obtain the delay tolerance value.

[0070] This application embodiment can not only control the downlink port module to send delay-tolerant messages when the port device meets the delay variation conditions, but also control the downlink port module to no longer support the LTR function. Specifically, it is shown below:

[0071] 2.1) The downlink port module experiences a Link Down (communication link disconnected).

[0072] In the case of a link down event in the downlink port module, this embodiment controls the downlink port module to send an invalid message to the uplink port module via step D, as follows: Step D, in response to the downlink port module detecting that the communication link between the port device and the PCIe switch has been disconnected, controls the downlink port module to send an invalid message to the uplink port module so that the uplink port module clears the latency tolerance data of the downlink port module.

[0073] Invalid messages belong to the message type in the TLP message defined by the PCIe protocol. When the downlink port module detects that the communication link between the port device and the PCIe switch has been disconnected, the downlink port module has no connected port device, meaning that the downlink port module no longer has a need to send latency tolerance values. The downlink port module sends an invalid message to the uplink port module, and the uplink port module clears the latency tolerance data about the downlink port module so that the uplink port module can release physical resources.

[0074] 2.2) The LTR mechanism of the downlink port module is disabled.

[0075] In this embodiment of the application, when the LTR mechanism of the downlink port module is enabled or disabled, the downlink port module is controlled to send an invalid message to the uplink port module through step E, as follows: Step E, in response to the downlink port module's delay tolerance mechanism being disabled, the downlink port module is controlled to send an invalid message to the uplink port module so that the uplink port module clears the delay tolerance data of the downlink port module.

[0076] The root consortium controls the downlink port module to disable the LTR mechanism. The downlink port module does not need to report the latency tolerance value of the port device it is connected to. The downlink port module sends an invalid message to the uplink port module so that the uplink port module clears the latency tolerance data of the downlink port module, thereby prompting the uplink port module to release the latency resources of the downlink port module.

[0077] Step S24: According to the standard TLP message routing mechanism, the delay-tolerant message is transmitted from the downlink port module to the uplink port module of the same partition.

[0078] In the PCIe protocol, the standard TLP message routing mechanism refers to the path selection and forwarding rules for TLP messages from the source device (such as a port device or PCIe switch) to the destination device (such as a root union). The internal virtual bus, following the standard TLP message routing mechanism, transmits delay-tolerant messages from the downlink port module to the uplink port module within the same partition.

[0079] Since the first delay tolerance message is a locally terminated message, it cannot be further transmitted to the uplink port module. In related technologies, in order to smoothly transmit the delay tolerance values ​​sent by each downlink port module, hardware signal lines need to be set between the downlink port module and the uplink port module. Then, the role of the superimposed port module can be flexibly switched, and the partition to which the port module belongs can also be flexibly switched, resulting in the need to lay out complex hardware signal lines between the two. However, the embodiment of this application generates a delay tolerance message based on the first delay tolerance message, and then transmits the delay tolerance message from the downlink port module to the uplink port module in the same partition according to the standard TLP message routing mechanism. It is not necessary to set up complex hardware signal lines between the internal virtual bus and the downlink port module, nor is it necessary to set up complex hardware signal lines between the internal virtual bus and the uplink port module. The delay tolerance message can be transmitted to the uplink port module through software only, so that the uplink port module can aggregate the delay tolerance values ​​transmitted by each downlink port module, and finally find the minimum delay tolerance value, reducing the occupation of physical resources.

[0080] In this embodiment of the application, through steps S241 to S243, delay-tolerant packets are transmitted from the downlink port module to the uplink port module of the same partition according to the standard TLP message routing mechanism, as detailed below:

[0081] Step S241: Obtain the delay-tolerant message transmitted by the downlink port module.

[0082] Step S242: In response to the delay tolerance message being an abnormal message, the downlink port module is notified to retransmit the delay tolerance message.

[0083] The delay tolerance message also carries the downlink port number. When the delay tolerance message is an abnormal message, this embodiment of the application extracts the downlink port number from the delay tolerance message and notifies the downlink port module that matches the downlink port number to retransmit the delay tolerance message.

[0084] In step S243, in response to the delay-tolerant message being a normal message, the delay-tolerant message is transmitted to the uplink port module of the same partition according to the standard TLP message routing mechanism.

[0085] In this embodiment of the application, if the delay tolerance message is an abnormal message, the downlink port module is notified to retransmit the delay tolerance message, ensuring that the uplink port module can reliably collect all delay tolerance messages sent by the downlink port modules, thereby comprehensively aggregating the delay tolerance values ​​of all port devices and ensuring the reliable operation of the LTR mechanism.

[0086] Step S25: Control the uplink port module to find the minimum latency tolerance value based on the latency tolerance messages of each downlink port module in the same partition.

[0087] In some embodiments, when the number of downlink port modules is 1, the uplink port module parses the delay tolerance message of the downlink port module to obtain a first delay tolerance value, and determines a minimum delay tolerance value based on the first delay tolerance value.

[0088] In other embodiments, when there are two or more downlink port modules, the embodiments of this application control the uplink port module to extract the delay tolerance value from the delay tolerance message of the downlink module in the same partition, control the uplink port module to record each delay tolerance value in a preset delay statistics table, and find the minimum delay tolerance value in the delay statistics table.

[0089] Please see Figure 5 The latency tolerance values ​​include the Snoop latency tolerance value and the No Snoop latency tolerance value. When the uplink port module is connected to N downlink port modules, the uplink port module sequentially records the Snoop latency tolerance value and the No Snoop latency tolerance value of each downlink port module in a preset latency statistics table, and then finds the minimum latency tolerance value in the latency statistics table.

[0090] Step S26: In response to the uplink port module detecting that the PCIe switch is in a latency tolerance reporting state, a second latency tolerance message is generated based on the minimum latency tolerance value.

[0091] The latency tolerance reporting status is the state in which the PCIe switch needs to report latency tolerance values. The latency tolerance reporting status can be represented by the following scenarios:

[0092] 1) The uplink port module detected a rising edge signal indicating that the LTR mechanism is enabled.

[0093] The rising edge signal is used to indicate that the LTR mechanism is enabled. When the uplink port module detects the rising edge signal, it determines that the PCIe switch is in a delay-tolerant reporting state.

[0094] 2) The uplink port module detected a high-level signal enabling the LTR mechanism, and the previous minimum delay tolerance value changed.

[0095] A high-level signal is used to indicate that the LTR mechanism is enabled and remains on. The uplink port module looks up the current minimum delay tolerance value from the delay statistics table and compares the current minimum delay tolerance value with the previous minimum delay tolerance value. If the current minimum delay tolerance value is equal to the previous minimum delay tolerance value, the uplink port module determines that the minimum delay tolerance value has not changed. If the current minimum delay tolerance value is less than the previous minimum delay tolerance value but equal to it, the uplink port module determines that the minimum delay tolerance value has changed.

[0096] Understandably, the root union can disable the LTR mechanism enable of the uplink port module. Specifically, when the uplink port module detects a falling edge signal indicating LTR mechanism enable, it determines that LTR mechanism enable is disabled, clears delay-tolerant data, and sends an invalid message to the root union to notify it that it does not need to pay attention to the delay-tolerant messages of the uplink port module.

[0097] The second delay-tolerant message is a message that conforms to the LTR mechanism in the PCIe protocol. In this embodiment of the application, the second delay-tolerant message is generated based on the minimum delay tolerance value through steps S261 to S264, as shown below:

[0098] Step S261: In response to the uplink port module detecting that the PCIe switch is in a delay tolerance reporting state, the minimum delay tolerance value is subtracted from the preset transmission delay value to obtain the final delay tolerance value.

[0099] The transmission delay value is the time delay in data transmission within the PCIe switch before the PCIe switch transmits the minimum delay tolerance value to the root federation. In this embodiment, the transmission delay value is subtracted from the minimum delay tolerance value to obtain a more accurate and reliable final delay tolerance value, ensuring that port devices can be allocated the appropriate resources in a timely and reliable manner.

[0100] Step S262: Detect whether the final delay tolerance value is greater than the preset delay threshold.

[0101] According to the PCIe protocol, the latency tolerance value needs to be within a certain range, and the latency tolerance value is not allowed to be too large. The preset latency threshold is the maximum latency tolerance value specified by the PCIe protocol.

[0102] Step S263: If the final delay tolerance value is greater than the preset delay threshold, determine the preset delay threshold as the target delay threshold, and generate a second delay tolerance message based on the target delay threshold.

[0103] If the final latency tolerance value is greater than the preset latency threshold, the uplink port module can only select the preset latency threshold to encapsulate the message into a second latency tolerance message, thereby meeting the requirements of the PCIe protocol.

[0104] Step S264: If the final delay tolerance value is less than or equal to the preset delay threshold, determine the final delay tolerance value as the target delay threshold, and generate a second delay tolerance message based on the target delay threshold.

[0105] If the final latency tolerance value is less than or equal to the preset latency threshold, the uplink port module selects the final latency tolerance value and encapsulates it into a second latency tolerance message.

[0106] In this embodiment, the minimum latency tolerance value is subtracted from the transmission latency value to obtain a reliable and accurate final latency tolerance value. Then, the final latency tolerance value is compared with a preset latency threshold to generate a second latency tolerance message that conforms to the PCIe protocol, ensuring that the second latency tolerance message can be correctly parsed by the root union.

[0107] Step S27: Control the uplink port module to report the second delay tolerance message to the root union.

[0108] The uplink port module needs to upload different latency tolerance messages to the root union sequentially according to a preset period. This avoids excessively frequent uploading of latency tolerance messages to the root union, which could lead to packet loss in the root union. In some embodiments, this application determines the past duration of the uplink port module sending the most recent latency tolerance information to the root union. In response to the past duration being equal to the preset period, the uplink port module is controlled to report the second latency tolerance message to the root union.

[0109] For example, the uplink port module sends the most recent latency tolerance information to the root union at time t1. Then, when it needs to send a second latency tolerance message to the root union, the uplink port module obtains the current time t2 and the past duration. t = t2 - t1, if the past duration If t is less than the preset period T, the uplink port module needs to wait and listen for the past duration. Does t equal the preset period T? If so, the past duration When t equals the preset period T, the uplink port module reports the second delay tolerance message to the root union.

[0110] This embodiment compares the past duration with a preset period. If the past duration equals the preset period, the uplink port module is controlled to report the second delay tolerance message to the root union. This avoids excessively frequent uploading of delay tolerance messages to the root union, which could lead to packet loss in the root union and improves the reliability of the root union receiving the second delay tolerance message.

[0111] To illustrate in detail the delay tolerance reporting method provided in the embodiments of this application, the embodiments of this application are combined with... Figure 3 A detailed explanation will be provided, taking the operation of each port module in the third partition 30a as an example, as follows:

[0112] 1) Port configuration.

[0113] According to the port configuration file, the PCIe switch 300 divides the third partition 30a and the fourth partition 30b, and configures port module 31 of the third partition 30a as an uplink port module, and port modules 32 and 33 as downlink port modules.

[0114] 2) Port device reporting latency tolerance value.

[0115] Port device 32a sends a first delay tolerance message F1 to port module 32, and port device 32b sends a first delay tolerance message F2 to port module 33. Both the first delay tolerance message F1 and the first delay tolerance message F2 carry the delay tolerance value of the corresponding port device.

[0116] 3) Generation of delay-tolerant messages.

[0117] Port module 32 generates a delay-tolerant message VDM1 based on the first delay-tolerant message F1, and port module 33 generates a delay-tolerant message VDM2 based on the first delay-tolerant message F2.

[0118] 4) Uplink port module aggregation delay tolerance value.

[0119] The internal virtual bus transmits delay-tolerant messages VDM1 and VDM2 to port module 31 according to the standard TLP message routing mechanism. It is understood that this embodiment does not require setting up complex hardware signal lines between the internal virtual bus and the downlink port module, nor does it require setting up complex hardware signal lines between the internal virtual bus and the uplink port module, thus reducing the consumption of physical resources.

[0120] 5) Obtaining the minimum delay tolerance value.

[0121] Port module 31 records the delay tolerance values ​​of delay-tolerant message VDM1 and delay-tolerant message VDM2 in the delay statistics table, and finds the minimum delay tolerance value from the delay statistics table.

[0122] 6) Generation and transmission of the second delay-tolerant message.

[0123] Port module 31 generates a second delay tolerance message based on the minimum delay tolerance value and uploads the second delay tolerance message to the third root consortium 31a.

[0124] In this embodiment of the application, the delay-tolerant message VDM1 and delay-tolerant message VDM2 are transmitted to the port module 31 according to the standard TLP message routing mechanism, which reduces the design and layout of internal hardware signal lines and reduces hardware overhead.

[0125] Understandably, both the uplink and downlink port modules can be flexibly switched to different port roles, and can also be flexibly assigned to different partitions, as shown below:

[0126] 1) In the same partition, the uplink port module is configured as the downlink port module.

[0127] In this embodiment of the application, based on the port configuration information sent by the root union, port configuration operations are performed on multiple port modules through steps S211 to S213, as detailed below:

[0128] Step S211: Obtain the port configuration information sent by the root union. The port configuration information is used to indicate that the uplink port modules belonging to the same partition are configured as downlink port modules.

[0129] In this embodiment, the target port number and downlink configuration type are extracted from the port configuration information, and an uplink port module with a port number matching the target port number is found in a preset port list. The port number is a numerical value that identifies the port, and the downlink configuration type is used to indicate that the port module is configured as a downlink port module.

[0130] Step S212: In response to the port configuration information, clear the latency tolerance data of the uplink port module.

[0131] The latency tolerance data is data related to the LTR mechanism recorded by the uplink port module. For example, the latency tolerance data includes a latency statistics table, which is a table in which the uplink port module records the latency tolerance values ​​transmitted by each downlink port module in the same partition. The uplink port module responds to the port configuration information and clears the latency statistics table in order to prepare for the switch of the uplink port module to the downlink port module, and to avoid the reservation of previous latency tolerance data from affecting the working reliability of the new downlink port module.

[0132] Step S213: Configure the uplink port module as a downlink port module.

[0133] Based on the uplink configuration type, this application embodiment configures the uplink port module as a downlink port module. For example, while clearing latency-tolerant data, this application embodiment enables the port module (i.e., before the switch, this port module was an uplink port module) to support receiving latency-tolerant messages (LTR messages) and enables the port module to send latency-tolerant packets. Thus, the port module possesses all the functions of a downlink port module, and therefore, this port module is configured as a downlink port module.

[0134] 2) Within the same partition, the downlink port module is configured as the uplink port module.

[0135] In this embodiment of the application, based on the port configuration information sent by the root union, port configuration operations are performed on multiple port modules through steps S214 to S215, as detailed below:

[0136] Step S214: Obtain the port configuration information sent by the root union. The port configuration information is used to indicate that the downlink port modules belonging to the same partition are configured as uplink port modules.

[0137] Step S215: In response to the port configuration information, configure the downlink port module as an uplink port module.

[0138] Please see Figure 6 In this embodiment of the application, based on port configuration information, port modules 31 and 33 of the third partition 30a are configured as downlink port modules, and port module 32 is configured as an uplink port module. Figure 6 The working principle of the PCIe switch shown is the same as described above, and will not be repeated here.

[0139] The embodiments of this application can flexibly configure port modules in the same partition to enter different port roles, so that the port modules can participate in the latency tolerance reporting process flexibly and reliably, meeting the needs of various application scenarios.

[0140] 3) Configure the downlink port module of one partition as the downlink port module or uplink port module of another partition.

[0141] In this embodiment of the application, based on the port configuration information sent by the root union, port configuration operations are performed on multiple port modules through steps S216 to S218, as detailed below:

[0142] Step S216: Obtain the port configuration information sent by the root union. The port configuration information is used to indicate whether the downlink port module of the initial partition is configured as the downlink port module or uplink port module of the specified partition.

[0143] Step S217: In response to the port configuration information, a first clear message is sent to the uplink port module of the initial partition to clear the delay-tolerant data of the downlink port module of the initial partition. The first clear message belongs to the message message type in the TLP message specified by the PCIe protocol.

[0144] Step S218: Configure the downlink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

[0145] 4) Configure the uplink port module of one partition as the downlink port module or uplink port module of another partition.

[0146] In this embodiment of the application, based on the port configuration information sent by the root union, port configuration operations are performed on multiple port modules through steps S219 to S221, as detailed below:

[0147] Step S219: Obtain the port configuration information sent by the root union. The port configuration information is used to indicate that the uplink port module of the initial partition is configured as the downlink port module or uplink port module of the specified partition.

[0148] In step S220, in response to the port configuration information, a second clear message is sent to the root union of the initial partition to clear the delay-tolerant data of the uplink port module of the initial partition. The second clear message belongs to the message type of TLP message specified by the PCIe protocol.

[0149] Step S221: Configure the uplink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

[0150] Please see Figure 7 In this embodiment, based on port configuration information, port modules 31, 32, and 35 are assigned to the third partition 30a, and port modules 33, 34, and 36 are assigned to the fourth partition 30b. The third partition 30a is the initial partition, and the fourth partition 30b is the designated partition.

[0151] For the third partition 30a, in this embodiment of the application, port module 31 is configured as an uplink port module, and port modules 32 and 35 are configured as downlink port modules.

[0152] For the fourth partition 30b, in this embodiment of the application, port module 34 is configured as an uplink port module, and port modules 33 and 36 are configured as downlink port modules.

[0153] Figure 7 The working principle of the PCIe switch shown is the same as described above, and will not be repeated here.

[0154] The port modules of the PCIe switch provided in this application embodiment can not only be flexibly switched to different port roles, but also flexibly divided into different partitions. However, when the minimum latency tolerance value is aggregated, the role change or partition change of the port module will not increase the difficulty. There is no need to lay out complex hardware signal lines in advance for the role change or partition change of the port module. This application embodiment only needs to transmit the latency tolerance value according to the standard TLP message routing mechanism. The uplink port modules can eventually aggregate the minimum latency tolerance value, reducing the layout and consumption of hardware signal lines.

[0155] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0156] As another aspect of the embodiments of this application, this application provides a delay tolerance reporting device. The delay tolerance reporting device can be a software module, which includes several instructions stored in a memory. A processor can access the memory, invoke the instructions for execution, and complete the delay tolerance reporting method described in the various embodiments above.

[0157] In some embodiments, the delay tolerance reporting device can also be constructed from hardware devices. For example, the delay tolerance reporting device can be constructed from one or more chips, which can work together to complete the delay tolerance reporting method described in the various embodiments above. As another example, the delay tolerance reporting device can also be constructed from various logic devices, such as general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, ARM (Acorn RISC Machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0158] Please see Figure 8 The delay tolerance reporting device 800 includes a port configuration module 81, a message acquisition module 82, a message generation module 83, a message routing module 84, a delay lookup module 85, a message generation module 86, and a message reporting module 87.

[0159] Port configuration module 81 is used to perform port configuration operations on multiple port modules in response to port configuration information sent by the root federation, obtaining uplink port modules and at least one downlink port module under different partitions. Message acquisition module 82 is used to acquire the first delay tolerance message transmitted by the port device received by the downlink port module. Message generation module 83 is used to control the downlink port module to generate a delay tolerance message based on the first delay tolerance message in response to the downlink port module detecting that the port device meets the delay change condition. The delay tolerance message carries the delay tolerance value after the delay change, and the delay tolerance message belongs to the message message type in the TLP message specified by the PCIe protocol. Message routing module 84 is used to transmit the delay tolerance message from the downlink port module to the uplink port module in the same partition according to the standard TLP message routing mechanism. Delay lookup module 85 is used to control the uplink port module to find the minimum delay tolerance value based on the delay tolerance messages of each downlink port module in the same partition. Message generation module 86 is used to generate a second delay tolerance message based on the minimum delay tolerance value in response to the uplink port module detecting that the PCIe switch is in a delay tolerance reporting state. The message reporting module 87 is used to control the uplink port module to report the second delay tolerance message to the root union.

[0160] In some embodiments, the delay lookup module 85 is specifically used to: control the uplink port module to extract the delay tolerance value from the delay tolerance message of the downlink module in the same partition, control the uplink port module to record each delay tolerance value in a preset delay statistics table, and find the minimum delay tolerance value in the delay statistics table.

[0161] In some embodiments, the message routing module 84 is specifically configured to: obtain the delay-tolerant message transmitted by the downlink port module; in response to the delay-tolerant message being an abnormal message, notify the downlink port module to retransmit the delay-tolerant message; and in response to the delay-tolerant message being a normal message, transmit the delay-tolerant message to the uplink port module in the same partition according to the standard TLP message routing mechanism.

[0162] In some embodiments, the delay-tolerant message also carries a downlink port number, and the message routing module 84 is specifically used to: extract the downlink port number from the delay-tolerant message in response to the delay-tolerant message being an abnormal message, and notify the downlink port module that matches the downlink port number to retransmit the delay-tolerant message.

[0163] In some embodiments, the message generation module 86 is specifically configured to: in response to the uplink port module detecting that the PCIe switch is in a delay tolerance reporting state, subtract a preset transmission delay value from the minimum delay tolerance value to obtain a final delay tolerance value, detect whether the final delay tolerance value is greater than a preset delay threshold, if the final delay tolerance value is greater than the preset delay threshold, determine the preset delay threshold as the target delay threshold, and generate a second delay tolerance message based on the target delay threshold; if the final delay tolerance value is less than or equal to the preset delay threshold, determine the final delay tolerance value as the target delay threshold, and generate a second delay tolerance message based on the target delay threshold.

[0164] In some embodiments, the message reporting module 87 is specifically configured to: determine the past duration of the uplink port module sending the most recent delay tolerance information to the root union, and in response to the past duration being equal to a preset period, control the uplink port module to report the second delay tolerance message to the root union.

[0165] In some embodiments, the message generation module 83 is specifically configured to: control the downlink port module to generate a delay-tolerant message in response to a change in the delay requirements of the port device detected by the downlink port module; or, control the downlink port module to generate a delay-tolerant message in response to a change in the parameters of the SNOOP delay or the NO SNOOP delay detected by the downlink port module; or, control the downlink port module to retransmit a delay-tolerant message in response to receiving message retransmission information sent by the internal virtual bus of the PCIe switch.

[0166] In some embodiments, the message generation module 83 is further configured to: in response to the downlink port module detecting that the communication link between the port device and the PCIe switch is disconnected, control the downlink port module to send an invalid message to the uplink port module so that the uplink port module clears the delay-tolerant data about the downlink port module; or, in response to the downlink port module's delay-tolerant mechanism being turned off, control the downlink port module to send an invalid message to the uplink port module so that the uplink port module clears the delay-tolerant data about the downlink port module, wherein the invalid message belongs to the message type in the TLP message specified by the PCIe protocol.

[0167] In some embodiments, the port configuration module 81 is specifically used to: obtain port configuration information sent by the root union, the port configuration information being used to indicate that uplink port modules belonging to the same partition are configured as downlink port modules; in response to the port configuration information, clear the latency tolerance data of the uplink port module and configure the uplink port module as a downlink port module.

[0168] In some embodiments, the port configuration module 81 is specifically used to: obtain port configuration information sent by the root union, the port configuration information being used to indicate that downlink port modules belonging to the same partition are configured as uplink port modules, and in response to the port configuration information, configure the downlink port modules as uplink port modules.

[0169] In some embodiments, the port configuration module 81 is specifically configured to: obtain port configuration information sent by the root union, the port configuration information being used to indicate that the downlink port module of the initial partition is configured as the downlink port module or uplink port module of the specified partition; in response to the port configuration information, send a first clear message to the uplink port module of the initial partition, so that the uplink port module of the initial partition clears the delay-tolerant data of the downlink port module of the initial partition; the first clear message belongs to the message message type in the TLP message specified by the PCIe protocol, and configures the downlink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

[0170] In some embodiments, the port configuration module 81 is specifically configured to: obtain port configuration information sent by the root union, the port configuration information being used to instruct the uplink port module of the initial partition to be configured as the downlink port module or uplink port module of the specified partition; in response to the port configuration information, send a second clear message to the root union of the initial partition, so that the root union of the initial partition clears the delay-tolerant data about the uplink port module of the initial partition; the second clear message belongs to the message message type in the TLP message specified by the PCIe protocol, and configures the uplink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

[0171] It should be noted that the aforementioned delay tolerance reporting device can execute the delay tolerance reporting method provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in the embodiments of the delay tolerance reporting device can be found in the delay tolerance reporting method provided in the embodiments of this application.

[0172] See Figure 9 , Figure 9 This is a schematic diagram of a PCIe switch provided in an embodiment of this application. The PCIe switch 900 includes one or more processors 91 and a memory 92. The memory 92 is connected to one or more processors 91, for example, via a bus.

[0173] Processor 91 is configured to support the PCIe switch in performing the corresponding functions in the methods described in the above method embodiments. The processor may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0174] Memory 92 is used to store program code, etc. Memory may include volatile memory (VM), such as random access memory (RAM); memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory may also include combinations of the above types of memory.

[0175] The memory 92 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the delay tolerance reporting method in the embodiments of this application. The processor executes various functional applications and data processing of the delay tolerance reporting method and delay tolerance reporting device by running the non-volatile software programs, instructions, and modules stored in the memory, that is, it realizes the functions of each module or unit of the delay tolerance reporting method and delay tolerance reporting device provided in the above method embodiments.

[0176] The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the latency tolerance reporting device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the latency tolerance reporting device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0177] The one or more modules are stored in the memory. When executed by the one or more processors, they perform the latency tolerance reporting method in any of the above method embodiments. For example, they perform the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0178] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a PCIe switch, cause the PCIe switch to perform the method described in the foregoing embodiments.

[0179] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0180] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A method for reporting delayed tolerance, characterized in that, The latency tolerance reporting method is applied to PCIe switches, which are configured with multiple port modules, and includes: In response to the port configuration information sent by the root union, port configuration operations are performed on multiple port modules to obtain uplink port modules and at least one downlink port module under different partitions; Obtain the first delay-tolerant message transmitted by the receiving port device of the downlink port module; In response to the downlink port module detecting that the port device meets the latency change condition, the downlink port module is controlled to generate a latency tolerance message based on the first latency tolerance message. The latency tolerance message carries the latency tolerance value after the latency change, and the latency tolerance message belongs to the message type of TLP message specified by the PCIe protocol. According to the standard TLP message routing mechanism, the delay-tolerant message is transmitted from the downlink port module to the uplink port module of the same partition; The uplink port module is controlled to find the minimum latency tolerance value based on the latency tolerance messages of each downlink port module in the same partition; In response to the uplink port module detecting that the PCIe switch is in a latency tolerance reporting state, a second latency tolerance message is generated based on the minimum latency tolerance value; The uplink port module is controlled to report the second delay tolerance message to the root union.

2. The method for reporting delay tolerance according to claim 1, characterized in that, The process of controlling the uplink port module to find the minimum latency tolerance value based on the latency tolerance messages of each downlink port module in the same partition includes: The uplink port module is controlled to extract the delay tolerance value from the delay tolerance packets of the downlink module in the same partition; The uplink port module is controlled to record each latency tolerance value in a preset latency statistics table; Find the minimum latency tolerance value in the latency statistics table.

3. The method for reporting delay tolerance according to claim 1, characterized in that, The step of transmitting the delay-tolerant message from the downlink port module to the uplink port module of the same partition according to the standard TLP message routing mechanism includes: Obtain the delay-tolerant message transmitted by the downlink port module; In response to the delay-tolerant message being an abnormal message, the downlink port module is notified to retransmit the delay-tolerant message; In response to the delay-tolerant message being a normal message, the delay-tolerant message is transmitted to the uplink port module of the same partition according to the standard TLP message routing mechanism.

4. The method for reporting delay tolerance according to claim 3, characterized in that, The delay-tolerant message also carries a downlink port number. The response that the delay-tolerant message is an abnormal message, notifying the downlink port module to retransmit the delay-tolerant message, includes: In response to the delay-tolerant message being an abnormal message, the downlink port number is extracted from the delay-tolerant message; The downlink port module matching the downlink port number is notified to retransmit the delay-tolerant message.

5. The method for reporting delay tolerance according to claim 1, characterized in that, In response to the uplink port module detecting that the PCIe switch is in a latency-tolerant reporting state, a second latency-tolerant message is generated based on the minimum latency tolerance value, including: In response to the uplink port module detecting that the PCIe switch is in a latency tolerance reporting state, the minimum latency tolerance value is subtracted from the preset transmission latency value to obtain the final latency tolerance value; Detect whether the final delay tolerance value is greater than the preset delay threshold; If the final latency tolerance value is greater than the preset latency threshold, the preset latency threshold is determined as the target latency threshold, and a second latency tolerance message is generated based on the target latency threshold. If the final latency tolerance value is less than or equal to the preset latency threshold, the final latency tolerance value is determined to be the target latency threshold, and a second latency tolerance message is generated based on the target latency threshold.

6. The method for reporting delay tolerance according to claim 1, characterized in that, The step of controlling the uplink port module to report the second latency-tolerant message to the root union includes: Determine the past duration of the uplink port module sending the most recent delay tolerance information to the root union; In response to the past duration being equal to a preset period, the uplink port module is controlled to report the second delay tolerance message to the root union.

7. The method for reporting delay tolerance according to claim 1, characterized in that, The step of controlling the downlink port module to generate a delay-tolerant message based on the first delay-tolerant message in response to the downlink port module detecting a delay change condition includes: In response to the downlink port module detecting a change in the latency requirements of the port device, the downlink port module is controlled to generate a latency-tolerant message; or... In response to a change in the parameters of the Snoop delay or the No Snoop delay detected by the downlink port module, the downlink port module is controlled to generate a delay-tolerant message; or, In response to the downlink port module receiving a message retransmission information sent by the internal virtual bus of the PCIe switch, the downlink port module is controlled to retransmit a delay-tolerant message.

8. The method for reporting delay tolerance according to claim 1, characterized in that, Also includes: In response to the downlink port module detecting that the communication link between the port device and the PCIe switch has been disconnected, the downlink port module is controlled to send an invalid message to the uplink port module, so that the uplink port module clears the latency-tolerant data related to the downlink port module; or, In response to the downlink port module's latency tolerance mechanism being disabled, the downlink port module is controlled to send an invalid message to the uplink port module, so that the uplink port module clears the latency tolerance data of the downlink port module. The invalid message belongs to the message type of TLP message specified in the PCIe protocol.

9. The method for reporting delay tolerance according to any one of claims 1 to 8, characterized in that, The process of performing port configuration operations on multiple port modules in response to port configuration information sent by the root union includes: Obtain the port configuration information sent by the root union, which is used to indicate that uplink port modules belonging to the same partition are configured as downlink port modules; In response to the port configuration information, the latency tolerance data of the uplink port module is cleared; Configure the uplink port module as a downlink port module.

10. The method for reporting delay tolerance according to any one of claims 1 to 8, characterized in that, The process of performing port configuration operations on multiple port modules in response to port configuration information sent by the root union includes: Obtain the port configuration information sent by the root union, which is used to indicate that downlink port modules belonging to the same partition are configured as uplink port modules; In response to the port configuration information, the downlink port module is configured as an uplink port module.

11. The method for reporting delay tolerance according to any one of claims 1 to 8, characterized in that, The process of performing port configuration operations on multiple port modules in response to port configuration information sent by the root union includes: Obtain the port configuration information sent by the root union, which is used to indicate whether the downlink port module of the initial partition is configured as the downlink port module or the uplink port module of the specified partition. In response to the port configuration information, a first clear message is sent to the uplink port module of the initial partition to clear the latency-tolerant data of the downlink port module of the initial partition. The first clear message belongs to the message type of TLP message specified by the PCIe protocol. Configure the downlink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

12. The method for reporting delayed tolerance according to any one of claims 1 to 8, characterized in that, The process of performing port configuration operations on multiple port modules in response to port configuration information sent by the root union includes: Obtain the port configuration information sent by the root union, which is used to indicate that the uplink port module of the initial partition is configured as the downlink port module or uplink port module of the specified partition. In response to the port configuration information, a second clear message is sent to the root union of the initial partition to clear the latency-tolerant data of the uplink port module of the initial partition. The second clear message belongs to the message type of TLP message specified by the PCIe protocol. Configure the uplink port module of the initial partition as the downlink port module or uplink port module of the specified partition.

13. A PCIe switch, characterized in that, The device includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, and the processor, when executing the one or more computer programs, causing the PCIe switch to implement the latency tolerance reporting method as described in any one of claims 1-12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the delay tolerance reporting method as described in any one of claims 1-12.

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