Memory, access method thereof and electronic equipment

Abstract

The invention discloses a memory, an access method thereof and electronic equipment. The memory comprises at least one memory array, a plurality of common word lines and a plurality of common bit lines, the storage array comprises multiple layers of storage unit arrays and vertically extending bit lines; the memory cell array comprises a plurality of memory cells and a plurality of word lines; the plurality of word lines are divided into a plurality of word line groups, and each word line group is connected with one common word line; each word line group comprises S word lines, and the S word lines are respectively connected with the storage units in the spaced columns; each row of bit lines corresponds to S common bit lines; each row of bit lines is divided into a plurality of bit line groups comprising two adjacent bit lines, and every S bit line groups are respectively connected to the S common bit lines corresponding to the row of bit lines. According to the scheme provided by the embodiment of the invention, the gating of the word lines can be realized without a word line gating transistor, the spacing between the bit lines working at the same time is large, the coupling is small, and the same common bit line can be connected with more bit lines, so that the number of the common bit lines is reduced.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, device design and manufacturing in the technical field of semiconductor, in particular to a memory and an access method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of a device is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in the process production may affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a memory and an access method thereof, and an electronic device, which realizes the selection of the word line of the memory of the horizontal word line and the vertical bit line without the word line selection transistor.

[0006] The present application provides a memory, comprising:

[0007] at least one storage array, a plurality of common word lines and a plurality of common bit lines;

[0008] The storage array comprises a plurality of layers of storage unit arrays stacked in a direction perpendicular to the substrate, and a plurality of bit lines extending in a direction perpendicular to the substrate and arranged in a first direction and a second direction;

[0009] The storage unit array comprises: a plurality of storage units arranged in the first direction and the second direction, a plurality of word lines extending in the second direction corresponding to each column of storage units arranged in the second direction, and the word lines connecting the corresponding column of storage units; and the bit lines connecting a plurality of storage units at the same position of different layers, the first direction and the second direction being parallel to the substrate and intersecting each other;

[0010] The plurality of word lines of the same storage unit array are divided into a plurality of word line groups, each word line group connecting one common word line, and different word line groups connecting different common word lines; each word line group comprises S word lines, and the S word lines in the same word line group are connected to the storage units of the adjacent columns, respectively;

[0011] Each row of bit lines distributed along the first direction corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups, each bit line group includes two adjacent bit lines, the plurality of bit line groups of each row of bit lines are arranged according to the arrangement order of the bit lines, each bit line group is connected to one of the S common bit lines corresponding to the row of bit lines, and the adjacent bit line groups in the plurality of bit line groups connected to the same common bit line are separated by S-1 bit line groups, and S is greater than or equal to 2.

[0012] In some embodiments, the S is 2, 3 or 4.

[0013] In some embodiments, the memory includes a plurality of memory arrays distributed along the second direction at intervals, and adjacent memory cells share the common word line, and in the plurality of word line groups of a memory array, the word line group in which the word line connected to the memory cell of an odd column is connected to the word line group of one of the two memory arrays adjacent to the memory array and connected to the same common word line, and the word line group in which the word line connected to the memory cell of an even column is connected to the word line group of the other of the two memory arrays adjacent to the memory array and connected to the same common word line.

[0014] In some embodiments, the plurality of columns of memory cells connected by the word line groups connected to the same common word line and located in different memory arrays are in the same column.

[0015] In some embodiments, the S is 2, and the common bit line extends along the first direction, a plurality of the common bit lines are distributed along the second direction at intervals, and at least between adjacent common bit lines in the plurality of common bit lines of the same memory cell array, a shielding line extending along the first direction is arranged.

[0016] In some embodiments, a first gating sub-circuit is arranged between each of the bit lines and the common bit line, the first gating sub-circuit is connected to a first gating control line, and the first gating sub-circuit is configured to electrically connect or disconnect the bit line and the common bit line under the control of the first gating control line.

[0017] In some embodiments, a plurality of first gating sub-circuits connected to the bit lines of the same column arranged along the second direction are connected to the same first gating control line.

[0018] In some embodiments, each of the bit lines is also connected to a preset voltage terminal through a second gating sub-circuit, the second gating sub-circuit is connected to a second gating control line, and the second gating sub-circuit is configured to electrically connect or disconnect the bit line and the preset voltage terminal under the control of the second gating control line.

[0019] In some embodiments, a plurality of second gating sub-circuits connected to the bit lines of the same column arranged along the second direction are connected to the same second gating control line.

[0020] The embodiment of the present disclosure provides an access method, applied to the memory described above, comprising:

[0021] In the data read-write stage, according to the word line group in which the target storage unit to be operated is connected, an activation signal is loaded on the common word line connected to the word line group, wherein the target storage unit comprises S column storage units, and the S column storage units are respectively connected to S word lines of the same word line group.

[0022] In some embodiments, the method further comprises loading a turn-on level signal on a first gating control line connected to a first gating subcircuit connected to the S column target bit lines respectively connected to the target storage unit, and loading an off level signal on a second gating control line connected to a second gating subcircuit connected to the S column target bit lines; loading an off level signal on a first gating control line not connected to the target bit line, and loading a turn-on level signal on a second gating control line not connected to the target bit line.

[0023] The embodiment of the present disclosure provides an electronic device comprising the memory described in any of the above embodiments.

[0024] In some embodiments, the electronic device further comprises a control circuit configured to access the memory according to the access method described above.

[0025] The application provides a memory and an access method thereof and an electronic device. The memory comprises at least one memory array, a plurality of common word lines and a plurality of common bit lines. The memory array comprises a plurality of memory cell arrays stacked in a direction perpendicular to a substrate, a plurality of bit lines extending in the direction perpendicular to the substrate and arranged in a first direction and a second direction. The memory cell array comprises a plurality of memory cells arranged in the first direction and the second direction, a plurality of word lines extending in the second direction and corresponding to each column of memory cells arranged in the second direction, and the word lines are connected to the corresponding column of memory cells. The bit lines are connected to a plurality of memory cells at the same position of different layers, and the first direction and the second direction are parallel to the substrate and cross each other. The plurality of word lines of the same memory cell array are divided into a plurality of word line groups, each word line group is connected to a common word line, and different word line groups are connected to different common word lines. Each word line group comprises S word lines, and the S word lines in the same word line group are respectively connected to memory cells separated by one column. Each row of bit lines arranged in the first direction corresponds to S common bit lines. Each row of bit lines is divided into a plurality of bit line groups, each bit line group comprises two adjacent bit lines, the plurality of bit line groups of each row of bit lines are arranged in the arrangement order of the bit lines, each bit line group is connected to one of the S common bit lines corresponding to the row of bit lines, and the adjacent bit line groups in the plurality of bit line groups connected to the same common bit line are separated by S-1 bit line groups. The S is greater than or equal to 2. The scheme provided by the embodiment of the application realizes word line selection without a word line selection transistor, the spacing between the bit lines working at the same time is large, the coupling capacitance between the bit lines is reduced, the interference between the bit lines is reduced, one common bit line can be connected to more bit lines, the number of common bit lines is reduced, and the number of sense amplifiers connected to the common bit lines is correspondingly reduced.

[0026] Other features and advantages of the application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the application. Other advantages of the application will be realized and attained by the embodiments of the application particularly pointed out in the specification.

[0027] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The drawings are provided for merely for illustrative purposes and are not intended to limit the scope of the application.

[0029] Figure 1 A logic circuit schematic diagram of the memory provided for some embodiments;

[0030] Figure 2 A bit line and common bit line connection schematic diagram provided for some embodiments;

[0031] Figure 3 Connection diagram of bit line and common bit line for another embodiment;

[0032] Figure 4 Connection diagram of bit line and common bit line for another embodiment;

[0033] Figure 5 Connection diagram of bit line and common bit line for another embodiment;

[0034] Figure 6 Connection diagram of bit line and common bit line for another embodiment. DETAILED DESCRIPTION

[0035] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0036] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0037] The embodiments of the present disclosure are not necessarily limited to the sizes of the components shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0038] The ordinal numbers "first", "second", "third", and the like in the present disclosure are set to avoid confusion of the components, and do not represent any order, number, or importance.

[0039] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, can be a contact connection or an integral connection; can be directly connected, or indirectly connected through an intermediate component, or the communication inside two elements. The specific meanings of the above terms in the present disclosure can be understood by the person of ordinary skill in the art according to the specific circumstances.

[0040] In the present disclosure, it can be that the first electrode is a drain electrode and the second electrode is a source electrode, or it can be that the first electrode is a source electrode and the second electrode is a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0041] In the present disclosure, "connection" includes a case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected components. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0042] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0043] Figure 1 A memory logic circuit schematic diagram is provided for an exemplary embodiment. As shown in Figure 1 The memory includes a plurality of memory arrays located in different regions of a substrate, and the plurality of memory arrays can be arranged along a second direction Y. The memory array can include a plurality of layers of memory cell arrays 10 stacked in a direction perpendicular to the substrate, a plurality of bit lines (BL) extending in a direction perpendicular to the substrate. The memory cell array 10 can include a plurality of memory cells 11 arranged in a first direction X and a second direction Y, a plurality of word lines (WL) extending in the second direction Y. The same column of memory cells along the second direction Y in the same layer are connected to the same WL. The memory cells 11 in different columns are connected to different WLs. The memory cells 11 in the same position of different layers are connected to the same BL. The plurality of BLs are arranged in the first direction X and the second direction Y. The memory can also include a plurality of common word lines (CWL) and a plurality of common bit lines (CBL).

[0044] The memory cell 11 can include a transistor and a capacitor, the transistor including a gate electrode, a first electrode, and a second electrode, the gate electrode of the transistor being connected to the WL, the first electrode of the transistor being connected to the BL, and the second electrode of the transistor being connected to a first end of the capacitor, and a second end of the capacitor being connected to a first predetermined voltage terminal V PL , such as a fixed potential, such as a value between a voltage corresponding to logical data "0" and a voltage corresponding to logical data "1", such as "0" corresponding to logical data "0" and VDD corresponding to logical data "1", and V PL , such as a fixed potential, such as a value between a voltage corresponding to logical data "0" and a voltage corresponding to logical data "1", such as "0" corresponding to logical data "0" and VDD corresponding to logical data "1", and V PLmay be 1 / 2 VDD.

[0045] The plurality of WLs of the same storage cell array are divided into a plurality of groups, referred to as word line groups, each WL belongs to only one word line group, each word line group includes two WLs, and the two WLs of the same word line group are separated by one WL, the WLs of the same word line group are connected to the same CWL, for example, the storage cell array includes N rows of storage cells and 2M columns of storage cells, i.e., N*2M storage cells, then it includes 2M WLs, the jth WL is connected to the jth column of storage cells, j is 1 to 2M. The 1st word line and the 3rd word line form the 1st word line group, which is connected to the 1st common word line CWL_0; the 2nd word line and the 4th word line form the 2nd word line group, which is connected to the 2nd common word line CWL_1; the 5th word line and the 7th word line form the 3rd word line group, which is connected to the 3rd common word line CWL_2; the 6th word line and the 8th word line form the 4th word line group, which is connected to the 4th common word line CWL_3; and so on, the 2M-3th word line and the 2M-1th word line form the M-1th word line group, which is connected to the M-1th common word line CWL_M-2; the 2M-2th word line and the 2Mth word line form the Mth word line group, which is connected to the Mth common word line CWL_M-1.

[0046] Each CWL connects the word lines of two word line groups, and the two word line groups belong to the storage cell arrays of the same layer of the two adjacent storage arrays, respectively, and the storage cells connected by the word lines of the two word line groups are in the same column. For example, Figure 1 The 3 adjacent storage arrays shown in FIG. 3 are the k-1th storage array, the kth storage array and the k+1th storage array, respectively, the common word line CWL_0 connects the 1st word line and the 3rd word line of the rth layer of storage cell arrays of the kth storage array, and also connects the 1st word line and the 3rd word line of the rth layer of storage cell arrays of the k-1th storage array.

[0047] The adjacent word line groups of the same memory cell array are connected to the same CWL as the word line groups of different memory arrays. The word line group in which the word lines connected to the memory cells of the odd columns are connected to the word line group of one of the two memory arrays adjacent to the memory array, and the word line group in which the word lines connected to the memory cells of the even columns are connected to the word line group of the other of the two memory arrays adjacent to the memory array. For example, the word line group in which the word lines connected to the memory cells of the odd columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells of the odd columns in the k-1th memory array, and the word line group in which the word lines connected to the memory cells of the even columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells of the even columns in the k+1th memory array, or the word line group in which the word lines connected to the memory cells of the odd columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells of the odd columns in the k+1th memory array, and the word line group in which the word lines connected to the memory cells of the even columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells of the even columns in the k-1th memory array, wherein the adjacent word line groups refer to the two word line groups in which there are adjacent word lines. For example, the first word line group, the third word line group, …, the M-1th word line group of the kth memory array are connected to the same common word line as the corresponding first word line group, the third word line group, …, the M-1th word line group of the k-1th memory array, respectively, and the second word line group, the fourth word line group, …, the Mth word line group of the kth memory array are connected to the same common word line as the corresponding second word line group, the fourth word line group, …, the Mth word line group of the k+1th memory array, respectively. As shown in FIG. 10, the first word line group of the kth memory array (including the word lines connected to the memory cells of the odd columns, the first word line and the third word line) is connected to the same common word line CWL_0 as the first word line group of the k-1th memory array, and the second word line group of the kth memory array (including the word lines connected to the memory cells of the even columns, the second word line and the fourth word line) is connected to the same common word line CWL_1 as the second word line group of the k+1th memory array. Figure 1

[0048] Each row of bit lines distributed along the first direction X corresponds to two CBLs, and each adjacent two BLs form a bit line group. The BLs of the same bit line group are connected to the same CBL, and the BLs of the adjacent bit line groups are connected to different CBLs corresponding to the two CBLs of the row of bit lines. The adjacent bit line groups refer to the two bit line groups in which there are adjacent bit lines. For example, as shown in FIG. 11, the first bit line group of the kth memory array is connected to the same common word line CWL_0 as the first bit line group of the k-1th memory array, and the second bit line group of the kth memory array is connected to the same common word line CWL_1 as the second bit line group of the k+1th memory array. Figure 2 ​As shown, the plurality of BLs of the i+1th row correspond to the common bit lines CBL_i_0 and CBL_i_1, i is 0 to N-1, wherein the bit lines of the 1st column and the 2nd column of the i+1th row form the 1st bit line group, the bit lines of the 3rd column and the 4th column of the i+1th row form the 2nd bit line group, and so on, the bit lines of the 2M-1th column and the 2Mth column of the i+1th row form the Mth bit line group, and the 1st bit line group, the 3rd bit line group, and the M-1th bit line group are connected to the common bit line CBL_i_0, and the 2nd bit line group, the 4th bit line group, and the Mth bit line group are connected to the common bit line CBL_i_1. The scheme provided in the embodiment has only two common bit lines in the region where a row of storage units is located, and the distance between the common bit lines is large, which can reduce the coupling between the common bit lines, so that one common bit line can connect more bit lines, and the corresponding memory can use fewer common bit lines, and the number of sense amplifiers connected to the common bit lines is reduced.

[0049] In some embodiments, the CBLs extend along a first direction X, and when each row of bit lines corresponds to two CBLs, at least between two adjacent CBLs, a shielding line extending along the first direction X is arranged. The shielding line can be connected to a third preset voltage terminal, and the voltage of the third preset voltage terminal is, for example, 0, 1 / 2VDD, VDD, etc. The shielding line can shield the adjacent CBLs and reduce the coupling capacitance between the adjacent CBLs. The shielding line can be consistent with the shape of the CBL, that is, the same plurality of conductive lines can be manufactured, part of which is used as a CBL and part of which is used as a shielding line, but is not limited thereto.

[0050] In some embodiments, a shielding line is arranged between adjacent CBLs. The shielding line can be arranged between the two CBLs corresponding to the bit lines of the same row, and can also be arranged between the CBLs corresponding to the bit lines of adjacent rows. For example, the bit lines of the first row correspond to the first CBL and the second CBL, the bit lines of the second row correspond to the third CBL and the fourth CBL, and the shielding line can be arranged between the first CBL and the second CBL, between the second CBL and the third CBL, and between the third CBL and the fourth CBL.

[0051] Among the M common word lines connected with each memory cell array, only one common word line is activated at the same time, so that only the transistor of the memory cell connected with the bit line of the 1st bit line among the multiple bit lines connected with the same common bit line is turned on. For example, when the common word line CWL_0 is activated, the transistors of the first column memory cell and the third column memory cell connected with the first word line and the third word line are turned on, and the BLs connected with the first column memory cell and the third column memory cell respectively perform data reading or writing through charge sharing, that is, the working BLs at this time are the BL connected with the first column memory cell and the BL connected with the third column memory cell, rather than the adjacent BLs. The first column BL and the third column BL are separated by two memory cells, the distance is very far, the coupling between the first column BL and the third column BL is very small, and the second column BL can shield the first column BL and the third column BL, so as to further reduce the coupling between the first column BL and the third column BL. Therefore, one common bit line can connect more bit lines, and the memory can use fewer common bit lines. Since the common bit line is connected with the sense amplifier, the number of common bit lines is reduced, and the number of sense amplifiers connected with the common bit line is also reduced.

[0052] In some embodiments, as shown in Figure 3 each BL can be connected to the CBL through a first gating sub-circuit 21, and the first gating sub-circuit is also connected with a first gating control line. The first gating sub-circuit 21 is configured to connect or disconnect the BL and the CBL (i.e., to make the BL and the CBL electrically connected, or disconnected) under the control of the first gating control line. The scheme provided in the embodiment can select only the target bit line to be operated and turn off the non-target bit line by setting the first gating sub-circuit, so as to reduce the capacitive reactance of the CBL, reduce power consumption, and improve operation speed. When the capacitive reactance of the CBL is smaller, the voltage change ΔVBL on the BL is larger after the BL and the memory cell perform charge sharing. Therefore, the CBL can connect more bit lines, and the memory can use fewer CBLs. Since the CBL is connected with the sense amplifier, the number of CBLs is reduced, and the number of sense amplifiers connected with the CBL can also be reduced. Alternatively, the number of bit lines connected with the CBL can remain unchanged, and a capacitor with a smaller capacitance value can be used, that is, a capacitor with a smaller area can be used, so as to reduce the area occupied by the memory cell and improve the device density. However, the embodiments of the present disclosure are not limited thereto, and in another exemplary embodiment, the first gating sub-circuit 21 can not be provided.

[0053] In some embodiments, as shown in Figure 3As shown, each bit line can also be connected to a second preset voltage terminal Vpre via a second gating sub-circuit 22. The second gating sub-circuit is also connected to a second gating control line. The second gating sub-circuit 22 is configured to connect or disconnect the bit line and the second preset voltage terminal Vpre under the control of the second gating control line (i.e., to electrically connect the bit line and the second preset voltage terminal Vpre, or disconnect them). The solution provided in this embodiment, by setting the second gating sub-circuit, can connect non-target bit lines to a preset voltage terminal, avoiding interference to the target bit line caused by voltage changes in non-target bit lines. However, this embodiment is not limited to this; in other embodiments, the second gating sub-circuit 22 may not be provided.

[0054] In some embodiments, the voltage of the second preset voltage terminal Vpre can be the value between the voltage corresponding to logic data "0" and the voltage corresponding to logic data "1", such as 1 / 2VDD.

[0055] In some embodiments, multiple first gating sub-circuits 21 connected to multiple BLs arranged in the same column along the second direction are connected to the same first gating control line. First gating sub-circuits 21 connected to BLs in different columns are connected to different first gating control lines; that is, the first gating sub-circuits 21 connected to 2M columns of BLs are respectively connected to 2M different first gating control lines. For example, as... Figure 3 As shown, the storage cell array includes N*2M bit lines. The bit line in the i-th row and j-th column is bit line BL_i-1_j-1, where i is from 1 to N and j is from 1 to 2M, i.e., BL_0_0 to BL_N-1_2M-1. The bit lines in the first column are connected to multiple first gating sub-circuits 21, all of which are connected to the first first gating control line Ctrl_0_0. The bit lines in the second column are connected to multiple first gating sub-circuits 21, all of which are connected to the second first gating control line Ctrl_0_3. The bit lines in the third column are connected to multiple first gating sub-circuits 21, all of which are connected to the third first gating control line Ctrl_1_0. The bit lines in the fourth column are connected to multiple first gating sub-circuits 21, all of which are connected to the fourth first gating control line Ctrl_1_3, and so on. The bit lines in the (2M-1)th column are connected to multiple first gating sub-circuits 21, all of which are connected to the (2M-1)th first gating control line Ctrl_M-1_0. The bit lines in the (2M)th column are connected to multiple first gating sub-circuits 21, all of which are connected to the (2M)th first gating control line Ctrl_M-1_3. The solution provided in this embodiment allows selection of a bit line using CBL and the first gating control line.

[0056] In some embodiments, multiple second gating sub-circuits 22, each connected to multiple bit lines arranged in the same column along the second direction, are connected to the same second gating control line. Second gating sub-circuits 22 connected to bit lines in different columns are connected to different second gating control lines. The second gating sub-circuits 22 connected to the 2M columns of bit lines are respectively connected to 2M different second gating control lines. For example, as... Figure 3 As shown, the multiple second gating sub-circuits 22 connected to the bit lines in the first column are all connected to the first second gating control line Ctrl_0_1; the multiple second gating sub-circuits 22 connected to the bit lines in the second column are all connected to the second second gating control line Ctrl_0_2; the multiple second gating sub-circuits 22 connected to the bit lines in the third column are all connected to the third second gating control line Ctrl_1_1; the multiple second gating sub-circuits 22 connected to the bit lines in the fourth column are all connected to the fourth second gating control line Ctrl_1_2, and so on. The multiple second gating sub-circuits 22 connected to the bit lines in the 2M-1 column are all connected to the 2M-1 second gating control line Ctrl_M-1_1; the multiple second gating sub-circuits 22 connected to the bit lines in the 2M column are all connected to the 2M second gating control line Ctrl_M-1_2.

[0057] During the read or write operation phase, the selection states of the first gating sub-circuit 21 and the second gating sub-circuit 22 connected to the same bit line BL are opposite.

[0058] In some embodiments, the first gating sub-circuit 21 may include a first transistor T1, the gate electrode of the first transistor T1 being connected to the first gating control line, the first electrode being connected to the bit line BL, and the second electrode being connected to the common bit line CBL. The structure of the first gating sub-circuit 21 described in this embodiment is merely an example, and other circuits capable of gating may also be used.

[0059] In some embodiments, the first transistor T1 may be an N-type transistor, but this disclosure is not limited thereto; the first transistor T1 may be a P-type transistor.

[0060] In some embodiments, the second gating sub-circuit 22 may include a second transistor T2, the gate electrode of which is connected to the second gating control line, the first electrode of which is connected to the bit line BL, and the second electrode of which is connected to the second preset voltage terminal Vpre. The structure of the second gating sub-circuit 22 described in this embodiment is merely an example and may be other circuits capable of gating.

[0061] In some embodiments, the second transistor T2 is, for example, an N-type transistor, but this disclosure is not limited thereto; the second transistor T2 may be a P-type transistor.

[0062] The embodiment of the present disclosure further provides an access method of the above memory, comprising:

[0063] In the data read-write stage, according to the word line group to which the word lines connected by the two columns of target storage units belong, an activation signal is loaded on the common word line connected by the word line group, a conduction level signal is loaded on the first gating control line corresponding to the two columns of target bit lines connected by the target storage units, so as to turn on the two columns of target bit lines and the corresponding common bit line; a second gating control line connected by the second gating subcircuit connected by the two columns of target bit lines is loaded with an off level signal, so that the target bit line is disconnected from the second preset voltage terminal; the first gating control line connected by the first gating subcircuit connected by the non-target bit line (i.e. the first gating control line connected by the first gating subcircuit connected by the non-target bit line) is loaded with an off level signal, and the second gating control line connected by the second gating subcircuit connected by the non-target bit line (i.e. the second gating control line connected by the second gating subcircuit connected by the non-target bit line) is loaded with a conduction level signal, so that the non-target bit line is connected to the second preset voltage terminal. Wherein, the word lines connected by the two columns of target storage units belong to the same word line group.

[0064] The conduction level signal is a signal that can make the corresponding gating subcircuit in a connected state, and the off level signal is a signal that can make the corresponding gating subcircuit in an off state. The data read-write stage can include a read data stage and a write data stage.

[0065] As shown in Figure 3 The target storage units are the storage units in the 2nd column and the 4th column, the word lines connected by the storage units in the 2nd column and the 4th column belong to the word line group connected by the common word line CWL_1, an activation signal is loaded on the common word line CWL_1, then the 2nd word line and the 4th word line are loaded with the activation signal, the transistors of the storage units in the 2nd column and the 4th column are turned on, the first gating control line (Ctrl_0_3, Ctrl_1_3) connected by the bit lines in the 2nd column and the 4th column is loaded with a conduction level signal, the second gating control line (Ctrl_0_2, Ctrl_1_2) connected by the bit lines in the 2nd column and the 4th column is loaded with an off level signal, so that the bit lines in the 2nd column and the 4th column (i.e. the target bit lines) are connected and communicated with the common bit line, and are disconnected from the second preset voltage terminal Vpre, the bit lines connected by the storage units in the 2nd column and the 4th column can share charges with the storage units, the first gating control line corresponding to the bit lines in the other columns except the 2nd column and the 4th column (i.e. the non-target bit line) is loaded with an off level signal, the second gating control line corresponding to the bit lines in the other columns except the 2nd column and the 4th column is loaded with a conduction level signal, so that the bit lines in the other columns except the 2nd column and the 4th column are disconnected from the corresponding common bit line and are connected to the second preset voltage terminal Vpre.

[0066] The solution provided in this embodiment can operate on two columns of memory cells without word line selection transistors, and can disconnect the connection between the common bit line and the non-target bit line, reducing the capacitive reactance of the common bit line. Furthermore, by connecting the non-target bit line to a fixed voltage terminal, the interference of the non-target bit line to the target bit line can be reduced.

[0067] In another exemplary embodiment, such as Figure 4 As shown, multiple word lines (WLs) of the same memory cell array are divided into multiple word line groups. Each word line belongs to only one word line group, and every four word lines form a word line group. The word lines in the same word line group are distributed along the first direction X, and adjacent word lines are separated by one word line. Taking a memory cell array including N rows of memory cells and 2M columns of memory cells (i.e., N*2M memory cells) and 2M WLs as an example, the j-th WL is connected to the j-th column of memory cells, where j is 1 to 2M. The 1st, 3rd, 5th, and 7th word lines form the 1st word line group, which is connected to the 1st common word line CWL_0; the 2nd, 4th, 6th, and 8th word lines form the 2nd word line group, which is connected to the 2nd common word line CWL_1, and so on. This embodiment provides a solution where more word lines are connected to the same common word line, which can reduce the number of common word lines, thereby reducing the area occupied by the common word line leads and reducing the number of word line drivers. However, this scheme increases the number of common bit lines. Therefore, an appropriate number of common word lines and common bit lines can be selected based on design requirements.

[0068] Similar to the embodiment where each word line group includes two word lines, each CWL connects the word lines of two word line groups, and the two word line groups can belong to the same layer of memory cell arrays of two adjacent memory arrays, and the memory cells connected by the word lines in the two word line groups can be in the same column.

[0069] Adjacent word line groups within the same memory cell array are connected to the same word line group (CWL) as word line groups from different memory arrays. If the current memory array containing the memory cell array comprises two adjacent memory arrays, referred to as the first memory array and the second memory array, then in the case of two adjacent word line groups of the memory cell array, one word line group is connected to the same CWL as the word line group of the first memory array, and the other word line group is connected to the same CWL as the word line group of the second memory array.

[0070] Correspondingly, each row of bit lines distributed along the first direction X corresponds to 4 CBLs. Within each row of bit lines, every two adjacent BLs form a bit line group. BLs within the same bit line group are connected to the same CBL. In multiple bit line groups arranged in the distribution order of the BLs within the same row, every four consecutively distributed bit line groups are connected to different CBLs within the four CBLs corresponding to that row of bit lines, and bit line groups connected to the same CBL are spaced three bit line groups apart. For example, as...Figure 5 As shown, the multiple BLs in the (i+1)th row correspond to four common bit lines CBL_i_0, CBL_i_1, CBL_i_2, and CBL_i_3, where i is from 0 to N-1. Specifically, the bit lines in the 1st and 2nd columns of the (i+1)th row form the first bit line group, the bit lines in the 3rd and 4th columns of the (i+1)th row form the second bit line group, the bit lines in the 5th and 6th columns of the (i+1)th row form the third bit line group, and the bit lines in the 7th and 8th columns of the (i+1)th row form the fourth bit line group. The first bit line group is connected to the common bit line CBL_i_0, the second bit line group is connected to the common bit line CBL_i_1, the third bit line group is connected to the common bit line CBL_i_2, and the fourth bit line group is connected to the common bit line CBL_i_3. The connection methods for the subsequent 5th to 8th bit line groups, and more bit line groups, are similar and will not be elaborated further. The connection method between the bit line group and CBL described above is only an example; other connection methods are possible.

[0071] In each memory cell array connected to multiple common word lines, only one common word line is active at any given time, so that only one of the multiple bit lines connected to the same common bit line has its transistors conducting.

[0072] In some embodiments, such as Figure 6 As shown, each BL is connected to the CBL via a first gating sub-circuit 21. The first gating sub-circuit 21 is also connected to a first gating control line. The first gating sub-circuit 21 is configured to connect or disconnect the BL and the CBL under the control of the first gating control line. The solution provided in this embodiment, by setting the first gating sub-circuit, can select only the target bit line to be operated on and turn off non-target bit lines, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and improving operating speed. However, this embodiment is not limited to this; in another exemplary embodiment, the first gating sub-circuit 21 may not be provided.

[0073] In some embodiments, such as Figure 6 As shown, each bit line can also be connected to a second preset voltage terminal Vpre via a second gating sub-circuit 22. The second gating sub-circuit 22 is also connected to a second gating control line. The second gating sub-circuit 22 is configured to connect or disconnect the bit line and the second preset voltage terminal Vpre under the control of the second gating control line. The solution provided in this embodiment, by setting the second gating sub-circuit, can connect non-target bit lines to the preset voltage terminal, avoiding interference to the target bit line caused by voltage changes in non-target bit lines. However, this embodiment is not limited to this; in other embodiments, the second gating sub-circuit 22 may not be provided.

[0074] In some embodiments, the first gating sub-circuits 21 connected to the bit lines in the same column in the second direction are connected to the same first gating control line, and the first gating sub-circuits 21 connected to the bit lines in different columns are connected to different first gating control lines. For example, as shown in FIG. 7, the first gating sub-circuits 21 connected to the bit lines in the first column are connected to the first first gating control line Ctrl_0_0, the first gating sub-circuits 21 connected to the bit lines in the second column are connected to the second first gating control line Ctrl_0_3, the first gating sub-circuits 21 connected to the bit lines in the third column are connected to the third first gating control line Ctrl_1_0, the first gating sub-circuits 21 connected to the bit lines in the fourth column are connected to the fourth first gating control line Ctrl_1_3, and so on, the first gating sub-circuits 21 connected to the bit lines in the 2M-1th column are connected to the 2M-1th first gating control line Ctrl_M-1_0, and the first gating sub-circuits 21 connected to the bit lines in the 2Mth column are connected to the 2Mth first gating control line Ctrl_M-1_3. Figure 6 As shown in FIG. 7, the memory cell array includes N*2M bit lines, and the bit line in the i-th row and the j-th column is BL_i-1_j-1, i is 1 to N, and j is 1 to 2M, i.e., BL_0_0 to BL_N-1_2M-1. The first gating sub-circuits 21 connected to the bit lines in the first column are all connected to the first first gating control line Ctrl_0_0, the first gating sub-circuits 21 connected to the bit lines in the second column are all connected to the second first gating control line Ctrl_0_3, the first gating sub-circuits 21 connected to the bit lines in the third column are all connected to the third first gating control line Ctrl_1_0, the first gating sub-circuits 21 connected to the bit lines in the fourth column are all connected to the fourth first gating control line Ctrl_1_3, and so on, the first gating sub-circuits 21 connected to the bit lines in the 2M-1th column are all connected to the 2M-1th first gating control line Ctrl_M-1_0, and the first gating sub-circuits 21 connected to the bit lines in the 2Mth column are all connected to the 2Mth first gating control line Ctrl_M-1_3.

[0075] In some embodiments, the second gating sub-circuits 22 connected to the bit lines in the same column in the second direction are connected to the same second gating control line, and the second gating sub-circuits 22 connected to the bit lines in different columns are connected to different second gating control lines, and the second gating sub-circuits 22 connected to the 2M bit lines are connected to 2M different second gating control lines. For example, as shown in FIG. 8, the second gating sub-circuits 22 connected to the bit lines in the first column are all connected to the first second gating control line Ctrl_0_1, the second gating sub-circuits 22 connected to the bit lines in the second column are all connected to the second second gating control line Ctrl_0_2, the second gating sub-circuits 22 connected to the bit lines in the third column are all connected to the third second gating control line Ctrl_1_1, the second gating sub-circuits 22 connected to the bit lines in the fourth column are all connected to the fourth second gating control line Ctrl_1_2, and so on, the second gating sub-circuits 22 connected to the bit lines in the 2M-1th column are all connected to the 2M-1th second gating control line Ctrl_M-1_1, and the second gating sub-circuits 22 connected to the bit lines in the 2Mth column are all connected to the 2Mth second gating control line Ctrl_M-1_2. Figure 3

[0076] The embodiments of the present disclosure also provide a memory access method, including:

[0077] ​In the data read / write phase, according to the target storage unit to be operated, an activation signal is loaded on a common word line connected to the word line group to which the target storage unit is connected, the target storage unit includes 4 columns of storage units, and the 4 columns of storage units are respectively connected to 4 word lines of the same word line group; a conduction level signal is loaded on a first gating control line connected to a first gating subcircuit connected to 4 columns of target bit lines connected to the target storage unit, so as to turn on the 4 columns of target bit lines and the corresponding common bit lines; a turn-off level signal is loaded on a second gating control line connected to a second gating subcircuit connected to the 4 columns of target bit lines, so as to turn off the target bit lines and the second preset voltage terminal; a turn-off level signal is loaded on the first gating control line connected to the non-target bit line, and a conduction level signal is loaded on the second gating control line connected to the non-target bit line, so as to disconnect the non-target bit line and the corresponding common bit line, and connect to the second preset voltage terminal.

[0078] As shown in Figure 6 The 2nd, 4th, 6th and 8th columns of storage units are target storage units, the word line group connected to the target storage unit is connected to the common word line CWL_1, and an activation signal is loaded on the common word line CWL_1, so that the 2nd, 4th, 6th and 8th word lines are loaded with activation signals, the transistors of the 2nd, 4th, 6th and 8th columns of storage units are turned on, the first gating control lines (Ctrl_0_3, Ctrl_1_3, Ctrl_2_3, Ctrl_3_3) connected to the 2nd, 4th, 6th and 8th columns of bit lines (i.e. target bit lines) are loaded with conduction level signals, the second gating control lines (Ctrl_0_2, Ctrl_1_2, Ctrl_2_2, Ctrl_3_2) connected to the 2nd, 4th, 6th and 8th columns of bit lines are loaded with turn-off level signals, so that the 2nd, 4th, 6th and 8th columns of bit lines are connected and communicated with the common bit lines, and are turned off from the second preset voltage terminal, so that the bit lines connected to the 2nd, 4th, 6th and 8th columns of storage units can share charges with the storage units. The first gating control lines connected to the bit lines (i.e. non-target bit lines) of the other columns except the 2nd, 4th, 6th and 8th columns are loaded with turn-off level signals, the second gating control lines connected to the bit lines (i.e. non-target bit lines) of the other columns except the 2nd, 4th, 6th and 8th columns are loaded with conduction level signals, so that the bit lines of the other columns except the 2nd, 4th, 6th and 8th columns are disconnected from the corresponding common bit lines, and are connected to the second preset voltage terminal Vpre.

[0079] The above embodiments take 2 or 4 word lines as an example for description. However, the embodiments of the present disclosure are not limited thereto, and the word line group can include other number of word lines, such as 3 word lines.

[0080] The embodiments of the present disclosure provide a memory, which can include:

[0081] at least one storage array, a plurality of common word lines and a plurality of common bit lines;

[0082] The memory array comprises a plurality of memory cell arrays stacked along a direction perpendicular to the substrate, a plurality of bit lines extending along a direction perpendicular to the substrate and arranged along a first direction X and a second direction Y;

[0083] The memory cell array comprises: a plurality of memory cells arranged along the first direction X and the second direction Y, a plurality of word lines extending along the second direction Y corresponding to each column of memory cells arranged along the second direction Y, and the word lines connecting the corresponding column of memory cells; and the bit lines connecting a plurality of memory cells at the same position of different layers;

[0084] The plurality of word lines of the same memory cell array are divided into a plurality of word line groups, each word line group connects a common word line, and different word line groups connect different common word lines; each word line group comprises S word lines, and the S word lines in the same word line group are respectively connected to memory cells that are spaced apart; the word lines of the same word line group are arranged along the first direction X, and adjacent word lines of the same word line group are spaced apart by one word line;

[0085] Each row of bit lines arranged along the first direction X corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups, each bit line group comprises two adjacent bit lines, that is, every two adjacent BLs form a bit line group, the plurality of bit line groups of each row of bit lines are arranged in the arrangement order of the bit lines, the bit lines of the same bit line group are connected to the same common bit line, each bit line group is connected to one of the S common bit lines corresponding to the row of bit lines, and adjacent bit line groups connected to the same common bit line are spaced apart by S-1 bit line groups. In the plurality of bit line groups arranged in the arrangement order of the BLs and formed by the BLs of the same row, the BLs of every S bit line groups are respectively connected to different CBLs of the S CBLs corresponding to the row of bit lines, each bit line group is connected to one CBL, and the S bit line groups are respectively connected to the S CBLs, and the S is greater than or equal to 2.

[0086] The S is greater than or equal to 2. The maximum value of S can be the number of common bit lines that can be accommodated in the region where the row of memory cells is located, for example, S can be 2, 3, 4, etc.

[0087] Similarly, each bit line is connected to a common bit line through a first gating subcircuit 21 and connected to a second preset voltage terminal Vpre through a second gating subcircuit 22, the plurality of first gating subcircuits 21 connected to the plurality of BLs of the same column are connected to the same first gating control line, and the plurality of second gating subcircuits 22 connected to the plurality of bit lines of the same column are connected to the same second gating control line. For details, please refer to the relevant description in the foregoing embodiment that each word line group comprises 2 word lines or 4 word lines.

[0088] The embodiment of the present disclosure further provides an access method of the above-mentioned memory, comprising:

[0089] In the data read / write phase, according to the word line group in which the target storage unit to be operated is connected, an activation signal is loaded on the common word line connected to the word line group; wherein the target storage unit includes S column storage units, and the S column storage units are respectively connected to S word lines of the same word line group.

[0090] In some embodiments, the method further comprises: S column bit lines respectively connected to the S column storage units are called S column target bit lines, a conductive level signal is loaded on a first gating control line connected to a first gating sub-circuit connected to the S column target bit lines, so as to turn on the S column target bit lines and the corresponding common bit lines; a turn-off level signal is loaded on a second gating control line connected to a second gating sub-circuit connected to the S column target bit lines, so as to avoid the S column target bit lines being connected to the second preset voltage terminal; a turn-off level signal is loaded on the first gating control line connected to the non-target bit lines, and a conductive level signal is loaded on the second gating control line connected to the non-target bit lines, so as to make the non-target bit lines connected to the second preset voltage terminal. The scheme provided in the embodiment can disconnect the common bit lines and the non-target bit lines, reduce the capacitive reactance of the common bit lines, and make the voltage of the non-target bit lines stable and reduce the interference on the target bit lines.

[0091] The embodiments of the present disclosure further provide an electronic device comprising the memory of any of the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0092] In some embodiments, the electronic device can further comprise a control circuit configured to access the memory according to any of the foregoing access methods. The control circuit can include a driver for generating control signals to the common word line, the first gating control line, and the second gating controller, and the like. The control circuit and a sense amplifier, and the like, realize the access to the memory.

[0093] Although the embodiments of the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined in the appended claims.

Claims

1. A memory, characterized in that, include: At least one memory array, multiple common word lines, and multiple common bit lines; The memory array includes a multilayer memory cell array stacked along a direction perpendicular to the substrate, and multiple bit lines distributed along a first direction and a second direction, extending along a direction perpendicular to the substrate. The memory cell array includes: a plurality of memory cells distributed along the first direction and the second direction; a plurality of word lines extending along the second direction corresponding one-to-one with each column of memory cells distributed along the second direction, and the word lines connecting to a corresponding column of memory cells; the bit lines connecting a plurality of memory cells at the same position on different layers; the first direction and the second direction are parallel to the substrate and intersect. The multiple word lines of the same memory cell array are divided into multiple word line groups, each word line group is connected to a common word line, and different word line groups are connected to different common word lines; each word line group includes S word lines, and the S word lines in the same word line group are respectively connected to memory cells in alternate columns; Each row of bit lines distributed along the first direction corresponds to S common bit lines; and each row of bit lines is divided into multiple bit line groups, each bit line group includes two adjacent bit lines, the multiple bit line groups of each row of bit lines are arranged in the order of bit line arrangement, each bit line group is connected to one of the S common bit lines corresponding to that row of bit lines, and the adjacent bit line groups connected to the same common bit line are spaced apart by S-1 bit line groups, where S is greater than or equal to 2.

2. The memory according to claim 1, characterized in that, S is 2, 3, or 4.

3. The memory according to claim 1, characterized in that, The memory includes multiple memory arrays spaced apart along the second direction, and adjacent memory cells share the common word line. Among the multiple word line groups of the memory array, the word line group containing the word line connected to the memory cells in the odd-numbered columns is connected to the word line group of one of the two adjacent memory arrays of the memory array with the same common word line, and the word line group containing the word line connected to the memory cells in the even-numbered columns is connected to the word line group of the other of the two adjacent memory arrays of the memory array with the same common word line.

4. The memory according to claim 3, characterized in that, Word line groups that are connected to the same common word line but located in different memory arrays have multiple columns of memory cells that are in the same column.

5. The memory according to claim 1, characterized in that, S is 2, and the common bit line extends along the first direction. Multiple common bit lines are distributed at intervals along the second direction. At least among the multiple common bit lines of the same memory cell array, a shield line extending along the first direction is provided between adjacent common bit lines.

6. The memory according to any one of claims 1 to 5, characterized in that, A first gating sub-circuit is provided between each bit line and the common bit line. The first gating sub-circuit is connected to a first gating control line and is configured to electrically connect or disconnect the bit line and the common bit line under the control of the first gating control line.

7. The memory according to claim 6, characterized in that, Multiple first gating sub-circuits, which are respectively connected to the bit lines arranged in the same column along the second direction, are connected to the same first gating control line.

8. The memory according to claim 7, characterized in that, Each bit line is also connected to a preset voltage terminal via a second gating sub-circuit, which is connected to a second gating control line. The second gating sub-circuit is configured to electrically connect or disconnect the bit line and the preset voltage terminal under the control of the second gating control line.

9. The memory according to claim 8, characterized in that, Multiple second gating sub-circuits, each connected to a bit line in the same column arranged along the second direction, are connected to the same second gating control line.

10. An access method, characterized in that, Applied to the memory as described in any one of claims 1 to 9, comprising: During the data read / write phase, an activation signal is applied to the common word line connected to the word line group to which the target storage unit to be operated belongs, based on the word line group to which the target storage unit is connected. The target storage unit includes S columns of storage units, and the S columns of storage units are respectively connected to S word lines of the same word line group.

11. The access method according to claim 10, characterized in that, The memory is the memory as described in claim 8 or 9, and the method further includes: loading a conduction level signal on a first gating control line connected to a first gating sub-circuit connected to an S column of target bit lines respectively connected to the target memory cell; loading a shutdown level signal on a second gating control line connected to a second gating sub-circuit connected to an S column of target bit lines; loading a shutdown level signal on a first gating control line not connected to the target bit lines; and loading a conduction level signal on a second gating control line not connected to the target bit lines.

12. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 9.

13. The electronic device according to claim 12, characterized in that, The electronic device further includes a control circuit configured to access the memory according to the access method of claim 10 or 11.

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