1S1R storage unit and preparation method thereof
By introducing an intermediate dielectric layer and annealing process into the 1S1R memory cell to form a nanocrystalline interface, the problems of unstable conductive filaments and performance fluctuations are solved, realizing a 1S1R memory cell with high reliability and electrical consistency, suitable for arrays with planar and vertical structures.
Patent Information
- Application Number
- CN202511303928.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2025-12-16
AI Technical Summary
Existing 1S1R memory cells suffer from unstable conductive filaments and high leakage current, and there are significant performance fluctuations among multiple cells. Material interface mismatch and component diffusion limit their application in large-scale integration.
By employing specific device structure and process design, including adding an intermediate dielectric layer between the gate layer and the buffer layer, and using an annealing process to crystallize the gate layer and the buffer layer to form a protruding nanocrystalline interface, the contact area and local field strength are increased, the generation position of conductive filaments is constrained, and the electrical uniformity is improved.
It improves the threshold switching characteristics of the device, reduces the forming voltage, enhances the robustness of the resistive switching layer conductive filaments, reduces the randomness of conductive filament generation, is suitable for planar and vertical 1S1R arrays, and improves electrical consistency.
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Figure CN121152218A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of semiconductor and CMOS hybrid integrated circuits, and particularly relates to a 1S1R memory cell structure and a preparation method thereof. BACKGROUND
[0002] Resistive random access memory (RRAM) is considered as one of the most integrated potential next-generation storage technologies due to its simple structure, small feature size, fast programming / erasing speed and compatibility with CMOS process. The mainstream RRAM-based storage array currently adopts a 1T1R architecture. Although the selection transistor can solve the problem of leakage current in the RRAM array, its 6F 2 feature size limits the scalability of the RRAM, and is not suitable for three-dimensional integration. A selector, a threshold switch device, is also a two-terminal structure, which is connected in series with the RRAM to form a 1S1R cell without increasing the additional area overhead, and is the most potential integrated architecture. The threshold transition characteristics of the selector can suppress the leakage current on the low-resistance RRAM in the non-selected cell. The 1S1R cell composed of the selector and the resistive memory is suitable for both memory and the implementation of a neuromorphic computing system. Therefore, the development of an integrated cell of a high-reliability, high-density selector device and a resistive device has great significance for realizing data storage and novel computing based on a large-scale memristor array.
[0003] However, there is an interface mismatch between the selector device and the resistive device at present. In addition, due to the uncontrollability of the conduction filament of the commonly used OxRAM type resistive device, the durability of the OxRAM type resistive device is unstable, and the retention characteristics are insufficient. Moreover, the materials of the two devices are usually different, and there is a problem of composition diffusion between the two devices when they are directly stacked, so that there is a large electrical characteristic fluctuation between different device cells. In addition, the selector based on the Mott material has a large leakage current, which limits its application in large-scale integration. SUMMARY
[0004] In view of the above problems, the application provides a 1S1R memory cell and a preparation method thereof, which adopts a special device structure and process design to solve the problems of unstable conduction filament and high leakage current in the prior art, and the problem of large performance fluctuation between multiple 1S1R cells.
[0005] The technical scheme adopted by the application is as follows: A 1S1R memory cell, comprising: a substrate, a first electrode layer, a selector layer, a buffer layer, a resistive layer and a second electrode layer, and the surface of the buffer layer in contact with the resistive layer has a protruding nanocrystalline interface.
[0006] Furthermore, an intermediate medium layer is added between the gating layer and the buffer layer of the 1S1R memory cell.
[0007] A method for fabricating a 1S1R memory cell includes the following steps: 1) Fabricate a first electrode layer on the substrate; 2) Then, a gate layer is fabricated on the first electrode layer; 3) A buffer layer is fabricated on the gated layer, which serves to adhere the gated layer and the resistive switching layer; then the fabrication... Annealing the device causes the gate layer and buffer layer to crystallize, and forms a protruding nanocrystalline interface on the surface of the buffer layer. The crystallization roughens the film surface, making the root mean square roughness of the buffer layer Rq = [2A, 50A], which increases the contact area with the resistive switching layer. 4) Prepare a resistive switching layer on the buffer layer; 5) A second electrode layer is fabricated on the resistive switching layer to form a complete device.
[0008] Furthermore, the through-layer material in the above process steps is at least one of niobium oxide (NbOx), vanadium oxide (VOx), germanium telluride (GeTex), germanium telluride (GeTex), germanium selenide (GeSex), iron oxide (FeOx), silicon oxide (SiOx), neodymium nickel oxide (NdNiOx), samarium nickel oxide (SmNiOx), lanthanum cobalt oxide (LaCoOx), gadolinium cobalt oxide (GdCoOx), and one or more combinations thereof, including multilayer structures or mixtures of multilayer materials; the preparation process is physical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, ion beam sputtering, electron beam evaporation, or thermal evaporation.
[0009] Furthermore, the materials of the first and second electrode layers in the above process steps are at least one of the following: vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), aluminum oxide (AlOx), aluminum titanium nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), and copper (Cu), and one or more of their alloys, including multilayer structures or mixtures of multilayer materials; they can also be conductive oxide semiconductors (ITO, IGZO, IAZO); the preparation process is physical vapor deposition, evaporation, plasma-enhanced chemical vapor deposition, atomic layer deposition, or chemical vapor deposition, and the electrode thickness is 10nm-2500nm.
[0010] Further, in the above process step, the buffer layer material is at least one of zinc oxide (ZnOx), nickel oxide (NiOx), titanium oxide (TiOx), chromium oxide (CrOx), molybdenum oxide (MoOx), tungsten oxide (WOx), bismuth oxide (BiOx), antimony oxide (SbOx), barium metatitanate (BaTiOx), indium oxide (InOx), vanadium oxide (VOx), niobium oxide (NbOx), strontium titanate (SrTiOx), aluminum titanate (AlTiOx), manganese oxide (MnOx), gallium nitride (GaNx), titanium oxide (TiOx), or metal titanium (Ti), metal nickel (Ni), metal zinc (Zn), metal chromium (Cr), metal molybdenum (Mo), metal tungsten (W), metal bismuth (Bi), metal antimony (Sb), metal indium (In), metal vanadium (V), metal niobium (Nb), metal manganese (Mn), metal neodymium (Nd), metal strontium (Sr), metal germanium (Ge), metal lanthanum (La), metal hafnium (Hf), metal gallium (Ga), metal aluminum (Al), metal zirconium (Zr), silicon (Si), metal ytterbium (Yb), metal magnesium (Mg), metal silver (Ag), and combinations thereof, and the buffer layer is a single-layer structure or a multi-layer structure; and the preparation process is physical vapor deposition, atomic layer deposition, or chemical vapor deposition.
[0011] Further, in the above process step, the resistive layer material is at least one of neodymium oxide (NdOx), tantalum oxide (TaOx), niobium oxide (NbOx), strontium oxide (SrOx), germanium oxide (GeOx), lanthanum oxide (LaOx), hafnium oxide (HfOx), gallium oxide (GaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), silicon oxide (SiOx), ytterbium oxide (YbOx), magnesium oxide (MgO), aluminum nitride (AlNx), germanium antimony tellurium (GeTex), scandium antimony tellurium (ScSbTe), indium silver antimony tellurium (InAgSbTe), germanium antimony (GeSb), germanium tellurium (GeTe), antimony tellurium (SbTe), copper sulfide (CuSx), germanium sulfide (GeSx), germanium selenide (GeSex), zinc sulfide (ZnS), aluminum borate (AlBO); or, at least one selected from the group consisting of strontium titanate (SrTiOx), zirconium titanate (ZrTiOx), barium titanate (BaTiOx), hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO); which has good resistive characteristics; and the preparation process is physical vapor deposition, atomic layer deposition, or chemical vapor deposition.
[0012] Further, the substrate material in the above process step is a semiconductor substrate material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or in some cases, a silicon-on-insulator (SOI) substrate material, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP).
[0013] Further, the annealing process in the above process step is a rapid thermal processing (RTP), a pulsed laser annealing (PLA), or a furnace tube annealing, and the annealing atmosphere is vacuum, air, hydrogen, or an inert gas (such as N2 or Ar), and the temperature range is 200-900℃, and the annealing time is 30 seconds-1 hour.
[0014] The technical effects of the present application are as follows: The 1S1R memory cell and the preparation method thereof of the present application, by annealing the device prepared by the first electrode layer, the gating layer and the buffer layer in the preparation process, the gating layer and the buffer layer are crystallized, the forming voltage is reduced after the gating layer is crystallized, the threshold transition characteristic yield of the device is improved, the buffer layer is crystallized to form a nano-crystalline interface with protrusions on the surface, the contact area of the buffer layer and the resistive switching layer is increased, and the local field strength is also increased by the nano-crystalline interface, so that the resistive switching layer is robust, the position of the formed resistive switching layer conductive filament has a certain regularity, the randomness of the conductive filament generation position is reduced, and the uniformity of the electrical property is improved. The 1S1R cell structure of the present application is not only suitable for the 1S1R array of the Crossbar structure, but also suitable for the 1S1R array of the vertical structure after proper modification. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 is the process flow chart of the 1S1R memory cell of the present application.
[0016] Figure 2 is the schematic diagram of the nano-crystalline formation of the 1S1R memory cell of the present application.
[0017] Figure 3 is the schematic diagram of the nano-crystalline induced conductive channel formation of the 1S1R memory cell of the present application.
[0018] Figure 4 is the schematic diagram of the device structure of the 1S1R memory cell of the present application.
[0019] Figure 5 is the schematic diagram of the device structure of the 1S1R memory cell of the present application. Figure 4 is the schematic diagram of the device structure of the 1S1R memory cell of the present application after adding an intermediate medium layer. DETAILED DESCRIPTION
[0020] The application will be further clarified by a specific embodiment with reference to the accompanying drawings.
[0021] Figure 1 is a process flow chart of the 1S1R memory cell of the application, comprising: (1) preparing a first electrode layer on a semiconductor substrate (2) preparing a selection layer on the first electrode layer (3) preparing a buffer layer on the selection layer and annealing the prepared device (4) preparing a resistive switching layer on the buffer layer (5) preparing a second electrode layer on the resistive switching layer to form a complete device.
[0022] In Figure 2 is a nanocrystal formation schematic diagram of the 1S1R memory cell of the application, after the first electrode layer, the selection layer and the buffer layer are prepared, the device is annealed to crystallize the selection layer and the buffer layer, after the selection layer is crystallized, the forming voltage can be reduced and the threshold switching (TS) yield of the device can be improved; after the buffer layer is annealed, a protruding nanocrystal interface is formed on the surface, the root mean square roughness is Rq = [2A, 50A], the contact area with the resistive switching layer is increased and the local field strength is increased.
[0023] Figure 3 is a nanocrystal induced conductive channel formation schematic diagram of the 1S1R memory cell of the application, after the buffer layer is annealed, a protruding nanocrystal interface is formed on the surface, the contact area between the buffer layer and the resistive switching layer is increased, the growth of the conductive filament or the phase change region is constrained, the growth of the conductive channel of the resistive switching layer is more regular, the protruding nanocrystal interface can increase the local field strength, the conductive filament of the resistive switching layer is robust, the position of the formed conductive filament of the resistive switching layer has a certain regularity, the randomness of the generation position of the conductive filament of the resistive switching layer is reduced, and the uniformity of the electrical property is improved.
[0024] Figure 4 is a device structure schematic diagram of the 1S1R memory cell of the application, comprising: a substrate, a first electrode layer, a selection layer, a buffer layer, a resistive switching layer and a second electrode layer, by introducing the buffer layer between the selection layer and the resistive switching layer, and annealing the device after the selection layer and the buffer layer are prepared, the selection layer and the buffer layer can be crystallized, and after the buffer layer is annealed, a protruding nanocrystal interface is formed on the surface.
[0025] Three specific embodiments of the preparation method of the application are given below.
[0026] Example 1 In example 1, the new memory adopts a TiN / NbOx / Ti / TaOx / TiN structure. The device structure is as shown in Figure 4 .
[0027] The embodiment provides a 1S1R structure. Compared with a conventional structure, the embodiment forms nanocrystals on the surface of a buffer layer by arranging the buffer layer and performing annealing treatment on the device, increases contact area of a resistance change layer, improves local field intensity through the nanocrystal protrusions, makes a conductive filament of the resistance change layer thinner, and makes the position of the conductive filament more regular, so that randomness of generation of the conductive filament position of the resistance change layer is reduced, and uniformity of electrical properties is improved.
[0028] 1) A first electrode layer TiN with a thickness of 50 nm is prepared on a prepared substrate by physical vapor deposition as a bottom electrode.
[0029] 2) A gate layer NbOx with a thickness of 25 nm is prepared on the first electrode layer by physical vapor deposition.
[0030] 3) A buffer layer Ti with a thickness of 3 nm is prepared on the gate layer by physical vapor deposition, and then the whole device is subjected to RTP annealing, the annealing temperature is 600 DEG C, and the annealing is performed in a vacuum for 60 seconds, so that the gate layer and the buffer layer are crystallized, and a nanocrystal interface of the buffer layer is formed.
[0031] 4) A resistance change layer TaOx with a thickness of 20 nm is prepared on the buffer layer by physical vapor deposition.
[0032] 5) A second metal layer TiN with a thickness of 50 nm is prepared on the resistance change layer by physical vapor deposition as a top electrode, and the device preparation is completed.
[0033] Embodiment Two In the embodiment two, a new type of memory adopts a Pt / NbOx / Ti / HfOx / TiN structure. Figure 4 .
[0034] The embodiment provides a 1S1R structure. Compared with a conventional structure, the embodiment forms nanocrystals on the surface of a buffer layer by arranging the buffer layer and performing annealing treatment on the device, increases contact area of a resistance change layer, improves local field intensity through the nanocrystal protrusions, makes a conductive filament of the resistance change layer thinner, and makes the position of the conductive filament more regular, so that randomness of generation of the conductive filament position of the resistance change layer is reduced, and uniformity of electrical properties is improved.
[0035] 1) A first electrode layer Pt with a thickness of 60 nm is prepared on a prepared substrate by physical vapor deposition as a bottom electrode.
[0036] 2) A gate layer NbOx with a thickness of 20 nm is prepared on the first electrode layer by atomic layer deposition.
[0037] 3) A buffer layer Ti with a thickness of 2 nm is prepared on the gating layer by physical vapor deposition, and then the whole device is subjected to pulsed laser annealing at an annealing temperature of 400°C for 150 seconds in an oxygen atmosphere, so that the gating layer and the buffer layer are crystallized and a nanocrystalline interface of the buffer layer is formed.
[0038] 4) A resistive switching layer HfOx with a thickness of 15 nm is prepared on the buffer layer by physical vapor deposition.
[0039] 5) A second metal layer TiN with a thickness of 60 nm is prepared on the resistive switching layer as a top electrode by physical vapor deposition, and the device preparation is completed.
[0040] Embodiment Three The new memory in Embodiment One adopts a TiN / NbOx / TiN / Ti / GeTe / TiN structure. The device structure is as shown in Figure 5 .
[0041] Based on the same inventive concept, the embodiment provides a 1S1R unit, an intermediate medium layer is added between the gating layer and the buffer layer, compared with the traditional 1S1R unit, the problem of mutual diffusion of the gating layer material and the resistive switching layer material can also be solved.
[0042] 1) A first electrode layer TiN with a thickness of 50 nm is prepared on the prepared substrate as a bottom electrode by physical vapor deposition.
[0043] 2) A gating layer NbOx with a thickness of 5 nm is prepared on the first electrode layer by atomic layer deposition.
[0044] 3) An intermediate medium layer TiN with a thickness of 10 nm is prepared on the gating layer by physical vapor deposition.
[0045] 4) A buffer layer Ti with a thickness of 3 nm is prepared on the intermediate medium layer by physical vapor deposition, and then the whole device is subjected to RTP annealing at an annealing temperature of 500°C for 60 seconds in a vacuum, so that the gating layer and the buffer layer are crystallized and a nanocrystalline interface of the buffer layer is formed.
[0046] 5) A resistive switching layer GeTe with a thickness of 15 nm is prepared on the buffer layer by physical vapor deposition.
[0047] 6) A second metal layer TiN with a thickness of 50 nm is prepared on the resistive switching layer as a top electrode by physical vapor deposition, and the device preparation is completed.
[0048] The hyphenated chemical composition notation used herein indicates the elements included in a particular compound or alloy and is intended to mean all stoichiometry involving the indicated elements.
[0049] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention should be determined by the claims.
Claims
1. A method for fabricating a 1S1R memory cell, characterized in that, Includes the following steps: 1) Fabricate a first electrode layer on a substrate; 2) Then, a gate layer is fabricated on the first electrode layer; 3) A buffer layer is prepared on the gate layer, which serves to adhere the gate layer and the resistive switching layer; then the prepared device is annealed to crystallize the gate layer and the buffer layer, and to form a protruding nanocrystalline interface on the surface of the buffer layer. The crystallization makes the film surface rough, and the root mean square roughness of the buffer layer surface is Rq = [2A, 50A]. 4) Prepare a resistive switching layer on the buffer layer; 5) A second electrode layer is fabricated on the resistive switching layer to form a complete device.
2. The preparation method according to claim 1, characterized in that, The gate layer material in the process steps is at least one of niobium oxide (NbOx), vanadium oxide (VOx), germanium telluride (GeTex), germanium telluride (GeTex), germanium selenide (GeSex), iron oxide (FeOx), silicon oxide (SiOx), neodymium nickel oxide (NdNiOx), samarium nickel oxide (SmNiOx), lanthanum cobalt oxide (LaCoOx), and gadolinium cobalt oxide (GdCoOx), or one or more combinations thereof, including multilayer structures or mixtures of multilayer materials; the gate layer preparation process is physical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, ion beam sputtering, electron beam evaporation, or thermal evaporation.
3. The preparation method according to claim 1, characterized in that, The materials for the first and second electrode layers in the process steps are at least one of the following: vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), aluminum oxide (AlOx), aluminum titanium nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), and copper (Cu), and one or more alloys thereof, including multilayer structures or mixtures of multilayer materials; they can also be conductive oxide semiconductors (ITO, IGZO, IAZO); the preparation process is physical vapor deposition, evaporation, plasma-enhanced chemical vapor deposition, atomic layer deposition, or chemical vapor deposition, and the electrode thickness is 10nm-2500nm.
4. The preparation method according to claim 1, characterized in that, The buffer layer material in the aforementioned process steps is zinc oxide (ZnOx), nickel oxide (NiOx), titanium oxide (TiOx), chromium oxide (CrOx), molybdenum oxide (MoOx), tungsten oxide (WOx), bismuth oxide (BiOx), antimony oxide (SbOx), barium metatitanate (BaTiOx), indium oxide (InOx), vanadium oxide (VOx), niobium oxide (NbOx), strontium titanate (SrTiOx), aluminum titanate (AlTiOx), manganese oxide (MnOx), gallium nitride (GaNx), titanium oxide (TiOx), or metallic titanium (Ti), metallic nickel (Ni), metallic zinc (Zn), and metallic chromium (Cr). The buffer layer comprises at least one of the following metals: molybdenum (Mo), tungsten (W), bismuth (Bi), antimony (Sb), indium (In), vanadium (V), niobium (Nb), manganese (Mn), neodymium (Nd), strontium (Sr), germanium (Ge), lanthanum (La), hafnium (Hf), gallium (Ga), aluminum (Al), zirconium (Zr), silicon (Si), ytterbium (Yb), magnesium (Mg), and silver (Ag), or one or more combinations thereof, wherein the buffer layer is a single-layer structure or a multi-layer structure; the buffer layer is prepared by physical vapor deposition, atomic layer deposition, or chemical vapor deposition.
5. The preparation method according to claim 1, characterized in that, The resistive switching layer material in the aforementioned process steps includes neodymium oxide (NdOx), tantalum oxide (TaOx), niobium oxide (NbOx), strontium oxide (SrOx), germanium oxide (GeOx), lanthanum oxide (LaOx), hafnium oxide (HfOx), gallium oxide (GaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), silicon oxide (SiOx), ytterbium oxide (YbOx), magnesium oxide (MgO), aluminum nitride (AlNx), germanium antimony tellurium (GeTex), scandium antimony tellurium (ScSbTe), indium silver antimony tellurium (InAgSbTe), and antimony. At least one of germanium (GeSb), germanium telluride (GeTe), antimony telluride (SbTe), copper sulfide (CuSx), germanium sulfide (GeSx), germanium selenide (GeSex), zinc sulfide (ZnS), and aluminum borate (AlBO); or at least one selected from the group consisting of strontium titanate (SrTiOx), zirconium titanate (ZrTiOx), barium titanate (BaTiOx), hafnium zirconium oxide (HfZrO), and hafnium aluminum oxide (HfAlO); the resistive switching layer is prepared by physical vapor deposition, atomic layer deposition, or chemical vapor deposition.
6. The preparation method according to claim 1, characterized in that, The substrate material in the process steps is a semiconductor substrate material or a silicon-on-insulator (SOI) substrate material.
7. The preparation method according to claim 1, characterized in that, The annealing process in the process steps is rapid annealing (RTP), pulsed laser annealing (PLA), or furnace tube annealing; the annealing atmosphere is vacuum, air, hydrogen, or inert gas, the temperature range is 200–900°C, and the annealing time is 30 seconds to 1 hour.
8. A 1S1R memory cell prepared using the preparation method as described in claim 1, characterized in that, include: The substrate comprises a first electrode layer, a gate layer, a buffer layer, a resistive switching layer, and a second electrode layer, wherein the surface of the buffer layer in contact with the resistive switching layer has a protruding nanocrystalline interface.
9. The 1S1R storage cell as described in claim 8, characterized in that, An intermediate medium layer is added between the gating layer and the buffer layer.