FeFET device based on 3D CIPS material and manufacturing method thereof

Abstract

The invention discloses a FeFET device based on a 3D CIPS material and a manufacturing method thereof, and relates to the technical field of integrated circuit manufacturing, a nickel-copper indium thiophosphate-nickel capacitor structure is constructed based on a metal-insulator-metal capacitor, copper indium thiophosphate is used as a dielectric material, high-temperature annealing is not needed, grain coarsening and polarization intensity reduction caused by high temperature are avoided, and the performance of the device is improved. And oxygen vacancies migrate and gather, ferroelectric fatigue is generated, and the performance is degraded. The copper-indium thiophosphate is a two-dimensional Van der Waals force layered material and has a space group structure of a monoclinic system, a single-layer crystal structure is of an octahedral structure, and copper ions, indium ions and thiophosphate anions occupy triangular symmetric sites in the octahedral structure and are periodically and alternately arranged. All-around grid surrounding and grid surrounding are achieved, a channel is completely wrapped, the electrostatic control capacity of the grid on the channel is enhanced, the short-channel effect is restrained, and passive power consumption is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, in particular to a FeFET device based on 3D CIPS material and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of the integrated circuit industry, according to Moore's law, the performance of transistors is continuously improved while the size of integrated circuits is continuously reduced; at present, due to the short channel effect, it is more and more difficult to reduce the size of the device, and the development of new devices and new processes is the innovative direction to further improve the performance;

[0003] Ferroelectric memory is a kind of random access memory, and the core device FeFET device has many advantages such as non-volatile data storage, high speed reading and writing, long service life and low power consumption, and is widely used in industrial, consumer electronics, communication facilities, automotive electronics, medical equipment and other fields.

[0004] FeFET device is a new type of transistor with ferroelectric material with ferroelectric polarization characteristics as gate insulating layer, and the commonly used ferroelectric material is doped hafnium oxide; hafnium oxide is a non-polar monoclinic phase under normal pressure, and needs to be doped to induce hafnium oxide to form a ferroelectric orthorhombic phase, that is, the doped hafnium oxide has a non-centrosymmetric orthorhombic phase structure, and the displacement between oxygen ions and hafnium ions in the orthorhombic phase forms a dipole moment, which generates spontaneous polarization, and an external electric field can realize information storage;

[0005] But the dopant needs a high crystallization temperature, and high temperature annealing is needed to promote the diffusion of dopant atoms in the hafnium oxide matrix material and promote the dispersion of the dopant in the hafnium oxide; and high temperature will cause the formation of silicon dioxide between hafnium oxide and silicon substrate, further, the formation of depolarization field, resulting in the increase of coercive voltage, aggravating the polarization reversal, leakage current, channel electron mobility, and the reduction of transistor performance.

[0006] And the existing process is a planar transistor arrangement technology, and the device size limits the further improvement of transistor performance, and the number of transistors that can be arranged on a unit silicon wafer is limited, while the 3D integrated process can arrange in three-dimensional space on the limited area of a unit transistor, further improve the number of transistors on a unit silicon wafer, significantly improve the integration, and improve the performance of the device.

[0007] In order to solve the above problems, the present application provides a FeFET device based on 3D CIPS material and a manufacturing method thereof. SUMMARY

[0008] The purpose of the present application is to provide a FeFET device based on 3D CIPS material and a manufacturing method thereof to solve the problems in the prior art.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] FeFET devices include: gate, channel layer, source, drain, molybdenum disulfide layer, and ferroelectric layer;

[0011] The gate is either polysilicon or aluminum.

[0012] The source is polycrystalline silicon;

[0013] The drain electrode is polycrystalline silicon;

[0014] A channel layer is provided between the source and the drain;

[0015] The channel layer material is either silicon dioxide or silicon wire;

[0016] The channel layer is provided with a molybdenum disulfide layer and a ferroelectric layer outside the channel layer;

[0017] The ferroelectric layer material is copper indium thiophosphate.

[0018] A more optimized source electrode thickness is 1-100nm;

[0019] The thickness of the drain electrode is 1-100 nm;

[0020] The diameter of the channel layer is 10-100 nm, and the length is 50-200 nm;

[0021] The thickness of the molybdenum disulfide layer is 5-10 nm;

[0022] The thickness of the ferroelectric layer is 5-10 nm.

[0023] The more optimized manufacturing method is either the post-groove process or the pre-groove process.

[0024] A more optimized post-groove process includes the following steps:

[0025] S1: Substrate material is doped to form the source; the gate is formed by alternating stacking of silicon dioxide and polysilicon in sequence, controlling the deposition thickness to 5-30nm.

[0026] S2: Vertical etching to form memory cell holes; copper indium thiophosphate and molybdenum disulfide are sequentially deposited on the walls of the memory cell holes to form a ferroelectric layer and a molybdenum disulfide layer, and silicon dioxide is filled into the memory cell holes;

[0027] S3: Deposit and grow polycrystalline silicon to form the drain; adjust the resistance value of the drain, etch to form the electrode pattern of the drain, and deposit a layer of silicon dioxide on the drain; planarize the surface of the drain, etch the electrode connection parts to form metal contact holes; deposit electrode contact metal in each metal contact hole to form electrodes; deposit polyimide on the deposited metal contact holes to form a passivation layer, and obtain the FeFET device.

[0028] A more optimized pre-channeling process includes the following steps:

[0029] S(1): Adjust the resistance value of the substrate to form the source; deposit silicon dioxide on the substrate material, etch to form the substrate opening of the silicon wire tube; grow to form the silicon wire tube, and deposit copper indium thiophosphate and molybdenum disulfide around the silicon wire tube in sequence to form the ferroelectric layer and molybdenum disulfide layer; deposit polycrystalline silicon, control the deposition thickness to 5-50nm, and obtain the first layer device;

[0030] S(2): Deposit a silicon dioxide layer on the first device to obtain a silicon dioxide layer; grow a silicon wire to form a silicon wire, and deposit copper indium thiophosphate and molybdenum disulfide around the silicon wire to form a ferroelectric layer and a molybdenum disulfide layer; deposit polycrystalline silicon to obtain the second device;

[0031] S(3): Vertical etching to form metal contact holes, and electrode contact metal is deposited in each metal contact hole to form an electrode;

[0032] S(4): Deposit a silicon dioxide layer on the silicon wire to obtain a silicon dioxide layer; deposit an aluminum metal gate on the silicon dioxide layer to obtain an aluminum metal gate layer; deposit a polyimide layer on the aluminum metal gate layer to obtain a passivation layer; etch the metal electrode to remove the passivation layer and deposit silicon dioxide; etch the silicon dioxide to expose the channel, deposit an aluminum layer on the silicon dioxide layer, connect it to form a drain, and perform pad opening treatment on the passivation layer to obtain a FeFET device.

[0033] In a more optimized version, in step S1, the dopant ion is any one of boron ions, phosphorus ions, and arsenic ions.

[0034] In a more optimized version, in step S3, the resistance value is adjusted to 1-20Ω / Sq.

[0035] In a more optimized manner, in step S(1), the resistance value is adjusted to 1-5KΩ / Sq.

[0036] In a more optimized configuration, the electrode contact metal is any one or more of titanium, titanium nitride, and tungsten.

[0037] A more optimized titanium deposition thickness is 1-20 nm;

[0038] The deposition thickness of the titanium nitride is 1-20 nm;

[0039] The tungsten deposition thickness is 10-20 nm.

[0040] Compared with the prior art, the beneficial effects of the present invention are:

[0041] 1. Copper indium thiophosphate (CuInP2S6, abbreviated as CIPS) is a two-dimensional van der Waals layered material with a monoclinic crystal system space group structure. The monolayer crystal structure is octahedral, with copper ions, indium ions, and thiophosphate anions occupying triangular symmetric sites in the octahedral structure and arranged periodically. The ferroelectric properties of copper indium thiophosphate originate from the asymmetric offset of copper and indium ions in the out-of-plane direction within the sulfur octahedral framework.

[0042] like Figure 1 The graph shows the applied electric field strength on the horizontal axis and the polarization intensity on the vertical axis. Curve 1 illustrates the change in polarization intensity as the applied electric field gradually increases from a negative field, passes through the positive critical point Ec (coercive field), and eventually reaches saturation polarization intensity. Curve 2 shows the change in polarization intensity as the applied electric field decreases from a large positive field, passes through the negative critical point Ec, and eventually reaches negative saturation polarization intensity. The two curves are completely separate, representing two entirely different states. Furthermore, even after high-temperature annealing, the residual polarization intensity Pr is still significantly higher than the saturation polarization intensity, ensuring the retention of the information represented by the polarization intensity.

[0043] This invention constructs a nickel-copper indium thiophosphate-nickel capacitor structure based on a metal-insulator-metal capacitor, using copper indium thiophosphate as the dielectric material. It eliminates the need for high-temperature annealing, directly addressing the technical pain points of hafnium oxide-based FeFET (ferroelectric field-effect transistor) device manufacturing processes. This avoids grain coarsening, reduced polarization intensity, oxygen vacancy migration and aggregation caused by high temperatures, which lead to ferroelectric fatigue and performance degradation.

[0044] 2. The manufacturing method of FeFET devices based on back-channel technology involves alternating stacking of silicon dioxide-polysilicon-silicon dioxide-polysilicon to construct a vertical gate with a bottom select gate-control gate-top select gate structure. First, the gate electrode is stacked to form the gate electrode, and then the channel is formed by vertical etching and filling. This achieves a full-ring gate, with the gate surrounding the channel on all four sides, completely enclosing the channel, enhancing the gate's electrostatic control capability over the channel, suppressing short-channel effects, and reducing passive power consumption.

[0045] By continuously stacking gates, a 3D NAND (data flash memory) structure array is formed through 3D integration technology, improving integration and ensuring compatibility with existing CMOS (complementary metal-oxide-semiconductor) processes.

[0046] 3. The manufacturing method of FeFET devices based on the first-channel process is to construct a vertical channel based on a self-aligned silicon wire, and then deposit copper indium thiophosphate, molybdenum disulfide and polysilicon sequentially around the silicon wire to form the gate electrode; first deposit and grow the silicon wire to form the channel, and then deposit polysilicon as the gate electrode.

[0047] Polysilicon is used as the gate electrode, forming a full-ring gate around the silicon wire. The gate surrounds the channel on all four sides, enhancing the gate's electrostatic control capability over the channel, suppressing short-channel effects, and reducing passive power consumption. The upper-layer devices are electrically connected to the lower-layer channels through vertical silicon wires as channels. Multi-layer channel stacking is achieved through 3D integration technology to increase the effective channel area, improve integration density, and ensure compatibility with existing CMOS processes. Attached Figure Description

[0048] Figure 1 This is a graph showing the variation of polarization intensity and electric field intensity of copper indium thiophosphate in this invention.

[0049] Figure 2 This is a schematic diagram of the FeFET device in Embodiment 1 of the present invention;

[0050] Figure 3 This is a schematic diagram of the structure of the first layer device in Embodiment 2 of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure of the second-layer device in Embodiment 2 of the present invention;

[0052] Figure 5 This is a process flow diagram of step six in Embodiment 2 of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] Example 1: Fabrication method of FeFET device based on back-channel process;

[0055] Step 1: Phosphine ions are generated by ionizing phosphine on the P-type silicon substrate material for ion implantation. The substrate is then annealed at 1050℃ to form the source electrode.

[0056] Step 2: A silicon dioxide layer is deposited on the substrate material by silane and oxygen gas deposition at a temperature of 700℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 18nm, to obtain the silicon dioxide layer.

[0057] By using silane and hydrogen gas deposition, a layer of polycrystalline silicon was deposited on a silicon dioxide layer at a temperature of 650℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 18nm, to obtain a polycrystalline silicon bottom select gate.

[0058] A silicon dioxide layer was deposited on the bottom selective gate of polycrystalline silicon by silane and oxygen gas deposition at a temperature of 700℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 18nm.

[0059] A polycrystalline silicon control gate was obtained by depositing a layer of polycrystalline silicon on a silicon dioxide layer at a temperature of 650℃ and a deposition rate of 9nm / min using silane and hydrogen gas deposition, with the deposition thickness controlled at 18nm.

[0060] A silicon dioxide layer was deposited on a polysilicon control gate by silane and oxygen gas deposition at a temperature of 700℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 18nm.

[0061] By using silane and hydrogen gas deposition, a layer of polycrystalline silicon was deposited on a silicon dioxide layer at a temperature of 650℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 18nm, to obtain a top-select gate polycrystalline silicon.

[0062] A silicon dioxide layer was deposited on the top gate of polycrystalline silicon by silane and oxygen gas deposition at a temperature of 700℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 18nm.

[0063] Step 3: Vertically etch the above-deposited silicon dioxide layer, polysilicon top select gate, silicon dioxide layer, polysilicon control gate, silicon dioxide layer, polysilicon bottom select gate, and silicon dioxide layer to the substrate material, controlling the aperture diameter to 55nm and the length to 126nm to form the memory cell aperture.

[0064] Step 4: A copper indium thiophosphate layer is deposited on the cell wall at 700°C and 9 nm / min using copper chloride, indium chloride, phosphine, hydrogen sulfide, and argon gas deposition to obtain a ferroelectric layer. A molybdenum disulfide layer is deposited on the ferroelectric layer at 800°C and 9 nm / min using molybdenum chloride, hydrogen sulfide, and argon gas deposition to obtain a molybdenum disulfide layer. Silane and oxygen gas deposition is used to fill the cell holes with silicon dioxide at 700°C and 9 nm / min.

[0065] Step 5: Polycrystalline silicon is deposited and grown using silane and hydrogen gas deposition at 650℃ and a deposition rate of 9nm / min to form the drain electrode; phosphorus ions are generated by ionization of phosphine for ion implantation, and the drain electrode is annealed at 1050℃ to adjust its resistance to 10Ω / Sq; photoresist is coated on the drain electrode, and an electrode pattern is formed on the photoresist by photolithography; the electrode pattern of the drain electrode is formed by etching at a power of 300W and an etching rate of 125nm / min; a layer of silicon dioxide is deposited on the drain electrode using silane and oxygen gas deposition at 700℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 20nm.

[0066] Step Six: Prepare a polishing slurry using ammonia monohydrate, hydrogen peroxide, and silicon dioxide. Planarize the drain surface under a pressure of 7 kPa and a rotation speed of 5 rpm. Etch with a mixture of carbon tetrafluoride and oxygen at an etching rate of 50 nm / min using a high-selectivity etching process to form metal contact holes. Deposit a titanium layer on the walls of each metal contact hole using titanium tetrafluoride and hydrogen gas at a temperature of 700℃ and a deposition rate of 9 nm / min, controlling the deposition thickness to 10 nm. Deposit a tungsten nitride layer on the titanium layer using tungsten hexafluoride and ammonia gas at a temperature of 400℃ and a deposition rate of 9 nm / min, controlling the deposition thickness to 10 nm. Deposit a tungsten nitride layer on the tungsten nitride layer using tungsten hexafluoride and hydrogen gas at a temperature of 700℃ and a deposition rate of 9 nm / min, controlling the deposition thickness to 15 nm, to form the electrode.

[0067] Step 7: Sublime is obtained by sublimation of pyromellitic dianhydride and diaminodiphenyl ether at 150°C; polyimide is deposited on the deposited metal contact holes at 350°C with a deposition rate controlled at 100 nm / min to form a passivation layer, thus obtaining the FeFET device.

[0068] Example 2: Fabrication method of FeFET device based on pre-channel technology;

[0069] Step 1: Phosphine ions are generated by ionizing phosphine on the P-type silicon substrate and implanted. The substrate is then annealed at 1050℃, and the resistance is adjusted to 3KΩ / Sq to form the source. A silicon dioxide layer is deposited on the substrate by silane and oxygen gas deposition at 700℃ and a deposition rate of 9nm / min, with the deposition thickness controlled at 13nm.

[0070] Step 2: Coat a silicon dioxide layer with photoresist, and form an etch-sized pattern on the photoresist using photolithography. Then, etch with sulfur hexafluoride and oxygen at an etching rate of 1 μm / min to form the substrate opening of the wire. Finally, directional growth is achieved on the underside of gold catalyst particles using silane catalysis at a temperature of 1100℃ and a pressure of 21 kPa, controlling the diameter of the silicon wire to be 55 nm and the height to be 125 nm, thus forming the silicon wire.

[0071] Step 3: Around the silicon wire, a copper indium thiophosphate layer is deposited on the silicon wire using copper chloride, indium chloride, phosphine, hydrogen sulfide, and argon gas deposition at a temperature of 700℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 8nm, to obtain the ferroelectric layer. Then, a molybdenum disulfide layer is deposited on the ferroelectric layer using molybdenum chloride, hydrogen sulfide, and argon gas deposition at a temperature of 800℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 8nm, to obtain the molybdenum disulfide layer. Finally, polycrystalline silicon is deposited and grown using silane and hydrogen gas deposition at a temperature of 650℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 28nm, to obtain the first device layer.

[0072] Step 4: A silicon dioxide layer is deposited on the first device using silane and oxygen gas deposition at 700℃ and a deposition rate of 9 nm / min. A silicon wire is then formed by directional growth of silane under gold catalyst particles at 1100℃ and 21 kPa. A copper indium thiophosphate layer is deposited around the silicon wire using copper chloride, indium chloride, phosphine, hydrogen sulfide, and argon gas deposition at 700℃ and a deposition rate of 9 nm / min, with a controlled deposition thickness of 8 nm, to obtain a ferroelectric layer. A molybdenum disulfide layer is then deposited on the ferroelectric layer using molybdenum chloride, hydrogen sulfide, and argon gas deposition at 800℃ and a deposition rate of 9 nm / min, with a controlled deposition thickness of 8 nm, to obtain a molybdenum disulfide layer. Finally, polycrystalline silicon is deposited and grown to obtain the second device.

[0073] Step 5: Vertical etching to form metal contact holes; Titanium layer is deposited on the walls of each metal contact hole using titanium tetrafluoride and hydrogen gas deposition at 700℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 10nm, to obtain a titanium layer; Tungsten nitride layer is deposited on the titanium layer using tungsten hexafluoride and ammonia gas deposition at 400℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 10nm, to obtain a tungsten nitride layer; Tungsten nitride layer is deposited on the tungsten nitride layer using tungsten hexafluoride and hydrogen gas deposition at 700℃ and a deposition rate of 9nm / min, with a controlled deposition thickness of 15nm, to obtain a tungsten layer, forming the electrode;

[0074] Step Six: A silicon dioxide layer is deposited on the silicon wire using silane and oxygen gas deposition at 700℃ and a deposition rate of 9 nm / min to obtain a silicon dioxide layer. An aluminum metal gate layer is then deposited on the silicon dioxide layer using aluminum trichloride and hydrogen gas deposition at 800℃ and a deposition rate of 9 nm / min to obtain an aluminum metal gate layer. Sublimation is performed using pyromellitic dianhydride and diaminodiphenyl ether at 150℃. A polyimide layer is then deposited on the aluminum metal gate layer at 350℃ with a controlled deposition rate of 100 nm / min to obtain a passivation layer. Chlorine gas is introduced for reactive ion etching to etch the metal electrode. The passivation layer is removed, and silicon dioxide is deposited. The silicon dioxide is etched to expose the channel, and an aluminum layer is deposited on the silicon dioxide layer and connected to form the drain. The passivation layer is then treated with pad opening and soldered for 50 seconds at a peak temperature of 245℃ to obtain the FeFET device.

[0075] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A FeFET device based on 3D CIPS material, characterized in that: The FeFET device includes: a gate, a channel layer, a source, a drain, a molybdenum disulfide layer, and a ferroelectric layer; The gate is either polysilicon or aluminum. The source is polycrystalline silicon; The drain electrode is polycrystalline silicon; A channel layer is provided between the source and the drain; The channel layer material is either silicon dioxide or silicon wire; The channel layer is provided with a molybdenum disulfide layer and a ferroelectric layer outside the channel layer; The ferroelectric layer material is copper indium thiophosphate.

2. The FeFET device based on 3D CIPS material according to claim 1, characterized in that: The source electrode thickness is 1-100 nm; The thickness of the drain electrode is 1-100 nm; The diameter of the channel layer is 10-100 nm, and the length is 50-200 nm; The thickness of the molybdenum disulfide layer is 5-10 nm; The thickness of the ferroelectric layer is 5-10 nm.

3. A method for fabricating FeFET devices based on 3D CIPS materials, characterized in that: The manufacturing method is either a post-groove process or a pre-groove process.

4. The method for manufacturing a FeFET device based on 3D CIPS material according to claim 3, characterized in that: The post-channel process includes the following steps: S1: Substrate material is doped to form the source; the gate is formed by alternating stacking of silicon dioxide and polysilicon in sequence, controlling the deposition thickness to 5-30nm. S2: Vertical etching to form memory cell holes; copper indium thiophosphate and molybdenum disulfide are sequentially deposited on the walls of the memory cell holes to form a ferroelectric layer and a molybdenum disulfide layer, and silicon dioxide is filled into the memory cell holes; S3: Deposit and grow polycrystalline silicon to form the drain; adjust the resistance value of the drain, etch to form the electrode pattern of the drain, and deposit a layer of silicon dioxide on the drain; planarize the surface of the drain, etch the electrode connection parts to form metal contact holes; deposit electrode contact metal in each metal contact hole to form electrodes; deposit polyimide on the deposited metal contact holes to form a passivation layer, and obtain the FeFET device.

5. The method for manufacturing a FeFET device based on 3D CIPS material according to claim 3, characterized in that: The pre-channeling process includes the following steps: S(1): Adjust the resistance value of the substrate to form the source; deposit silicon dioxide on the substrate material, etch to form the substrate opening of the silicon wire tube; grow to form the silicon wire tube, and deposit copper indium thiophosphate and molybdenum disulfide around the silicon wire tube in sequence to form the ferroelectric layer and molybdenum disulfide layer; deposit polycrystalline silicon, control the deposition thickness to 5-50nm, and obtain the first layer device; S(2): Deposit a silicon dioxide layer on the first device to obtain a silicon dioxide layer; grow a silicon wire to form a silicon wire, and deposit copper indium thiophosphate and molybdenum disulfide around the silicon wire to form a ferroelectric layer and a molybdenum disulfide layer; deposit polycrystalline silicon to obtain the second device; S(3): Vertical etching to form metal contact holes, and electrode contact metal is deposited in each metal contact hole to form an electrode; S(4): Deposit a silicon dioxide layer on the silicon wire to obtain a silicon dioxide layer; deposit an aluminum metal gate on the silicon dioxide layer to obtain an aluminum metal gate layer; deposit a polyimide layer on the aluminum metal gate layer to obtain a passivation layer; etch the metal electrode to remove the passivation layer and deposit silicon dioxide; etch the silicon dioxide to expose the channel, deposit an aluminum layer on the silicon dioxide layer, connect it to form a drain, and perform pad opening treatment on the passivation layer to obtain a FeFET device.

6. The method for manufacturing a FeFET device based on 3D CIPS material according to claim 4, characterized in that: In step S1, the doped ion is any one of boron ion, phosphorus ion, and arsenic ion.

7. The method for manufacturing a FeFET device based on 3D CIPS material according to claim 4, characterized in that: In step S3, the resistance value is adjusted to 1-20Ω / Sq.

8. The method for manufacturing a FeFET device based on 3D CIPS material according to claim 5, characterized in that: In step S(1), the resistance value is adjusted to 1-5KΩ / Sq.

9. The method for manufacturing a FeFET device based on 3D CIPS material according to any one of claims 4-5, characterized in that: The electrode contact metal is any one or more of titanium, titanium nitride, and tungsten.

10. The method for manufacturing a FeFET device based on 3D CIPS material according to claim 9, characterized in that: The titanium deposition thickness is 1-20 nm; The deposition thickness of the titanium nitride is 1-20 nm; The tungsten deposition thickness is 10-20 nm.

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