Same-thickness crosstalk-free two-dimensional floating gate structure integrated with / without access region device
By designing a crosstalk-free two-dimensional floating gate structure of the same thickness, the problem of incomparable performance between devices with and without access regions was solved. This achieved material and thickness consistency, simplified the fabrication process, and improved the reliability and performance comparison capability of the devices.
Patent Information
- Application Number
- CN202511296371.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-11
- Publication Date
- 2025-12-16
AI Technical Summary
In the existing technology, the performance of two-dimensional floating gate devices with and without access areas cannot be effectively compared due to differences in material types or thicknesses, which hinders in-depth research on storage performance and optimization of device design.
A crosstalk-free two-dimensional floating gate structure with and without access regions is designed. The consistency of material and thickness of each layer is ensured by mechanical stripping and PDMS-assisted dry transfer technology. Independent floating gate layers with and without access regions are formed by etching and evaporation processes to achieve electrical isolation and electrode connection.
While ensuring consistent materials and thickness, the problem of stored charge crosstalk was effectively eliminated, the fabrication process was simplified, and the fabrication efficiency and reliability of the device were improved, providing a scientific approach for performance comparison and optimization.
Smart Images
Figure CN121152268A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a same-thickness non-crosstalk two-dimensional floating gate structure integrated with access region device or without access region device. BACKGROUND
[0002] At present, when the traditional floating gate memory device is scaled down to the order of ten nanometers, it faces severe challenges such as retention degradation, endurance limitation, adjacent cell interference, preparation process limitation and random telegraph noise; and two-dimensional materials have unique advantages such as atomic thickness, ultra-high stacking freedom, excellent optoelectronic properties and rich material system, which have become a key direction to break through the bottleneck of traditional technology. At present, the floating gate field effect transistor based on two-dimensional heterostructure has to a great extent alleviated the core problems of traditional devices.
[0003] However, the two-dimensional floating gate device structures with access region and without access region which are focused on in current research still have significant research limitations:
[0004] Firstly, the access region refers to the region where the source and drain electrodes do not coincide with the floating gate layer in the vertical direction. The existence of the access region in the device structure leads to the difference in channel control mode and charge tunneling path of the floating gate device. However, due to the difference in the types of materials (including channel layer, tunneling layer and floating gate layer) of the two structure devices with and without access region, the properties of the two devices are greatly different, and the performance of the two devices cannot be effectively compared.
[0005] Secondly, even if the materials of each layer of the device are the same, the thickness of each layer of material will also have a significant impact on the performance of the device. The thickness of the channel layer affects the band gap width, and thus affects the working current size; the thickness of the tunneling layer affects the tunneling barrier size, which directly affects the charge tunneling starting voltage and tunneling current size; the thickness of the floating gate layer affects its quantum capacitance and state density, and thus affects the storage window size. Therefore, under the condition that the thickness of each layer of material is different, the storage performance of the two structure devices cannot be effectively compared.
[0006] In summary, due to the difference in material type or thickness, the storage performance (such as storage window, retention, endurance, etc.) of the two structure devices with and without access region cannot be effectively compared and analyzed, and the specific influence mechanism of channel control mode and charge tunneling path on storage performance is still unclear. This limits the in-depth study of the performance difference between the two common floating gate structure devices, and hinders the further optimization of the design of floating gate memory devices. SUMMARY
[0007] The embodiment of the present application provides a same-thickness non-crosstalk two-dimensional floating gate structure integrated with access region device and non-access region device, to solve the technical problem of how to design and prepare a floating gate memory device structure in the prior art, so that the same-thickness non-crosstalk two-dimensional floating gate structure integrated with access region device and non-access region device can realize effective comparison of the performance of the two structure devices in the same device under the premise of ensuring that the materials and thicknesses of all layers are completely the same, thereby determining the influence mechanism of different channel control modes and charge tunneling paths on the storage performance.
[0008] In view of the above technical problems, the embodiment of the present application provides a same-thickness non-crosstalk two-dimensional floating gate structure integrated with access region device and non-access region device, comprising:
[0009] A substrate layer, comprising a bottom gate electrode arranged at the bottom layer of the access region device and the non-access region device;
[0010] An insulating layer above the substrate layer, the insulating layer fully covering the bottom gate electrode;
[0011] An access region floating gate layer and a non-access region floating gate layer above the insulating layer, the width of the access region floating gate layer being smaller than the width of the non-access region floating gate layer, the thicknesses of the access region floating gate layer and the non-access region floating gate layer being equal and being made of the same material;
[0012] A tunneling layer above the access region floating gate layer and the non-access region floating gate layer;
[0013] A channel layer above the tunneling layer, the access region floating gate layer and the channel layer not being in contact with each other, and the non-access region floating gate layer and the channel layer not being in contact with each other;
[0014] An access region floating gate electrode above the access region floating gate layer, the access region floating gate electrode being electrically connected with the access region floating gate layer, and the access region floating gate electrode and the channel layer not being in contact with each other;
[0015] An access region source electrode and an access region drain electrode arranged symmetrically about the two ends of the channel layer in the direction of the access region floating gate layer;
[0016] A non-access region floating gate electrode above the non-access region floating gate layer, the non-access region floating gate electrode being electrically connected with the non-access region floating gate layer, and the non-access region floating gate electrode and the channel layer not being in contact with each other;
[0017] A non-access region source electrode and a non-access region drain electrode arranged symmetrically about the two ends of the channel layer in the direction of the non-access region floating gate layer.
[0018] Optionally, the bottom gate electrode is made of heavily p-type doped monocrystalline silicon or heavily n-type doped monocrystalline silicon material; and the insulating layer is silicon dioxide.
[0019] Optionally, the access area floating gate layer and the non-access area floating gate layer are made of graphene or molybdenum telluride with equal thickness.
[0020] Optionally, the tunneling layer is made of hexagonal boron nitride; and the channel layer is made of a transition metal chalcogenide, which includes tungsten diselenide, molybdenum disulfide or molybdenum ditelluride.
[0021] Optionally, the access area floating gate electrode, the access area source electrode, the access area drain electrode, the non-access area floating gate electrode, the non-access area source electrode and the non-access area drain electrode are made of one or more of gold, silver, platinum, titanium, chromium and nickel.
[0022] Optionally, the access area source electrode and the access area drain electrode do not overlap with the access area floating gate layer in the vertical direction; and the non-access area source electrode and the non-access area drain electrode overlap with the non-access area floating gate layer in the vertical direction.
[0023] The application further provides a preparation method of the same-thickness non-crosstalk two-dimensional floating gate structure of the integrated access / non-access area device, which comprises the following steps:
[0024] S1. Obtain two-dimensional material layers with equal thickness as the access area floating gate layer and the non-access area floating gate layer of the device by a mechanical exfoliation method, wherein the two-dimensional material thin layer is graphene or molybdenum telluride; and transfer the two-dimensional material layers to a clean SiO2 / p ++ Si substrate layer by using a PDMS assisted dry transfer method.
[0025] S2. Spin a layer of PMMA photoresist on the substrate layer carrying the access area floating gate layer and the non-access area floating gate layer to form a protective layer.
[0026] Perform pattern exposure on the PMMA photoresist by using an electron beam lithography (EBL) process; after exposure, form a PMMA photoresist etching-resistant layer by developing and fixing steps; wherein the part to be etched is not covered by PMMA to expose it; and the other part is protected by PMMA.
[0027] Put the sample treated by the electron beam exposure and developing and fixing process into a reactive ion etching (RIE) device, use oxygen as the etching gas, and etch the floating gate layer with uniform thickness into two separated parts with relatively narrow and wide rectangular shapes respectively, which will be the access area floating gate layer and the non-access area floating gate layer respectively.
[0028] Remove the PMMA photoresist etching-resistant layer on the sample by using acetone to restore the surface of the floating gate layer.
[0029] S3, preparation and transfer of the tunneling layer and the channel layer:
[0030] The two-dimensional material of the tunneling layer and the channel layer with uniform thickness is prepared by a mechanical exfoliation method, and the tunneling layer is transferred to the separated floating gate layer with an access region and the floating gate layer without an access region at a preset angle and position by using a PDMS-assisted dry transfer method.
[0031] The channel layer is transferred to the transferred tunneling layer by using a PDMS-assisted dry transfer method; in the vertical direction, the channel layer needs to cover most of the area of the floating gate layer with an access region and the floating gate layer without an access region;
[0032] S4, preparation of electrodes and bottom gate:
[0033] A layer of PMMA photoresist is coated on the surface of the sample as a patterning mask, and a preset electrode pattern is exposed to the photoresist by using an electron beam exposure process;
[0034] Under high vacuum conditions, metal materials are evaporated onto the surface of the sample by a thermal evaporation process to form electrode structures; the evaporated metal will form two pairs of source electrodes, drain electrodes and floating gate electrodes in the device without an access region and the device with an access region according to the pattern exposed by the electron beam; that is, the floating gate electrode with an access region, the source electrode with an access region, the drain electrode with an access region, the floating gate electrode without an access region, the source electrode without an access region and the drain electrode without an access region.
[0035] Part of the silicon dioxide on the surface of the silicon wafer substrate is removed by using a diamond knife, and part of the bare heavily doped silicon is used as a common bottom gate.
[0036] In the present application, the device with an access region and the device without an access region are integrated, and the channel layer, the tunneling layer and the floating gate layer of the two devices share the same two-dimensional material with uniform thickness, respectively, which ensures the consistency of the thickness and properties of the layers of the two devices. This design enables effective comparison of the storage performance of the devices with / without an access region structure under strict control of variables, providing a scientific and reliable way to explore the universal difference in storage performance of the two common floating gate structure devices, which helps to understand the specific influence mechanism of different channel control modes and charge tunneling paths on the storage performance.
[0037] The application effectively solves the problem of storage charge crosstalk between devices caused by sharing the same piece of floating gate layer material by etching the floating gate layer into two separate parts, and the two parts are derived from the same thickness uniform two-dimensional material, under the premise of ensuring the same material thickness. In addition, the micro-nano processing flow of the application is relatively simple and easy to realize, integrates two common structure floating gate devices into the same two-dimensional material heterostructure, realizes strict control variables under the same thickness and material properties, which not only improves the preparation efficiency of the device, but also reduces the preparation cost, and provides strong support for the further research and practical application of two-dimensional floating gate memory devices. BRIEF DESCRIPTION OF DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0039] Figure 1 is a schematic diagram of the same thickness crosstalk-free two-dimensional floating gate structure integrated with / without access region devices in an embodiment of the application;
[0040] Figure 2 is an optical picture of the same thickness crosstalk-free two-dimensional floating gate structure integrated with / without access region devices in an embodiment of the application;
[0041] Figure 3 is an optical picture of the construction process of the same thickness crosstalk-free two-dimensional floating gate structure integrated with / without access region devices in an embodiment of the application;
[0042] Figure 4 is an optical picture of the two-dimensional heterostructure in step S4 in an embodiment of the application;
[0043] Figure 5 is a process flow diagram of step S2 in an embodiment of the application;
[0044] Figure 6 is a process flow diagram of steps S3-S4 in an embodiment of the application.
[0045] The reference signs in the specification are as follows:
[0046] 1-substrate layer, 2-insulating layer, 3-floating gate layer with access region, 4-floating gate layer without access region, 5-tunneling layer, 6-channel layer, 7-floating gate electrode with access region, 8-source electrode with access region, 9-drain electrode with access region, 10-floating gate electrode without access region, 11-source electrode without access region, 12-drain electrode without access region. DETAILED DESCRIPTION
[0047] In order to make the technical problems, technical solutions and beneficial effects solved by the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.
[0048] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.
[0049] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between the two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0050] As shown in the drawings, an embodiment of the present application provides a same-thickness crosstalk-free two-dimensional floating gate structure integrated with access zone device, comprising: Figures 1 to 6 A substrate layer 1, comprising a bottom gate electrode arranged at the bottom layer of the access zone device; the bottom gate electrode serves as the bottom gate of the device and also plays a supporting role.
[0051] An insulating layer 2 above the substrate layer 1, the insulating layer 2 fully covers the bottom gate electrode; the insulating layer 2 plays a role of isolating the bottom gate electrode and preventing leakage current.
[0052] An access zone floating gate layer 3 and a non-access zone floating gate layer 4 above the insulating layer 2, the width of the access zone floating gate layer 3 is less than the width of the non-access zone floating gate layer 4, the thickness of the access zone floating gate layer 3 and the non-access zone floating gate layer 4 is equal and made of the same material; the width of the access zone floating gate layer 3 and the non-access zone floating gate layer 4 can be set according to requirements.
[0053]
[0054] A tunnel layer 5 is located above the access region floating gate layer 3 and the non-access region floating gate layer 4; in the vertical direction, the tunnel layer 5 covers most of the access region floating gate layer 3 and the non-access region floating gate layer 4.
[0055] A channel layer 6 is located above the tunnel layer 5; the access region floating gate layer 3 and the channel layer 6 are not in contact with each other, and the non-access region floating gate layer 4 and the channel layer 6 are not in contact with each other; the channel layer 6 is electrically isolated from the access region floating gate layer 3 and the non-access region floating gate layer 4 by the tunnel layer 5, and is electrically isolated from the bottom gate electrode by the insulating layer 2, and is subjected to voltage regulation by the two floating gate layers and the bottom gate electrode.
[0056] An access region floating gate electrode 7 is located above the access region floating gate layer 3; the access region floating gate electrode 7 is electrically connected to the access region floating gate layer 3, and in the horizontal direction, the access region floating gate electrode 7 and the channel layer 6 are not in contact with each other.
[0057] An access region source electrode 8 and an access region drain electrode 9 are located above the channel layer 6 in the direction of the access region floating gate layer 3 and are symmetrically arranged about the two ends of the channel layer 6; and are electrically connected based on the channel layer 6; in the horizontal direction, the access region source electrode 8 and the access region drain electrode 9 are not in contact with each other; in the vertical direction, the access region source electrode 8, the access region drain electrode 9 and the floating gate electrode 3 have no overlapping area.
[0058] A non-access region floating gate electrode 10 is located above the non-access region floating gate layer 4; the non-access region floating gate electrode 10 is electrically connected to the non-access region floating gate layer 4, and in the horizontal direction, the non-access region floating gate electrode 10 and the channel layer 6 are not in contact with each other.
[0059] A non-access region source electrode 11 and a non-access region drain electrode 12 are located above the channel layer 6 in the direction of the non-access region floating gate layer 4 and are symmetrically arranged about the two ends of the channel layer 6; and are electrically connected based on the channel layer 6; in the horizontal direction, the non-access region source electrode 11 and the non-access region drain electrode 12 are not in contact with each other; in the vertical direction, the non-access region source electrode 11, the non-access region drain electrode 12 and the floating gate electrode 4 have overlapping areas.
[0060] In an embodiment, the bottom gate electrode is made of heavily p-type doped monocrystalline silicon (p ++ Si) or heavily n-type doped monocrystalline silicon (n ++ Si) material; the insulating layer 2 is silicon dioxide (SiO2).
[0061] In an embodiment, the access region floating gate layer 3 and the non-access region floating gate layer 4 are both made of graphene (Gr) or molybdenum ditelluride (MoTe2) with equal thickness.
[0062] In an embodiment, the tunneling layer 5 is made of hexagonal boron nitride (h-BN); the channel layer 6 is made of transition metal dichalcogenide (TMDs), including tungsten diselenide (WSe2), molybdenum disulfide (MoS2) or molybdenum ditelluride (MoTe2).
[0063] In an embodiment, the access region floating gate electrode 7, the access region source electrode 8, the access region drain electrode 9, the non-access region floating gate electrode 10, the non-access region source electrode 11 and the non-access region drain electrode 12 are all made of one or more of gold, silver, platinum, titanium, chromium and nickel.
[0064] In an embodiment, the access region source electrode 8 and the access region drain electrode 9 have no overlapping area with the access region floating gate layer 3; the non-access region source electrode 11 and the non-access region drain electrode 12 have overlapping area with the non-access region floating gate layer 4.
[0065] As shown in Figures 2 to 6 The present application also provides a preparation method of the same-thickness non-crosstalk two-dimensional floating gate structure of the integrated access / non-access region device, comprising:
[0066] S1, obtain a two-dimensional material layer with equal thickness as the access region floating gate layer 3 and the non-access region floating gate layer 4 of the device by mechanical exfoliation method, the two-dimensional material thin layer is graphene or molybdenum ditelluride; use PDMS assisted dry transfer method to transfer the two-dimensional material layer to a clean SiO2 / p ++ Si substrate layer 1;
[0067] As shown in Figure 5 S2 is to spin a layer of PMMA photoresist on the substrate layer 1 carrying the access region floating gate layer 3 and the non-access region floating gate layer 4 to form a protective layer.
[0068] Use electron beam exposure (EBL) process to pattern expose the PMMA photoresist, after exposure, through development and fixing steps to make PMMA photoresist etching resist layer; wherein the part that needs to be etched is not covered with PMMA to expose it; other parts are protected by PMMA.
[0069] The sample processed by electron beam exposure and developing fixation process is put into a reactive ion etching (RIE) device, and an oxygen (O2) gas is used as etching gas to etch the uniform thickness floating gate layer into two separated parts with relatively narrow and wide rectangular shapes, which will be used as the access region floating gate layer 3 and the non-access region floating gate layer 4 respectively.
[0070] The PMMA photoresist etch-resistant layer on the sample is removed using acetone to restore the surface of the floating gate layer.
[0071] As can be understood, in this step S2, the original single floating gate layer is ingeniously etched into two independent parts, i.e., the access region floating gate layer and the non-access region floating gate layer. Both of the two floating gate layers are derived from the same piece of two-dimensional material with uniform thickness, which fundamentally ensures their consistency in thickness and material properties. At the same time, the problem of charge crosstalk caused by sharing the same floating gate layer is effectively eliminated through physical separation. This innovative design not only ensures the high consistency of the floating gate layers of the access region and non-access region devices in physical properties, but also fundamentally solves the problem of storage charge crosstalk caused by sharing the floating gate layer in traditional design, providing a solid foundation for subsequent device performance testing and comparative analysis.
[0072] As shown in Figure 3 , Figure 4 , Figure 6 , the S3 is the preparation and transfer of the tunneling layer 5 and the channel layer 6.
[0073] The two-dimensional materials of the tunneling layer 5 and the channel layer 6 with uniform thickness are prepared by mechanical exfoliation method, and the PDMS-assisted dry transfer method is used to transfer the tunneling layer 5 to the separated access region floating gate layer 3 and non-access region floating gate layer 4 at a preset angle and position.
[0074] The PDMS-assisted dry transfer method is used to transfer the channel layer 6 to the transferred tunneling layer 5; in the vertical direction, the channel layer 6 needs to cover most of the area of the access region floating gate layer 3 and the non-access region floating gate layer 4.
[0075] Understandably, in this step S3, the key of this step is that the tunneling layer 5 and the channel layer 6 of the two devices share the same piece of two-dimensional material with uniform thickness respectively, so as to ensure the same thickness and material properties. Its functions and purposes mainly have three aspects: first, to ensure that the two devices with access area and without access area maintain high consistency in the material properties of the tunneling layer 5 and the channel layer 6, providing a fair test basis for subsequent performance comparison; second, to realize precise coverage of the tunneling layer 5 and the channel layer 6 through precise transfer angle and position control, creating conditions for electrical connection and function realization of the device; third, this design of sharing the same material helps to simplify the preparation process, improve the consistency and reliability of the device, and at the same time reduce the risk of performance fluctuation caused by material differences.
[0076] As shown in Figure 6 S4, preparation of electrodes and bottom gate:
[0077] A layer of PMMA photoresist is coated on the surface of the sample as a patterning mask, and an electronic beam exposure process is used to expose the preset electrode pattern to the photoresist.
[0078] Under high vacuum conditions, metal material is evaporated onto the surface of the sample by a thermal evaporation process to form an electrode structure; the evaporated metal will form two pairs of source electrodes, drain electrodes and floating gate electrodes in the device without access area and the device with access area according to the pattern exposed by the electron beam; that is, the floating gate electrode 7 of the device with access area, the source electrode 8 of the device with access area, the drain electrode 9 of the device with access area, the floating gate electrode 10 of the device without access area, the source electrode 11 of the device without access area and the drain electrode 12 of the device without access area.
[0079] A diamond knife is used to remove part of the silicon dioxide on the surface of the silicon substrate, and part of the heavily doped silicon is exposed as a common bottom gate.
[0080] Understandably, in this step S4, by coating PMMA photoresist on the surface of the sample and using an electron beam exposure process, the preset electrode pattern is accurately transferred to the photoresist, and then under high vacuum conditions, metal material is evaporated onto the surface of the sample by a thermal evaporation process, thereby forming a specific electrode structure. This process not only ensures the accurate patterning of the electrodes, but also realizes the electrical connection of the two pairs of source electrodes, drain electrodes and floating gate electrodes of the device without access area and the device with access area, providing the necessary conditions for subsequent device testing and performance evaluation. In addition, by using a diamond knife to remove part of the silicon dioxide on the surface of the silicon substrate, part of the heavily doped silicon is exposed as a common bottom gate, providing a unified gate control for the entire device, simplifying the electrical control and testing process of the device. This step not only ensures the consistency and reliability of the device, but also realizes the difference in electrical characteristics between the device with access area and the device without access area, laying a solid foundation for subsequent performance testing and comparative analysis.
[0081] In an embodiment, the preset angle and position in step S3 need to satisfy:
[0082] The tunneling layer 5 covers most of the separate access region floating gate layer 3 and non-access region floating gate layer 4 to ensure that the access region device and the non-access region device have the same thickness and material properties of the tunneling layer; part of the access region floating gate layer 3 and the non-access region floating gate layer 4 is not covered by the tunneling layer 5 to ensure that a small part of the floating gate layer is exposed, which facilitates the subsequent direct contact of the access region floating gate electrode 7 and the non-access region floating gate electrode 10 with the access region floating gate layer 3 and the non-access region floating gate layer 4, respectively, to realize electrical connection.
[0083] In an embodiment, in step S4, in the non-access region device, the non-access region source electrode 11 and the non-access region drain electrode 12 have a coincident region with the non-access region floating gate layer 4 in the vertical direction, so that there is no access region in the device, and a source / drain electrode / tunneling layer / floating gate layer heterostructure is formed, so that there is a charge tunneling path from the source / drain electrode to the floating gate layer in the device.
[0084] In the access region device, the access region source electrode 8 and the access region drain electrode 9 have no coincident region with the access region floating gate layer 3 in the vertical direction, so that there is an access region in the device, and there is also no charge tunneling path from the source / drain electrode to the floating gate layer in the device due to the absence of a source / drain electrode / tunneling layer / floating gate layer heterostructure.
[0085] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.
Claims
1. A two-dimensional floating gate structure of the same thickness with / without access area devices, characterized in that, include: The substrate layer (1) includes a bottom gate electrode disposed at the bottom layer of the device with / without access region; An insulating layer (2) is located above the substrate layer (1), and the insulating layer (2) completely covers the bottom gate electrode; Located above the insulating layer (2) are a floating gate layer (3) with an access area and a floating gate layer (4) without an access area. The width of the floating gate layer (3) with an access area is smaller than the width of the floating gate layer (4) without an access area. The floating gate layer (3) with an access area and the floating gate layer (4) without an access area have the same thickness and are made of the same material. The tunneling layer (5) is located above the floating gate layer (3) with access area and the floating gate layer (4) without access area; The channel layer (6) located above the tunnel layer (5) has an access area floating gate layer (3) that does not contact the channel layer (6) and an accessless floating gate layer (4) that does not contact the channel layer (6). The access area floating gate electrode (7) is located above the access area floating gate layer (3). The access area floating gate electrode (7) is electrically connected to the access area floating gate layer (3). The access area floating gate electrode (7) is not in contact with the channel layer (6). The channel layer (6) is located in the direction of the floating gate layer (3) with access area, and the source electrode (8) and the drain electrode (9) with access area are symmetrically arranged about both ends of the channel layer (6); The no-access area floating gate electrode (10) is located above the no-access area floating gate layer (4). The no-access area floating gate electrode (10) is electrically connected to the no-access area floating gate layer (4). The no-access area floating gate electrode (10) is not in contact with the channel layer (6). The source electrode (11) and drain electrode (12) of the no-access area are located in the direction of the channel layer (6) toward the no-access area floating gate layer (4) and are symmetrically arranged about both ends of the channel layer (6).
2. The two-dimensional floating gate structure of the same thickness with / without access area devices according to claim 1, characterized in that, The bottom gate electrode is made of heavily p-type doped single-crystal silicon or heavily n-type doped single-crystal silicon; the insulating layer (2) is silicon dioxide.
3. The two-dimensional floating gate structure with / without access area devices of the same thickness and no crosstalk as described in claim 2, characterized in that, Both the floating gate layer (3) with access area and the floating gate layer (4) without access area are made of graphene or molybdenum telluride of equal thickness.
4. The two-dimensional floating gate structure of the same thickness with / without access area devices according to claim 3, characterized in that, The tunneling layer (5) is made of hexagonal boron nitride; the channel layer (6) is made of transition metal chalcogenides, including tungsten diselenide, molybdenum disulfide or molybdenum ditelluride.
5. The two-dimensional floating gate structure of the same thickness with / without access area devices according to claim 4, characterized in that, The floating gate electrode (7) with access area, the source electrode (8) with access area, the drain electrode (9) with access area, the floating gate electrode (10) without access area, the source electrode (11) without access area, and the drain electrode (12) without access area are all made of one or more of gold, silver, platinum, titanium, chromium, and nickel.
6. The two-dimensional floating gate structure of the same thickness with / without access area devices according to claim 5, characterized in that, The source electrode (8) with access area and the drain electrode (9) with access area have no overlapping area in the vertical direction with the floating gate layer (3) with access area; the source electrode (11) without access area and the drain electrode (12) without access area have overlapping area in the vertical direction with the floating gate layer (4) without access area.
7. A method for fabricating a two-dimensional floating gate structure of the same thickness with / without access region devices, characterized in that, include: S1. Two-dimensional material layers of equal thickness are obtained by mechanical exfoliation to serve as the floating gate layer (3) with access region and the floating gate layer (4) without access region of the device. The two-dimensional material thin layer is graphene or molybdenum telluride. The upper two-dimensional material layer is transferred to a clean SiO2 / p surface using a PDMS-assisted dry transfer method. ++ On the Si substrate (1); S2. A layer of PMMA photoresist is spin-coated onto the substrate layer (1) containing the floating gate layer (3) with access area and the floating gate layer (4) without access area to form a protective layer; Electron beam lithography (EBL) is used to pattern PMMA photoresist. After exposure, a PMMA photoresist etch-resistant layer is formed through development and fixing steps. The areas to be etched are exposed without being covered by PMMA, while other areas are protected by PMMA. The sample that has been processed by electron beam exposure and development and fixing is placed in a reactive ion etching (RIE) device. Oxygen is used as the etching gas. Under the preset radio frequency voltage and gas pressure, the uniform thickness of the floating gate layer is etched into two separate parts with narrower and wider rectangular shapes, respectively. These two parts will be used as the floating gate layer with access area (3) and the floating gate layer without access area (4), respectively. Acetone was used to remove the PMMA photoresist resist layer on the sample, restoring the surface of the floating gate layer. Preparation and transfer of S3, tunneling layer (5) and channel layer (6): Two-dimensional materials of tunneling layer (5) and channel layer (6) with uniform thickness were prepared by mechanical peeling method. The tunneling layer (5) was transferred to the separated floating gate layer (3) with access area and floating gate layer (4) without access area at a preset angle and position using a PDMS-assisted dry transfer method. Using a PDMS-assisted dry transfer method, the trench layer (6) is transferred to the tunnel layer (5) after the transfer is completed; in the vertical direction, the trench layer (6) needs to cover most of the area of the access area floating gate layer (3) and the non-access area floating gate layer (4); S4. Fabrication of electrodes and bottom gate: A layer of PMMA photoresist is coated on the sample surface as a patterning mask, and the preset electrode pattern is exposed onto the photoresist using an electron beam exposure process. Under high vacuum conditions, metal materials are deposited onto the sample surface through a thermal evaporation process to form an electrode structure. The deposited metal will form two pairs of source electrodes, drain electrodes, and floating gate electrodes in the device without access area and the device with access area, respectively, according to the pattern exposed by the electron beam. That is, the floating gate electrode with access area (7), the source electrode with access area (8), the drain electrode with access area (9), the floating gate electrode without access area (10), the source electrode without access area (11), and the drain electrode without access area (12). A diamond cutter was used to remove part of the silicon dioxide from the surface of the silicon substrate, exposing some of the heavily doped silicon as a common bottom gate.
8. The method for fabricating a two-dimensional floating gate structure of the same thickness with / without access area devices according to claim 7, characterized in that, The preset angle and position in step S3 must meet the following requirements: The tunnel layer (5) simultaneously covers most of the separated access area floating grid layer (3) and non-access area floating grid layer (4); some areas of the access area floating grid layer (3) and non-access area floating grid layer (4) are not covered by the tunnel layer (5).
9. The method for fabricating a two-dimensional floating gate structure of the same thickness without crosstalk that integrates devices with / without access areas according to claim 7, characterized in that, In step S4: In the device without access region, the source electrode (11) and the drain electrode (12) of the without access region overlap with the floating gate layer (4) of the without access region in the vertical direction to form a heterogeneous structure; In the device with access area, there is no overlap between the access area source electrode (8) and the access area drain electrode (9) and the access area floating gate layer (3).