Semiconductor structure and method of manufacturing semiconductor device

Abstract

The structure includes a combined semiconductor die, an interposer, and a solder bump coupled between the combined semiconductor die and the interposer. The combined semiconductor die includes a first cell region and a second cell region over a semiconductor substrate. The first cell region adjoins the second cell region. The first cell region includes a first device portion and a first dummy portion. The second cell region includes a second device portion and a second dummy portion. The first dummy portion includes a first conductive feature, and the second dummy portion includes a second conductive feature in physical contact with the first conductive feature. The embodiment of the invention also relates to a semiconductor structure and a method for manufacturing the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor structures and methods of fabricating semiconductor devices. BACKGROUND

[0002] Improvements in packaging of components seek to provide smaller packages that occupy less area than previous packages. Examples of types of packages for semiconductors include quad flat packages (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chip (FC), three-dimensional integrated circuits (3DIC), wafer level packages (WLP), package on package (PoP), system on chip (SoC), or system on integrated circuit (SoIC) devices. Some of these three-dimensional devices (e.g., 3DIC, SoC, SoIC) are fabricated by placing chips on top of chips at the wafer level of the semiconductor. These three-dimensional devices provide improved integration density and other advantages such as faster speed and higher bandwidth due to the reduced length of interconnects between stacked chips. However, there are many challenges associated with three-dimensional devices.

[0003] For example, in the packaging of integrated circuits, multiple device dies can be bonded on an interposer wafer, which can include multiple interposers disposed therein. After the device dies are bonded, an underfill is dispensed to fill the gap between the device dies and the interposer wafer. A curing process can then be implemented to cure the underfill. Molding compound can be applied to encapsulate the device dies. The resulting interposer wafer and top dies can then be sawn into multiple packages, where the packages include exposed electrical connections (e.g., solder balls). The packages are then bonded to a package substrate or printed circuit board. SUMMARY

[0004] Some embodiments of the present application provide a method of fabricating a semiconductor device, comprising: forming a first unit area over a semiconductor substrate using a first mask, the first unit area comprising a first device portion and a first dummy portion, the first dummy portion comprising a first alignment mark; forming a second unit area over the semiconductor substrate using a second mask different from the first mask, the second unit area comprising a second device portion and a second dummy portion, the second dummy portion adjacent to the first dummy portion, the second dummy portion comprising a second alignment mark corresponding to the first alignment mark; and forming a single first die comprising the first unit area and the second unit area together.

[0005] Some embodiments of the application provide a method of manufacturing a semiconductor device, comprising: forming a first unit area over a semiconductor substrate using a first mask, the first unit area comprising a first device portion and a first dummy portion, the first unit area comprising an intermediate mask size limit size; forming a second unit area over the semiconductor substrate using a second mask, the second unit area comprising a second device portion and a second dummy portion, the second dummy portion in physical contact with the first dummy portion, the second unit area comprising the intermediate mask size limit size; and forming a single first die comprising the first unit area and the second unit area together.

[0006] Some embodiments of the application provide a semiconductor structure, comprising: a combined semiconductor die comprising a first unit area and a second unit area over a semiconductor substrate, the first unit area adjoining the second unit area, the first unit area comprising a first device portion and a first dummy portion, the second unit area comprising a second device portion and a second dummy portion, the first dummy portion comprising a first conductive component, the second dummy portion comprising a second conductive component connected with the first conductive component; an interposer; and a solder bump coupled between the combined semiconductor die and the interposer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the illustrative embodiments can be best understood with reference to the following detailed description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or equivalent elements in the figures. It is emphasized that, according to the standard practice in the industry, various components are not necessarily drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A top view of a combined semiconductor die is shown in accordance with some embodiments.

[0009] Figure 2 A cross-sectional view of a package comprising a combined semiconductor die is shown in accordance with some embodiments.

[0010] Figure 3 A cross-sectional view of a dummy portion of a combined semiconductor die is shown in accordance with some embodiments.

[0011] Figures 4A to 4J Structures in various stages of a process are shown in accordance with some embodiments.

[0012] Figure 5 A flowchart of a process is shown in accordance with some embodiments.

[0013] Figures 6 to 8 Some example implementations are shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, embodiments of the present disclosure can refer to a component resting, being, located, being positioned, and / or being formed "adjacent" to one or more other components. This term is used to express that a spatial or functional relationship exists between the components. Such positional relationship can include direct contact and / or non-contact between the components. In addition, the present disclosure embodiments can repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the

[0015] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element's or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] Embodiments of the present disclosure are directed to substrates or interconnect device dies and to interconnect structures having additional dies connected thereto, such as integrated system-on-a-chip (SoIC) package designs and structures.

[0017] Modern data at scale, such as analytic data or AI programming, can easily overwhelm memory and compute resources on computing servers. For example, deriving meaningful insights from big data requires rich analytics. The throughput demand for massive data in the big data and AI fields is increasing. This is true both with respect to the exponential growth in the amount of data and with respect to the increasing number and complexity of formats of data that such platforms must manage. Today, AI and big data chipsets need to manage not only relational data, but also text, video, images, emails, social network information streams, real-time data streams, sensor data, and the like.

[0018] Figure 1 A top view of a combined semiconductor die 100 is schematically shown in accordance with some embodiments. The semiconductor die 100 can include two or more unit dies or unit die regions ("unit regions") 110. Four unit regions 110a, 110b, 110c, 110d are shown Figure 1In some implementations, the unit regions 110a, 110b, 110c, and 110d include similar sizes, similar circuit structures, and similar functional blocks. For example, each of the unit regions 110 includes graphics processing unit (“GPU”) circuitry for a super artificial intelligence (“AI”) application. In some implementations, one or more of the unit regions 110 includes a different size, a different circuit structure, or different functional blocks than the other unit regions 110 in the combined semiconductor die 100. For example, in some implementations, one or more of the unit regions 110 is a memory chip and one or more of the unit regions 110 is an AI GPU chip.

[0019] The stitch region 110ab is disposed between the unit region 110a and the unit region 110b and includes a respective dummy portion of each of the unit region 110a and the unit region 110b. The stitch region 110ac is disposed between the unit region 110a and the unit region 110c and includes a respective dummy portion of each of the unit region 110a and the unit region 110c. The stitch region 110bd is disposed between the unit region 110b and the unit region 110d and includes a respective dummy portion of each of the unit region 110b and the unit region 110d. The stitch region 110cd is disposed between the unit region 110c and the unit region 110d and includes a respective dummy portion of each of the unit region 110c and the unit region 110d. In some implementations, the dummy portions do not include functional blocks or circuitry of the corresponding unit regions 110, but the dummy portions include components for “stitching” or connecting the adjacent unit regions 110. For example, the dummy portions each include alignment marks and conductive or metallic components. The metallic components connect circuitry of the adjacent unit regions 110. The alignment marks are used, among other things, to align the metallic components of adjacent dummy portions in formation of the adjacent unit regions 110.

[0020] The stitch regions each include a respective dummy portion of an adjacent unit region 110 and thus are partially superimposed with each of the adjacent unit regions 110. The stitch regions are disposed within the combined semiconductor die 100 and are referred to as “in-die superimposed” regions for purposes of the description to distinguish from superimposed regions formed outside and between two dies or chips. Portions of the unit regions other than the dummy portions are referred to as “device portions.” The device portions of the unit regions include semiconductor devices, e.g., transistors, that form functional blocks of the unit regions. The device portions can include various devices formed thereon. For example, the various devices can include active components, passive components, or a combination thereof. For example, the device portions can include circuit components that form a memory array or other memory structure. For example, the device portions can include circuit components that provide functional blocks such as communication, logic, graphics, general purpose processing, or other data processing functionality. In some embodiments, the device portions can include GPUs for super AI applications.

[0021] Each of the stitching regions 110ab, 110ac, 110bd, and 110cd includes a width W1. In some embodiments, the width W1 is in the range of about 10 μm to about 40 μm (inclusive). For example, the width W1 is about 20 μm. The combined semiconductor die 100 and adjacent semiconductor die 102 ( Figure 1 The physical distance W2 between the combined semiconductor die 100 (either a combined semiconductor die or a unit semiconductor die, e.g., a single unit having only a device portion, as shown in the dashed box in the diagram) ranges from about 40 μm to about 300 μm. In some embodiments, both the combined semiconductor die 100 and the adjacent semiconductor die 102 are positioned on an interposer die (“interposer”) or a package substrate (…). Figure 1 (Not shown in the image). Due to physical design rules or limitations, such as spacing margins for die processing or solder bump or solder ball spacing, the physical distance W2 cannot be reduced indefinitely, so that the width W1 of the stitching area will always be less than the physical distance W2 between adjacent semiconductor dies positioned on the interposer or package substrate.

[0022] Figure 2 Showing from Figure 1 The cross-sectional view shown by section line 2-2 is a cross-sectional view of the package structure 201 including the combined semiconductor die 100. According to some embodiments of the present disclosure, each of the cell regions 110a, 110c includes a corresponding device portion 110a1, 110c1 and a corresponding pseudo-portion 110a2, 110c2. The pseudo-portions 110a2, 110c2 are adjacent to each other. In some embodiments, the pseudo-portions 110a2, 110c2 are adjacent to each other. Each device portion 110a1, 110c1 includes an integrated circuit device 210 (210a, 210c) formed on a semiconductor substrate 200. Representative integrated circuit devices 210 include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device 210 are not shown herein. In some embodiments of the present disclosure, the integrated circuit device 210 is a graphics processing unit.

[0023] In some embodiments, each of the pseudo-parts 110a2 and 110c2 does not include an active device such as a transistor or diode, and may or may not include passive devices. The pseudo-parts 110a2 and 110c2 may include conductive components 220 (220a, 220c) disposed in or on one or more metallization layers, such as metal pads or lines. Conductive traces and vias that electrically interconnect the conductive components on different metallization layers may also be formed in each of the pseudo-parts 110a2 and 110c2.

[0024] Substrate 200 can be a semiconductor substrate or a dielectric substrate. When substrate 200 includes a semiconductor substrate, it can be formed of crystalline silicon, crystalline germanium, silicon-germanium, or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. Semiconductor substrate 200 can also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) can be formed in semiconductor substrate 200 to isolate active regions in semiconductor substrate 200. When substrate 200 includes a dielectric substrate, it can be formed of silicon oxide, silicon carbide, silicon nitride, etc. Through-holes (not shown) can be formed to extend into semiconductor substrate 200, wherein the through-holes are used to electrically couple components on opposite sides of semiconductor die 100. The through-holes can be insulated from substrate 200 by an isolation layer.

[0025] Let's refer to each other. Figure 1 and Figure 2 In some embodiments, cell regions 110a and 110c each have a size defined by applicable intermediate mask size constraints, for example, 26 mm × 33 mm. The combined semiconductor die 100 integrates or combines two or more fully intermediate mask size-constrained cell regions arranged relative to each other in at least one direction. Figure 1 As shown, as an example, the combined semiconductor die 100 integrates or combines four cell regions, each with a size constrained by the full intermediate mask size, arranged in two directions (x-axis and y-axis). The x-axis dimension D1 of the combined semiconductor die 100 is equal to the sum of the corresponding x-axis dimensions D1a and D1c of adjacent cell regions 110a and 110c. In some embodiments, the dimensions D1a and D1c of cell regions 110a and 110c are each substantially 33 mm, which is the full intermediate mask size constraint in the x-axis (or y-axis) direction. The y-axis dimension D2 of the combined semiconductor die 100 is equal to the sum of the corresponding y-axis dimensions D2a and D2b of adjacent cell regions 110a and 110b. In some embodiments, the dimensions D2a and D2b of cell regions 110a and 110b are each substantially 26 mm, which is the full intermediate mask size constraint in the y-axis (or x-axis) direction. Therefore, the combined semiconductor die 100 has a dimension D1 of approximately 66 mm and a dimension D2 of approximately 52 mm. It should be noted that the complete intermediate mask size constraints shown herein are based on current i193 and EUV lithography steppers with dimensions of 26 mm × 33 mm or 858 mm. 2of the maximum field size. The full intermediate mask size or the size of the cell region 110 can vary with different lithography steppers. For example, for a high-NA EUV lithography stepper, the intermediate mask limit will be 26 mm x 16.5 mm or 429 mm 2 .

[0026] The dummy portions 110a2, 110b2, 110c2, 110d2 are included in the corresponding cell regions 110a, 110b, 110c, 110d. The full intermediate mask size of a cell region includes the size of the dummy portions of the cell region. If a cell region 110 is adjacent to more than one neighboring cell region, it can include more than one dummy portion adjacent to each of the neighboring cell regions 110. The dummy portion 110a2 includes a width W3a in the x-axis, the cell region 110a is adjacent to the cell region 110c along the x-axis, and the dummy portion 110c2 includes a width W3c in the x-axis, the cell region 110a is adjacent to the cell region 110c along the x-axis. The width of a dummy portion in a direction in which the dummy region or its cell region is adjacent to a neighboring cell region (e.g., W3a, W3c) is in a range from about 5 um to about 20 um. In some embodiments, adjacent dummy portions (e.g., 110a2 and 110c2) have substantially the same width. In some embodiments, adjacent dummy portions (e.g., 110a2 and 110c2) have different widths. In some embodiments, if a cell region 110 includes multiple dummy portions, the dummy portions in the same cell region 110 include the same width in the respective direction each of which is adjacent to a neighboring cell region. In some embodiments, the dummy portions in the same cell region 110 can have different widths.

[0027] Two adjacent dummy portions (e.g., 110a2, 110c2) together serve to connect the active devices in the corresponding device portions 110a1, 110c1. The two dummy portions 110a2, 110c2 abut each other and thus form a stitched region 110ac that includes a metal feature 220 extending from the cell region 110a to the cell region 110c. The metal feature 220 includes a metal feature 220a in the dummy portion 110a2 and a metal feature 220c in the dummy portion 110c2. The metal features 220a, 220c are stitched or connected together at a boundary line 222ac between the cell region 110a and the cell region 110c.

[0028] In some embodiments, the stitching region is a strip, which can have a uniform width. In some embodiments, the strip-sized stitching region extends from a first side of a cell region (e.g., 110a) to a second side of the cell region along a direction (e.g., y-axis direction) that is transverse to the direction (e.g., x-axis direction), corresponding two cell regions (e.g., 110a, 110c) are arranged relative to each other along the direction.

[0029] In some embodiments, the adjacent cell regions 110a, 110c can have substantially the same size, but in some embodiments, their sizes or shapes can be different from each other.

[0030] Regions 110b and 110d have a stitching region 110bd. The metal components extending from region 110b to region 110d are stitched together in region 110bd. In an embodiment, the stitching region 110bd is a strip, which can have a uniform width. In addition, regions 110b and 110d can have substantially the same size or shape; but in other embodiments, their sizes and shapes can be different from each other.

[0031] Semiconductor package structure 201 can include one or more combined semiconductor dies, each including a plurality of cell regions and stitching regions between adjacent cell regions. Semiconductor package structure 201 can also include one or more unit semiconductor dies, each similar to a cell region in a combined semiconductor die with or without dummy portions. The combined semiconductor dies and / or the unit semiconductor dies can be positioned on an interposer 230 or a package substrate. The semiconductor dies are electrically coupled to the interposer 230 through coupling components such as solder bumps 232. The interposer 230 can include a redistribution RDL layer 234 adjacent to the coupling components 232. For example, the RDL layer 234 of the interposer 230 can include 3-5 layers each having a pitch of about 720 nm. Details of the package structure 201 will be further provided herein.

[0032] Figure 3 Details of exemplary dummy portions 110a2, 110c2 are shown in cross-section. As shown in Figure 3 Devices 210a, 210c, e.g., GPU devices, are formed on a substrate 200. An interlayer dielectric (ILD) is formed over the semiconductor substrate 200.

[0033] Pseudo portions 110a2, 110c2 are formed as part of a back end of line (BEOL) metallization structure above devices 210a, 210c, respectively. The BEOL structure includes a lower metallization level 310 and a redistribution level 312 above lower metallization level 310. The BEOL structure shown as lower metallization level 310 and redistribution level 312 can include interlayer dielectric (ILD) and one or more intermetal dielectric (IMD) layers (not specifically shown for brevity), individual metal components (e.g., wires, interconnect components, metal patterns) of conductive components 220 (220a, 220c) including pseudo portions 110a2, 110c2, and one or more passivation layers. In some embodiments, the ILD can be formed of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN or Si3N4), silicon carbide (SiC), etc., and can be deposited by any suitable deposition process. Herein, a “suitable deposition process” can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high-density plasma CVD (HDPCVD) process, a low-pressure CVD process, a metal organic CVD (MOCVD) process, a plasma-enhanced CVD (PECVD) process, a sputtering process, laser ablation, etc.

[0034] The IMD layer can include an ultra-low-k (ELK) dielectric material having a dielectric constant (k) less than about 2.6, such as from 2.5 to 2.2. In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous carbon fluoride, poly-p-xylylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE) (Teflon), or a silicon oxide carbon polymer (SiOC). In some embodiments, the ELK dielectric material can include a porous version of an existing dielectric material, such as porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous silk, or porous SiO2. The IMD layer can be formed by any suitable deposition process. In some embodiments, the IMD layer can be deposited by a PECVD process or by a spin-on process.

[0035] The metal components can include wires, lines, and via structures. The metal components can be formed of any suitable electrically conductive material, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, silver, gold, combinations thereof, etc. Other suitable electrically conductive materials (e.g., conductive nitride compounds) are also possible and within the scope of embodiments of the present disclosure.

[0036] In some implementations, the conductive features 220 (220a, 220c) are formed as part of an RDL level 312 above the lower metallization level 310. The RDL level 310 can include 2-4 layers of metal traces and have a pitch of, for example, 720 nm. Other configurations or pitches of the RDL level 312 are possible and included in embodiments of the present disclosure. Each of the conductive features 220 can include the same conductive material of the respective metallization level, for example, copper, aluminum, silver, or gold. For example, the conductive features 220 can be greater than 80% copper by atomic percentage, such as greater than 90% or greater than 95%, although greater or lesser percentages can be used.

[0037] In some embodiments, the conductive features 220 can be formed by a dual damascene process or by multiple single damascene processes. A single damascene process typically forms and fills a single feature with a metal material (e.g., copper) at each damascene stage. A dual damascene process typically forms and fills two features with copper at once, for example, a trench and an overlapping via can be filled with a single copper deposition using a dual damascene process. In some embodiments, the conductive features 220 can be formed by an electroplating process.

[0038] For example, a damascene process can include patterning a dielectric layer (e.g., an IMD layer) to form openings, such as trenches and / or vias, for example, through-via holes. A deposition process can be implemented to deposit a conductive metal, for example, copper, in the openings. Then, a planarization process, such as chemical mechanical planarization (CMP), can be implemented to remove excess metal, for example, copper.

[0039] For example, the patterning, metal deposition, and planarization processes can be implemented on each of the dielectric layers (e.g., IMD layers) in order to form the conductive features 220.

[0040] In some embodiments, a barrier layer (not shown) can be disposed between the dielectric layers and the conductive features 220 to prevent unwanted metal diffusion. For example, the barrier layer can include Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other suitable barrier layer materials are also within the contemplation of embodiments of the present disclosure.

[0041] Figures 4A to 4J Representative semiconductor structures at different stages of a manufacturing process to form a semiconductor package structure including a combined semiconductor die are shown. Figure 5 An example manufacturing process is shown. In Figures 4A to 4J In the example shown in FIG. 1 1 1, the example combined semiconductor die includes two cell regions adjacent to each other for illustrative purposes. It should be understood that similar manufacturing processes can be used to manufacture a combined semiconductor die having more than two cell regions. Reference is made to Figure 5 Reference is also made to Figure 4AIn processing operation 510, devices 420a and alignment marks 422a are formed on first cell region 410a on wafer 200. Figure 4A Wafer 200 is shown from a top view and combined semiconductor dies 410 on wafer 200 are shown from a cross-sectional view. For example, forming first devices 420a includes a first exposure procedure through first photomask 412a. First photomask 412a is placed so as to expose (e.g., directly above) only the portion of photoresist on wafer 400 on first cell region 410a that includes the associated dummy portion 410a2. First photomask 412a (limited by the maximum size of the middle mask field therein) does not cover first cell region 410a and adjacent second cell region 410b. Rather, first photomask 412a is used to expose only the portion of photoresist on first cell region 410a that includes the associated dummy portion. First exposure is implemented to expose the portion of photoresist through mask openings 414a, with the remaining portion of photoresist not exposed.

[0042] In some embodiments, alignment marks 422a are formed in dummy portion 410a2 of cell region 410a.

[0043] In operation 520, also with reference to Figure 4B Devices 420b and alignment marks 422b are formed on second cell region 410b on wafer 400. Operation 520 includes a second exposure through second photomask 412b. Second photomask 412b is placed so as to expose (e.g., directly above) second cell region 410b that includes the associated dummy portion 410b2. Second photomask 412b is used to expose the portion of photoresist on second cell region 410b that includes the associated dummy portion 410b2, but not first cell region 410a. Second photomask 412b is placed so that the exposed photoresist portions in second cell region 410b abut those of first cell region 410a. In particular, dummy portion 410b2 is exposed to directly contact or abut corresponding dummy portion 410a2. Then, second exposure in operation 520 is implemented to expose the portion of photoresist on second cell region 410b through mask openings 414b on second photomask 412b. In Figure 4B In FIG. 5, opening 414a of first mask 412a is shown for illustrative purposes only to show the relative position of opening 414a of first mask 412a relative to opening 414b of second mask 412b. It should be understood that second mask 412b does not include opening 414a.

[0044] In some embodiments, alignment marks 422b are formed in dummy portion 410b2 of cell region 410b. Alignment marks 422a, 422b are used to facilitate alignment of the conductive features formed on dummy portions 410a2, 410b2 with each other, such that the conductive features in dummy portions 410a2, 410b2 are connected or stitched together. In some embodiments, alignment marks 422a can be aligned with corresponding alignment marks 422b. In some embodiments, alignment marks 422a can be offset from corresponding alignment marks 422b in a predetermined manner.

[0045] It should be noted that the formation of each of device 420a or device 420b can involve multiple photoresists and exposures using multiple masks. The description regarding masks 412a, 412b and related exposures can apply to each of the photoresists and exposures used in the formation of device 420a, 420b.

[0046] In operation 530, also referring to Figure 4C A metallization level 430a is formed on cell region 410a. Metallization level 430a includes conductive features 432a in dummy portion 410a2. In some embodiments, metallization level 430a including conductive features 432a is formed as or at a redistribution level RDL of a combined semiconductor die to be formed. For example, metallization level 430a including conductive features 432a is formed adjacent to a surface of a combined semiconductor die to be formed, which is configured to be coupled to an interposer 230 (or a carrier substrate) through coupling features such as solder bumps 232. For example, metallization level 430a is on top of BEOL metallization levels and interconnect structures therebetween. Metallization level 430a is also on top of metal pads, if any.

[0047] Metallization level 430a as a RDL layer can be formed using a polymer process or a metal damascene process. For example, in a polymer process, the passivation layer can be an organic material.

[0048] In operation 540, also referring to Figure 4DA metallization level 430b is formed over the cell region 410b. The metallization level 430b includes conductive features 432b in the dummy portion 410b2. The conductive features 432b are each in direct physical contact with a corresponding conductive feature 432a, thereby causing the dummy portions 410a2 and 410b2 to be connected or stitched together and become the stitched region 410ab. The alignment marks 422a, 422b are used to facilitate the conductive features 432b each being aligned with and in direct physical contact with a corresponding conductive feature 432a, and the features 432a each being aligned with and in direct physical contact with a corresponding conductive feature 432b.

[0049] As shown in FIG. 4B, the formation of the metallization level 430a, 430b also uses a separate mask 442a, 442b, respectively, similar to the formation of the devices 420a, 420b. Figure 4E Figure 4E It should be understood that each of the metallization levels can require multiple masks and exposures to form the features thereon. The description of the masks 442a, 442b applies to each of such masks and exposures, which are included within the scope of the embodiments of the present disclosure.

[0050] It should be understood that each of the metallization levels can require multiple masks and exposures to form the features thereon. The description of the masks 442a, 442b applies to each of such masks and exposures, which are included within the scope of the embodiments of the present disclosure.

[0051] It should also be understood that while the description herein provides examples of masks (e.g., 442a, 442b) for the cell regions 410a, 410b corresponding to exposures in the respective cell regions 410a, 410b that are contiguous and in contact with each other, such examples do not limit the scope of the embodiments of the present disclosure. In some alternative or additional implementations, the separate masks 442a, 442b can each overlap and pattern photoresist on the corresponding cell region 410a, 410b and on contiguous portions of the adjacent cell region 410b, 410a, respectively. For example, the mask 442a can overlap and pattern photoresist on the dummy portion 410b2 of the cell region 410b adjacent to the cell region 410a and the mask 442b can overlap and pattern photoresist on the dummy portion 410a2 of the cell region 410a adjacent to the cell region 410b. That is, the photoresist on the stitched region 410ab can undergo a double exposure through the mask 442a and the mask 442b in sequence. ​

[0052] In some alternative or additional embodiments, the photoresist on the stitching region 410ab can be exposed using one of the masks 442a or 442b. For example, the mask 442a can have openings to expose portions of the photoresist on the cell region 410a and on the stitching region 410ab, which includes the dummy portion 410a2 of the cell region 410a and the dummy portion 410b2 of the cell region 410b. The mask 442b can overlap and expose only portions of the photoresist on the device portion 410b1 of the cell region 410b.

[0053] In operation 550, also with reference to Figure 4F , the combined semiconductor die 401 is singulated from the wafer 400. For example, the die 401 is singulated along the scribe lines A and B Figure 4D , among others. The scribe lines A and B each follow an edge of the cell region that is different from those of the dummy portions. The combined semiconductor die 401 includes the device regions 410a1, 410b1 and the stitching region 410ab between the device regions, all as part of a single die. The stitching region 410ab includes the dummy portion 410a2 of the cell region 410a and the dummy portion 410b2 of the cell region 410b.

[0054] In operation 560, also with reference to Figure 4G , the combined semiconductor die 401 is coupled to the interposer 230. As shown in Figure 4G , the combined semiconductor die 401 is mounted on the interposer 230. The interposer 230 can include a suitable material, such as a semiconductor material (e.g., a silicon substrate), a ceramic material, an organic material (e.g., a polymer and / or a thermoplastic material), a glass material, combinations thereof, and the like. Other suitable substrate materials are within the contemplation of embodiments of the present disclosure. In various embodiments, the interposer 230 can include a redistribution structure or layer 234. The redistribution layer 234 can be electrically coupled to one or more of the coupling components 232 between the combined semiconductor die 401 and the interposer 230.

[0055] The interposer 230 can be an organic interposer or can be a silicon interposer, both of which are included within the scope of embodiments of the present disclosure.

[0056] The combined semiconductor die 401 can be electrically coupled to the interposer 230 via a plurality of coupling components (e.g., solder bumps 232) that connect respective bonding pads or micro-bumps (not specifically shown) of the combined semiconductor die 401 and the interposer 230. The redistribution interconnect structure 234 can be configured to be electrically coupled to the combined semiconductor die 401 to allow signal propagation between the combined semiconductor die 401 and the interposer 230 and / or other dies or substrates coupled to the interposer 230.

[0057] In view of the fact that the combined semiconductor die 401 includes a stitched region 401ab having conductive components 432 (432a, 432b) connected to each other, the devices in the cell region 410a and the devices in the cell region 410b can be connected to each other using the conductive components 432 for signal propagation between them. Thus, the devices in the combined semiconductor die 401 can not rely on interconnects through the RDL layer 234 of the interposer 230 for signal propagation between them.

[0058] Referring to Figure 4H , a plurality of combined semiconductor dies 401 (401-1, 401-2, and 401-3 are shown) can be mounted on the interposer 230. According to various embodiments, the semiconductor device or package 450 can include a plurality of integrated circuit (IC) semiconductor dies including the plurality of combined semiconductor dies 401 and / or other semiconductor dies (not specifically shown for brevity) on the interposer 230. In various implementations, each of the combined dies or other semiconductor dies can be configured as a three-dimensional device such as a three-dimensional integrated circuit (3DIC), a system-on-chip (SOC) device, or a system-on- integrated circuit (SoIC) device. The other semiconductor dies can be integrated circuit IC device dies or integrated passive device dies IPD or other components.

[0059] Referring to Figure 4I In some implementations, the two combined semiconductor dies 401-1 and 401-2 can be positioned adjacent to each other on the interposer 230. Due to physical limitations in the processing dies, there is a distance W2 between the two combined semiconductor dies 401-1 and 401-2. In some implementations, the distance W2 is in the range of 40um to 300um. The redistribution structure 236 can include portions 236 configured to electrically couple the combined semiconductor dies 401-1 and 401-2 to each other and configured to allow signal propagation between the devices in the combined semiconductor dies 401-1 and 401-2. The devices within each of the combined semiconductor dies 401-1, 401-2 can be connected through the respective stitched regions 401-1ab, 401-2ab, respectively.

[0060] In operation 570, also referring to Figure 4J The interposer 230 having the combined semiconductor dies 401-1, 401-2 coupled thereon is coupled to the package substrate 460. As shown in Figure 4J The interposer 230 can be coupled to the package substrate 460 through coupling components such as solder bumps 462. The package substrate 460 can also be electrically coupled to a printed circuit board (PCB) (not shown) via coupling components (e.g., solder balls 464) that connect respective bump structures of the package substrate 460 and the PCB.

[0061] Figure 6 Embodiments are shown in which, in each combined die 610-1, 610-2, the cell regions 610-1a, 610-1b, 610-2a, 610-2b are arranged relative to adjacent cell regions along the y-axis direction, and the two combined dies 610-1, 610-2 are arranged relative to each other in the x-axis direction, which is different from the y-axis direction.

[0062] Figure 7 Embodiments are shown in which the cell regions 710a, 710b can include a size that is not a full intermediate mask size limit. For example, the cell regions 710a, 710b can be formed using masks that overlap each other in the y-axis direction, such that each cell region 710a, 710b includes a dimension of a full intermediate mask size, e.g., 33 mm, in the x-axis direction, and a dimension of 0.75 times a full intermediate mask size, e.g., 0.75 x 26 mm = 19.5 mm, in the y-axis direction.

[0063] Figure 8 Embodiments are shown in which, in each combined die 710-1, 710-2, the cell regions 710-1a, 710-1b, 710-2a, 710-2b are arranged relative to adjacent cell regions along the y-axis direction, and the two combined dies 710-1, 710-2 are also arranged relative to each other in the y-axis direction.

[0064] Described embodiments of the subject matter can include one or more of the following taken alone or in combination. For example, in a first embodiment, a method of manufacturing a semiconductor device includes forming a first cell region over a semiconductor substrate using a first mask, the first cell region including a first device portion and a first dummy portion, the first dummy portion including a first alignment mark; forming a second cell region over the semiconductor substrate using a second mask different from the first mask, the second cell region including a second device portion and a second dummy portion, the second dummy portion being adjacent to the first dummy portion, the second dummy portion including a second alignment mark corresponding to the first alignment mark; and forming a single first die including the first cell region and the second cell region together.

[0065] In a second embodiment, a method of manufacturing a semiconductor device includes forming a first cell region over a semiconductor substrate using a first mask, the first cell region including a first device portion and a first dummy portion, the first cell region including a size of an intermediate mask size limit; forming a second cell region over the semiconductor substrate using a second mask, the second cell region including a second device portion and a second dummy portion, the second dummy portion being in physical contact with the first dummy portion, the second cell region including a size of the intermediate mask size limit; and forming a single first die including the first cell region and the second cell region together.

[0066] In a third embodiment, a structure includes: a combined semiconductor die including a first unit area and a second unit area over a semiconductor substrate, the first unit area abutting the second unit area, the first unit area including a first device portion and a first dummy portion, the second unit area including a second device portion and a second dummy portion, the first dummy portion including a first conductive feature, the second dummy portion including a second conductive feature connected with the first conductive feature; an interposer; and a solder bump coupled between the combined semiconductor die and the interposer.

[0067] Some embodiments of the application provide a method of manufacturing a semiconductor device, including: forming a first unit area over a semiconductor substrate using a first mask, the first unit area including a first device portion and a first dummy portion, the first dummy portion including a first alignment mark; forming a second unit area over the semiconductor substrate using a second mask different from the first mask, the second unit area including a second device portion and a second dummy portion, the second dummy portion adjacent to the first dummy portion, the second dummy portion including a second alignment mark corresponding to the first alignment mark; and forming a single first die including the first unit area and the second unit area together.

[0068] In some embodiments, the first dummy portion is contiguous to the second dummy portion. In some embodiments, the first dummy portion includes a first conductive feature in a redistribution metallization level, the second dummy portion includes a second conductive feature in the redistribution metallization level, and the second conductive feature is in contact with the first conductive feature. In some embodiments, the method further includes coupling the first die to an interposer, wherein the first conductive feature and the second conductive feature are each closer to the interposer than the semiconductor substrate. In some embodiments, the first die is coupled to the interposer by a coupling feature positioned between the first die and the interposer, and wherein the interposer includes a redistribution structure electrically coupled to the coupling feature. In some embodiments, the method includes coupling a second die to the interposer, the second die being separated from the first die by a distance, wherein the first die is connected to the second die by a first portion of the redistribution structure of the interposer. In some embodiments, the first conductive feature is formed in a redistribution layer in the first cell region. In some embodiments, the first mask is used to expose a first photoresist portion on the first cell region, and the second mask is used to expose a second photoresist portion on the second cell region. In some embodiments, the first cell region and the second cell region each have a size of about 33 mm x 26 mm. In some embodiments, the first die has a size of about 33 mm x 52 mm. In some embodiments, the first die has a size of about 66 mm x 26 mm. In some embodiments, the first dummy portion has a dimension in a direction between the first cell region and the second cell region in a range from about 5 um to about 20 um, inclusive.

[0069] Some embodiments of the application provide a method of manufacturing a semiconductor device, comprising: forming a first unit area over a semiconductor substrate using a first mask, the first unit area comprising a first device portion and a first dummy portion, the first unit area comprising an intermediate mask size limit size; forming a second unit area over the semiconductor substrate using a second mask, the second unit area comprising a second device portion and a second dummy portion, the second dummy portion in physical contact with the first dummy portion, the second unit area comprising the intermediate mask size limit size; and forming a single first die comprising the first unit area and the second unit area together. In some embodiments, the first unit area comprises a first side of 26 mm and a second side of 33 mm, the second unit area comprises a first side of 26 mm and a second side of 33 mm, and the first side of the first unit area is in physical contact with the first side of the second unit area. In some embodiments, the first unit area comprises a first side of 26 mm and a second side of 33 mm, the second unit area comprises a first side of 26 mm and a second side of 33 mm, and the second side of the first unit area is in physical contact with the second side of the second unit area. In some embodiments, the first dummy portion comprises a first conductive component, the second dummy portion comprises a second conductive component, and the second conductive component is in physical contact with the first conductive component. In some embodiments, the first dummy portion comprises a first alignment component, the second dummy portion comprises a second alignment component, and the second alignment component corresponds to the first alignment component.

[0070] Some embodiments of the application provide a semiconductor structure, comprising: a combined semiconductor die comprising a first unit area and a second unit area over a semiconductor substrate, the first unit area adjoining the second unit area, the first unit area comprising a first device portion and a first dummy portion, the second unit area comprising a second device portion and a second dummy portion, the first dummy portion comprising a first conductive component, the second dummy portion comprising a second conductive component connected with the first conductive component; an interposer; and a solder bump coupled between the combined semiconductor die and the interposer.

[0071] In some embodiments, the first device portion comprises a first graphics processing unit, and the second device portion comprises a second graphics processing unit. In some embodiments, the first unit area and the second unit area each comprise an intermediate mask size limit size.

[0072] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first cell region is formed over a semiconductor substrate using a first mask. The first cell region includes a first device portion and a first pseudo portion. The first pseudo portion includes a first alignment mark. A second cell region is formed over the semiconductor substrate using a second mask that is different from the first mask. The second cell region includes a second device portion and a second pseudo portion. The second pseudo portion is adjacent to the first pseudo portion and includes a second alignment mark corresponding to the first alignment mark. as well as A single first die is formed, comprising the first unit region and the second unit region together.

2. The method according to claim 1, wherein, The first pseudo-part is adjacent to the second pseudo-part.

3. The method according to claim 1, wherein, The first pseudo-part includes a first conductive component in the redistributed metallization layer, the second pseudo-part includes a second conductive component in the redistributed metallization layer, and the second conductive component is in contact with the first conductive component.

4. The method of claim 3, further comprising coupling the first die to an interposer, wherein, The first conductive component and the second conductive component are each closer to the interposer layer than the semiconductor substrate.

5. The method according to claim 4, wherein, The first die is coupled to the interposer layer via a coupling component positioned between the first die and the interposer layer, and The intermediate layer includes a redistribution structure electrically coupled to the coupling component.

6. The method of claim 5, further comprising coupling a second die to the interposer layer, wherein the second die is spaced apart from the first die by a distance. in, The first die is connected to the second die through a first portion of the redistribution structure of the intermediate layer.

7. The method according to claim 3, wherein, The first conductive component is formed in the redistribution layer in the first unit region.

8. The method according to claim 1, wherein, The first mask is used to expose a first photoresist portion on the first cell region, and the second mask is used to expose a second photoresist portion on the second cell region.

9. A method for manufacturing a semiconductor device, comprising: A first cell region is formed over a semiconductor substrate using a first mask. The first cell region includes a first device portion and a first pseudo portion. The size of the first cell region is limited by an intermediate mask size. A second unit region is formed over the semiconductor substrate using a second mask. The second unit region includes a second device portion and a second pseudo portion. The second pseudo portion is in physical contact with the first pseudo portion. The size of the second unit region is limited by the size of the intermediate mask. as well as A single first die is formed, comprising the first unit region and the second unit region together.

10. A semiconductor structure comprising: A combined semiconductor die includes a first unit region and a second unit region above a semiconductor substrate. The first unit region is adjacent to the second unit region. The first unit region includes a first device portion and a first pseudo portion. The second unit region includes a second device portion and a second pseudo portion. The first pseudo portion includes a first conductive component. The second pseudo portion includes a second conductive component connected to the first conductive component. Intermediate layer; as well as Solder bumps are coupled between the combined semiconductor die and the interposer.

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