A GaN HEMT / MOSFET monolithic integrated cascade device and its fabrication method

Abstract

The application discloses a GaN HEMT / MOSFET monolithic integrated cascade device and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a GaN HEMT device and a GaN MOSFET device which are electrically connected through a metal interconnection structure; the GaN MOSFET device is prepared above a vertical structure of the GaN HEMT device, and a projection position of the GaN MOSFET device is located between a gate and a drain of the GaN HEMT device; isolation grooves are arranged between different GaN HEMT / MOSFET cascade devices distributed along a transverse direction of a substrate, and electrical isolation between different cascade devices is realized through the isolation grooves. The application reduces interface defects through one-time epitaxial growth, reduces a chip area through vertical integration, improves a device voltage resistance and high-frequency performance, and is suitable for the field of high-efficiency power conversion.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically, it relates to a GaN HEMT / MOSFET monolithic integrated cascade device and its fabrication method. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs), as core devices of third-generation semiconductors, have demonstrated revolutionary potential in high-efficiency power conversion and high-frequency applications due to their wide bandgap, high electron saturation velocity, and excellent voltage withstand capability. Compared with traditional silicon-based devices, GaN HEMTs have significant advantages such as low on-resistance, fast switching speed, and good high-temperature stability, which can significantly improve energy conversion efficiency and reduce system size. However, the inherent normally-on characteristic (depletion-mode) of traditional GaN HEMTs poses a significant safety hazard, leading to a direct short circuit in the system when the gate is runaway. To address this, the industry has explored various normally-off technologies. While p-GaN gate and grooved gate solutions can achieve normally-off operation, they face challenges such as low threshold voltage and poor reliability. Therefore, cascaded devices compatible with CMOS processes have emerged. Currently, most methods integrate discrete MOSFETs with GaN HEMT packages and achieve normally-off functionality through interconnection via circuit metal leads. Although this offers the advantage of simple driving, the parasitic inductance and resistance introduced by the interconnections severely restrict the high-frequency performance of the devices, limiting further increases in power density.

[0003] Against this technological backdrop, monolithic integration technology based on GaN materials has become an important development direction. This approach integrates enhancement-mode Si-based MOSFETs and depletion-mode GaN HEMTs on the same substrate, using metal interconnect methods to achieve cascaded enhancement-mode GaN HEMT devices. This retains the intrinsic performance advantages of GaN materials, achieves safe normally-off operation, and completely eliminates the influence of packaging parasitic parameters, laying a solid foundation for building next-generation high-performance, high-reliability power integrated circuits. GaN MOSFETs have received extensive research in recent years due to their smaller geometric size and higher power density compared to Si-based MOSFETs. However, the cascading methods used are generally lateral expansion monolithic heterogeneous integration, which not only limits chip area by Moore's Law, preventing further reduction in device size, but also causes the accumulation of interface defects. Therefore, vertical monolithic integration structures have practical value for the application of GaN devices. Summary of the Invention

[0004] The purpose of this invention is to provide a GaN HEMT / MOSFET monolithic integrated cascaded device and its fabrication method, mainly to solve the problems of high integration interface defect density, low breakdown voltage, and large dynamic on-resistance under high frequency operation in existing monolithic heterogeneous integration.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A GaN HEMT / MOSFET monolithic integrated cascaded device includes a GaN HEMT device and a GaN MOSFET device electrically connected via a metal interconnect structure on the same wafer. The GaN MOSFET device is fabricated above the vertical structure of the GaN HEMT device, with its projected position located between the gate and drain of the GaN HEMT device. A high-resistivity GaN layer serves as an electrical insulating layer between the epitaxial structures of the GaN HEMT device and the GaN MOSFET device. An isolation trench is provided between the GaN HEMT / MOSFET monolithic integrated cascaded devices distributed along the lateral direction of the substrate to achieve electrical isolation between the devices. The isolation trench extends into a buffer layer of the GaN HEMT device. The wafer region with the isolation trench is a passive region, and the wafer region outside the passive region is an active region. The GaN HEMT / MOSFET monolithic integrated cascaded device is fabricated in the active region.

[0007] Furthermore, in this invention, the GaN HEMT device includes a substrate and an epitaxial structure of the GaN HEMT device consisting of a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a capping layer sequentially disposed on the substrate from bottom to top. A dense dielectric layer is disposed above the capping layer. The source and drain of the GaN HEMT device are disposed in a groove formed by etching the dense dielectric layer to the capping layer. The gate of the GaN HEMT device is disposed in a portion of the area above the capping layer. In this case, a two-dimensional electron gas layer is formed near the upper surface of the channel layer at the interface between the channel layer and the barrier layer due to the polarization effect.

[0008] Furthermore, in this invention, a second buffer layer is provided above the capping layer, and a GaN MOSFET device is disposed above the second buffer layer. The GaN MOSFET device includes a high-resistivity GaN layer and a P-GaN body region disposed sequentially above the second buffer layer; two in-situ heavily doped N+ well regions grown epitaxially in the etched area by selectively etching a portion of the P-GaN body region; a dense dielectric layer disposed above the P-GaN body region and the N+ well region; a source and a drain of the GaN MOSFET device respectively disposed in the groove formed by etching the dense dielectric layer to the top of the N+ well region; and a gate of the GaN MOSFET device disposed above the dense dielectric layer between the N+ well regions.

[0009] Furthermore, in this invention, after the electrode portions of the GaN HEMT device and GaN MOSFET device are fabricated, they are covered with a passivation layer. Electrode openings are formed by etching the passivation layer above the electrode portions. Metal interconnect structures are fabricated in the electrode openings and interconnected to form metal interconnects. Specifically, the source of the GaN HEMT device is connected to the drain of the GaN MOSFET device, and a connecting metal line is led out to connect to an external ground electrode to form a first interconnect metal. The gate of the GaN HEMT device is connected to the source of the GaN MOSFET device to form a second interconnect metal. A connecting metal line is led out from the gate of the GaN MOSFET device to connect to an external gate driving circuit to form a third interconnect metal. A connecting metal line is led out from the drain of the GaN HEMT device to connect to the output terminal of an external circuit to form a fourth interconnect metal.

[0010] Furthermore, in this invention, the nucleation layer of the GaN HEMT device is made of AlN material with a thickness ranging from 20 to 100 nm; the buffer layer is intentionally doped high-resistivity GaN material with a thickness ranging from 300 to 1000 nm; the channel layer is unintentionally doped intrinsic GaN material with a thickness ranging from 100 to 300 nm; and the barrier layer is made of Al with gradually decreasing Al content. x Ga (1-x) The material is N, where 0.25≤x≤0.75 and the thickness ranges from 15 to 30 nm; the capping layer is AlN material with a thickness range of 2 to 10 nm.

[0011] Furthermore, in this invention, the second buffer layer is a deliberately doped high-resistivity GaN material with a thickness ranging from 100 to 1000 nm; the high-resistivity GaN layer is a deliberately doped high-resistivity GaN material with a thickness ranging from 1000 to 3000 nm; the P-GaN bulk region is a doped P-type material with a thickness ranging from 300 to 600 nm; the N+ well region is an in-situ heavily doped N-type ion and epitaxially grown N-type GaN material with a thickness ranging from 100 to 300 nm; wherein, the high-resistivity GaN layer and the P-GaN bulk region together constitute the epitaxial layer structure of the GaNMOSFET device.

[0012] Furthermore, in this invention, the dense dielectric layer is made of Al2O3 or SiO2 material, with a thickness ranging from 15 to 50 nm.

[0013] Furthermore, in this invention, the source, drain, drain, and source of the GaN HEMT device are one or more metal stacked structures selected from Ti / TiN / Al / W, with a thickness ranging from 100 to 200 nm; the gate of the GaN HEMT device is one or more metal stacked structures selected from Ti / W, with a thickness ranging from 100 to 200 nm; the gate of the GaN MOSFET device is made of polycrystalline silicon, with a thickness ranging from 100 to 200 nm; and the first, second, third, and fourth interconnect metals are made of Al or Cu metal materials.

[0014] This invention also provides a method for fabricating a GaN HEMT / MOSFET monolithic integrated cascade device, comprising the following steps:

[0015] A substrate is provided, on which a core layer, a first buffer layer, a channel layer, a barrier layer, a capping layer, a second buffer layer, a high-resistivity GaN layer, and a P-GaN bulk region are sequentially grown to complete the epitaxial layer growth of a monolithic integrated cascaded device.

[0016] After selectively etching the P-GaN body region of the GaN MOSFET device, N-type ions are in-situ heavily doped and then an N-type ion heavily doped GaN epitaxial layer is grown until its surface is flush with the surface of the P-GaN body region to obtain an N+ well region.

[0017] The epitaxial layer structure of the GaN MOSFET device is etched down to the capping layer, and a dense dielectric layer is deposited on the epitaxial layer away from the substrate surface.

[0018] The dense dielectric layer in the source and drain regions of GaN HEMT devices and GaN MOSFET devices is etched by selective etching process to expose the capping layer in the source and drain regions of GaN HEMT devices and the N+ well region in the source and drain regions of GaN MOSFET devices.

[0019] By selectively etching a region that has been partially etched to the dense dielectric layer, the region is selectively etched again to the buffer layer. The etched region is the passive region, and the unetched region is the active region. The GaN HEMT / MOSFET monolithic integrated cascade device is fabricated in the active region. The two active regions are separated by the passive region, thereby forming electrical isolation between the devices.

[0020] Source metal and drain metal are deposited in the source and drain trenches of the GaN HEMT device and GaN MOSFET device, respectively, and the source and drain of the GaN HEMT device and the GaN MOSFET device are obtained by low-temperature rapid annealing.

[0021] A gate metal for the GaN HEMT device is fabricated above a dense dielectric layer between the source and drain electrodes, and a Schottky contact is formed between the gate of the GaN HEMT device and the underlying dense dielectric layer.

[0022] A GaN MOSFET device gate is fabricated on top of a dense dielectric layer between the two N+ well regions of the GaN MOSFET device. The gate material is polycrystalline silicon, and a Schottky contact is formed with the underlying dense dielectric layer.

[0023] A passivation layer is deposited over the active and passive regions, and the surface of the passivation layer is planarized by chemical mechanical polishing.

[0024] The passivation layer above the source, drain, and gate of GaN HEMT and GaN MOSFET devices is etched to form electrode openings. Metal is deposited in the openings to obtain a metal interconnect structure, thus completing the device fabrication.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) This invention achieves a vertically stacked epitaxial layer structure for GaN HEMT and GaN MOSFET devices through a single epitaxial growth process, and sets a high-resistivity GaN layer as an insulating layer between the epitaxial layers of the two devices. This not only forms good electrical isolation between the devices, but also avoids interface defects introduced by heterogeneous integration and secondary epitaxy. At the same time, the AlN capping layer not only improves the deposition quality of the epitaxial layer of the GaN MOSFET device, but also blocks the downward diffusion of ions during heavy ion doping of the epitaxial layer of the GaN MOSFET device, ensuring that the integrity of the two-dimensional electron gas (2DEG) at the interface between the channel layer and the barrier layer is not affected.

[0027] (2) This invention vertically integrates the GaN MOSFET device above the GaN HEMT device, with its projected position located between the gate and drain of the lower GaN HEMT device. This fully utilizes the vertical space of the wafer, reducing the chip area. At the same time, the path of the metal interconnect structure (such as the first interconnect metal connecting the HEMT source and the MOSFET drain) is shortened, effectively reducing parasitic inductance and significantly reducing switching losses at high frequencies, making it particularly suitable for high-frequency power conversion scenarios.

[0028] (3) This invention improves device reliability through a dual withstand voltage mechanism:

[0029] Vertical direction: HEMT buffer layer one and MOSFET buffer layer two share the voltage, and the high-resistivity GaN layer acts as an insulating layer to block longitudinal leakage.

[0030] Lateral direction: Isolation trenches extending deep into the buffer layer are set between adjacent GaN HEMT / MOSFET monolithically integrated cascaded devices to form passive region isolation and avoid lateral crosstalk. In addition, the MOSFET metal electrode can act as a "floating field plate" between the gate and drain of the HEMT device, optimizing the electric field distribution between the gate and drain, thereby improving the device breakdown voltage and meeting the requirements of high voltage applications. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a GaN HEMT / MOSFET monolithic integrated cascaded device provided in Embodiment 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the epitaxial layer fabrication of a GaN HEMT / MOSFET monolithic integrated cascade device provided in Embodiment 1 of the present invention;

[0033] Figure 3 This is a schematic diagram of the N+ well region fabrication of a GaN HEMT / MOSFET monolithic integrated cascaded device provided in Embodiment 1 of the present invention;

[0034] Figure 4This is a schematic diagram of epitaxial layer etching for a GaN HEMT / MOSFET monolithic integrated cascade device provided in Embodiment 1 of the present invention;

[0035] Figure 5 This is a schematic diagram of device isolation and ohmic groove etching for a GaN HEMT / MOSFET monolithic integrated cascaded device provided in Embodiment 1 of the present invention;

[0036] Figure 6 This is a schematic diagram of electrode fabrication for a GaN HEMT / MOSFET monolithic integrated cascade device provided in Embodiment 1 of the present invention;

[0037] Figure 7 This is a schematic diagram of the interconnect metal layer fabrication of a GaN HEMT / MOSFET monolithic integrated cascade device provided in Embodiment 1 of the present invention;

[0038] Figure 8 This is a circuit diagram of a GaN HEMT / MOSFET monolithic integrated cascaded device provided in Embodiment 1 of the present invention;

[0039] Figure 9 This is a top view schematic diagram of the main structure of a GaN HEMT / MOSFET monolithic integrated cascaded device provided in Embodiment 1 of the present invention;

[0040] Figure 10 This is a three-dimensional structural schematic diagram of a GaN HEMT / MOSFET monolithic integrated cascaded device provided in Embodiment 1 of the present invention;

[0041] Figure 11 This is a schematic diagram of another GaN HEMT / MOSFET monolithic integrated cascade device provided in Embodiment 2 of the present invention.

[0042] The names corresponding to the reference numerals in the attached figures are as follows:

[0043] 100 - Cascaded device, 101 - Substrate, 102 - Nucleation layer, 103 - Buffer layer one, 104 - Channel layer, 105 - Barrier layer, 106 - Capping layer, 107 - Buffer layer two, 108 - High-resistivity GaN layer, 109 - P-GaN bulk region, 110 - Two-dimensional electron gas layer, 111 - N+ well region, 112 - Dense dielectric layer, 113 - Source and drain trenches of GaN HEMT device, 114 - Source and drain trenches of GaN MOSFET device, 115 - Device isolation region, 116 - Source of GaN HEMT device, 117 - Drain of GaN HEMT device, 118 - Drain of GaN MOSFET device, 119 - Source of GaN MOSFET device, 120 - Gate of GaN HEMT device, 121 - GaN MOSFET device gate, 122-passivation layer, 123-first interconnect metal, 124-second interconnect metal, 125-third interconnect metal, 126-fourth interconnect metal, 1-GaN HEMT device, 2-GaN MOSFET device, 3-metal interconnect structure. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0045] like Figure 1 As shown, this embodiment provides a GaN HEMT / MOSFET monolithic integrated cascade device 100, see [link to documentation]. Figure 1 This is a schematic diagram of the structure of a GaN HEMT / MOSFET monolithic integrated cascade device 100 provided in this embodiment. The cascade device 100 includes a GaN HEMT (High Electron Mobility Transistor) device 1, a GaN MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device 2, and a metal interconnect structure 3.

[0046] In this embodiment, the substrate 101 can be a silicon substrate, sapphire substrate, silicon carbide substrate, gallium oxide substrate, etc., to provide a process platform for the subsequent formation of semiconductor structures; the thickness of the substrate 101 can be 300μm-800μm.

[0047] In this embodiment, the epitaxial layer of the GaN HEMT device 1 is fabricated on one side of the substrate 101. Its structure, from bottom to top, consists of an AlN nucleation layer 102 with a thickness ranging from 20 to 100 nm, a high-resistivity GaN buffer layer 103 with a thickness ranging from 300 to 1000 nm, an unintentionally doped intrinsic GaN channel layer 104 with a thickness ranging from 100 to 300 nm, and an Al layer with a gradually decreasing Al composition and a thickness ranging from 15 to 30 nm. x Ga (1-x) An N (0.25≤x≤0.75) barrier layer 105 and an AlN capping layer 106 with a thickness ranging from 2 to 10 nm. A two-dimensional electron gas layer 110 is formed at the interface between the channel layer 104 and the barrier layer 105 due to the polarization effect.

[0048] In this embodiment, the epitaxial layers of GaN HEMT device 1 and GaN MOSFET device 2 are transitioned by a capping layer 106 and a second buffer layer 107. Since the AlN capping layer 106 has a large bandgap and a high-quality crystal surface, it is possible to grow a high-quality second buffer layer 107, thereby achieving electrical isolation from the epitaxial layer of the lower GaN HEMT device 1 and blocking the downward diffusion of ions when the epitaxial layer of GaN MOSFET device 2 is highly doped in situ. The second buffer layer 107 is a high-resistivity GaN material with a thickness of 100~1000nm.

[0049] In this embodiment, the epitaxial structure of the GaN MOSFET device 2 is fabricated above the buffer layer 107. The structure consists of a high-resistivity GaN layer 108 with a thickness ranging from 1000 to 3000 nm and a P-GaN body region 109 with a thickness ranging from 300 to 600 nm, wherein the P-GaN body region 109 has an N+ well region grown in situ by in-situ doping of N-type material with a thickness ranging from 100 to 300 nm.

[0050] In this embodiment, the epitaxial layer is selectively etched to the AlN capping layer 106. After etching, the surface of the epitaxial layer is covered with a dense dielectric layer 112 of Al2O3 or SiO2 with a thickness ranging from 15 to 50 nm to improve the surface defects of the epitaxial layer after etching.

[0051] In this embodiment, selective depth etching of the epitaxial layer can be vertical etching, trapezoidal etching, and inverted trapezoidal etching. The etched AlN capping layer 106 surface serves as a process platform for fabricating the electrode of GaN HEMT device 1, while the unetched P-GaN body region surface serves as a process platform for fabricating the electrode of GaN MOSFET device 2.

[0052] In this embodiment, electrical isolation between different GaN HEMT / MOSFET monolithic integrated cascaded devices 100 distributed in the lateral direction of the wafer is achieved by selectively etching the epitaxial layer into the buffer layer 103. The etched area is called the device isolation region 115, which is used to block the electrical connection between different cascaded devices 100.

[0053] In this embodiment, the metal electrodes of the GaN HEMT device source 116 and GaN HEMT device drain 117 are fabricated in the source-drain groove 113 of the GaN HEMT device with an AlN capping layer 106 etched with a dense dielectric layer 112. The metal material is one or more metals stacked in Ti / TiN / Al / W, with a thickness ranging from 100 to 200 nm.

[0054] In this embodiment, the gate 120 metal of the GaN HEMT device is fabricated above a partially dense dielectric layer 112 between the source and drain. The metal material is a stack of one or more metals in Ti / W, with a thickness ranging from 100 to 200 nm.

[0055] In this embodiment, the source 119 and drain 118 of the GaN MOSFET device are respectively fabricated in the source-drain groove 114 of the GaN MOSFET device above the N+ well region 111 etched with a dense dielectric layer 112. The metal material is one or more metals stacked in Ti / TiN / Al / W, with a thickness ranging from 100 to 200 nm.

[0056] In this embodiment, the gate 121 of the GaN MOSFET device is metal-coated on top of the dense dielectric layer 112 between the N+ well regions 111 of the GaN MOSFET device. The gate 121 of the GaN MOSFET device is made of polycrystalline silicon and has a thickness ranging from 100 to 200 nm.

[0057] In this embodiment, a passivation layer 122 is deposited on the wafer surface facing away from the substrate after electrode fabrication. The electrode portions of GaN HEMT device 1 and GaN MOSFET device 2 are exposed by etching the passivation layer 122 above the electrodes, and the electrodes are led out using a metal deposition process. The source 116 of GaN HEMT device and the drain 118 of GaN MOSFET device are connected by a first interconnect metal 123 and connected to the ground electrode of an external circuit, serving as the source of cascaded device 100. The gate 120 of GaN HEMT device and the source 119 of GaN MOSFET device are connected by a second interconnect metal 124. The gate 121 of GaN MOSFET device is led out through a third interconnect metal 125 and serves as the gate of cascaded device 100, connected to an external gate driving circuit. The drain 117 of GaN HEMT device is led out through a fourth interconnect metal 126 and serves as the drain of cascaded device 100, connected to an external output circuit.

[0058] In this embodiment, the passivation layer 122 is SiN. x The material has a thickness ranging from 3000 to 5000 nm. After the passivation layer 122 is deposited, the surface of the passivation layer is planarized by chemical mechanical polishing (CMP).

[0059] In this embodiment, the metal interconnect structure 3 is obtained by sputtering or deposition of Al or Cu metal.

[0060] This embodiment also provides a method for fabricating a GaN HEMT / MOSFET monolithic integrated cascade device 100, such as... Figures 2 to 7 As shown, the specific steps include the following:

[0061] Step S11: Select substrate 101. The substrate can be any one of sapphire (Al2O3) substrate, Si substrate, GaN substrate, or SiC substrate. In this embodiment, Si is selected as the substrate. After selecting substrate 101, the substrate 101 is cleaned, and an epitaxial layer is grown on the substrate using MOCVD. The layers are, in sequence, a 20-100 nm thick AlN nucleation layer 102, a 300-1000 nm thick high-resistivity GaN buffer layer 103, a 100-300 nm thick unintentionally doped intrinsic GaN channel layer 104, and a 15-30 nm thick Al layer with gradually decreasing Al composition. x Ga (1-x) 105. N (0.25≤x≤0.75) barrier layer, 106. 2~10nm thick AlN capping layer, 107. 100~1000nm thick high-resistivity GaN buffer layer, 1000~3000nm thick high-resistivity GaN layer, and 300~600nm thick P-GaN bulk region.

[0062] Step S12: The epitaxial wafer is removed from the MOCVD chamber. A photolithography process is used to form a mask for the areas where the source and drain electrodes need to be formed. The P-GaN bulk region 109 in the mask area is etched using reactive ion dry etching to a depth of 100-300 nm. The etched epitaxial wafer is then immersed in a solution of dilute HCl (15%) and ultrapure water diluted at a ratio of 1:10 to remove etching residues. Defects after etching are passivated by plasma cleaning. The cleaned epitaxial wafer is then placed back into the MOCVD reaction chamber, and an N-type doped source silane (SiH4) is introduced. An in-situ selected region doping process is used to grow an N+ well region 111 with a thickness of 100-300 nm in the etched area, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The growth surface is flush with the surface of the P-GaN bulk region 109. The in-situ doping process avoids surface decomposition, impurity diffusion and the impact on the crystal quality of the underlying GaN epitaxial layers caused by high-temperature annealing. It is a relatively ideal method for high-concentration selective doping.

[0063] Step S13: A photoresist mask is formed on a portion of the epitaxial layer using photolithography. A reactive ion dry etching process is used to etch the epitaxial layer without the photoresist mask until the capping layer 106 is exposed, thus obtaining the epitaxial layer process platform for fabricating the electrode portion of the GaN HEMT device 1. After etching, the epitaxial wafer is cleaned to remove the photoresist, and then the epitaxial wafer is wetted with dilute HCl (15% concentration) and ultrapure water diluted at a ratio of 1:10 to remove residual stains after etching. Then, the defects after etching are passivated by plasma cleaning. The cleaned epitaxial wafer is transferred to a plasma-enhanced chemical vapor deposition (PECVD) apparatus for the deposition of a dense dielectric layer 112. In this embodiment, SiO2 is used as the dense dielectric layer material, and the deposition thickness is 15~50nm.

[0064] In step S14, a photoresist mask is formed on a portion of the dense dielectric layer 112 using photolithography, and a reactive ion dry etching process is used to completely etch the dense dielectric layer 112 without the photoresist mask, exposing the capping layer 106 beneath the dense dielectric layer 112, thus obtaining the source-drain ohmic groove 113 of the GaN HEMT device 1 and the source-drain groove 114 of the GaN MOSFET device 2. A photoresist mask is then formed on the epitaxial wafer using photolithography again, and the epitaxial layer outside the GaN HEMT / MOSFET monolithic integrated cascade device 100 is etched into the buffer layer 103 using a reactive ion dry etching process, achieving electrical isolation between different GaN HEMT / MOSFET monolithic integrated cascade devices 100 in the lateral direction of the wafer. The etched area is called the device isolation region 115 or passive region, and the unetched area surrounded by the region is the active region on the wafer, used to fabricate the cascade device 100.

[0065] Step S15: Immerse the etched wafer in a solution of dilute HCl (15%) and ultrapure water diluted at a ratio of 1:10 to remove etching residue, and passivate the etched defects by plasma cleaning. Under the mask protection of the photoresist, deposit one or more metal stacks of Ti / TiN / Al / W with a thickness of 100~200nm directly in the source and drain trenches 113 of the GaN HEMT device and the source and drain trenches 114 of the GaN MOSFET device using a metal deposition process. Then, through a metal lift-off process and low-temperature rapid annealing, obtain the GaN HEMT device source 116, GaN HEMT device drain 117, and GaN MOSFET device source 119 with good ohmic contact with the bottom epitaxial layer. The drain 118 of the MOSFET device is subjected to a low-temperature rapid annealing temperature of 550~750℃ and an annealing time of 60s~180s. Using the same photolithography and metal deposition process, one or more metal stacks of Ti / W with a thickness of 100~200nm are deposited on the upper surface of the dense dielectric layer 112 between the source 116 and drain 117 of the GaN HEMT device 1. After metal stripping, the gate 120 of the GaN HEMT device 1 is obtained. Finally, the wafer is cleaned using organic and inorganic cleaning methods and dried with nitrogen. The photolithography process is used again to form a photoresist mask pattern on part of the dense dielectric layer 112. A 100~200nm thick polysilicon is deposited on the upper surface of the dense dielectric layer 112 between the N+ well regions of the GaN MOSFET device 2 as the gate 121 of the GaN MOSFET device 2.

[0066] Step S16: Deposit a 3000~5000 nm thick SiN layer on the side of the wafer away from the substrate using PECVD. x A passivation layer 122 is deposited to completely cover the wafer surface. After deposition, the passivation layer 122 is planarized using chemical mechanical polishing (CMP). An aperture mask is formed in the electrode area of ​​the cascaded device 100 using photolithography. The passivation layer 122 above the electrodes is etched using reactive ion dry etching to form electrode vias. After etching, the wafer is wetted with a mixture of dilute HCl (15%) and ultrapure water at a ratio of 1:10 to remove residual stains. A metal interconnect structure 3 is fabricated in the vias using metal sputtering to complete the fabrication of the cascaded device 100. The metal interconnect structure 3 is made of Al or Cu metal.

[0067] like Figure 8The diagram shows a cascaded device consisting of a normally open HEMT device and a MOSFET device, forming a common-source, common-gate configuration. Typically, the device within the red dashed box is a high-voltage normally open GaN HEMT device, and the device within the black dashed box is a low-voltage normally off Si MOSFET device. Figure 8 As can be seen, the gate of the MOSFET device serves as the gate of the cascaded device, receiving the gate drive signal from the external drive circuit. The source of the MOSFET device is connected to the gate of the HEMT device and serves as the source of the cascaded device, connected to the ground electrode of the external circuit. The drain of the HEMT device serves as the drain of the cascaded device, outputting a signal to the external circuit. The cascaded GaN HEMT device utilizes the positive threshold voltage of the MOSFET and the high off-state blocking voltage of GaN to achieve enhanced characteristics while retaining the advantages of GaN HEMT devices such as high withstand voltage and high frequency, thus realizing the high-voltage normally-off characteristics of the overall cascaded device.

[0068] like Figure 9 The diagram shown is a top view of the main structure of the GaN HEMT / MOSFET monolithic integrated cascade device 100. The vertical projection of the GaN MOSFET device structure onto the position between the gate and drain of the lower GaN HEMT device is clearly visible, which helps save chip area. Furthermore, compared to monolithic integrated cascade devices where GaN HEMT and GaN MOSFETs are laterally distributed on the wafer, this arrangement shortens the length of metal interconnects, significantly reducing parasitic effects caused by metal interconnects, and positively impacting the performance of high-frequency GaN switching devices.

[0069] like Figure 10 The figure shows a three-dimensional structural diagram of a GaN HEMT / MOSFET monolithic integrated cascade device 100. The epitaxial layer is etched using a trapezoidal etching method. In order to effectively increase the device area of ​​the GaN MOSFET device 2, vertical etching methods and inverted trapezoidal etching methods can also be used.

[0070] In summary, the GaN HEMT / MOSFET monolithic integrated cascaded device 100 fabricated using this embodiment 1 reduces interface defects caused by heterogeneous integration and secondary epitaxy in the cascaded device through a one-time epitaxial layer deposition, thus improving the device's carrier transport capability. It fully utilizes the large wafer area between the GaN HEMT device gate 120 and the GaN HEMT device drain 117, and places a relatively small GaN MOSFET device 2 vertically above the gate and drain. This not only significantly saves chip area but also reduces parasitic effects due to shorter metal interconnects, making the chip more advantageous for high-frequency applications. This device layout method changes the voltage load from the buffer layer 103 below the GaN HEMT device gate 120 and the GaN HEMT device drain 117 to a shared voltage load from the lower buffer layer 103 and the upper GaN MOSFET device buffer layer 107. The metal electrode of MOSFET device 2 also acts as a gate floating field plate, improving the electric field distribution and increasing the device's withstand voltage level, thereby optimizing the device's breakdown characteristics. By electrically connecting the upper GaN MOSFET device 2 and the lower GaN HEMT device 1 through metal interconnection to form a cascaded device 100, not only can the threshold voltage of the normally open HEMT device be shifted in the forward direction to become a normally closed device, but the overall electrical performance of the device can also be improved, providing valuable experience for the further industrialization of GaN devices.

[0071] Nevertheless, the GaN HEMT / MOSFET monolithic integrated cascaded device 100 provided in Embodiment 1 has relatively strict requirements on the spacing between the gate 120 of the GaN HEMT device and the drain 117 of the GaN HEMT device, as well as the size of the GaN MOSFET device 2. Moreover, the small size of the GaN MOSFET device 2 still poses a significant challenge for current semiconductor processes, thus limiting its practical application. To further expand the application scope of this embodiment, the present invention also proposes Embodiment 2, with the device structure schematic diagram shown below. Figure 11 As shown.

[0072] Example 2

[0073] As another embodiment of the present invention, a schematic diagram of another GaN HEMT / MOSFET monolithic integrated cascaded device 100 provided in this embodiment is shown below. Figure 11As shown, the fabrication method and steps of the cascaded device 100 are the same as those in Example 1. The main difference is the change in the arrangement position of the GaN MOSFET device 2. The GaN HEMT device 1 and the GaN MOSFET device 2 are arranged in the lateral extension direction of the wafer, that is, the GaN MOSFET device 2 is located in the lateral direction of the GaN HEMT device 1 instead of the vertical projection direction. This method does not have specific requirements on the size of the GaN HEMT device 1 and the GaN MOSFET device 2, and is especially suitable for devices with a small gap between the gate 120 and the drain 117 of the GaN HEMT device. However, compared with Example 1, Example 2 does not reduce the chip area, and there is only a lower buffer layer 103 between the gate 120 and the drain 117 of the GaN HEMT device as the device voltage withstand layer. Under high voltage conditions at the drain 117 of the GaN HEMT device, the device is prone to breakdown, so the device has a low voltage withstand. Since the device is distributed in the lateral direction, the metal interconnect is longer, and the large parasitic effect of the metal line will affect the switching characteristics of the device and reduce its performance.

[0074] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A GaN HEMT / MOSFET monolithic integrated cascaded device, characterized in that, The invention includes the fabrication of GaN HEMT devices and GaN MOSFET devices electrically connected via a metal interconnect structure on the same wafer. The GaN MOSFET device is fabricated above the vertical structure of the GaN HEMT device, with its projected position located between the gate and drain of the GaN HEMT device. A high-resistivity GaN layer serves as an electrical insulating layer between the epitaxial structures of the GaN HEMT and GaN MOSFET devices. Isolation trenches are provided between the GaN HEMT / MOSFET monolithically integrated cascaded devices distributed along the lateral direction of the substrate, providing electrical isolation between the devices. The isolation trenches extend into the buffer layer of the GaN HEMT device. The wafer region containing the isolation trenches is a passive region, and the wafer region outside the passive region is an active region. The GaN HEMT / MOSFET monolithically integrated cascaded devices are fabricated within the active region. The GaN HEMT device includes a substrate and an epitaxial structure of the GaN HEMT device consisting of a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a capping layer disposed sequentially from bottom to top on the substrate. A dense dielectric layer is disposed above the capping layer. The source and drain of the GaN HEMT device are disposed in a groove formed by etching the dense dielectric layer to the capping layer. The gate of the GaN HEMT device is disposed in a portion of the area above the capping layer. A two-dimensional electron gas layer is formed near the upper surface of the channel layer at the interface between the channel layer and the barrier layer due to the polarization effect. Above the capping layer is a second buffer layer, and above the second buffer layer is a GaN MOSFET device. The GaN MOSFET device includes a high-resistivity GaN layer and a P-GaN body region sequentially disposed above the second buffer layer; two in-situ heavily doped N+ well regions that are selectively etched into the P-GaN body region and epitaxially grown in the etched area; a dense dielectric layer disposed above the P-GaN body region and the N+ well region; the source and drain of the GaN MOSFET device respectively disposed in the groove formed by etching the dense dielectric layer to the top of the N+ well region; and the gate of the GaN MOSFET device disposed above the dense dielectric layer between the N+ well regions. The epitaxial structures of the GaN HEMT device and the GaN MOSFET device are formed by a single epitaxial growth process to create a vertically stacked epitaxial layer structure.

2. The GaN HEMT / MOSFET monolithic integrated cascade device according to claim 1, characterized in that, After the electrode portions of the GaN HEMT and GaN MOSFET devices are fabricated, they are covered with a passivation layer. Electrode openings are formed by etching the passivation layer above the electrode portions. Metal interconnect structures are fabricated in the electrode openings and interconnected to form metal interconnects. Specifically, the source of the GaN HEMT device is connected to the drain of the GaN MOSFET device, and a connecting metal line is led out to connect to an external ground electrode to form a first interconnect metal. The gate of the GaN HEMT device is connected to the source of the GaN MOSFET device to form a second interconnect metal. A connecting metal line led out from the gate of the GaN MOSFET device is connected to an external gate driving circuit to form a third interconnect metal. A connecting metal line led out from the drain of the GaN HEMT device is connected to the output terminal of an external circuit to form a fourth interconnect metal.

3. A GaN HEMT / MOSFET monolithic integrated cascade device according to claim 2, characterized in that, The nucleation layer of the GaN HEMT device is made of AlN material with a thickness of 20-100 nm; the buffer layer is intentionally doped high-resistivity GaN material with a thickness of 300-1000 nm; the channel layer is unintentionally doped intrinsic GaN material with a thickness of 100-300 nm; and the barrier layer is made of Al with gradually decreasing Al content. x Ga (1-x) The material is N, where 0.25≤x≤0.75 and the thickness is 15~30nm; the capping layer is AlN material with a thickness of 2~10nm.

4. A GaN HEMT / MOSFET monolithic integrated cascade device according to claim 3, characterized in that, The second buffer layer is a deliberately doped high-resistivity GaN material with a thickness of 100~1000nm; the high-resistivity GaN layer is a deliberately doped high-resistivity GaN material with a thickness of 1000~3000nm; the P-GaN bulk region is a doped P-type material with a thickness of 300~600nm; the N+ well region is an in-situ heavily doped N-type ion epitaxially grown N-type GaN material with a thickness of 100~300nm; wherein, the high-resistivity GaN layer and the P-GaN bulk region together constitute the epitaxial layer structure of the GaN MOSFET device.

5. A GaN HEMT / MOSFET monolithic integrated cascade device according to claim 4, characterized in that, The dense dielectric layer is made of Al2O3 or SiO2 material and has a thickness of 15~50nm.

6. A GaN HEMT / MOSFET monolithic integrated cascade device according to claim 5, characterized in that, The source, drain, drain, and source of the GaN HEMT device are one or more metal stacked structures of Ti / TiN / Al / W, with a thickness of 100-200 nm; the gate of the GaN HEMT device is one or more metal stacked structures of Ti / W, with a thickness of 100-200 nm; the gate of the GaN MOSFET device is made of polycrystalline silicon, with a thickness of 100-200 nm; the first, second, third, and fourth interconnect metals are Al or Cu metal materials.

7. A method for fabricating a GaN HEMT / MOSFET monolithic integrated cascaded device, characterized in that, The method for fabricating the GaN HEMT / MOSFET monolithic integrated cascade device as described in claim 6 includes the following steps: A substrate is provided, on which a core layer, a first buffer layer, a channel layer, a barrier layer, a capping layer, a second buffer layer, a high-resistivity GaN layer, and a P-GaN bulk region are sequentially grown to complete the epitaxial layer growth of a monolithic integrated cascaded device. After selective etching of the P-GaN bulk region, N-type ions are in-situ heavily doped and then an N-type ion heavily doped GaN epitaxial layer is grown until its surface is flush with the surface of the P-GaN bulk region to obtain an N+ well region. The epitaxial layer structure of the monolithic integrated cascaded device is etched down to the capping layer, and a dense dielectric layer is deposited on the epitaxial layer away from the substrate surface. The dense dielectric layer in the source and drain regions of GaN HEMT devices and GaN MOSFET devices is etched by selective etching process to expose the capping layer in the source and drain regions of GaN HEMT devices and the N+ well region in the source and drain regions of GaN MOSFET devices. The region partially etched to the dense dielectric layer is selectively etched again to the buffer layer 1 using a selective etching process. The etched region is a passive region, and the unetched region is an active region. The GaN HEMT / MOSFET monolithic integrated cascade device is fabricated in the active region. The two active regions are separated by the passive region, thereby forming electrical isolation between the devices. Source metal and drain metal are deposited in the source and drain trenches of the GaN HEMT device and GaN MOSFET device, and the source and drain of the GaN HEMT device and the GaN MOSFET device are obtained by low-temperature rapid annealing, respectively. A gate metal for the GaN HEMT device is fabricated above a dense dielectric layer between the source and drain electrodes, and a Schottky contact is formed between the gate of the GaN HEMT device and the underlying dense dielectric layer. A GaN MOSFET device gate is fabricated on top of a dense dielectric layer between the two N+ well regions of the GaN MOSFET device. The gate material is polycrystalline silicon, and a Schottky contact is formed with the underlying dense dielectric layer. A passivation layer is deposited over the active and passive regions, and the surface of the passivation layer is planarized by chemical mechanical polishing. The passivation layer above the source, drain, and gate of GaN HEMT and GaN MOSFET devices is etched to form electrode openings. Metal is deposited in the openings to obtain a metal interconnect structure, thus completing the device fabrication.

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