Backside illuminated image sensor preparation method and backside illuminated image sensor

Abstract

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises a plurality of trench isolation parts distributed at intervals along a first direction, and forming a plurality of trench isolation parts distributed at intervals along the first direction after a first lamination layer is formed on the back surface of the substrate, the plurality of first photosensitive parts extend into the first lamination layer along a second direction close to the substrate; after a second lamination layer covering the first photosensitive parts is formed, forming a plurality of second photosensitive parts which are distributed at intervals along the first direction, penetrate through the second lamination layer along the second direction and extend into the first photosensitive parts; and after a third lamination layer covering the plurality of second photosensitive parts is formed, forming a plurality of isolation columns which are distributed at intervals along the first direction, penetrate through the third lamination layer, the second lamination layer and the first lamination layer along the second direction and extend to the plurality of trench isolation parts. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a method for fabricating a back-illuminated image sensor and the back-illuminated image sensor itself. Background Technology

[0002] Back-side illumination (BSI) image sensors are a type of image sensor that offers better performance than front-side illumination image sensors in low-light conditions.

[0003] However, the photosensitivity of BSI image sensors manufactured using existing BSI image sensor fabrication methods cannot meet practical needs. Therefore, improving the photosensitivity of BSI image sensors has become one of the urgent technical problems to be solved. Summary of the Invention

[0004] Therefore, it is necessary to address the technical problem of insufficient light sensitivity of existing BSI image sensors by providing a back-illuminated image sensor fabrication method and a back-illuminated image sensor.

[0005] In a first aspect, this disclosure provides a method for fabricating a back-illuminated image sensor, comprising:

[0006] A substrate is provided, the substrate including a plurality of trench isolation portions spaced apart along a first direction, and after a first stack is formed on the back side of the substrate, a plurality of first photosensitive portions spaced apart along the first direction and extending into the first stack along a second direction close to the substrate are formed.

[0007] After forming a second stack covering multiple first photosensitive portions, multiple second photosensitive portions are formed that are spaced apart along a first direction, penetrate the second stack along a second direction, and extend into the first photosensitive portions.

[0008] After forming a third stack covering multiple second photosensitive portions, multiple isolation pillars are formed that are spaced apart along a first direction, penetrate the third stack, the second stack, and the first stack along a second direction, and extend to multiple trench isolation portions; the first stack, the second stack, and the third stack all include a target semiconductor layer; the first photosensitive portion, the second photosensitive portion, and the target semiconductor layer each include different Group V elements.

[0009] In the back-illuminated image sensor fabrication method described above, a plurality of trench isolation portions spaced apart along a first direction are formed in a substrate, the first direction being parallel to the back surface of the substrate; after forming a first stack including a target semiconductor layer on the back surface of the substrate, a plurality of first photosensitive portions spaced apart along the first direction and extending into the first stack along a second direction close to the substrate are formed, such that the target semiconductor layer of the first stack covers the bottom of the first photosensitive portions; after forming a second stack covering the plurality of first photosensitive portions, a plurality of second photosensitive portions spaced apart along the first direction, penetrating the second stack along the second direction and extending into the first photosensitive portions are formed, such that the target semiconductor layer of the second stack covers the bottom of the first photosensitive portions; after forming a second stack covering the plurality of first photosensitive portions, a plurality of second photosensitive portions spaced apart along the first direction, penetrating the second stack along the second direction and extending into the first photosensitive portions are formed, such that the target semiconductor layer of the second stack covers the bottom of the first photosensitive portions. A conductor layer circumferentially surrounds the second photosensitive portion, and the top of the first photosensitive portion circumferentially surrounds and covers the bottom of the second photosensitive portion. After forming a third stack covering multiple second photosensitive portions, multiple isolation pillars are formed, spaced apart along a first direction, penetrating the third stack, second stack, and first stack along a second direction, and extending to the top surface of multiple trench isolation portions. This ensures that the target semiconductor layer of the third stack covers and circumferentially surrounds the top of the second photosensitive portion, and adjacent photosensitive stacks along the first direction are isolated by the isolation pillars. The photosensitive stack includes a first photosensitive portion, a second photosensitive portion, a first stack covering the first photosensitive portion, a second stack surrounding the second photosensitive portion, and a third stack covering the second photosensitive portion. Within the photosensitive stack, the first photosensitive portion, the second photosensitive portion, and the target semiconductor layer each include different Group V elements. The photosensitive stack doped with different pentavalent elements will generate a concentration gradient within it after photoexcitation. This difference is used to optimize the transport path of photogenerated carriers and reduce the recombination rate during diffusion. Under the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. In addition, since pentavalent elements have a higher atomic mass than silicon, their mobility is lower during epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing pentavalent elements with different dopants in multiple stages can improve the uniformity of doping concentration in the pixel area.

[0010] Furthermore, the isolation pillar and the trench isolation portion can together constitute the target isolation portion, which can effectively avoid signal crosstalk between adjacent photosensitive stacks along the first direction; and, during the fabrication of the isolation pillar, multiple photosensitive stacks distributed at intervals along the first direction are fabricated simultaneously, which effectively reduces the complexity and cost of the fabrication process.

[0011] In some embodiments, the first photosensitive portion circumferentially surrounds and covers the bottom of the second photosensitive portion; the third stack circumferentially surrounds and covers the top of the second photosensitive portion.

[0012] In some embodiments, the top surface of the trench isolation portion is located inside the bottom surface of the isolation column.

[0013] In some embodiments, the first photosensitive part includes a SiP layer; the second photosensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

[0014] In some embodiments, the first stack includes a first target semiconductor layer and a first dielectric layer stacked along a second direction; the target semiconductor layer covers a plurality of first photosensitive portions, and the top surface of the target semiconductor layer is higher than the top surface of the plurality of first photosensitive portions.

[0015] In some embodiments, after forming a plurality of isolation pillars, the method further includes: self-aligning the plurality of isolation pillars to form a plurality of grids located directly above the plurality of isolation pillars; and forming a filter between adjacent grids along a first direction.

[0016] Secondly, this disclosure provides a back-illuminated image sensor, fabricated using the back-illuminated image sensor fabrication method of any of the foregoing embodiments. The back-illuminated image sensor includes a substrate, a first stack, a plurality of first photosensitive portions, a second stack, a plurality of second photosensitive portions, a third stack, and a plurality of isolation pillars. The substrate includes a plurality of trench isolation portions spaced apart along a first direction. The first stack is located on the back side of the substrate. The plurality of first photosensitive portions are spaced apart along the first direction and extend into the first stack along a second direction close to the substrate. The second stack covers the plurality of first photosensitive portions. The plurality of second photosensitive portions are spaced apart along the first direction, penetrate the second stack along the second direction, and extend into the first photosensitive portions. The third stack covers the plurality of second photosensitive portions. The plurality of isolation pillars are spaced apart along the first direction, penetrate the third stack, the second stack, and the first stack along the second direction, and extend into the plurality of trench isolation portions.

[0017] In some embodiments, the first photosensitive portion circumferentially surrounds and covers the bottom of the second photosensitive portion; the third stack circumferentially surrounds and covers the top of the second photosensitive portion; and the top surface of the trench isolation portion is located inside the bottom surface of the isolation post.

[0018] In some embodiments, the first stack, the second stack, and the third stack all include a target semiconductor layer; the first photosensitive portion, the second photosensitive portion, and the target semiconductor layer each include different Group 5 elements.

[0019] In some embodiments, the first photosensitive part includes a SiP layer; the second photosensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

[0020] The back-illuminated image sensor fabrication method and the back-illuminated image sensor disclosed in this embodiment have the following unexpected technical effects:

[0021] The target semiconductor layer of the first stack covers the bottom of the first photosensitive portion; after forming a second stack covering multiple first photosensitive portions, multiple second photosensitive portions are formed that are spaced apart along a first direction, penetrate the second stack along a second direction, and extend into the first photosensitive portion, such that the target semiconductor layer of the second stack circumferentially surrounds the second photosensitive portion, and the top of the first photosensitive portion circumferentially surrounds and covers the bottom of the second photosensitive portion; after forming a third stack covering multiple second photosensitive portions, multiple isolation pillars are formed that are spaced apart along a first direction, penetrate the third stack, the second stack, and the first stack along a second direction, and extend to the top surface of multiple trench isolation portions, such that the target semiconductor layer of the third stack covers and circumferentially surrounds the top of the second photosensitive portion, and adjacent photosensitive stacks along the first direction are isolated by the isolation pillars, the photosensitive stack includes a first photosensitive portion, a second photosensitive portion, a first stack covering the first photosensitive portion, a second stack surrounding the second photosensitive portion, and a third stack covering the second photosensitive portion. The first photosensitive section, the second photosensitive section, and the target semiconductor layer within the photosensitive stack each comprise different Group 5 elements. When photosensitive stacks doped with different pentavalent elements are photoexcited, a concentration gradient is generated within them. This difference optimizes the transport path of photogenerated carriers, reducing the recombination rate during diffusion. Through the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. Furthermore, since pentavalent elements have higher atomic masses than silicon, their mobility during epitaxial growth is lower, leading to uneven doping concentrations in a single doped layer. Growing different pentavalent elements in multiple stages can improve the uniformity of doping concentration in the pixel region.

[0022] Furthermore, the isolation pillar and the trench isolation portion can together constitute the target isolation portion, which can effectively avoid signal crosstalk between adjacent photosensitive stacks along the first direction; and, during the fabrication of the isolation pillar, multiple photosensitive stacks distributed at intervals along the first direction are fabricated simultaneously, which effectively reduces the complexity and cost of the fabrication process. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of a back-illuminated image sensor fabrication method provided in one embodiment;

[0025] Figure 2 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first stack on a substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0026] Figure 3 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first groove on the substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0027] Figure 4 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first photosensitive part on the substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0028] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the second stack in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0029] Figure 6 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the second groove in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0030] Figure 7 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming the second photosensitive part in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0031] Figure 8 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the third stack in step S30 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0032] Figure 9 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the isolation pillar in step S30 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0033] Figure 10 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a grid in a back-illuminated image sensor fabrication method provided in one embodiment.

[0034] Figure 11 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a filter in a back-illuminated image sensor fabrication method provided in one embodiment.

[0035] Explanation of reference numerals in the attached figures:

[0036] 10. Substrate; 10a. Back side; 101. Trench isolation portion; 102. Etch stop layer; 103. Interlayer dielectric layer; 21. First target semiconductor layer; 22. First dielectric layer; 20. First stacked layer; 31. First trench; 32. First sacrificial layer; 30. First photosensitive portion; 41. Second target semiconductor layer; 42. Second dielectric layer; 40. Second stacked layer; 51. Second trench; 52. Second sacrificial layer; 50. Second photosensitive portion; 61. Third target semiconductor layer; 62. Third dielectric layer; 60. Third stacked layer; 70. Isolation pillar; 80. Grating; 81. First grating material layer; 82. Second grating material layer; 83. Third grating material layer; 90. Filter. Detailed Implementation

[0037] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0043] In this embodiment of the disclosure, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the direction away from the substrate surface (the thickness direction of the substrate) is, for example, a second direction. In this embodiment of the disclosure, the first direction can be the ox direction, and the second direction can be the oz direction.

[0044] Please refer to Figure 1 In some embodiments, a method for fabricating a back-illuminated image sensor is provided, comprising:

[0045] Step S10: Provide a substrate, the substrate including a plurality of trench isolation portions spaced apart along a first direction, after forming a first stack on the back side of the substrate, form a plurality of first photosensitive portions spaced apart along the first direction and extending into the first stack along a second direction close to the substrate;

[0046] Step S20: After forming a second stack covering multiple first photosensitive portions, a plurality of second photosensitive portions are formed that are spaced apart along a first direction, penetrate the second stack along a second direction, and extend into the first photosensitive portions;

[0047] Step S30: After forming a third stack covering multiple second photosensitive portions, multiple isolation pillars are formed that are spaced apart along a first direction, penetrate the third stack, the second stack, and the first stack along a second direction, and extend to multiple trench isolation portions; the first stack, the second stack, and the third stack all include a target semiconductor layer; the first photosensitive portion, the second photosensitive portion, and the target semiconductor layer each include different Group V elements.

[0048] For example, please continue to refer to Figure 1A plurality of trench isolation portions are formed in a substrate at intervals along a first direction, which may be parallel to the back surface of the substrate. After forming a first stack including a target semiconductor layer on the back surface of the substrate, a plurality of first photosensitive portions are formed at intervals along the first direction and extending into the first stack along a second direction close to the substrate, such that the target semiconductor layer of the first stack covers the bottom of the first photosensitive portions. After forming a second stack covering the plurality of first photosensitive portions, a plurality of second photosensitive portions are formed at intervals along the first direction, penetrating the second stack along the second direction and extending into the first photosensitive portions, such that the target semiconductor layer of the second stack circumferentially surrounds the second photosensitive portion. The photosensitive layer consists of a first photosensitive layer whose top circumferentially surrounds and encloses the bottom of a second photosensitive layer. After forming a third stack covering multiple second photosensitive layers, multiple isolation pillars are formed, spaced apart along a first direction, penetrating the third stack, second stack, and first stack along a second direction, and extending to the top surface of multiple trench isolation layers. This ensures that the target semiconductor layer of the third stack covers and circumferentially surrounds the top of the second photosensitive layer, and adjacent photosensitive stacks along the first direction are isolated by the isolation pillars. The photosensitive stack includes a first photosensitive layer, a second photosensitive layer, a first stack covering the first photosensitive layer, a second stack surrounding the second photosensitive layer, and a third stack covering the second photosensitive layer. Within the photosensitive stack, the first photosensitive layer, the second photosensitive layer, and the target semiconductor layer each contain different Group V elements. The photosensitive stack doped with different pentavalent elements will generate a concentration gradient within it after photoexcitation. This difference is used to optimize the transport path of photogenerated carriers and reduce the recombination rate during diffusion. Under the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. In addition, since pentavalent elements have a higher atomic mass than silicon, their mobility is lower during epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing pentavalent elements with different dopants in multiple stages can improve the uniformity of doping concentration in the pixel area.

[0049] Furthermore, the isolation pillar and the trench isolation portion can together constitute the target isolation portion, which can effectively avoid signal crosstalk between adjacent photosensitive stacks along the first direction; and, during the fabrication of the isolation pillar, multiple photosensitive stacks distributed at intervals along the first direction are fabricated simultaneously, which effectively reduces the complexity and cost of the fabrication process.

[0050] Please refer to Figure 2 In some embodiments, the provided substrate 10 includes a plurality of trench isolation portions 101 spaced apart along a first direction, such as the ox direction. The material of the trench isolation portions 101 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or combinations thereof.

[0051] As an example, please continue to refer to Figure 2The trench isolation portion 101 can be used to isolate electrons and light energy. The shape of the longitudinal section (the section parallel to the Zox plane) of the trench isolation portion 101 may include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or a combination of regular trapezoids, inverted trapezoids, rectangles, etc. This disclosure does not impose specific limitations on the shape, material, or size of the trench isolation portion 101, as long as it can isolate electrons, light energy, doped ions, etc. Furthermore, this embodiment does not impose specific limitations on the spacing between adjacent trench isolation portions 101, and it can be set according to actual needs.

[0052] As an example, please continue to refer to Figure 2 The substrate 10 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0053] As an example, please continue to refer to Figure 2 P-type ions, such as boron ions, can be implanted into the substrate 10 by ion implantation to form a P-type substrate.

[0054] Please continue to refer to this. Figure 2 In some embodiments, the front side of the trench isolation portion 101 is covered with an etch stop layer 102, and the side of the etch stop layer 102 opposite to the trench isolation portion 101 includes an interlayer dielectric layer 103.

[0055] For example, please continue to refer to Figure 2 After forming the etch stop layer 102, metal is deposited to form a partial interconnect structure, and an interlayer dielectric layer 103 is formed on this basis. When the etch stop layer 102 is multilayered, other process problems caused by cracks in a single layer and / or failure of the metal interconnect structure can be avoided. The interlayer dielectric layer 103 can be silicon oxide or other dielectric material layers. In addition, metal interconnect structures can be formed on the interlayer dielectric layer 103 as metal interconnect portions of the device.

[0056] Of course, this embodiment only illustrates one method. As long as the metal interconnect structure can be formed reasonably, the thickness of the etching stop layer 102 and the interlayer dielectric layer 103 is not limited and can be adjusted according to specific process requirements.

[0057] Please continue to refer to this. Figure 2 In some embodiments, after forming a shallow trench (STI) within the substrate 10 and filling the STI with dielectric material, a trench isolation portion 101 can be formed. Subsequently, the substrate 10 can be flipped over, and the back side of the substrate 10 can be thinned and planarized to expose the back side of the trench isolation portion 101. This facilitates the formation of a PN junction between the P-type substrate and the N-type photosensitive stack.

[0058] For example, please continue to refer to Figure 2 A first target semiconductor layer 21 is epitaxially grown on the back side 10a of a substrate 10 with a flat top surface. The thickness of the first target semiconductor layer 21 can be 50 nanometers to 60 nanometers. For example, the thickness of the first target semiconductor layer 21 can be 50 nanometers, 55 nanometers, or 60 nanometers. The first target semiconductor layer 21 may include a SiAs layer, which is used to characterize silicon material doped with arsenic (As).

[0059] For example, please continue to refer to Figure 2 After forming a first target semiconductor layer 21 on the back side 10a of the substrate 10 using a selective epitaxial growth process, a first dielectric layer 22 is formed on the top surface of the first target semiconductor layer 21. The first target semiconductor layer 21 and the first dielectric layer 22 together constitute a first stack 20. The first dielectric layer 22 is used to protect the first target semiconductor layer 21 from damage during subsequent etching or polishing processes.

[0060] For example, please continue to refer to Figure 2 The thickness of the first dielectric layer 22 can be 1 nm to 2 nm. For example, the thickness of the first dielectric layer 22 can be 1 nm, 1.5 nm, or 2 nm. The material of the first dielectric layer 22 can include silicon oxide.

[0061] Please refer to Figure 3 In some embodiments, after a first patterned photoresist layer (not shown) is formed on the top surface of the first stack 20, the first patterned photoresist layer includes an opening pattern for defining the shape, position, and size of the first groove 31. Based on the first patterned photoresist layer, the first stack 20 is etched to form a plurality of first grooves 31 spaced apart along a first direction within the first stack 20. The first stack 20 between adjacent first grooves 31 along the first direction serves to form a first sacrificial layer 32.

[0062] Please refer to Figure 4 In some embodiments, a selective epitaxial growth process can be used to form a first photosensitive portion 30 within the first groove 31. The first photosensitive portion 30 fills the first groove 31, and the top surface of the first photosensitive portion 30 is higher than the top surface of the first dielectric layer 22. The first photosensitive portion 30 may include a SiP layer, which is used to characterize silicon material doped with phosphorus (P).

[0063] Please refer to Figure 5 In some embodiments, a selective epitaxial growth process can be used to form a second target semiconductor layer 41 covering the first photosensitive portion 30 and the first sacrificial layer 32, wherein the top surface of the second target semiconductor layer 41 is higher than the top surface of the first photosensitive portion 30. The material of the second target semiconductor layer 41 can be the same as the material of the first target semiconductor layer 21.

[0064] For example, please continue to refer to Figure 5 The second target semiconductor layer 41 may include a SiAs layer, which is used to characterize silicon material doped with arsenic (As).

[0065] For example, please continue to refer to Figure 5 A second dielectric layer 42 is formed on the top surface of the second target semiconductor layer 41, and the thickness of the second dielectric layer 42 is less than the thickness of the second target semiconductor layer 41. The second target semiconductor layer 41 and the second dielectric layer 42 are used to jointly constitute the second stack 40. The second dielectric layer 42 is used to protect the second target semiconductor layer 41 from damage during subsequent etching or polishing processes.

[0066] For example, please continue to refer to Figure 5 The material of the second dielectric layer 42 may include silicon oxide.

[0067] Please refer to Figure 6 In some embodiments, after a second patterned photoresist layer (not shown) is formed on the top surface of the second stack 40, the second patterned photoresist layer includes an opening pattern for defining the shape, position, and size of the second grooves 51. Based on the second patterned photoresist layer, the second stack 40 is etched to form a plurality of second grooves 51 spaced apart along a first direction within the second stack 40. The second stack 40 between adjacent second grooves 51 along the first direction serves to form a second sacrificial layer 52.

[0068] Please refer to Figure 7 In some embodiments, a selective epitaxial growth process can be used to form a second photosensitive portion 50 within the second groove 51. The second photosensitive portion 50 fills the second groove 51, and the top surface of the second photosensitive portion 50 is higher than the top surface of the second dielectric layer 42. The second photosensitive portion 50 may include a SiSb layer, which is used to characterize silicon material doped with antimony (Sb).

[0069] Please refer to Figure 8 In some embodiments, a selective epitaxial growth process can be used to form a third target semiconductor layer 61 covering the second photosensitive portion 50 and the second sacrificial layer 52, with the top surface of the third target semiconductor layer 61 being higher than the top surface of the second photosensitive portion 50. The material of the third target semiconductor layer 61 can be the same as the material of the second target semiconductor layer 41.

[0070] For example, please continue to refer to Figure 8 The third target semiconductor layer 61 may include a SiAs layer, which is used to characterize silicon material doped with arsenic (As).

[0071] For example, please continue to refer to Figure 8 A third dielectric layer 62 is formed on the top surface of the third target semiconductor layer 61, and the thickness of the third dielectric layer 62 is less than the thickness of the third target semiconductor layer 61. The third target semiconductor layer 61 and the third dielectric layer 62 are used together to form a third stack 60.

[0072] For example, please continue to refer to Figure 8 The material of the third dielectric layer 62 may include silicon oxide. During the subsequent etching process to remove the second sacrificial layer 52 and the first sacrificial layer 32, the third dielectric layer 62 can protect the third target semiconductor layer 61 from etching damage.

[0073] Please continue to refer to this. Figure 8 In some embodiments, the first photosensitive part 30 includes a SiP layer; the second photosensitive part 50 includes a SiSb layer; and the target semiconductor layer includes a SiAs layer. The photosensitive stack doped with different pentavalent elements will generate a concentration gradient within it after photoexcitation. This difference is used to optimize the transport path of photogenerated carriers and reduce the recombination rate during diffusion. Under the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved.

[0074] For example, an N-type photosensitive stack can form a PN junction of a photodiode with a P-type substrate. Please refer to [reference needed]. Figure 9 In some embodiments, after forming the third dielectric layer 62, a third patterned photoresist layer (not shown) may be formed on the top surface of the third dielectric layer 62. The third patterned photoresist layer includes an opening pattern for defining the shape, position, and size of the isolation pillars 70. The third stack 60 is etched based on the third patterned photoresist layer, and the second sacrificial layer 52 and the first sacrificial layer 32 are removed to obtain a plurality of isolation grooves (not shown) spaced apart along a first direction. The isolation grooves expose the top surface of the trench isolation portion 101.

[0075] Please continue to refer to this. Figure 9 In some embodiments, a deposition process can be used to fill at least the isolation material in multiple isolation grooves, and then the top surface of the isolation material can be planarized to obtain an isolation pillar 70 with its top surface flush with the top surface of the third dielectric layer 62.

[0076] Please refer to Figure 10In some embodiments, after forming the isolation pillar 70, a grid material stack (not shown) covering the top surface of the isolation pillar 70 and the top surface of the third dielectric layer 62 can be formed. The grid material stack includes a first grid material layer 81, a second grid material layer 82, and a third grid material layer 83 sequentially stacked along a second direction away from the substrate. The material of the first grid material layer 81 may include HfO2. The material of the second grid material layer 82 may include TiN. The material of the third grid material layer 83 may include Al.

[0077] Please continue to refer to this. Figures 10-11 In some embodiments, after forming the grid material stack, a fourth patterned photoresist layer (not shown) may be formed on the top surface of the grid material stack. The fourth patterned photoresist layer includes an opening pattern for defining the shape, position and size of the filter 90. The grid material stack is etched based on the fourth patterned photoresist layer to form a grid 80 directly above the isolation pillar 70.

[0078] Please continue to refer to this. Figures 10-11 In some embodiments, after forming the grid 80, the following steps are also included:

[0079] A filter 90 is formed between adjacent grids 80 along a first direction, such as the ox direction.

[0080] For example, please continue to refer to Figure 11 The filter 90 includes, but is not limited to, a red filter, a yellow filter, and a blue filter, and the three filters are arranged adjacent to each other as a pixel group. Among them, the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves.

[0081] Please continue to refer to this. Figure 11 In some embodiments, a back-illuminated image sensor is provided, fabricated using the back-illuminated image sensor fabrication method described in any of the foregoing embodiments. The back-illuminated image sensor includes a substrate 10, a first stack 20, a plurality of first photosensitive portions 30, a second stack 40, a plurality of second photosensitive portions 50, a third stack 60, and a plurality of isolation pillars 70. The substrate 10 includes a plurality of trench isolation portions 101 spaced apart along a first direction. The first stack 20 is located on the back surface 10a of the substrate 10. The plurality of first photosensitive portions 30 are spaced apart along the first direction. The first stack 20 is distributed at intervals and extends into the first stack 20 along a second direction close to the substrate 10; the second stack 40 covers a plurality of first photosensitive portions 30; a plurality of second photosensitive portions 50 are distributed at intervals along the first direction, penetrate the second stack 40 along the second direction, and extend into the first photosensitive portions 30; the third stack 60 covers a plurality of second photosensitive portions 50; a plurality of isolation pillars 70 are distributed at intervals along the first direction, penetrate the third stack 60, the second stack 40, and the first stack 20 along the second direction, and extend to the top surface of a plurality of trench isolation portions 101.

[0082] Please continue to refer to this. Figure 11 In some embodiments, the first photosensitive portion 30 circumferentially surrounds and covers the bottom of the second photosensitive portion 50; the third stack 60 circumferentially surrounds and covers the top of the second photosensitive portion 50; and the top surface of the trench isolation portion 101 is located inside the bottom surface of the isolation pillar 70.

[0083] Please continue to refer to this. Figure 11 In some embodiments, the first stack 20, the second stack 40, and the third stack 60 all include a target semiconductor layer; the first photosensitive portion 30, the second photosensitive portion 50, and the target semiconductor layer each include different Group 5 elements. Group 5 elements include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0084] Please continue to refer to this. Figure 11 In some embodiments, the target semiconductor layer includes a first target semiconductor layer 21, a second target semiconductor layer 41, and a third target semiconductor layer 61. The first stack 20 includes the first target semiconductor layer 21 and a first dielectric layer 22 stacked along a second direction away from the substrate; the second stack 40 includes the second target semiconductor layer 41 and a second dielectric layer 42 stacked along a second direction away from the substrate; and the third stack 60 includes the third target semiconductor layer 61 and a third dielectric layer 62 stacked along a second direction away from the substrate. The first target semiconductor layer 21, the second target semiconductor layer 41, and the third target semiconductor layer 61 all include a SiAs layer, which is used to characterize silicon material doped with arsenic (As).

[0085] Please continue to refer to this. Figure 11 In some embodiments, the first photosensitive part 30 includes a SiP layer; the second photosensitive part 50 includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

[0086] Please continue to refer to this. Figures 1-11 The back-illuminated image sensor fabrication method and back-illuminated image sensor in this disclosure embodiment have the following unexpected technical effects:

[0087] The target semiconductor layer of the first stack 20 covers the bottom of the first photosensitive portion 30; after forming the second stack 40 covering the plurality of first photosensitive portions 30, a plurality of second photosensitive portions 50 are formed, spaced apart along the first direction, penetrating the second stack 40 along the second direction, and extending into the first photosensitive portion 30, such that the target semiconductor layer of the second stack 40 circumferentially surrounds the second photosensitive portion 50, and the top of the first photosensitive portion 30 circumferentially surrounds and covers the bottom of the second photosensitive portion 50; after forming the third stack 60 covering the plurality of second photosensitive portions 50, a plurality of second photosensitive portions 50 are formed, spaced apart along the first direction. A cloth, extending along a second direction through a third stack 60, a second stack 40, and a first stack 20, and extending to a plurality of isolation pillars 70 on the top surface of a plurality of trench isolation portions 101, such that the target semiconductor layer of the third stack 60 covers and circumferentially surrounds the top of the second photosensitive portion 50, and adjacent photosensitive stacks along the first direction are isolated by the isolation pillars 70. The photosensitive stack includes a first photosensitive portion 30, a second photosensitive portion 50, a first stack 20 covering the first photosensitive portion 30, a second stack 40 surrounding the second photosensitive portion 50, and a third stack 60 covering the second photosensitive portion 50. Within the photosensitive stack, the first photosensitive portion 30, the second photosensitive portion 50, and the target semiconductor layer each contain different Group V elements. The photosensitive stack doped with different pentavalent elements will generate a concentration gradient within it after photoexcitation. This difference is used to optimize the transport path of photogenerated carriers and reduce the recombination rate during the diffusion process. Under the combined effect of both, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. In addition, since pentavalent elements have a higher atomic mass than silicon, their mobility is lower during epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing pentavalent elements with different dopants in multiple stages can improve the uniformity of doping concentration in the pixel area.

[0088] Furthermore, the isolation pillar 70 and the trench isolation portion 101 can together constitute the target isolation portion, which can effectively avoid signal crosstalk between adjacent photosensitive stacks along the first direction; and, during the fabrication of the isolation pillar 70, multiple photosensitive stacks spaced apart along the first direction are fabricated simultaneously, which effectively reduces the complexity and cost of the fabrication process.

[0089] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, include: A substrate is provided, the substrate including a plurality of trench isolation portions spaced apart along a first direction; After forming a first stack on the back side of the substrate, a plurality of first photosensitive portions are formed, which are spaced apart along the first direction and extend into the first stack along a second direction close to the substrate. After forming a second stack covering the plurality of first photosensitive portions, a plurality of second photosensitive portions are formed that are spaced apart along the first direction, penetrate the second stack along the second direction, and extend into the first photosensitive portions; After forming a third stack covering the plurality of second photosensitive portions, a plurality of isolation pillars are formed, spaced apart along the first direction, penetrating the third stack, the second stack, and the first stack along the second direction, and extending to the plurality of trench isolation portions; the first stack, the second stack, and the third stack all include a target semiconductor layer; the first photosensitive portion, the second photosensitive portion, and the target semiconductor layer each include different Group 5 elements.

2. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The first photosensitive part circumferentially surrounds and covers the bottom of the second photosensitive part; The third layer circumferentially surrounds and covers the top of the second photosensitive part.

3. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The top surface of the trench isolation section is located inside the bottom surface of the isolation column.

4. The method for fabricating a back-illuminated image sensor according to any one of claims 1-3, characterized in that, The first photosensitive part includes a SiP layer; the second photosensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

5. The method for fabricating a back-illuminated image sensor according to any one of claims 1-3, characterized in that, The first stack includes a first target semiconductor layer and a first dielectric layer stacked along the second direction; The target semiconductor layer covers the plurality of first photosensitive portions, and the top surface of the target semiconductor layer is higher than the top surface of the plurality of first photosensitive portions.

6. The method for fabricating a back-illuminated image sensor according to any one of claims 1-3, characterized in that, After forming the plurality of isolation pillars, the method further includes: Self-aligning with the plurality of isolation posts to form a plurality of grids located directly above the plurality of isolation posts; A filter is formed between adjacent grids along the first direction.

7. A back-illuminated image sensor, characterized in that, The back-illuminated image sensor is fabricated using the method described in any one of claims 1-6, wherein the back-illuminated image sensor comprises: A substrate, wherein the substrate includes a plurality of trench isolation portions spaced apart along a first direction; The first stack is located on the back side of the substrate; Multiple first photosensitive portions are spaced apart along the first direction and extend into the first stack along a second direction close to the substrate; The second layer covers the plurality of first photosensitive units; Multiple second photosensitive portions are spaced apart along the first direction, penetrate the second stack along the second direction, and extend into the first photosensitive portion; The third layer covers the plurality of second photosensitive units; Multiple isolation pillars are spaced apart along the first direction, penetrate the third stack, the second stack, and the first stack along the second direction, and extend to the multiple trench isolation sections.

8. The back-illuminated image sensor according to claim 7, characterized in that, The first photosensitive part circumferentially surrounds and covers the bottom of the second photosensitive part; The third layer circumferentially surrounds and covers the top of the second photosensitive part; The top surface of the trench isolation section is located inside the bottom surface of the isolation column.

9. The back-illuminated image sensor according to claim 7 or 8, characterized in that, The first stack, the second stack, and the third stack all include a target semiconductor layer; The first photosensitive part, the second photosensitive part, and the target semiconductor layer each comprise different Group 5 elements.

10. The back-illuminated image sensor according to claim 9, characterized in that, The first photosensitive part includes a SiP layer; the second photosensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

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