A tbc cell and method of making the same

Abstract

The present application relates to the field of solar cells, and particularly relates to a TBC cell and a preparation method thereof. A predetermined pattern is formed on a polysilicon layer on the back of a silicon wafer by printing a sucrose solution using screen printing, and a temporary carbon film mask is formed by carbonizing the sucrose solution after drying. Then, an aluminum oxide sol is sprayed on the surface of the silicon wafer with the carbon film mask, the film plays a self-protection role in the deposition process, and is easy to remove after deposition. The method only needs to perform deposition of a tunneling oxide layer and a polysilicon layer once, greatly reducing the cost of mask, polysilicon layer deposition and wet etching in the production process.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a TBC cell and its preparation method. Background Technology

[0002] As the core component of the photovoltaic industry, solar cells have undergone continuous technological iterations around the two major goals of "improving conversion efficiency and reducing manufacturing costs." Mainstream solar cells are primarily divided into two categories: crystalline silicon cells and thin-film cells. Crystalline silicon cells, due to their abundant raw material reserves and high stability, occupy more than 95% of the global photovoltaic market share. They have evolved from traditional Al-BSF cells to high-efficiency structures such as passivated emitter and back contact cells (PERC cells), tunneling oxide passivated contact cells (TOPCon cells), and interdigitated back contact cells (IBC cells). Thin-film cells, represented by cadmium telluride and perovskite cells, possess characteristics such as flexibility and thinness, but are limited by the toxicity of raw materials or insufficient stability of the perovskite layer, and have not yet achieved large-scale mass production.

[0003] Currently, improvements in crystalline silicon solar cells mainly focus on "optimizing passivation effects" and "reducing light-shielding losses." TBC (Tunnel Oxide Passivated Contact Back Contact) cells combine the excellent passivation technology of TOPCon (tunnel oxide passivated contact) cells with the advantage of IBC (interdigitated back contact) cells having no grid lines blocking the back side. Its ultra-thin tunnel oxide layer and doped polycrystalline silicon layer form a "tunneling-passivation" composite structure, which can effectively suppress carrier recombination on the back side and improve the cell's open-circuit voltage. By arranging P-type and N-type electrodes in an interdigitated pattern on the back side of the cell, light-shielding losses from the front grid lines are completely eliminated, resulting in a significant increase in short-circuit current density compared to PERC cells of the same size.

[0004] However, despite the significant performance advantages of TBC batteries, the mainstream process for fabricating the key PIN structure on the back of TBC batteries (i.e., the N+ region, the local P+ region, and the isolation region in between) faces severe challenges. This process typically requires multiple high-temperature doping depositions, laser processes, and multiple masking and defilming steps. This highly cumbersome process not only significantly extends the processing time, severely restricting production capacity, but also introduces additional manufacturing costs, limiting the large-scale commercial application of TBC batteries.

[0005] Therefore, there is an urgent need to develop a simplified and low-cost method for preparing TBC batteries that can reduce production costs while ensuring efficient and selective doping of TBC batteries. Summary of the Invention

[0006] This invention provides a method for preparing a TBC battery, characterized by comprising the following steps:

[0007] (1) Silicon wafer pretreatment;

[0008] (2) A tunneling oxide layer and a polycrystalline silicon layer are deposited sequentially on the back side of the silicon wafer;

[0009] (3) Sucrose mask printing: The second doped region pattern is printed on the polycrystalline silicon layer using sucrose solution, and the sucrose is dried to carbonize it and form a solid carbon film mask;

[0010] (4) Spraying alumina sol: Spraying alumina sol onto the surface of the solid carbon film mask, drying it to form an alumina sol layer;

[0011] (5) Deposition and high-temperature treatment of the first heavy doping region: The first doping source is deposited in the area covered by the non-solid carbon film mask, and then annealed or diffused at high temperature to form the first heavy doping region with the opposite electrical properties to the second heavy doping region; at high temperature, the solid carbon film mask is burned, and the alumina sol layer is transformed into a brittle alumina protective layer. The ash of the burned solid carbon film mask is wrapped in the alumina protective layer.

[0012] (6) Remove the alumina protective layer and carbon film ash to expose the silicon wafer surface corresponding to the second heavy doping region;

[0013] (7) Deposition of the second heavily doped region: A second doping source is deposited and diffused on the silicon wafer surface corresponding to the second heavily doped region to form the second heavily doped region;

[0014] (8) Remove residual BSG and PSG glass layers;

[0015] (9) Gap area grooving: Grooves are made between the first heavy doping zone and the second heavy doping zone to form a gap area;

[0016] (10) Deposition of passivation layer;

[0017] (11) Printed electrode.

[0018] This invention employs screen printing to form a predetermined pattern using a sucrose solution on the polysilicon layer (poly-Si) on the back of a silicon wafer. After drying, the sucrose solution is carbonized to form a temporary carbon mask. Then, an alumina sol is sprayed onto the silicon wafer surface with the carbon mask. This film provides self-protection during deposition and is easily removed after deposition. This method requires only one deposition of the tunnel oxide layer and poly-Si, significantly reducing the costs of mask, poly-Si deposition, and wet etching during production.

[0019] The sucrose mask printing step involves printing a sucrose solution onto the silicon layer on the back of the silicon wafer to form a pre-defined second heavily doped region pattern. This second heavily doped region pattern corresponds to either a P+ or n+ region pattern. After the sucrose solution dries, it is carbonized to form a temporary carbon film mask. By printing the sucrose solution and carbonizing it to form a temporary carbon film mask, the second heavily doped region pattern can be precisely defined, providing accurate grinding protection for subsequent doping processes. This ensures that a heavily doped region highly matches the pre-defined p+ or n+ region pattern is formed on the silicon layer, laying the foundation for simplified processes. Furthermore, sucrose is widely available and inexpensive, reducing the cost of battery manufacturing.

[0020] The alumina region is slightly larger than the sucrose carbon film mask region, which can fully cover any tiny gaps or printing deviations that may exist at the edges of the sucrose carbon film mask, preventing impurities from entering from the edges in subsequent processes and providing support for the formation of a reducing atmosphere in the mask-protected area in subsequent processes. In this invention, "the alumina region is slightly larger than the sucrose carbon film mask region" means that the alumina region is 2-3 micrometers larger than the sucrose mask region.

[0021] When the first heavily doped region is formed by deposition, an atomic deposition process combined with high-temperature annealing or high-temperature diffusion is used. At high temperatures, the sucrose carbon film burns and decomposes, consuming local oxygen and generating a reducing atmosphere below the area it covers. This effectively protects the silicon / polycrystalline silicon surface in this region from excessive oxidation, while allowing the first element to diffuse into the silicon in the non-masked area, forming the first heavily doped region. After combustion, the carbon film ash is encapsulated in a catalytic alumina layer. The high-temperature annealing or high-temperature diffusion refers to the temperature of a conventional high-temperature annealing or thermal diffusion process.

[0022] When the first doping source is a boron source, the second doping source is a phosphorus source; when the first doping source is a phosphorus source, the second doping source is a boron source.

[0023] The first doped region and the second doped region have opposite electrical properties; specifically, the second doped region is usually an n+ region and the first doped region is a p+ region; alternatively, the second doped region can be a p+ region and the first doped region can be an n+ region.

[0024] Furthermore, the high-temperature annealing or high-temperature diffusion is carried out under inert gas protection, or in an oxygen-deficient atmosphere containing trace amounts of oxygen. This avoids excessive oxidation of the silicon wafer, ensures the stability of the reducing atmosphere of the sucrose carbon film, and improves the formation quality of the first doped region.

[0025] Furthermore, the sucrose concentration is 20-70%, specifically, the sucrose concentration is 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 70% or any intermediate value of two or more; more preferably, the sucrose concentration is 40-70%.

[0026] Furthermore, in step (3), the drying temperature is 80~160℃. Specifically, the drying and carbonization temperature is 80℃, 90℃, 95℃, 100℃, 110℃, 120℃, 130℃, 140℃, 150℃, 155℃, 160℃ or any intermediate value of both; more preferably, the drying and carbonization temperature is 120~150℃.

[0027] Furthermore, in step (4), the drying temperature is 60~150℃. Specifically, the drying and curing temperature is 60℃, 70℃, 80℃, 90℃, 95℃, 100℃, 105℃, 110℃, 120℃, 130℃, 140℃, 150℃ or any intermediate value of two or more; more preferably, the drying and curing temperature is 80~120℃.

[0028] Furthermore, in step (6), the silicon wafer is sprayed with hot water at 60~95℃ or immersed in acid to remove the alumina protective layer and carbon film ash. This invention utilizes the characteristic that the embrittled alumina layer rapidly hydrolyzes, expands, and disintegrates into fine particles upon contact with water. Hot water spraying or a low-concentration acid solution can easily remove the alumina protective layer and carbon film ash. The operation is simple, the process cost is low, and there is no violent reaction. It can efficiently expose the silicon surface previously covered by the carbon film while avoiding damage to the already formed heavily doped region of the silicon wafer.

[0029] Furthermore, the thickness of the tunneling oxide layer is 2-3 nm, specifically, the thickness of the tunneling oxide layer is 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm or any intermediate value of any two; the thickness of the polycrystalline silicon layer is 150 nm-250 nm, specifically, the thickness of the polycrystalline silicon layer is 150 nm, 170 nm, 190 nm, 200 nm, 220 nm, 240 nm, 250 nm or any intermediate value of any two.

[0030] Furthermore, the BSG and PSG glass layers are removed by cleaning with an etching solution. Specifically, the etching solution can be a diluted hydrofluoric acid, a hydrofluoric acid-nitric acid mixture, a hydrofluoric acid-hydrochloric acid mixture, sodium hydroxide, or potassium hydroxide solution.

[0031] Furthermore, in step (9), laser grooving or mechanical grooving is used to groove the designed gap between the first heavily doped region and the second heavily doped region with opposite electrical properties, remove the polysilicon and tunneling oxide layer in the trench until the silicon body is exposed, and realize the electrical isolation of the PN region.

[0032] Furthermore, a passivation layer and an anti-reflection layer are deposited on both the front and back sides of the silicon wafer. The passivation layer can be a single-layer passivation layer or a stacked passivation layer.

[0033] Specifically, the passivation layer is AlO. x The antireflection layer is SiN x .

[0034] Specifically, the passivation layer has a thickness of 4-6 nm, and the antireflection layer has a thickness of 70-100 nm.

[0035] Furthermore, contact electrodes are printed in the first heavily doped region and the second heavily doped region respectively using screen printing technology. That is, electrode paste is printed in the p+ region and n+ region on the back side to form contact electrodes, and sintering is performed to form good ohmic contact.

[0036] In another aspect, the present invention provides a TBC battery prepared by the above method.

[0037] Compared with the prior art, the beneficial effects of the present invention are:

[0038] 1) Simplified process and high compatibility with existing production lines: Using screen-printed sucrose solution as a temporary mask, the material cost is low, it is compatible with existing screen printing equipment, eliminates the traditional photolithography and mask deposition / removal processes, shortens the process flow, and reduces equipment investment and process losses.

[0039] 2) Self-protective reducing atmosphere: The high-temperature combustion of the sucrose carbon film generates a local reducing atmosphere, which can protect the silicon surface from oxidation under the high temperature of boron diffusion or phosphorus diffusion, eliminating the need for additional protective gas or protective layer and simplifying the high-temperature process protection logic.

[0040] 3) High-efficiency mask removal: Utilizing the characteristics of alumina sol becoming brittle at high temperatures and disintegrating upon contact with water, carbon ash mask and alumina carrier can be efficiently removed after rinsing with hot water or soaking in dilute acid, without residual pollution or damage to silicon wafers.

[0041] 4) Definition of doped regions: Sucrose masks can clearly divide boron-doped (p+) and phosphorus-doped (n+) regions. Combined with laser grooving or mechanical grooving, the two regions can be effectively isolated to avoid doping overflow and boundary blurring, and reduce carrier recombination loss.

[0042] 5) Silicon wafer surface protection: The entire process from mask covering to removal does not damage the silicon wafer surface structure. Combined with passivation process, the integrity of the silicon wafer surface can be maintained, providing a foundation for improving battery conversion efficiency.

[0043] 6) Cost control: Sucrose, alumina solvent and other materials are inexpensive and readily available, screen printing technology is mature, easy to operate and low in cost, mask removal does not require chemical reagents, and the cost of the entire preparation process is significantly reduced compared with the traditional TBC preparation process.

[0044] 7) Environmental friendliness: Mask removal is mainly done with hot water, reducing the discharge of chemical etching waste liquid; the sucrose combustion products and alumina sol hydrolysis products have no toxic residues, which meet the requirements of industrial environmental protection. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the silicon wafer structure after completing steps 1-4 in Embodiment 1 of the present invention;

[0047] Figure 2 This is a schematic diagram of the silicon wafer structure after steps 5-6 are completed in Embodiment 1 of the present invention;

[0048] Figure 3 This is a schematic diagram of the silicon wafer structure after steps 7-8 are completed in Embodiment 1 of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure of the TBC silicon wafer prepared in Example 1 of the present invention.

[0050] The structure consists of: 1. Silicon substrate; 2. Tunneling oxide layer; 3. Polycrystalline silicon layer; 4. Sucrose mask layer; 5. Alumina sol layer; 6. Boron doped layer; 7. BSG layer; 8. Phosphorus doped layer; 9. Passivation layer; 10. Antireflective layer; 11. Electrode. Detailed Implementation

[0051] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0052] Example 1

[0053] A method for preparing a TBC battery includes the following steps:

[0054] (1) Silicon wafer pretreatment: Select an N-type silicon wafer substrate, clean and polish it to remove impurities and damaged layers from the surface;

[0055] (2) On the surface of the pretreated silicon wafer substrate, a tunneling oxide layer with a thickness of 2.5 nm and a polycrystalline silicon layer with a thickness of 200 nm are sequentially deposited on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD) technology.

[0056] (3) Sucrose mask printing: Prepare a 40% sucrose solution and use a screen printing machine to print the n+ region pattern on the polycrystalline silicon layer on the back of the silicon wafer. Dry at 100°C to dehydrate and carbonize the sucrose to form a solid carbon film pattern.

[0057] (4) Spraying alumina sol: Spray a layer of alumina sol evenly on the surface of the silicon wafer with solid carbon film pattern, and dry it at 120°C to allow the sol to initially solidify. The alumina area should be slightly larger than the sucrose mask area, and the alumina area should be 3 micrometers larger than the sucrose mask area.

[0058] (5) Boron doping and high-temperature treatment: BBr3 gas was introduced into the furnace tube by chemical vapor deposition and then annealed at 900°C. At high temperature, the sucrose carbon film burned (C + O2 -> CO2), consuming the local oxygen in the area it covered, creating a reducing atmosphere below the area to protect the polycrystalline silicon / silicon below from oxidation; at the same time, boron in BSG diffused into the silicon in the non-carbon film covered area to form p+ region; the alumina sol layer was transformed into a brittle alumina layer and encapsulated the ash after carbon combustion.

[0059] (6) The silicon wafer after high-temperature treatment is sprayed with hot water at a temperature of 80°C to wash away the embrittled alumina layer and the carbon ash residue encapsulated therein, exposing the region corresponding to the n+ region on the silicon wafer.

[0060] (7) Phosphorus deposition and diffusion: Phosphorus deposition and diffusion are performed on the regions corresponding to the exposed n+ regions on the silicon wafer at a deposition and diffusion temperature of 500℃ to form n+ regions;

[0061] (8) Remove residual BSG and PSG glass layers: Clean the silicon wafer with a 35% hydrofluoric acid solution to remove residual BSG and PSG glass layers;

[0062] (9) Gap region grooving: A laser is used to groove the designed gap between the p+ region and the n+ region, remove the polysilicon and tunneling oxide layer in the trench, retain the silicon substrate, and form a gap region. The laser wavelength is 200nm, the power is ≥1W, the scanning speed is 5m / s, and the frequency is 2000 kHz.

[0063] (10) Deposit passivation layer and antireflection layer: Deposit aluminum oxide passivation layer and silicon nitride antireflection layer sequentially on the front and back sides of the silicon wafer; the aluminum oxide passivation layer has a thickness of 6 nm and the silicon nitride antireflection layer has a thickness of 70 nm.

[0064] (11) Screen-printed electrodes: Silver paste is printed on the p+ and n+ regions on the back of the silicon wafer using screen printing technology, and then sintered to form contact electrodes.

[0065] Example 2

[0066] A method for preparing a TBC battery includes the following steps:

[0067] (1) Silicon wafer pretreatment: Select a P-type silicon wafer substrate, clean and polish it to remove impurities and damaged layers from the surface;

[0068] (2) On the surface of the pretreated silicon wafer substrate, a tunneling oxide layer with a thickness of 2 nm and a polycrystalline silicon layer with a thickness of 150 nm are deposited sequentially on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD) technology.

[0069] (3) Sucrose mask printing: Prepare a 20% sucrose solution and use a screen printing machine to print the p+ region pattern on the polycrystalline silicon layer on the back of the silicon wafer. Dry the sucrose at 160°C to dehydrate and carbonize it, forming a solid carbon film pattern.

[0070] (4) Spraying alumina sol: Spray a layer of alumina sol evenly on the surface of the silicon wafer with solid carbon film pattern, and dry it at 150°C to allow the sol to initially solidify. The alumina area should be 3 micrometers larger than the sucrose mask area.

[0071] (5) Phosphorus doping and high-temperature treatment: A mixture of POCl3 and O2 gas was introduced into the furnace tube by chemical vapor deposition and then diffused at 500°C for 30 min to generate a phosphosilicate glass layer (PSG layer) and an n+ region. At high temperature, the sucrose carbon film burned (C + O2 -> CO2), consuming the local oxygen in the area it covered, creating a reducing atmosphere below the region to protect the polycrystalline silicon / silicon below from oxidation; the alumina sol layer was transformed into a brittle alumina layer and encapsulated the ash after carbon combustion.

[0072] (6) The silicon wafer after high-temperature treatment is sprayed with hot water at a temperature of 60°C to wash away the embrittled alumina layer and the carbon ash residue encapsulated therein, exposing the region corresponding to the n+ region on the silicon wafer.

[0073] (7) Boron deposition and diffusion: Boron deposition and diffusion are performed on the p+ region exposed on the silicon wafer. BBr3 gas is introduced into the furnace tube by chemical vapor deposition and the deposition and diffusion temperature is 950℃ to form the p+ region.

[0074] (8) Remove residual BSG and PSG glass layers: Clean the silicon wafer with a 35% hydrofluoric acid solution to remove residual BSG and PSG glass layers;

[0075] (9) Gap region grooving: A laser is used to groove the designed gap between the p+ region and the n+ region, remove the polysilicon and tunneling oxide layer in the trench, retain the silicon substrate, and form a gap region. The laser wavelength is 200nm, the power is ≥1W, the scanning speed is 5m / s, and the frequency is 2000 kHz.

[0076] (10) Deposit passivation layer and antireflection layer: Deposit aluminum oxide passivation layer and silicon nitride antireflection layer sequentially on the front and back sides of the silicon wafer; the aluminum oxide passivation layer has a thickness of 6 nm and the silicon nitride antireflection layer has a thickness of 70 nm.

[0077] (11) Screen-printed electrodes: Silver paste is printed on the p+ and n+ regions on the back of the silicon wafer using screen printing technology, and then sintered to form contact electrodes.

[0078] Example 3

[0079] A method for preparing a TBC battery includes the following steps:

[0080] (1) Silicon wafer pretreatment: Select an N-type silicon wafer substrate, clean and polish it to remove impurities and damaged layers from the surface;

[0081] (2) On the surface of the pretreated silicon wafer substrate, a tunneling oxide layer with a thickness of 3 nm and a polycrystalline silicon layer with a thickness of 250 nm are sequentially deposited on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD) technology.

[0082] (3) Sucrose mask printing: Prepare a 70% sucrose solution and use a screen printing machine to print the n+ region pattern on the polycrystalline silicon layer on the back of the silicon wafer. Dry at 80°C to dehydrate and carbonize the sucrose to form a solid carbon film pattern.

[0083] (4) Spraying alumina sol: Spray a layer of alumina sol evenly on the surface of the silicon wafer with solid carbon film pattern, and dry it at 60°C to allow the sol to initially solidify. The alumina area should be 2 micrometers larger than the sucrose mask area.

[0084] (5) Boron doping and high-temperature treatment: BBr3 gas was introduced into the furnace tube by chemical vapor deposition and then annealed at 950°C. At high temperature, the sucrose carbon film burned (C + O2 -> CO2), consuming the local oxygen in the area it covered, creating a reducing atmosphere below the area to protect the polycrystalline silicon / silicon below from oxidation; at the same time, boron in BSG diffused into the silicon in the non-carbon film covered area to form p+ region; the alumina sol layer was transformed into a brittle alumina layer and encapsulated the ash after carbon combustion.

[0085] (6) The silicon wafer after high-temperature treatment is sprayed with hot water at a temperature of 95°C to wash away the embrittled alumina layer and the carbon ash residue encapsulated therein, exposing the region corresponding to the n+ region on the silicon wafer.

[0086] (7) Phosphorus deposition and diffusion: Phosphorus deposition and diffusion are performed on the regions corresponding to the exposed n+ regions on the silicon wafer at a deposition and diffusion temperature of 500℃ to form n+ regions;

[0087] (8) Remove residual BSG and PSG glass layers: Clean the silicon wafer with a 35% hydrofluoric acid solution to remove residual BSG and PSG glass layers;

[0088] (9) Gap region trenching: Using mechanical tools, trenches are made at the design gap between the p+ region and the n+ region to remove the polysilicon and tunneling oxide layer in the trench, leaving the silicon substrate to form the Gap region;

[0089] (10) Deposit passivation layer and antireflection layer: Deposit aluminum oxide passivation layer and silicon nitride antireflection layer sequentially on the front and back sides of the silicon wafer; the aluminum oxide passivation layer has a thickness of 6 nm and the silicon nitride antireflection layer has a thickness of 70 nm.

[0090] (11) Screen-printed electrodes: Silver paste is printed on the p+ and n+ regions on the back of the silicon wafer using screen printing technology, and then sintered to form contact electrodes.

[0091] Comparative Example 1

[0092] A method for preparing a TBC battery includes the following steps:

[0093] (1) Polish the surface of the single-crystal silicon wafer on both sides;

[0094] (2) A 2.5 nm thick tunneling oxide layer is deposited on the back side of the silicon wafer using low-pressure chemical vapor deposition technology; then SiH4 reaction gas is introduced to deposit a 200 nm polycrystalline silicon layer on the surface of the tunneling oxide layer.

[0095] (3) The silicon wafer is placed in the furnace tube for boron doping to form a BSG layer with a thickness of 150 nm;

[0096] (4) Using a laser to create an N-type region and a gap region on the back of the silicon wafer;

[0097] (5) Etching is performed using a 1.5% sodium hydroxide alkaline solution;

[0098] (6) A 2.5 nm tunneling oxide layer and a 250 nm polycrystalline silicon layer were deposited using low-pressure chemical vapor deposition;

[0099] (7) Place the silicon wafer into the furnace tube for phosphorus doping;

[0100] (8) Use a laser to prepare a gap region on a silicon wafer with a wavelength of 200 nm, power ≥ 1 W, scanning speed of 5 m / s, and frequency of 2000 kHz, and then perform acid washing, water washing, and drying.

[0101] (9) A 0.5% NaOH solution was used to etch and prepare a textured surface on the front side of the silicon wafer;

[0102] (10) The silicon wafer is placed in 35% HF for 1200 seconds to remove the BSG and PSG layers; then RCA cleaning is performed to remove surface contaminants.

[0103] (11) A dense Al2O3 passivation layer with a thickness of 6 nm was deposited by ALD atomic layer deposition method, and an 80 nm SiNx antireflection layer was formed on the front and back of the silicon wafer by PECVD method.

[0104] (12) Print Ag paste on the back of the silicon wafer, dry and sinter it to obtain the back metal electrode.

[0105] The TBC cells prepared in Examples 1-3 and Comparative Example 1 were subjected to performance tests. The specific performance parameters were cell conversion efficiency Eta, open-circuit voltage Uoc, current Isc, and fill factor FF. The test results are shown in Table 1.

[0106] Table 1

[0107]

[0108] As shown in Table 1, comparing Examples 1-3 with Comparative Example 1, the TBC battery prepared by the present invention using a sucrose mask combined with alumina sol protection process outperforms the TBC battery prepared by the traditional multiple mask-etching process in all aspects of battery performance. Comparing Example 1 with Comparative Example 1, the TBC battery prepared within the preferred range of the present invention achieves a conversion efficiency of 26.23%, a significant improvement over Comparative Example 1 using the traditional process. Simultaneously, its open-circuit voltage and short-circuit current also show an improvement trend, indicating that the sucrose mask combined with alumina sol protection process of the present invention has a positive effect on enhancing passivation and reducing optical losses. The reason for this is that the local reducing atmosphere provided by the sucrose carbon film at high temperatures effectively suppresses oxidation of the polycrystalline silicon layer surface, ensuring the quality of the doped interface. At the same time, the temporary protection and easy removal characteristics of the alumina solvent layer avoid surface damage and impurity introduction caused by the traditional multiple mask-etching process, thereby reducing carrier recombination loss and improving the battery's fill factor and overall efficiency. Furthermore, the process of this invention requires only a single deposition of the tunnel oxide layer and the polycrystalline silicon layer, significantly reducing the number of high-temperature processes and mask usage, thereby lowering production costs, process complexity, and carrier recombination risk. Therefore, this invention not only offers superior battery efficiency but also possesses excellent process compatibility and scalable production potential.

[0109] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that, Includes the following steps: (1) Silicon wafer pretreatment; (2) A tunneling oxide layer and a polycrystalline silicon layer are deposited sequentially on the back side of the silicon wafer; (3) Sucrose mask printing: The second doped region pattern is printed on the polycrystalline silicon layer using sucrose solution, and the sucrose is dried to carbonize it and form a solid carbon film mask; (4) Spraying alumina sol: Spraying alumina sol onto the surface of the solid carbon film mask, drying and curing to form an alumina sol layer; (5) Deposition and high-temperature treatment of the first heavily doped region: The first doping source is deposited in the non-solid carbon film mask covering area of ​​the silicon wafer, and then annealed or diffused at high temperature to form the first heavily doped region with the opposite electrical properties to the second heavily doped region; at high temperature, the solid carbon film mask is burned, and the alumina sol layer is transformed into a brittle alumina protective layer. The ash of the burned solid carbon film mask is wrapped in the alumina protective layer. (6) Remove the alumina protective layer and carbon film ash to expose the silicon wafer surface corresponding to the second heavy doping region; (7) Deposition of the second heavily doped region: A second doping source is deposited and diffused on the silicon wafer surface corresponding to the second heavily doped region to form the second heavily doped region; (8) Remove residual BSG and PSG glass layers; (9) Gap area grooving: Grooves are made between the first heavy doping zone and the second heavy doping zone to form a gap area; (10) Deposition of passivation layer and antireflection layer; (11) Printed electrode.

2. The method for preparing a TBC battery according to claim 1, characterized in that, The sucrose concentration is 20-70%.

3. The method for preparing a TBC battery according to claim 1, characterized in that, In step (3), the drying temperature is 80~160℃.

4. The method for preparing a TBC battery according to claim 1, characterized in that, In step (4), the drying temperature is 60~150℃.

5. The method for preparing a TBC battery according to claim 1, characterized in that, In step (6), the silicon wafer is sprayed with hot water at 60~95℃ or immersed in acid to remove the alumina protective layer and carbon film ash.

6. The method for preparing a TBC battery according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 2~3nm, and the thickness of the polycrystalline silicon layer is 150nm~250nm.

7. The method for preparing a TBC battery according to claim 1, characterized in that, The BSG and PSG glass layers were removed by cleaning with an etching solution.

8. The method for preparing a TBC battery according to claim 1, characterized in that, In step (9), laser grooving or mechanical grooving is used.

9. The method for preparing a TBC battery according to claim 1, characterized in that, The passivation layer is AlO. x and SiN x A stacked passivation film; contact electrodes are printed in the first heavily doped region and the second heavily doped region respectively using screen printing technology.

10. A TBC battery, characterized in that, TBC batteries prepared using the preparation method described in any one of claims 1-9.

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