Light emitting diode, manufacturing method and light emitting device

Abstract

The invention provides a light-emitting diode, a manufacturing method and a light-emitting device.The light-emitting diode comprises a substrate, a buffer layer located on the upper surface of the substrate and a semiconductor lamination layer, and the semiconductor lamination layer sequentially comprises a first semiconductor layer, an active layer and a second semiconductor layer from bottom to top; at least part of the surface, not covered by the semiconductor lamination layer, of the buffer layer is arranged to be a coarsened structure. By arranging the coarsening structure on the surface of the buffer layer, the incident angle is randomized, the total reflection condition of light on a semiconductor / air interface is destroyed, more light rays escape from the side wall, the photoelectric conversion efficiency and / or luminance of the LED are / is improved, the coarsening structure is formed by means of hole defects generated in the growth process of the buffer layer, and the light emitting efficiency of the LED is improved. After the ISA process, the holes are expanded through corrosion to form a coarsening structure, so that an additional photoetching step is avoided, and the chip process is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a light emitting diode, a manufacturing method and a light emitting device. BACKGROUND

[0002] A light emitting diode (LED) is a kind of semiconductor device, and its basic structure includes a PN junction between a P-type semiconductor and an N-type semiconductor. When a forward voltage is applied to the LED, electrons and holes recombine at the junction of the PN junction, releasing energy in the form of photons, which form light radiation.

[0003] According to different light emitting wavelengths, light emitting diodes can be divided into red light LEDs, violet light LEDs, infrared light LEDs and ultraviolet light LEDs, etc. Ultraviolet light emitting diodes are widely used in medical treatment, plant lighting, disinfection and sterilization, air and water purification, etc. However, due to the internal total reflection loss of the traditional LED structure, the strong absorption loss of the epitaxial structure to ultraviolet light, the polarization characteristics of the ultraviolet LED chip and other factors, the photoelectric conversion efficiency of the current ultraviolet light LED is generally low, which seriously affects the light output efficiency of the ultraviolet light LED, further affects the product performance of the light emitting device, and restricts its large-scale industrialization and popularization and application.

[0004] Therefore, in the chip design and manufacturing process, it is urgent to provide an improved technical solution to the above-mentioned deficiencies in the prior art. SUMMARY

[0005] In view of the defects and deficiencies of the above prior art LED chip, the present application provides a light emitting diode, a manufacturing method and a light emitting device to improve the photoelectric conversion efficiency and / or luminous brightness of the LED.

[0006] In order to achieve the above-mentioned purpose and other related purposes, in a first aspect, the present application provides a light emitting diode, which at least comprises:

[0007] a substrate and a semiconductor stack located on the upper surface of the substrate, the semiconductor stack having a lower surface close to the substrate and an opposite upper surface, the semiconductor stack comprising a first semiconductor layer, an active layer and a second semiconductor layer in sequence from the lower surface to the upper surface;

[0008] a buffer layer located between the substrate and the semiconductor stack, at least part of the surface of the buffer layer not covered by the semiconductor stack is provided with a roughened structure.

[0009] In a second aspect, the present application further provides a manufacturing method of a light emitting diode, which at least comprises the following steps:

[0010] providing a substrate;

[0011] forming a buffer layer on the substrate, the buffer layer comprising AlN material;

[0012] forming a first semiconductor layer, an active layer and a second semiconductor layer on the substrate in sequence to obtain a semiconductor stack; etching the semiconductor stack to form a mesa structure;

[0013] performing an ISA process to divide a plurality of independent light emitting units, and removing edge portions of the light emitting units to expose the buffer layer to form a platform and a sidewall surrounding the semiconductor stack;

[0014] etching the exposed buffer layer to form a roughened structure, the roughened structure being a continuous irregular concave-convex rough surface.

[0015] In a third aspect, the present application also provides a light emitting device, which comprises:

[0016] a packaging substrate;

[0017] at least one light emitting diode arranged on a surface of the packaging substrate, the packaging substrate being electrically connected with an electrode structure of the light emitting diode; the light emitting diode being the light emitting diode provided in the above technical solution.

[0018] Compared with the prior art, the light emitting diode, the manufacturing method and the light emitting device provided by the present application have at least the following beneficial effects:

[0019] The light emitting diode provided by the present application has a roughened structure on the surface of the buffer layer, which randomizes the incident angle, destroys the total reflection condition of light at the semiconductor / air interface, reduces the total reflection loss, makes more light escape from the sidewall, and improves the light emitting efficiency and device brightness of the light emitting diode.

[0020] The manufacturing method of the light emitting diode provided by the present application takes advantage of the naturally existing pores in the AlN buffer layer during growth, expands these pores to form a roughened structure by etching after the ISA process, optimizes the light scattering effect, improves the light emitting performance, and avoids additional photolithography steps, thereby optimizing the chip manufacturing process.

[0021] In addition, the light emitting device provided by the present application comprises the light emitting diode provided in the above technical solution, and therefore has the same good technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a planar SEM image of a light emitting diode in the prior art;

[0023] Figure 2 is a structure schematic view of the light emitting diode provided in Embodiment One of the present application;

[0024] Figure 3 for Figure 2 A magnified view of part A;

[0025] Figure 4 A planar SEM image of a light-emitting diode with a coarsened structure;

[0026] Figure 5 This is a flowchart illustrating the fabrication process of the light-emitting diode provided in Embodiment 2 of this application;

[0027] Figure 6 This is a schematic diagram of the structure of the light-emitting device provided in this application.

[0028] List of reference numerals in the attached diagram:

[0029] 10. Substrate; 20. Buffer layer; 20a. Platform; 20b. Sidewall; 201. Roughened structure; 210. Low-temperature buffer layer; 220. High-temperature buffer layer;

[0030] 30. Semiconductor stack; 310. First semiconductor layer; 320. Active layer; 330. Second semiconductor layer;

[0031] 40. Transparent conductive layer; 510. First contact electrode; 520. Second contact electrode; 60. Insulating layer; 710. First pad; 720. Second pad;

[0032] OP1, First opening; OP2, Second opening;

[0033] 101. Packaging substrate; 102. Light-emitting element. Detailed Implementation

[0034] UVC (ultraviolet light) epitaxy requires the growth of an AlN buffer layer on a flat sapphire substrate. Due to the characteristics of AlN, its vertical growth rate is relatively fast. After the bottom layer growth is completed, small pores will form in the AlN layer. During LED chip fabrication, these pores will be exposed after the ISA (Installation and Separation) process. (See [link to documentation]). Figure 1 , Figure 1 The image shows a planar SEM image of a light-emitting diode in the prior art. Several pits exposed on the surface of the layer can be clearly seen in the image. The pits are discontinuous and there are surface platforms of the AlN layer between the pits. The above-mentioned structural defects cause light to be confined inside the device due to total internal reflection or to be absorbed and lost by the pits.

[0035] Based on the background technology and the aforementioned technical deficiencies, this application provides a light-emitting diode (LED) to effectively solve or improve the above-mentioned technical problems. The LED provided in this application includes at least:

[0036] A substrate and a semiconductor stack located on the upper surface of the substrate, the semiconductor stack having a lower surface near the substrate and an opposite upper surface, the semiconductor stack comprising a first semiconductor layer, an active layer and a second semiconductor layer sequentially from the lower surface to the upper surface;

[0037] A buffer layer is located between the substrate and the semiconductor stack, wherein at least a portion of the surface of the buffer layer not covered by the semiconductor stack is configured with a roughened structure.

[0038] By adopting the above technical solution, a roughened structure is provided on at least part of the surface of the buffer layer, which can effectively increase the reflection and scattering of light, allowing more light to escape from the chip, thereby improving the brightness of the light-emitting diode and improving the light extraction efficiency.

[0039] In some embodiments, the roughened structure is a continuous, irregularly uneven rough surface. This irregularly uneven rough surface can prevent total internal reflection, further enhancing the light scattering effect, making the light field distribution more uniform, and improving the uniformity of the light emission space.

[0040] In some embodiments, the buffer layer comprises AlN material, and the thickness of the buffer layer is between 1.0 μm and 10.0 μm. Selecting an AlN material of suitable thickness as the buffer layer provides sufficient buffering effect to meet the requirements of lattice matching and thermal matching, without significantly adversely affecting the optical and electrical performance of the chip, thus ensuring the overall performance of the chip.

[0041] In some embodiments, the semiconductor stack is disposed on the buffer layer, and the horizontal projection of the semiconductor stack lies within the horizontal projection range of the buffer layer, so that the buffer layer has a platform and sidewalls surrounding the semiconductor stack; wherein, the roughening structure is disposed on the surface of the platform and / or the sidewalls. Disposing the roughening structure on the exposed platform and / or the sidewall surface of the buffer layer increases the light reflection and scattering area, improves the lateral light extraction rate, and further enhances the brightness of the light-emitting diode.

[0042] In some embodiments, the roughened surface of the platform along the center-to-edge direction of the light-emitting diode has a width d, 2.0 μm ≤ d ≤ 10.0 μm. This width depends on the location and size of the cut track and the size of the light-emitting area of ​​the light-emitting element.

[0043] In some embodiments, the roughened surface of the sidewall along the thickness direction of the light-emitting diode has a height h, where 1.0 μm ≤ h ≤ 10.0 μm. This height depends on the thickness of the buffer layer.

[0044] In some embodiments, the roughness of the roughened structure is between 3.0 nm and 5.0 μm.

[0045] In some embodiments, the depth of the roughened structure is between 0.1 μm and 7.0 μm. Suitable roughness and pore depth are used to achieve good scattering effects and ensure the buffer layer has good structural strength.

[0046] In some embodiments, the distribution density of the pores in the coarsened structure in the buffer layer is between 1 × 10⁻⁶. 4 / cm 2 ~9×10 7 / cm 2 A suitable pore density can create an appropriate amount of roughness on the surface of the buffer layer, ensuring sufficient reflection and scattering effects while avoiding excessive pore density that could damage the buffer layer structure and cause excessive scattering and absorption of light.

[0047] In some embodiments, the buffer layer comprises a low-temperature buffer layer and a high-temperature buffer layer from bottom to top, and the roughening structure is disposed on the platform of the high-temperature buffer layer and / or the sidewall surface of the high-temperature buffer layer. By providing the low-temperature buffer layer and the high-temperature buffer layer, the epitaxial quality is improved while retaining the roughening capability.

[0048] In some embodiments, a transparent conductive layer is also included, which is located above the second semiconductor layer. The transparent conductive layer can improve the conductivity and transparency of the electrode, and reduce the absorption and blocking of light by the electrode.

[0049] In some implementations, it also includes:

[0050] The first contact electrode is located on the first semiconductor layer and is electrically connected to the first semiconductor layer;

[0051] The second contact electrode is located above the transparent conductive layer and is electrically connected to the second semiconductor layer.

[0052] In some implementations, it also includes:

[0053] An insulating layer is located above and on the sidewalls of the semiconductor stack, and has a first opening and a second opening, wherein the first opening is located above the first semiconductor layer and the second opening is located above the second semiconductor layer;

[0054] The first pad is electrically connected to the first semiconductor layer through the first opening;

[0055] The second pad is electrically connected to the second semiconductor layer through the second opening.

[0056] This application also provides a method for manufacturing a light-emitting diode, which includes at least the following steps:

[0057] Provide a substrate;

[0058] A buffer layer is formed on the substrate, the buffer layer comprising AlN material;

[0059] A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially formed on the substrate to obtain a semiconductor stack; the semiconductor stack is etched to form a mesa structure.

[0060] The ISA process is performed to divide the light-emitting units into several independent light-emitting units, and the edge portions of the light-emitting units are removed so that the buffer layer exposes the platform and sidewalls surrounding the semiconductor stack.

[0061] The exposed buffer layer is etched to form a roughened structure, which is a continuous, random, uneven rough surface. Utilizing the voids and defects generated during the growth of the AlN buffer layer, etching expands these voids to form a rough surface, disrupting the total internal reflection condition at the semiconductor / air interface, reducing the total internal reflection ratio, and allowing more light to escape from the sidewalls, thus improving the brightness of the LED. Furthermore, this method uses the natural voids exposed after ISA as etching starting points, forming the roughened structure in one step, avoiding additional photolithography, and simplifying the chip manufacturing process.

[0062] In some embodiments, the etching solution is at least one of TMAH solution, KOH solution, and NaOH solution. A suitable etching solution is selected as needed to control the morphology and size of the coarsened structure.

[0063] In some embodiments, the exposed buffer layer is partially or completely immersed in a 40%–50% KOH solution for chemical etching at a temperature between 35°C and 65°C for a time between 1 min and 10 min, to form a roughened structure on the platform and / or sidewalls of the buffer layer. By defining the etching process parameters, the etching process can be precisely controlled to form a high-quality roughened structure.

[0064] In some embodiments, the light-emitting wavelength of the light-emitting diode is between 200 nm and 420 nm. This method is particularly suitable for improving the light extraction efficiency of ultraviolet LEDs.

[0065] This application also provides a light-emitting device, the light-emitting device comprising:

[0066] Packaging substrate;

[0067] At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode provided by the above technical solution.

[0068] The following embodiments, namely Embodiments 1 to 3, illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0069] The composition and dopants of each layer in the semiconductor laser element described in this application can be analyzed using any suitable method, such as secondary ion mass spectrometry (SIMS). The thickness of each layer in the semiconductor laser element described in this application can be analyzed using any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM), in conjunction with, for example, the depth positions of each layer on a SIMS image.

[0070] Example 1:

[0071] See Figures 2 to 4 This embodiment provides a light-emitting diode (LED) including a substrate 10, a buffer layer 20 located on the substrate 10, and a semiconductor stack 30. The semiconductor stack 30 has a lower surface near the substrate 10 and an opposite upper surface. From the lower surface to the upper surface, the semiconductor stack 30 sequentially includes a first semiconductor layer 310, an active layer 320, and a second semiconductor layer 330. The buffer layer 20, located between the substrate 10 and the semiconductor stack 30, is made of AlN material and serves to relieve stress, reducing lattice mismatch between the substrate 10 and the first semiconductor layer 310 formed thereon, thereby improving epitaxial quality. At least a portion of the surface of the buffer layer 20 not covered by the semiconductor stack 30 is configured as a roughened structure 201. This roughened structure 201 can effectively increase light reflection and scattering, allowing more light to escape from the chip, thereby improving the brightness of the LED and enhancing light extraction efficiency. Because ultraviolet LEDs suffer from severe internal light loss, a large number of photons undergo total internal reflection inside the chip and cannot be effectively emitted to the outside of the chip, resulting in low light emission efficiency. Therefore, by setting a roughened structure 201 in the buffer layer 20, its light emission efficiency can be effectively improved. The technical solution provided in this embodiment is particularly effective for ultraviolet LEDs, that is, light-emitting diodes with emission wavelengths between 200nm and 420nm.

[0072] See Figure 2The substrate 10 can be a growth substrate, including but not limited to nitride semiconductors, SiC, or sapphire substrates. Optionally, the substrate 10 is a sapphire substrate, which has extremely high chemical stability, is not easily corroded by chemicals such as acids and alkalis, and has good thermal conductivity and stable electrical insulation properties, as well as high transparency over a wide wavelength range from ultraviolet to infrared. Optionally, the substrate 10 is a surface-patterned sapphire substrate. Further, the thickness of the substrate 10 is between 40 μm and 500 μm.

[0073] See also Figure 2 A buffer layer 20 is disposed on the substrate 10, and the thickness of the buffer layer 20 is between 1.0 μm and 10.0 μm. As an example, the thickness of the buffer layer 20 can be 2.0 μm, 4.0 μm, 6.0 μm, or 8.0 μm. If the buffer layer 20 is too thin, for example, less than 1.0 μm, it cannot provide good stress adaptation. If its thickness is too large, for example, greater than 10.0 μm, the accumulation of internal structural stress will increase the risk of epitaxial layer cracking, and the resulting void defects will also increase, leading to a decrease in light extraction efficiency. By depositing a buffer layer 20 of appropriate thickness, the defect density, structural stress, and light extraction efficiency can be balanced.

[0074] See also Figure 2 The buffer layer 20 includes a low-temperature buffer layer 210 (MT-AlN) and a high-temperature buffer layer 220 (HT-AlN) from bottom to top. By setting the low-temperature buffer layer 210 and the high-temperature buffer layer 220, the epitaxial quality is improved while the roughening ability is retained.

[0075] Furthermore, the thickness of the low-temperature buffer layer 210 is between 10nm and 100nm. As a nucleation layer, it has low internal stress and wets with the sapphire substrate, thus better realizing the structural transition between the substrate 10 and the epitaxial structure. At the same time, it can also serve as a good transition between the substrate 10 and the high-temperature buffer layer 220.

[0076] Furthermore, the high-temperature buffer layer 220 above the low-temperature buffer layer 210 has a smoother growth surface. Therefore, the upper surface of the high-temperature buffer layer 220 can provide a better process plane for epitaxial growth, resulting in an epitaxial structure with higher crystal quality. The thickness of the high-temperature buffer layer 220 is between 0.5 μm and 10 μm. As a dislocation blocking layer, it can effectively reduce defect density. However, due to the characteristics of AlN material, the longitudinal growth rate is relatively fast. After the bottom layer growth is completed, small pores will be formed in the high-temperature buffer layer 220. By performing surface treatment on the buffer layer 20, such as chemical etching, the existing small pores are used as a breakthrough point to form a roughened surface morphology. The specific structure is as follows: Figure 3 As shown, comparison Figure 1 and Figure 3It can be clearly seen that the original small holes are corroded to form a roughened structure 201. This roughened structure 201 can increase the reflection of internal light and improve the brightness of LED output.

[0077] In some embodiments, since the thickness of the low-temperature buffer layer 210 is much smaller than that of the high-temperature buffer layer 220, and the low-temperature buffer layer 210 has fewer natural defects and pores, the roughening structure 201 is only disposed on the surface of the platform 20a and its sidewall 20b of the high-temperature buffer layer 220. Furthermore, the high-temperature AlN layer has high crystal quality, and its surface roughening does not affect the stress buffering effect of the underlying low-temperature layer. Roughening the platform 20a of the high-temperature buffer layer 220 allows it to better reflect the light from the underlying layer. Roughening its sidewall 20b can reduce lateral total internal reflection loss and improve the brightness of the emitted light. Disposing the roughening structure 201 on the surface of the platform 20a and sidewall 20b of the high-temperature buffer layer 220 provides sufficient buffering effect to meet the requirements of lattice matching and thermal matching, without significantly adversely affecting the optical and electrical performance of the chip, thus ensuring the overall performance of the chip.

[0078] See also Figure 2 The semiconductor stack 30 is disposed on the buffer layer 20, and the horizontal projection of the semiconductor stack 30 is located within the horizontal projection range of the buffer layer 20, so that the buffer layer 20 has a platform 20a and a sidewall 20b surrounding the semiconductor stack 30. Adjacent light-emitting units are electrically isolated from each other through a groove between the substrate 10 and the buffer layer 20.

[0079] In some embodiments, the roughened structure 201 is disposed on the surface of the platform 20a. The roughened structure 201 on the surface of the platform 20a is a continuous, randomly uneven rough surface. The randomly uneven rough surface can prevent total internal reflection of light, further enhancing the light scattering effect, making the light field distribution more uniform, and improving the uniformity of the light emission space. Furthermore, the entire upper surface of the platform 20a of the buffer layer 20 is set as the roughened structure 201, that is, there is no flat surface in the area of ​​the roughened structure 201, so as to maximize the utilization of the platform structure and improve the light emission efficiency. Furthermore, along the direction from the center to the edge of the light-emitting diode, the roughened surface on the platform 20a has a width d, 2.0μm≤d≤10.0μm. It is understood that this width d depends on the position and size of the cutting channel and the size of the light-emitting area of ​​the light-emitting element. If the width is too large, it will lead to a reduction in the light-emitting area, affecting the brightness; or it will lead to insufficient insulation performance between the light-emitting elements, affecting the product yield. As an example, the width d can be 4.0 μm, 5.0 μm, 6.0 μm, or 8.0 μm. When the entire upper surface of the platform 20a of the buffer layer 20 is set as the roughened structure 201, the width of the roughened structure 201 is consistent with the width of the platform 20a. Further, the roughness of the roughened structure 201 on the surface of the platform 20a is between 3.0 nm and 5.0 μm, and the depth of the uneven pores is between 0.1 μm and 7.0 μm. If the roughness is too small or the pore depth is too shallow, for example, the roughness is less than 3 nm or the pore depth is less than 0.1 μm, the surface roughening effect will be negligible, and the effect on light reflection will be minimal, failing to improve brightness. If the roughness is too large or the pore depth is too deep, the mechanical strength of the buffer layer 20 may decrease, making it prone to chipping during subsequent core cutting, causing damage to the light-emitting unit structure. Experiments have verified that when the roughness and hole depth of the roughened structure 201 are within the aforementioned parameter range, the chip brightness improvement is most significant, and the buffer layer 20 can be ensured to have good structural strength. Furthermore, the roughness of the roughened structure 201 located on the surface of platform 20a is between 4.0 nm and 1.0 μm, and the hole depth of the uneven shape is between 2.0 μm and 5.0 μm.

[0080] In some embodiments, the roughening structure 201 is disposed on the surface of the sidewall 20b, and the roughening structure 201 on the surface of the sidewall 20b can also be a continuous, random, uneven rough surface. Further, along the thickness direction of the light-emitting diode, the rough surface on the sidewall 20b has a height h, 1.0 μm ≤ h ≤ 10.0 μm. It is understood that this height depends on the thickness of the buffer layer 20. As an example, the height h can be 2.0 μm, 4.0 μm, 6.0 μm, or 8.0 μm. When the entire surface of the sidewall 20b of the buffer layer 20 is set as the roughening structure 201, the height of the roughening structure 201 is consistent with the thickness of the buffer layer 20. Further, the same applies to the roughening structure 201 located on the surface of the platform 20a. The roughness of the roughening structure 201 on the surface of the sidewall 20b is also between 3.0 nm and 5.0 μm, and the depth of the uneven pores is between 0.1 μm and 7.0 μm. Furthermore, the roughness of the roughened structure 201 on the surface of sidewall 20b is between 4.0 nm and 1.0 μm, and the depth of the convex-concave pores is between 2.0 μm and 5.0 μm. Furthermore, the surface roughness parameters of the sidewall 20b surface are the same as those of the platform 20a surface to simplify the process flow.

[0081] In some embodiments, the roughening structure 201 is simultaneously disposed on the surfaces of both the platform 20a and the sidewall 20b. The roughening structure 201 on the platform 20a and the roughening structure 201 on the sidewall 20b work together to increase light reflection at different locations, thereby improving the overall brightness of the LED. Furthermore, the roughening structure 201 completely covers both the platform 20a and the sidewall 20b; that is, the exposed areas of the buffer layer 20 are all provided with the roughening structure 201. This maximizes the utilization of the natural pores and defects in the buffer layer 20, while increasing the light reflection and scattering area, improving the lateral light extraction rate, and further enhancing the brightness of the LED.

[0082] In some embodiments, the distribution density of the pores in the roughened structure 201 in the buffer layer 20 is between 1 × 10⁻⁶. 4 / cm 2 ~9×10 7 / cm 2 The distribution density specifically refers to the pore distribution density on the surface of the buffer layer 20. A suitable pore distribution density allows the surface of the buffer layer to form an appropriate amount of roughness, ensuring sufficient reflection and scattering effects while avoiding excessive pore density that could damage the buffer layer structure and cause excessive scattering and absorption of light. Furthermore, the pore distribution density on the platform 20a and sidewall 20b of the buffer layer 20 is the same to achieve a uniform and reliable light reflection effect. As an example, the pore distribution density on the platform 20a and sidewall 20b can be between 1 × 10⁻⁶. 5 / cm 2 ~9×10 6 / cm2 between.

[0083] See also Figure 2 A semiconductor stack 30 is disposed on the buffer layer 20. The semiconductor stack 30 includes a first semiconductor layer 310, an active layer 320, and a second semiconductor layer 330 stacked sequentially from bottom to top. The overall film thickness of the semiconductor stack 30 is between 2 μm and 10 μm. In some embodiments, the first semiconductor layer 310, the active layer 320, and the second semiconductor layer 330 may be formed of a group III gallium nitride series compound semiconductor, such as GaN, AlN, InGaN, AlGaN, InAlGaN, and at least one of the above materials. The first semiconductor layer 310 is an electron-providing layer and can be formed by implanting an n-type dopant (e.g., Si, Ge, Se, Te, C, etc.). The second semiconductor layer 330 is a hole-providing layer and can be formed by implanting a p-type dopant (e.g., Mg, Zn, Be, Ca, Sr, Ba, etc.). The active layer 320 is a layer in which electrons and holes recombine to output light of a predetermined wavelength. It can be formed from a multilayer semiconductor thin film with alternating single-layer or multi-layer quantum well structures of potential well layers and barrier layers. The active layer 320 is selected with different material compositions or ratios depending on the wavelength of the output light. It can use group III to group V compound semiconductor materials, such as at least one of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs(InGaAs) / AlGaAs, or GaP(InGaP) / AlGaP. After MESA and ISA processes, the edge portion of the first semiconductor layer 310 is etched away, exposing the high-temperature buffer layer 220 to the platform 20a and sidewalls 20b surrounding the semiconductor stack 30.

[0084] See also Figure 2 A transparent conductive layer 40 is formed on the semiconductor stack 30 to reduce light absorption and improve light extraction efficiency. Since the current spreading capability of the second semiconductor layer 330 is usually lower than that of the first semiconductor layer 310, a current spreading layer 300 is placed on the upper surface of the second semiconductor layer 330 to achieve higher current injection efficiency. The transparent conductive layer 40 is formed above the second semiconductor layer 330, and its material can be ITO, InO, SnO, CTO, AZO, ATO, GZO, ZnO, GaP, or a combination thereof. The thickness of the transparent conductive layer 40 is between 5 nm and 50 nm. Further, the material of the transparent conductive layer 40 is ITO, AZO, or GZO. Transparent conductive materials such as ITO can effectively conduct current while maintaining high optical transmittance and reducing light loss. Its thickness is between 8 nm and 20 nm to balance conductivity and transmittance. As an example, the thickness of the transparent conductive layer 40 is 10 nm, 12 nm, 15 nm, or 18 nm.

[0085] See also Figure 2 A first contact electrode 510 is formed on the first semiconductor layer 310. The material of this electrode may include any one or a combination of two or more of Pd, Pt, Ni, Au, Ti, W, Cr, Cu, Ag, Zn, Sn, In, Al, Ir, or Rh. The first contact electrode 510 is electrically connected to the first semiconductor layer 310. A second contact electrode 520 is formed on the transparent conductive layer 40. The material of this second contact electrode 520 may be the same as that of the first contact electrode 510. The second contact electrode 520 is electrically connected to the second semiconductor layer 330.

[0086] See also Figure 2 An insulating layer 60 is formed above and on the sidewalls of the first contact electrode 510, the second contact electrode 520, and the semiconductor stack 30. The insulating layer 60 can be an insulating material containing one or more of SiO2, SiN, Al2O3, and ZrO2, for example, a single-layer insulating material layer or a DBR structure, to reflect light of different specific wavelengths. Further, the film thickness of the insulating layer 60 is between 1.0 μm and 10.0 μm. The insulating layer 60 has a first opening OP1 and a second opening OP2, wherein the first opening OP1 is located above the first semiconductor layer 310, and the second opening OP2 is located above the second semiconductor layer 330, so as to realize the electrical connection between the first semiconductor layer 310 and the second semiconductor layer 330 and the pad, respectively.

[0087] See also Figure 2 A pad electrode is disposed on the insulating layer 60, including a first pad 710 and a second pad 720. The first pad 710 and the second pad 720 may be made of the same material, including a single film of a single material or an alloy of at least two materials selected from Au, Sn, Ni, Pb, Ag, In, Cr, Ge, Si, Ti, W and Pt, or a multilayer structure including a combination of them. The first pad 710 is formed in the first opening OP1 and is in contact with the first contact electrode 510. The second pad 720 is formed in the second opening OP2 and is electrically connected to the second contact electrode 520.

[0088] The light-emitting diode provided in this embodiment can have a polygonal shape, such as a triangle, hexagon, rectangle, or square. The size of the light-emitting diode can be, for example, a square shape or a rectangular shape of similar size, such as 300μm×100μm, 300μm×120μm, 300μm×150μm, 300μm×200μm, 600μm×200μm, 600μm×150μm, 600μm×120μm, and 1200μm×200μm, but is not particularly limited thereto.

[0089] Example 2:

[0090] See Figure 5 This embodiment provides a method for manufacturing a light-emitting diode, which includes the following steps:

[0091] S10: A substrate 10 is provided. The substrate 10 can be a sapphire substrate, and its surface is etched to obtain a patterned sapphire substrate. The thickness of the substrate 10 is between 40μm and 500μm, but not limited to this. The etching method includes, for example, using dry etching to create protrusions without a fixed slope, or using wet etching to create protrusions with a certain slope, so that light is reflected multiple times and the light extraction efficiency of the LED is improved.

[0092] S20: A buffer layer 20 is formed on the substrate 10. The buffer layer 20 contains AlN material and its thickness is between 1.0 μm and 10.0 μm, but not limited to this. The buffer layer 20 prevents impurities on the surface of the substrate 10 from adversely affecting epitaxial growth. The buffer layer 20 is formed on the substrate 10 by methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating. It should be noted that other semiconductor layers to be epitaxially grown can also be formed using the same method. When doping each layer into p-type or n-type, it is sufficient to use a dopant source gas that matches the desired dopant type; this will not be elaborated further.

[0093] Specifically, the steps for forming the buffer layer 20 include:

[0094] S21: A low-temperature AlN layer is formed on the substrate 10, with a deposition thickness between 10 nm and 100 nm and a process temperature between 500 °C and 800 °C. It serves as a nucleation layer and is immersed in the sapphire substrate, thus better realizing the transition between the substrate 10 and the epitaxial structure.

[0095] S22: A high-temperature AlN layer is formed on top of a low-temperature AlN layer, with a deposition thickness between 0.5 μm and 10 μm, and a process temperature between 800℃ and 1200℃. For example... Figure 1 As shown, due to the characteristics of AlN material, the longitudinal growth rate of AlN at high temperature is relatively fast. After the bottom layer growth is completed, small pores will gradually form as the material is deposited. These pores can serve as the etching starting point for subsequent processes, which is conducive to forming a roughened surface to improve the light emission angle and the light emission brightness of the LED.

[0096] S30: A first semiconductor layer 310, an active layer 320, and a second semiconductor layer 330 are sequentially formed on the buffer layer 20 to obtain a semiconductor stack 30. Subsequently, the semiconductor stack 30 is etched to form a mesa structure, specifically by removing portions of the second semiconductor layer 330 and the active layer 320 to expose a portion of the surface of the first semiconductor layer 310. This mesa structure includes two parts: a mesa exposing the second semiconductor layer 330 and a mesa exposing the first semiconductor layer 310.

[0097] The overall thickness of the semiconductor stack 30 is between 2 μm and 10 μm, but not limited to this. The first semiconductor layer 310 is an electron-providing layer, which can be formed by implanting n-type dopant, and its thickness is between 0.5 μm and 5 μm, but not limited to this. The active layer 320 has a thickness between 3 nm and 2000 nm, but not limited to this. The second semiconductor layer 330 is a hole-providing layer, which can be formed by implanting p-type dopant, and its thickness is between 0.1 μm and 5 μm, but not limited to this.

[0098] In an optional embodiment, the semiconductor stack 30 may be provided with other semiconductor functional layers, such as electron blocking layers or spacer layers, as needed between the first semiconductor layer 310 and the active layer 320 and between the active layer 320 and the second semiconductor layer 330.

[0099] S40: Perform the ISA process to divide the area into several independent light-emitting units and remove the edge portion of each light-emitting unit so that the buffer layer 20 exposes the platform and sidewalls surrounding the semiconductor stack 30. Specifically, after the ISA process, the edge portion of the first semiconductor layer 310 is etched away, exposing the platform 20a and sidewalls 20b surrounding the semiconductor stack 30 of the buffer layer 20 (high-temperature buffer layer 220), and also exposing the small hole defects generated in the high-temperature buffer layer 220 during the AlN material growth process.

[0100] S50: The exposed buffer layer 20 is immersed in a 40%–50% (mass fraction) alkaline solution for chemical etching. The process temperature is between 35℃ and 65℃, and the process time is between 1 min and 10 min, to form a roughened structure 201 on the platform 20a and sidewall 20b of the buffer layer 20. The resulting roughened structure 201 is a continuous, random, uneven rough surface. By limiting the etching process parameters, the etching process can be precisely controlled to form a high-quality roughened structure 201.

[0101] As an example, the exposed buffer layer 20 was completely immersed in a 40% TMAH (tetramethylammonium hydroxide) solution for chemical etching at a temperature of 35°C for 10 minutes. The natural pores of the buffer layer 20 itself were used as the etching center to obtain a random roughened surface with a roughness between 4 nm and 5 nm.

[0102] As an example, the exposed buffer layer 20 was completely immersed in a 40% TMAH solution for chemical etching. The chemical etching was carried out at a temperature of 45°C for 10 minutes. The natural pores of the buffer layer 20 itself were used as the etching center to obtain a random roughened surface with a roughness between 6 nm and 7 nm.

[0103] As an example, the exposed buffer layer 20 was completely immersed in a 45% KOH (potassium hydroxide) solution for chemical etching. The chemical etching was carried out at a temperature of 50°C for 5 minutes. The natural pores of the buffer layer 20 itself were used as the etching center to obtain a random roughened surface with a roughness between 4 nm and 5 nm.

[0104] As an example, the exposed buffer layer 20 was completely immersed in a 50% KOH solution for chemical etching at a temperature of 64°C for 5 minutes. Using the natural pores of the buffer layer 20 itself as the etching center, a random roughened surface with a roughness between 3 nm and 4 nm was obtained.

[0105] As an example, the exposed buffer layer 20 was completely immersed in a 50% NaOH (sodium hydroxide) solution for chemical etching at a temperature of 45°C for 1 minute. Using the natural pores of the buffer layer 20 itself as the etching center, a random roughened surface with a roughness between 3 nm and 5 nm was obtained.

[0106] As an example, the exposed buffer layer 20 was completely immersed in a 40% TMAH solution for chemical etching at a temperature of 35°C for 10 minutes. The natural pores of the buffer layer 20 itself were used as the etching center to obtain a random roughened surface with a roughness between 4 nm and 5 nm.

[0107] The above-mentioned alkaline solution of suitable concentration can be prepared by mixing alkaline raw materials with deionized water in the appropriate proportion.

[0108] The principle of the aforementioned chemical etching process is as follows: Utilizing the pores and defects generated during the growth of the buffer layer AlN material, etching expands these pores to form a rough surface, disrupting the total internal reflection conditions at the semiconductor / air interface, reducing the total internal reflection ratio, and allowing more light to escape from the sidewalls, thus improving the brightness of the LED. Furthermore, this method uses the natural pores exposed after ISA as the etching starting point, enabling the formation of the roughened structure 201 in one step, avoiding additional photolithography and simplifying the chip manufacturing process.

[0109] S60: A transparent conductive layer 40 is formed on the semiconductor stack 30, for example, by depositing an 8nm to 20nm thick ITO material by physical vapor deposition or chemical vapor deposition to improve the current transmission performance on the P side.

[0110] S70: Forming contact electrodes on the semiconductor stack 30 by physical vapor deposition or magnetron sputtering, specifically including the steps of forming a first contact electrode 510 on the first semiconductor layer 310 and forming a second contact electrode 520 on the transparent conductive layer 40. The first contact electrode 510 and the second contact electrode 520 can be made of the same material, including any one or a combination of two or more of Pd, Pt, Ni, Au, Ti, W, Cr, Cu, Ag, Zn, Sn, In, Al, Ir or Rh.

[0111] S80: An insulating layer 60 is further formed using physical vapor deposition or chemical vapor deposition. The insulating layer 60 can be an insulating material containing one or more of SiO2, SiN, Al2O3, and ZrO2, such as a single-layer insulating material layer or a DBR structure, to reflect light of different specific wavelengths. Subsequently, the insulating layer 60 is patterned by photolithography and etching. The insulating layer 60 covering the first contact electrode 510 is partially etched away to form the first opening OP1, and the insulating layer 60 covering the second contact electrode 520 is partially etched away to form the second opening OP2, so as to facilitate the subsequent formation of the pad electrode.

[0112] S90: A first pad 710 and a second pad 720 are formed on the insulating layer 60 by electroplating, physical vapor deposition, or chemical vapor deposition. The first pad 710 and the second pad 720 may be made of the same material, including a single film of a single material or an alloy of at least two materials selected from Au, Sn, Ni, Pb, Ag, In, Cr, Ge, Si, Ti, W, and Pt, or a multilayer structure including a combination of them. The first pad 710 is formed in the first opening OP1 and is in contact with the first contact electrode 510, and the second pad 720 is formed in the second opening OP2 and is electrically connected to the second contact electrode 520.

[0113] Example 3:

[0114] See Figure 6 This embodiment provides a light-emitting device, which is a flip-chip LED product, including a packaging substrate 101; at least one light-emitting element 102 disposed on the surface of the packaging substrate 101, and the packaging substrate 101 is electrically connected to the electrode structure of the light-emitting diode. The light-emitting element 102 is the light-emitting diode provided in Embodiment 1 of this application, or a light-emitting diode manufactured by the manufacturing method of Embodiment 2 of this application. The light-emitting element 102 is electrically connected to the packaging substrate 101 through a first pad 710 and a second pad 720.

[0115] In summary, the light-emitting diode, manufacturing method, and light-emitting device provided in this application effectively overcome the various shortcomings of the prior art and have high industrial application value.

[0116] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A light-emitting diode, characterized in that, At least including: A substrate and a semiconductor stack located on the upper surface of the substrate, the semiconductor stack having a lower surface near the substrate and an opposite upper surface, the semiconductor stack comprising a first semiconductor layer, an active layer and a second semiconductor layer sequentially from the lower surface to the upper surface; A buffer layer is located between the substrate and the semiconductor stack, wherein at least a portion of the surface of the buffer layer not covered by the semiconductor stack is configured with a roughened structure.

2. The light-emitting diode according to claim 1, characterized in that, The roughened structure is a continuous, random, uneven rough surface.

3. The light-emitting diode according to claim 1, characterized in that, The buffer layer comprises AlN material, and the thickness of the buffer layer is between 1.0 μm and 10.0 μm.

4. The light-emitting diode according to claim 1, characterized in that, The semiconductor stack is disposed on the buffer layer, and the horizontal projection of the semiconductor stack is located within the horizontal projection range of the buffer layer, so that the buffer layer has a platform and sidewalls surrounding the semiconductor stack; wherein, the roughened structure is disposed on the surface of the platform and / or the sidewalls.

5. The light-emitting diode according to claim 4, characterized in that, Along the direction from the center to the edge of the light-emitting diode, the rough surface located on the platform has a width d, 2.0 μm ≤ d ≤ 10.0 μm.

6. The light-emitting diode according to claim 4, characterized in that, Along the thickness direction of the light-emitting diode, the rough surface located on the sidewall has a height h, 1.0 μm ≤ h ≤ 10.0 μm.

7. The light-emitting diode according to claim 4, characterized in that, The roughness of the roughened structure is between 3.0 nm and 5.0 μm.

8. The light-emitting diode according to claim 4, characterized in that, The depth of the coarsened structure is between 0.1 μm and 7.0 μm.

9. The light-emitting diode according to claim 1, characterized in that, The density of the pores in the coarsened structure within the buffer layer is between 1×10⁻⁶. 4 / cm 2 ~9×10 7 / cm 2 .

10. The light-emitting diode according to claim 1, characterized in that, The buffer layer comprises a low-temperature buffer layer and a high-temperature buffer layer from bottom to top, and the roughened structure is disposed on the platform of the high-temperature buffer layer and / or the sidewall surface of the high-temperature buffer layer.

11. A method for manufacturing a light-emitting diode, characterized in that, At least the following steps are included: Provide a substrate; A buffer layer is formed on the substrate, the buffer layer comprising AlN material; A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially formed on the substrate to obtain a semiconductor stack. The semiconductor stack is etched to form a mesa structure; The ISA process is performed to divide the light-emitting units into several independent light-emitting units, and the edge portions of the light-emitting units are removed so that the buffer layer exposes the platform and sidewalls surrounding the semiconductor stack. The exposed buffer layer is etched to form a roughened structure, which is a continuous, random, uneven rough surface.

12. The method for manufacturing a light-emitting diode according to claim 11, characterized in that, The exposed buffer layer is partially or completely immersed in a 40% to 50% KOH solution for chemical etching at a temperature between 35°C and 65°C for a time between 1 min and 10 min, in order to form a roughened structure on the platform and / or sidewalls of the buffer layer.

13. A light-emitting device, characterized in that, The light-emitting device includes: Packaging substrate; At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode according to any one of claims 1 to 10.

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