Semiconductor device, power conversion device, semiconductor device manufacturing method, and power conversion device manufacturing method

Abstract

The purpose of the present invention is to suppress melting of an electrode even when a high voltage is applied. This semiconductor device is provided with: at least one first groove formed from the upper surface of a base region to the inside of a drift layer in a cell region; a second groove formed from the upper surface of the base region to the inside of the drift layer in a termination region surrounding the cell region in plan view; and a source region. The first gate electrode and the second gate electrode are electrically connected, and the depth of the second groove is deeper than the depth of the first groove.

Description

TECHNICAL FIELD

[0001] The technology disclosed in the present application relates to semiconductor technology. BACKGROUND

[0002] A semiconductor device using a silicon carbide (SiC) substrate (hereinafter referred to as "SiC semiconductor device") is superior in voltage resistance and heat resistance compared to a semiconductor device using a silicon (Si) substrate (hereinafter referred to as "Si semiconductor device").

[0003] In order to realize high voltage resistance, low loss, or use in a high temperature environment of a semiconductor device, conventionally, SiC semiconductor devices have been applied to power semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs).

[0004] SiC has a higher insulating breakdown field strength compared to Si. Therefore, a voltage resistance layer (drift layer) for realizing the same voltage resistance can be thinned in a SiC semiconductor device compared to a Si semiconductor device. In addition, the impurity doping amount of the voltage resistance layer can be increased in a SiC semiconductor device compared to a Si semiconductor device.

[0005] For these reasons, a SiC semiconductor device can achieve a significantly reduced on-resistance compared to a Si semiconductor device. For example, the on-resistance of a SiC-MOSFET having a voltage resistance of 1 kV or more and 1.2 kV or less is 5 mΩcm 2 Hereinafter, this is a value of one-half or less compared to the on-resistance of a Si-MOSFET or Si-IGBT having the same voltage resistance.

[0006] In the future, with a reduction in manufacturing costs, improvement in process technology, and other performance improvements, it is expected that most of the Si-IGBTs used as inverter components will be replaced with SiC semiconductor devices.

[0007] Now, in order to reduce the loss at the time of energization of a SiC semiconductor device, a trench gate type SiC-MOSFET or SiC-IGBT has been developed.

[0008] However, in a trench gate type SiC-MOSFET or SiC-IGBT, there is a problem in which an electric field is concentrated at a corner portion of the bottom of the trench in a cell region and breaks down the gate insulating film.

[0009] In this regard, for example, Patent Document 1 discloses a method of forming a diffusion layer of p-type in a manner of surrounding the trench bottom to moderate the electric field at the trench bottom. According to this method, the electric field concentration at the trench bottom is suppressed, and the gate insulating film is prevented from being broken down.

[0010] Prior Art Documents

[0011] Patent Documents

[0012] Patent Document 1: Japanese Patent Application Publication No. 2007-173319 SUMMARY

[0013] Problems to be Solved by the Invention

[0014] In a SiC-MOSFET or SiC-IGBT of the trench gate type, in a case where switching operation is performed in a state of a large current and a high voltage, the gate insulating film is broken down at the electric field concentration site of the trench bottom of the cell region, energy is concentrated at the broken-down site and heat is generated, causing the electrode to melt. Further, there is a problem that, due to the melting, the melted metal adheres to the measuring device, maintenance of the measuring device is required, and measurement of other chips becomes difficult.

[0015] In the configuration shown in Patent Document 1, although the gate insulating film is difficult to be broken down, since the site of the electric field concentration is the trench bottom of the cell region, in a case where the chip is broken down, energy is concentrated at the broken-down site and heat is generated, causing the electrode to melt.

[0016] The technology disclosed in the present application specification is completed in view of the above-described problems, and is a technology capable of suppressing melting of the electrode even in a case where a high voltage is applied.

[0017] Means for Solving the Problems

[0018] The semiconductor device according to a first aspect of the technology disclosed in the present application includes: a SiC substrate of a first conductivity type; a drift layer of the first conductivity type formed on an upper surface of the SiC substrate; a base region of a second conductivity type different from the first conductivity type formed in a surface layer of the drift layer; at least one first trench formed in a unit region in a manner reaching inside the drift layer from an upper surface of the base region; a second trench formed in a termination region surrounding the unit region in a plan view in a manner reaching inside the drift layer from the upper surface of the base region; a source region of the first conductivity type partially formed in a surface layer of the base region sandwiching the first trench; a first gate electrode formed in the first trench in a manner surrounded by a gate insulating film; at least one second gate electrode formed in the second trench in a manner surrounded by the gate insulating film; an interlayer insulating film formed covering the first gate electrode and the second gate electrode; a source electrode formed in a manner in contact with the source region; and a drain electrode formed on a lower surface of the SiC substrate opposite to the upper surface, the first gate electrode and the second gate electrode being electrically connected, the depth of the second trench being deeper than the depth of the first trench.

[0019] Effects of the Invention

[0020] According to at least the first aspect of the technology disclosed in the present application, the electric field at the bottom of the second trench of the termination region is larger than the electric field at the bottom of the first trench of the unit region when a high voltage is applied. Therefore, breakdown of the gate insulating film is likely to occur in the termination region, and is relatively difficult to occur in the unit region in which a large current flows, and thus, heat generation at the breakdown site is suppressed, and as a result, melting of the electrode can be suppressed.

[0021] Furthermore, the objects, features, aspects and advantages of the technology disclosed in the present application will become clearer with the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a cross-sectional view showing a structure example of the SiC semiconductor device of the embodiment.

[0023] Figure 2 is a flowchart showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0024] Figure 3 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0025] Figure 4 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0026] Figure 5 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0027] Figure 6 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0028] Figure 7 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0029] Figure 8 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0030] Figure 9 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0031] Figure 10 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0032] Figure 11 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0033] Figure 12 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0034] Figure 13 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0035] Figure 14 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0036] Figure 15 is a cross-sectional view schematically showing an example of a current path at the time of current conduction of the SiC semiconductor device of the embodiment.

[0037] Figure 16 is a cross-sectional view showing an example of a structure of the SiC semiconductor device of the embodiment.

[0038] Figure 17 is a cross-sectional view showing Figure 16 is a schematic view showing an electric field distribution in the B-B' cross section and the C-C' cross section in

[0039] Figure 18 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0040] Figure 19is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0041] Figure 20 is a cross-sectional view showing an example of a structure of the SiC semiconductor device of the embodiment.

[0042] Figure 21 is a cross-sectional view showing an example of a structure of the SiC semiconductor device of the embodiment.

[0043] Figure 22 is a view obtained by combining a plan view and a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0044] Figure 23 is a cross-sectional view showing an example of a structure of the SiC semiconductor device of the embodiment.

[0045] Figure 24 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0046] Figure 25 is a cross-sectional view showing an example of a structure of the SiC semiconductor device of the embodiment.

[0047] Figure 26 is a cross-sectional view showing an example of a manufacturing process of the SiC semiconductor device of the embodiment.

[0048] Figure 27 is a cross-sectional view showing an example of a structure of the SiC semiconductor device of the embodiment.

[0049] Figure 28 is a view conceptually showing an example of a structure of a power conversion system including the power conversion device of the embodiment. DETAILED DESCRIPTION

[0050] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, detailed features and the like are also shown for the purpose of explanation of the technology, but they are examples, and not all features are necessary features for enabling the embodiments.

[0051] In addition, the drawings are schematically shown, and structures and the like are appropriately omitted or simplified in the drawings for the purpose of explanation. Further, the mutual relationship of the size and the position of structures and the like shown in different drawings is not necessarily accurately recorded, and can be appropriately changed. Furthermore, even in drawings other than cross-sectional views, hatching is sometimes added so that the contents of the embodiments are easily understood.

[0052] Further, in the explanation shown below, the same reference numerals are attached to the same structural elements and illustrated, and their names and functions are also the same. Therefore, detailed explanation about them is sometimes omitted in order to avoid repetition.

[0053] Further, in the explanation described in the present application, in the case where it is described that "provided with", "including", or "having" a certain structural element, etc., it is not an exclusive expression that excludes the existence of other structural elements, unless otherwise specified.

[0054] Further, in the explanation described in the present application, even if ordinal numbers such as "1st" or "2nd" are used at times, these terms are used only for the convenience of easily understanding the contents of the embodiments, and the contents of the embodiments are not limited to the order, etc. that can be generated by these ordinal numbers.

[0055] Further, in the explanation described in the present application, even if terms indicating a specific position or direction such as "upper", "lower", "left", "right", "side", "bottom", "surface", or "back" are used at times, these terms are used only for the convenience of easily understanding the contents of the embodiments, and are not related to the position or direction when actually implementing the embodiments.

[0056] Further, in the explanation described in the present application, in the case where it is described as "upper surface of …" or "lower surface of …", etc., in addition to the upper surface itself or the lower surface itself of the structural element that is the object, a state where other structural elements are formed on the upper surface or the lower surface of the structural element that is the object is also included. That is, for example, in the case where it is described as "B is provided on the upper surface of A", it is not hindered that other structural elements "C" are interposed between A and B.

[0057] <1st Embodiment>

[0058] Hereinafter, the semiconductor device and the manufacturing method of the semiconductor device of the present embodiment will be described.

[0059] <Structure of Semiconductor Device>

[0060] Figure 1 is a cross-sectional view showing a structure example of the SiC semiconductor device of the present embodiment. Figure 1 The SiC semiconductor device shown is an example of a SiC-n type MOSFET of a trench gate structure, and shows a cell region 11 and a termination region 12 of the main parts of the SiC semiconductor device.

[0061] Hereinafter, the SiC-n type MOSFET will be described, but even the SiC-p type MOSFET or the SiC-IGBT can be applied. Further, the overall structure of the SiC semiconductor device is Figure 1The unit region 11 of the main part shown is a continuous structure. The larger the size of the current flowing in the SiC semiconductor device, the larger the proportion of the unit region 11 in the overall structure of the SiC semiconductor device.

[0062] As shown in Figure 1 , the SiC semiconductor device is provided with: an n-type SiC substrate 1; an n-type drift layer 2 formed on the upper surface of the n-type SiC substrate 1; a p-type base region 3 formed in the surface layer of the n-type drift layer 2; a plurality of grooves 102 formed in the unit region 11 in such a way as to reach inside the n-type drift layer 2 from the upper surface of the p-type base region 3; a groove 104 formed in the termination region 12 that surrounds the unit region 11 in plan view in such a way as to reach inside the n-type drift layer 2 from the upper surface of the p-type base region 3; a p-type base region 5 formed on the bottom surface of the groove 102 opposite the n-type drift layer 2; a p-type base region 5 formed on the bottom surface of the groove 104 opposite the n-type drift layer 2; an n-type source region 4 formed locally in the surface layer of the p-type base region 3 sandwiching the groove 102; a gate insulating film 6 formed inside the groove 102 in contact with the side surface and the bottom surface and in contact with a part of the upper surface of the p-type base region 3 and inside the groove 104 in contact with the side surface and the bottom surface; a gate electrode 7 formed inside the groove 102 in such a way as to be surrounded by the gate insulating film 6; a gate electrode 70 formed inside the groove 104 in such a way as to be surrounded by the gate insulating film 6; a gate electrode 71 formed inside the groove 104 separate from the gate electrode 70 and surrounded by the gate insulating film 6; an interlayer insulating film 8 formed covering the gate electrode 7, the gate electrode 70, and the gate electrode 71; a source electrode 9 formed covering the interlayer insulating film 8, the p-type base region 3, and the n-type source region 4; and a drain electrode 10 formed on the lower surface (the surface on the side opposite the upper surface) of the n-type SiC substrate 1.

[0063] Here, the depth of the groove 104 is formed to be deeper than the depth of the groove 102.

[0064] Figure 2 is a flowchart showing an example of the manufacturing process of the SiC semiconductor device of the present embodiment. Furthermore, Figures 3 to 14 is a cross-sectional view showing an example of the manufacturing process of the SiC semiconductor device of the present embodiment. Figure 1 The SiC semiconductor device shown is manufactured according to the manufacturing process shown in Figure 2 .

[0065] First, as shown in the example of Figure 3 , an n-type drift layer 2 composed of n-type SiC is formed as an epitaxial film on the first main surface (hereafter denoted as the upper surface) of an n-type SiC substrate 1 (step ST1).

[0066] Next, as shown inFigure 4 As shown in the example, after forming a mask (not shown here) composed of a photoresist or the like, p-type impurity ions are implanted into the surface of the n-type drift layer 2, forming a p-type base region 3 on the surface of the n-type drift layer 2 (step ST2). Examples of p-type impurities include boron (B) or aluminum (Al).

[0067] After that, as Figure 5 As shown in the example, after forming a mask 13 on the p-type base region 3 using a photoresist, n-type impurity ions are implanted into the surface layer of the p-type base region 3 to form an n-type source region 4 on the surface layer of the p-type base region 3 (step ST3). Examples of n-type impurities include phosphorus (P) or nitrogen (N).

[0068] Subsequently, to activate the p-type base region 3 and the n-type source region 4, the SiC wafer is heat-treated at high temperature using a heat treatment apparatus (not shown here). In this way, the p-type ions implanted into the p-type base region 3 and the n-type ions implanted into the n-type source region 4 are electrically activated.

[0069] Next, as Figure 6 As shown in the example, after forming a mask 14 using a resist for the cell region, a trench-type groove 102 of the cell region is formed on the upper surface of the p-type base region 3 and the n-type source region 4 by using plasma dry etching or the like (step ST4).

[0070] Next, as Figure 7 As shown in the example, after forming a mask 15, which is different from mask 14, using a resist for the terminal region, a trench-type groove 104 for the terminal region is formed on the upper surface of the p-type base region 3 by means of plasma dry etching or the like. The depth of the groove 104 is formed to be deeper than the depth of the groove 102.

[0071] In the absence of a mask that can form the slot 102 of the unit region 11 or the slot 104 of the terminal region 12, Figure 5 For example, an oxide film made of TEOS is formed on the upper surface of the p-type base region 3. The oxide film is then dry-etched using a photoresist mask, thereby forming a deeper trench.

[0072] Next, as Figure 8 As shown in the example, in order to mitigate the electric field applied to the bottom of the trench gate, a p-type base region 5 can also be formed at the bottom of trench 102 and trench 104. Examples of p-type impurities include boron (B) or aluminum (Al).

[0073] Next, in order to remove the plasma damage caused when the trench gate was formed, a thermal oxidation method was used to... Figure 8 The top and side surfaces of the structure shown are oxidized.

[0074] In order to remove plasma damage, it is desirable Figure 8 The upper surface and the side surface of the configuration shown are oxidized in a large amount. However, due to this thermal oxidation, the impurity layer (p-type base region 3, n-type source region 4, p-type base region 5) formed in the surface layer of the n-type drift layer 2 is reduced. Therefore, the surface layer of the n-type drift layer 2 of SiC can be thermally oxidized, for example, in a thickness of 20 nm or more and 80 nm or less, and more preferably, for example, in a thickness of 30 nm or more and 70 nm or less. In addition, the inventors confirmed that plasma damage when the trench gate is formed can be sufficiently removed by thermal oxidation in this thickness by measuring the leakage current between the gate electrode 7 and the source electrode 9.

[0075] Next, as shown in the example of Figure 9 , the gate insulating film 6 is formed by a thermal oxidation method or a deposition method such as chemical vapor deposition (step ST5).

[0076] Next, as shown in the example of Figure 10 , the electrode layer 72 is formed on the upper surface of the gate insulating film 6 in a manner of filling the trench 102 and the trench 104 (step ST6).

[0077] Then, as shown in the example of Figure 11 , the electrode layer 72 is patterned so that the remaining portion of the electrode layer 72 is removed. Here, for etching of the electrode layer 72, anisotropy-high etching such as dry etching using plasma is used. By performing anisotropy-high etching, the gate electrode 7 is formed inside the trench 102 which becomes a trench, the gate electrode 70 (a separate gate electrode formed separately from the side surface of the inner periphery side of the trench 104) is formed directly below the mask 16 formed in the termination region, and the gate electrode 71 (a contact gate electrode formed in contact with the side surface of the inner periphery side of the trench 104) is formed in the portion of the termination region adjacent to the cell region.

[0078] In Figure 12 , a schematic top view and a cross-sectional view of the configuration shown in Figure 11 are shown in combination. As shown in the example of Figure 12 , the gate electrode 7 inside the trench 102, the gate electrode 70 formed directly below the mask 16 formed in the termination region, and the gate electrode 71 of the portion of the termination region adjacent to the cell region are all connected.

[0079] Next, the interlayer insulating film 8 is formed using a chemical vapor deposition (CVD) method. Thereafter, as shown in the example of Figure 13 , photolithography and patterning based on etching processing are performed, and the remaining portion of the interlayer insulating film 8 is removed together with the gate insulating film 6 (step ST7).

[0080] The corner of the interlayer insulating film 8 can also be rounded by introducing impurities such as boron (B) or phosphorus (P) into the interlayer insulating film 8. As described above, the interlayer insulating film 8 is formed by deposition and patterning, but the material deposited is, for example, silicon nitride (SixNy) or silicon oxide (SiO2), and the thickness of the interlayer insulating film 8 is, for example, preferably 0.5 μm or more and 2.0 μm or less.

[0081] Next, as shown in the example of FIG. 6, the source electrode 9 is formed using aluminum, an aluminum alloy composed of aluminum and silicon, an aluminum alloy composed of aluminum and copper, or nickel, and a barrier metal composed of titanium or a titanium compound such as titanium nitride (TiN) is appropriately used (step ST8). Figure 14 Subsequently, as necessary, the n-type SiC substrate 1 is thinned by mechanical processing using a grinding tool with respect to the surface of the n-type SiC substrate 1 on the side opposite the first main surface, that is, the second main surface (hereinafter referred to as the lower surface) (step ST9).

[0082] Then, a nickel film of about 600 nm is formed on the lower surface of the n-type SiC substrate 1 using a sputtering method or the like, and thereby the drain electrode 10 is formed (step ST10). As a result, the SiC semiconductor device having the configuration shown in the example of FIG. 7 is formed.

[0083] Figure 1

[0084] In addition, with respect to the upper surface of the nickel film that becomes the drain electrode 10, the wettability of the solder alloy with respect to nickel deteriorates due to oxidation of the uppermost surface, and the bonding state at the time of die bonding deteriorates. Therefore, a metal such as gold or silver that has low reactivity with the outside can also be formed as a protective film on the upper surface of the nickel film, and a laminated film composed of the nickel film and the gold or silver can be used as the drain electrode 10.

[0085] Figure 15 is a cross-sectional view schematically showing an example of a current path at the time of current conduction of the SiC semiconductor device of the present embodiment.

[0086] In Figure 15 , a case in which a voltage of the threshold value or more is applied to the gate electrode 7 and the potential of the source electrode 9 is higher than the potential of the drain electrode 10 is shown by a solid line A, and the threshold value is a reference for the voltage at which current flows in the SiC semiconductor device.

[0087] As shown in Figure 15 , the current flowing in the entire electrode surface of the drain electrode 10 is concentrated in the n-type source region 4 on the upper surface side of the SiC semiconductor device. Therefore, on the upper surface side of the SiC semiconductor device, the current flows only in the cell region 11, and no current flows in the termination region 12.​​

[0088] When the difference between the potential of the source electrode 9 and the potential of the drain electrode 10 becomes large and the electric field of the gate insulating film 6 reaches the insulating breakdown electric field, the gate insulating film 6 is broken down. In the case where the breakdown site of the gate insulating film 6 is the cell region 11, since this site is a site where current flows, the amount of heat at the time of breakdown becomes large, and the gate electrode 7 is melted. On the other hand, in the case where the breakdown site of the gate insulating film 6 is the termination region 12, since this site is a site where current does not flow, the amount of heat at the time of breakdown becomes small, and the melting of the gate electrode 7 is suppressed.

[0089] Figure 16 is a cross-sectional view showing a structure example of the SiC semiconductor device of the present embodiment. Furthermore, Figure 17 is a schematic view showing Figure 16 the electric field distribution in the B-B' cross section and the C-C' cross section. In Figure 17 , the vertical axis represents the electric field, and the horizontal axis represents the depth. Furthermore, in Figure 17 , the electric field distribution in the B-B' cross section is represented by a broken line, and the electric field distribution in the C-C' cross section is represented by a solid line.

[0090] In Figure 16 , in the case where the distance between the bottom of the trench 102 of the cell region 11 and the lower surface of the n-type drift layer 2 is set to LI, and the distance between the bottom of the trench 104 of the termination region 12 and the lower surface of the n-type drift layer 2 is set to L2, LI > L2 is obtained. That is, of the trench 102 and the trench 104 which are also formed on the upper surface of the p-type base region 3, the trench 104 is deeper than the trench 102.

[0091] Thus, as shown in Figure 17 , in the case where the electric field applied to the bottom of the trench 102 of the cell region 11 is set to El, and the electric field applied to the bottom of the trench 104 of the termination region 12 is set to E2, El < E2 is obtained.

[0092] Therefore, the gate insulating film 6 of the termination region 12 reaches the insulating breakdown electric field at a lower voltage than the gate insulating film 6 of the cell region 11, and thus the gate insulating film 6 of the site where current does not flow at all is broken down in the SiC semiconductor device of the present embodiment. Thus, the amount of heat at the time of breakdown becomes small, and the melting of the gate electrode 7 can be suppressed.

[0093] In the case where a withstand voltage of V1 is assumed in the SiC semiconductor device, the gate insulating film 6 must not be broken down at a voltage lower than V1. Therefore, in the case where the impurity concentration of the n-type drift layer 2 is assumed to be N1, the insulating breakdown electric field of the gate insulating film 6 is assumed to be Ec, the elementary charge is assumed to be q, and the dielectric constant of SiC is assumed to be Ec, it is necessary, according to Gauss's law, for L2 to satisfy V1 < Ec x L2 - (q x N1 / Ec) x L2 x L2. When L2 is too short (too small), the above equation cannot be satisfied.

[0094] <2nd Embodiment>

[0095] The semiconductor device and the manufacturing method of the semiconductor device according to the present embodiment will be described. In the following description, the same reference numerals are assigned to the same structural elements as those described in the above-described embodiments, and detailed description thereof will be appropriately omitted.

[0096] <Structure of Semiconductor Device>

[0097] A manufacturing method of an SiC semiconductor device in which L1 > L2 can be achieved even when grooves 102 of the cell region 11 and grooves 104 of the termination region 12 are processed in the same run compared to the first embodiment will be described.

[0098] First, steps ST1 to ST3 are implemented in the same manufacturing process as in the case of the first embodiment. In this way, the configuration shown in Figure 5 is formed.

[0099] Next, a resist-based mask 17 is formed in the cell region 11 and the termination region 12. Thereafter, as shown in the example of Figure 18 , grooves 102 of the cell region 11 and grooves 104 of the termination region 12 are formed in the same run by dry etching using plasma or the like (step ST4). In addition, Figure 18 is a cross-sectional view showing an example of the manufacturing process of the SiC semiconductor device according to the present embodiment.

[0100] Here, in order to make L1 > L2 in the dry etching in the same run, in the case where the width (width in plan view) of the bottom of the groove 102 of the cell region 11 is assumed to be W1 and the width (width in plan view) of the bottom of the groove 104 of the termination region 12 is assumed to be W2, the mask pattern of the mask 17 is formed so as to make W1 < W2.

[0101] The wider the width of the bottom of the groove, the more easily the etching gas reacts, and therefore, if W1 < W2, the groove 102 of the cell region 11 and the groove 104 of the termination region 12 which become L1 > L2 can be formed in one process by the dry etching in the same run.

[0102] Similar to the first embodiment, when it is not possible to provide a mask that can form the groove 102 of the unit region 11 or the groove 104 of the terminal region 12, for example, the oxide film made of TEOS is placed... Figure 5 A film is formed on the upper surface of the p-type base region 3, and the oxide film is dry-etched using a photoresist mask, thereby forming a deeper trench.

[0103] According to the manufacturing method described above, the first embodiment can be formed. Figure 7 The construction shown. Then, as... Figure 8 As shown in the example, in order to mitigate the electric field applied to the bottom of the trench gate, a p-type base region 5 can also be formed at the bottom of trench 102 and trench 104. Examples of p-type impurities include boron (B) or aluminum (Al).

[0104] Then, by performing the same steps as steps ST5 to ST10 shown in the first embodiment, a product is formed. Figure 1 The example shows a SiC semiconductor device with the structure shown.

[0105] According to the manufacturing method of this embodiment, compared with the first embodiment, the formation process of the resist mask for forming the trench 104 of the terminal region 12, the dry etching process, the resist cleaning process, etc., can be omitted. Therefore, SiC semiconductor devices can be manufactured at a low manufacturing cost.

[0106] Here, when the groove 102 of the unit region 11 and the groove 104 of the terminal region 12 are formed in the same stroke using the manufacturing method of this embodiment, the lengths of L1 and L2 are difficult to control compared to the case where they are formed separately as shown in the first embodiment. Therefore, it is necessary to control the process conditions such as the type of gas, pressure, or temperature of the dry etching process so that the desired V1 is achieved by satisfying the shorter length L2 = V1 < Ec × L2 - (q × N1 / εc) × L2 × L2.

[0107] If L2 = V1 < Ec × L2 - (q × N1 / εc) × L2 × L2 and W1 < W2, then it is possible to manufacture a SiC semiconductor device that achieves the desired V1 and becomes L1 > L2.

[0108] <Third Implementation>

[0109] The semiconductor device and its manufacturing method according to this embodiment will be described. Furthermore, in the following description, structural elements identical to those described in the above-described embodiments are illustrated using the same reference numerals, and their detailed descriptions are omitted where appropriate.

[0110] <On the structure of semiconductor devices>

[0111] The SiC semiconductor device is explained as follows: the SiC semiconductor device is such that, compared with the first embodiment, the angle of the corner between the bottom surface and the side surface of the trench 104A of the termination region 12 is α, and becomes 90° < α, and, in the case where the depth of the trench 104A of the termination region 12 formed in a manner of surrounding the unit region 11 in plan view is A, the distance between the trench 102 existing at the outermost periphery of the unit region 11 and the trench 104A of the termination region 12 is B, and β = arctan(B / A), as a condition for forming the trench 104A in a manner of separating from the trench 102 existing at the outermost periphery of the unit region 11, it becomes 90° < α < 90° + β.

[0112] First, the steps ST1 to ST3 are implemented in the same manufacturing process as the case shown in the first embodiment. In this way, the configuration shown in Figure 5 is formed.

[0113] Next, as shown in the example of Figure 6 , after the mask 14 is formed using the unit region resist, the trench-type trench 102 of the unit region is formed by dry etching using plasma or the like (step ST4).

[0114] Next, the resist-based mask 18 is formed in the unit region 11 and the termination region 12. The mask 18 has an inclined surface 18A at a position corresponding to the boundary of the termination region 12 and the unit region 11. After that, as shown in the example of Figure 19 , the trench 104A of the termination region 12 is formed by dry etching using plasma or the like. Here, Figure 19 is a cross-sectional view showing an example of the manufacturing process of the SiC semiconductor device of the present embodiment.

[0115] The trench 104A has an inclined side surface corresponding to the inclined surface 18A. Specifically, the trench 104A can be formed in a manner that the angle α between the bottom and the side surface of the trench 104A of the termination region 12 becomes 90° < α < 90° + β.

[0116] As in the first embodiment, in the case where a mask capable of forming the trench 102 of the unit region 11 or the trench 104A of the termination region 12 cannot be disposed, for example, an oxide film using TEOS as a raw material is formed on the upper surface of the p-type base region 3 in Figure 5 , and the oxide film is dry etched using a resist mask, whereby a deeper trench can be formed.

[0117] In forming the mask of the oxide film described above, the mask of the oxide film can also be made to have a slope by using a mask 18 having a slope. Thereafter, in order to relax the electric field applied to the bottom of the trench gate, a base region 5 of p-type can also be formed at the bottom of the trench 102 and the trench 104. As the impurity of p-type, boron (B) or aluminum (Al) or the like is exemplified.

[0118] Then, by going through the same procedures as the steps ST5 to ST10 shown in the first embodiment, a SiC semiconductor device satisfying 90° < α < 90° + β as shown in the example is formed. Figure 20 Figure 20 is a cross-sectional view showing a structure example of the SiC semiconductor device of the present embodiment.

[0119] The SiC semiconductor device of the present embodiment is such that the angle α between the bottom and the side surface of the trench 104A of the termination region 12 is larger than 90° compared to the first embodiment, and thus the electric field concentrated at the corner on the inner peripheral side of the trench 104 can be relaxed.

[0120] The electric field applied to the corner of the gate electrode 71A in contact with the side surface of the trench 104A of the termination region 12 is approximately considered as the electric field formed by the circular-shaped electrode of the radius R in contact with the bottom and the side wall of the trench 104A through the perpendicular bisector of the bottom of the gate electrode 71A in contact with the side surface of the trench 104A of the termination region 12.

[0121] Figure 21 is a cross-sectional view showing a structure example of the SiC semiconductor device of the present embodiment. As Figure 21 As shown in the example of the SiC semiconductor device of the present embodiment, when the electric field is considered by the circular-shaped electrode of the radius R in contact with the bottom and the side wall of the trench 104A through the perpendicular bisector of the bottom of the gate electrode 71A in contact with the side surface of the trench 104A of the termination region 12, the potential difference between the source electrode 9 and the drain electrode 10 is V2, and according to Gauss' law, the magnitude of the electric field becomes E ∝ V2 / R, and thus the larger R is, the smaller the electric field is. Further, the relationship of R / (d / 2) = tan(α / 2) holds for α and R, and thus the larger α is, the smaller the electric field is.

[0122] As a result, the larger α is, the smaller the electric field applied to the gate insulating film 6 is, and thus the breakdown of the gate insulating film 6 is suppressed.

[0123] <4th Embodiment>

[0124] A semiconductor device and a method of manufacturing a semiconductor device of the present embodiment will be described. In the following description, the same reference numerals are assigned to the same structural elements as those described in the above-described embodiments, and the detailed description thereof is appropriately omitted.

[0125] <Structure of Semiconductor Device>

[0126] ​A SiC semiconductor device in which the distance between the gate electrode 70 formed in the trench 104 of the termination region 12 and the side surface of the trench 104 can be controlled compared to the case shown in the first embodiment, the termination region 12 being formed so as to surround the cell region 11 in plan view, will be described.

[0127] First, the steps ST1 to ST6 are implemented in the same manufacturing process as the case shown in the first embodiment. In this way, the configuration shown in the example of Figure 11 is formed.

[0128] Next, in order to remove the gate electrode 71 of the portion in contact with the side surface of the trench 104, the gate electrode 71 of the portion in contact with the side surface of the trench 104 is patterned using the mask 19 composed of a resist, and is removed by wet etching or dry etching, as shown in the example of Figure 22 . Alternatively, the gate electrode 71 of the portion in contact with the side surface of the trench 104 is removed by dry etching using the mask 19 composed of a resist, and further wet etching or dry etching (i.e., etching treatment is performed multiple times), whereby the gate electrode 71 of the portion in contact with the side surface of the trench 104 is removed. In this way, the gate electrode 70 can be formed so as to be separated from the side surface of the inner periphery side of the trench 104. In addition, the gate electrode 70 can be formed so as to be separated from the side surface of the inner periphery side of the trench 104 by a predetermined distance. Figure 22 is a view obtained by combining a plan view and a sectional view showing an example of the manufacturing process of the SiC semiconductor device of the present embodiment.

[0129] Then, the SiC semiconductor device of the configuration shown in the example of Figure 23 is formed by going through the same process as the steps ST7 to ST10 shown in the first embodiment. In addition, Figure 23 is a sectional view showing an example of the configuration of the SiC semiconductor device of the present embodiment.

[0130] According to the manufacturing method of the present embodiment, by adjusting the mask pattern in the process of forming the gate electrode 70 of the termination region 12 shown in Figure 11 , the size of the distance W3 between the gate electrode 70 and the side surface of the trench 104 can be set.

[0131] If W3 is increased, the distance between the cell region 11 (refer to Figure 15 ) in which the current flows and the electric field concentration site in the trench 104 of the termination region 12 can be increased. Therefore, compared to the case shown in the first embodiment, the melting of the gate electrode 7 can be suppressed.

[0132] On the other hand, when W3 is increased, the surface area of the SiC semiconductor device also becomes large, and therefore, as a result, the manufacturing cost of the SiC semiconductor device becomes high.

[0133] According to the manufacturing method of this embodiment, W3 can be controlled to an arbitrary length, and therefore, the value of W3 can be adjusted to be optimal by comparing manufacturing cost and resistance to melting.

[0134] in addition, Figure 22 and Figure 23 The side surface of the inner peripheral side of the groove 104 where only the gate electrode 70 is formed, as shown, can also be Figure 19 , Figure 20 and Figure 21 The inclined plane shown.

[0135] <Fifth Implementation>

[0136] The semiconductor device and its manufacturing method according to this embodiment will be described. Furthermore, in the following description, structural elements that are the same as those described in the above-described embodiments are illustrated using the same reference numerals, and their detailed descriptions are omitted where appropriate.

[0137] <On the structure of semiconductor devices>

[0138] The following SiC semiconductor device will be described: Compared with the first embodiment, the current density of the current flowing in the source electrode adjacent to the terminal region 12 can be reduced, thereby suppressing the heating in the terminal region 12 where the electric field is concentrated.

[0139] First, following the same manufacturing process as in the first embodiment, steps ST1 to ST3 are performed. Then, in step ST4, after forming a mask 15A (different from mask 14) using a resist for the terminal region, a trench 104 (see reference) is formed on the upper surface of the p-type base region 3 using plasma dry etching or the like for the terminal region. Figure 24 Here, the distance between the grooves 104 and 102 formed by the mask 15A is greater than the distance between the grooves 102. Furthermore, the depth of the grooves 104 in the unit region 11 is greater than the depth of the grooves 102. Additionally, Figure 24 This is a cross-sectional view illustrating an example of the manufacturing process of the SiC semiconductor device according to this embodiment.

[0140] Then, by performing the same steps as steps ST5 to ST10 shown in the first embodiment, a product is formed. Figure 25 The example illustrates the construction of a SiC semiconductor device. Additionally... Figure 25 This is a cross-sectional view showing a structural example of the SiC semiconductor device according to this embodiment.

[0141] like Figure 25As shown, the distance (W4) between the interlayer insulating film 8 formed on the groove 104 and the interlayer insulating film 8 formed on the groove 102 is larger than the distance (W5) between the interlayer insulating films 8 on the groove 102. If W4 is increased, the current density in the source electrode 9 between the cell region 11 and the termination region 12 of the flow current can be reduced. Thus, the heat generation caused by the current in the termination region 12 can be reduced to suppress melting.

[0142] On the other hand, when W4 is large, the surface area of the SiC semiconductor device is also large, and therefore, as a result, the manufacturing cost of the SiC semiconductor device is high.

[0143] According to the manufacturing method of the present embodiment, W4 can be controlled to an arbitrary length according to the shape of the mask 15A, and therefore, W4 can be adjusted to an optimum value in comparison between the manufacturing cost and the resistance to melting.

[0144] In addition, Figure 24 and Figure 25 The side surface of the inner periphery side of the groove 104 shown can also be Figure 19 , Figure 20 and Figure 21 the inclined surface shown.

[0145] <6th Embodiment>

[0146] The semiconductor device and the manufacturing method of the semiconductor device of the present embodiment will be described. In the following description, the same reference numerals are assigned to the same structural elements as those described in the above-described embodiments, and the detailed description thereof will be appropriately omitted.

[0147] <Structure of Semiconductor Device>

[0148] A SiC semiconductor device in which heat generation in the termination region 12 in which the electric field is concentrated can be suppressed by cutting off the current flowing in the side wall of the groove 104 of the termination region 12 compared to the first embodiment will be described.

[0149] First, steps ST1 to ST6 are performed in the same manufacturing process as that shown in the first embodiment. Thereafter, in step ST7, the photolithography for forming the interlayer insulating film 8 and the patterning based on the etching process are changed so that the interlayer insulating film 8 of the termination region 12 and the interlayer insulating film 8 of the cell region 11 adjacent to each other are connected. In this way, the configuration shown is formed. In addition, Figure 26 is a cross-sectional view showing an example of the manufacturing process of the SiC semiconductor device of the present embodiment. Figure 26

[0150] ​Then, by performing the same steps as steps ST8 to ST10 shown in the first embodiment, a product is formed. Figure 27 The example illustrates the construction of a SiC semiconductor device. Additionally... Figure 27 This is a cross-sectional view showing a structural example of the SiC semiconductor device according to this embodiment.

[0151] exist Figure 27 In the configuration shown, the source electrode 9 adjacent to the terminal region 12 is blocked from contacting the p-type base region 3. By adopting this configuration, the current density between the unit region 11 and the terminal region 12 can be cut off. Therefore, the heat generated by the current in the terminal region 12 can be reduced, and melting can be suppressed.

[0152] in addition, Figure 26 and Figure 27 The inner circumferential side of the groove 104 shown can also be Figure 19 , Figure 20 and Figure 21 The inclined plane shown.

[0153] <Seventh Implementation>

[0154] The power conversion device and its manufacturing method according to this embodiment will be described. In the following description, structural elements that are the same as those described in the above-described embodiments are illustrated with the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0155] <Regarding the structure of power conversion devices>

[0156] This embodiment applies the semiconductor device described in the above-described embodiments to a power conversion device. The power conversion device used is not limited to a specific application, but the following description focuses on its application to a three-phase inverter.

[0157] Figure 28 This is a diagram that conceptually illustrates a structural example of a power conversion system including the power conversion device of this embodiment.

[0158] like Figure 28 As shown in the example, the power conversion system includes a power source 2100, a power conversion device 2200, and a load 2300. The power source 2100 is a DC power source and supplies DC power to the power conversion device 2200. The power source 2100 can be constructed from various power sources, such as a DC system, solar cells, or batteries. Furthermore, the power source 2100 can be constructed from a rectifier circuit or an AC-DC converter connected to an AC system. Alternatively, the power source 2100 can be constructed by converting DC power output from a DC system into a specified power.

[0159] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts direct-current electric power supplied from the power supply 2100 into alternating-current electric power, and supplies the alternating-current electric power to the load 2300.

[0160] Further, as shown in the example of FIG. 2, the power conversion device 2200 includes a conversion circuit 2201 that converts direct-current electric power into alternating-current electric power and outputs the alternating-current electric power, a drive circuit 2202 that outputs a drive signal for driving each switching element of the conversion circuit 2201, and a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202. Figure 28

[0161] The load 2300 is a three-phase motor driven by the alternating-current electric power supplied from the power conversion device 2200. Note that the load 2300 is not limited to a specific use, and is a motor mounted on various electric appliances, such as a motor for a hybrid automobile, an electric automobile, a railway vehicle, an elevator, or an air conditioning device.

[0162] Hereinafter, the power conversion device 2200 will be described in detail. The conversion circuit 2201 includes switching elements and freewheeling diodes (not shown in the drawing). The direct-current electric power supplied from the power supply 2100 is converted into alternating-current electric power by switching operations of the switching elements, and is supplied to the load 2300.

[0163] The specific circuit structure of the conversion circuit 2201 has various circuit structures, but the conversion circuit 2201 of the present embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and six freewheeling diodes connected in reverse parallel to the respective switching elements.

[0164] The semiconductor device of any of the above-described embodiments is applied to at least one of the respective switching elements and the respective freewheeling diodes in the conversion circuit 2201. The six switching elements are connected in series in two switching elements each to constitute an upper arm and a lower arm, and the respective upper and lower arms constitute respective phases (i.e., a U phase, a V phase, and a W phase) of the full-bridge circuit. Further, output terminals of the respective upper and lower arms (i.e., three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0165] The drive circuit 2202 generates a drive signal for driving the switching elements of the conversion circuit 2201, and supplies the drive signal to control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on a control signal output from the control circuit 2203 described later, a drive signal that causes the switching elements to be in an on state and a drive signal that causes the switching elements to be in an off state are output to the control electrodes of the respective switching elements.

[0166] ​The drive signal is a voltage signal above the threshold voltage of the switching element in the case where the switching element is maintained in the on state (i.e., an on signal), and becomes a voltage signal below the threshold voltage of the switching element in the case where the switching element is maintained in the off state (i.e., an off signal).

[0167] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that the desired electric power is supplied to the load 2300. Specifically, based on the electric power that should be supplied to the load 2300, the time (i.e., the on time) during which each of the switching elements of the conversion circuit 2201 should be in the on state is calculated. For example, the conversion circuit 2201 can be controlled by PWM control that modulates the on time of the switching element in accordance with the voltage that should be output.

[0168] Then, the control circuit 2203 outputs a control command (i.e., a control signal) to the drive circuit 2202 so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each point in time. The drive circuit 2202 outputs the on signal or the off signal as the drive signal to the control electrode of each of the switching elements based on the control signal.

[0169] In the power conversion device 2200 of the present embodiment, the semiconductor device of any of the above-described embodiments is applied as the switching element of the conversion circuit 2201, and thus the on-resistance after the energization cycle can be stabilized.

[0170] In addition, in the present embodiment, an example in which the semiconductor device of any of the above-described embodiments is applied to a two-level three-phase inverter is described, but the application example is not limited thereto, and the semiconductor device of any of the above-described embodiments can be applied to various power conversion devices.

[0171] Further, in the present embodiment, a two-level power conversion device is described, but the semiconductor device of any of the above-described embodiments can also be applied to a three-level or multi-level power conversion device. Further, in the case where electric power is supplied to a single-phase load, the semiconductor device of any of the above-described embodiments can also be applied to a single-phase inverter.

[0172] Further, in the case where electric power is supplied to a direct-current load or the like, the semiconductor device of any of the above-described embodiments can also be applied to a DC-DC converter or an AC-DC converter.

[0173] Further, the power conversion device using the semiconductor device of any of the above-described embodiments is not limited to the case where the load is the motor, and can be used as, for example, a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power feeding system. Further, the power conversion device using the semiconductor device of any of the above-described embodiments can also be used as a power conditioner in a solar power generation system or a power storage system.

[0174] The semiconductor switching element used in the above-described embodiments is not limited to a switching element composed of a silicon (Si) semiconductor, and can be composed of a non-Si semiconductor material having a wider band gap than the Si semiconductor.

[0175] As the wide band gap semiconductor that is the non-Si semiconductor material, for example, there are silicon carbide, a gallium nitride-based material, or diamond.

[0176] The switching element composed of the wide band gap semiconductor can be used in a high voltage region where single-stage operation is difficult in the Si semiconductor, and can greatly reduce switching loss generated at the time of switching operation. Thus, power consumption can be greatly reduced.

[0177] Further, the switching element composed of the wide band gap semiconductor has small power consumption and high heat resistance. Thus, in the case of composing a power module provided with a cooling unit, the fins of a heat sink can be downsized, and thus the semiconductor module can be further downsized.

[0178] Further, the switching element composed of the wide band gap semiconductor is suitable for high frequency switching operation. Thus, in the case of being applied to a converter circuit where high frequency is required, by high frequency of the switching frequency, a reactor or a capacitor connected to the converter circuit can also be downsized.

[0179] Thus, the semiconductor switching element in the above-described embodiments also achieves the same effects in the case of being a switching element composed of a wide band gap semiconductor such as silicon carbide.

[0180] <Effects Produced by the Above-Described Embodiments>

[0181] Next, examples of effects produced by the above-described embodiments are shown. In the following description, the effects are described based on the specific structures exemplified in the above-described embodiments, but other specific structures exemplified in the present specification can be substituted within a range where the same effects are produced. That is, in the following, for convenience, any one of the corresponding specific structures is sometimes described representatively, but other specific structures corresponding to the representatively described specific structures can be substituted.

[0182] Further, the substitution can also be made across a plurality of embodiments. That is, the same effect can also be obtained when combining the respective structures exemplified in different embodiments.

[0183] According to the above-described embodiment, the semiconductor device is provided with the n-type SiC substrate 1, the n-type drift layer 2, the p-type base region 3, at least one first trench, the second trench, the n-type source region 4, the first gate electrode, at least one second gate electrode, the interlayer insulating film 8, the source electrode 9, and the drain electrode 10. Here, the first trench corresponds to the trench 102 or the like, for example. Further, the second trench corresponds to the trench 104, the trench 104A, or the like, for example. Further, the first gate electrode corresponds to the gate electrode 7 or the like, for example. Further, the second gate electrode corresponds to the gate electrode 70, the gate electrode 71, the gate electrode 71A, or the like, for example. The n-type drift layer 2 is formed on the upper surface of the n-type SiC substrate 1. The p-type base region 3 is formed in the surface layer of the n-type drift layer 2. The trench 102 is formed in the cell region 11 in such a manner as to reach the n-type drift layer 2 from the upper surface of the p-type base region 3. In the termination region 12 that surrounds the cell region 11 in plan view, the trench 104 is formed in such a manner as to reach the n-type drift layer 2 from the upper surface of the p-type base region 3. The n-type source region 4 is partially formed in the surface layer of the p-type base region 3 with the trench 102 interposed therebetween. The gate electrode 7 is formed in the trench 102 in such a manner as to be surrounded by the gate insulating film 6. The gate electrode 70 is formed in the trench 104 in such a manner as to be surrounded by the gate insulating film 6. The interlayer insulating film 8 is formed so as to cover the gate electrode 7 and the gate electrode 70. The source electrode 9 is formed so as to be in contact with the n-type source region 4. The drain electrode 10 is formed on the lower surface of the n-type SiC substrate 1, which is the surface on the side opposite to the upper surface. Here, the gate electrode 7 and the gate electrode 70 are electrically connected. Further, the depth of the trench 104 is deeper than the depth of the trench 102.

[0184] According to such a structure, when a high voltage is applied, the electric field at the bottom of the trench 104 of the termination region 12 is larger than the electric field at the bottom of the trench 102 of the cell region 11. Therefore, breakdown of the gate insulating film 6 is likely to occur in the termination region 12, and is relatively unlikely to occur in the cell region 11 in which a large current flows, and thus, heat generation at the breakdown site is suppressed, and as a result, melting of the gate electrode 7 can be suppressed.

[0185] Further, the same effect can be obtained even when other structures exemplified in the present specification are appropriately added to the above-described structure, or even when other structures in the present specification that are not mentioned are appropriately added to the above-described structure.

[0186] Further, according to the above-described embodiment, the width (W1) in plan view of the trench 102 is narrower than the width (W2) in plan view of the trench 104. According to such a structure, the wider the width of the bottom of the trench, the more easily the etching gas reacts, and thus, if W1 < W2 is provided, the trench 102 of the unit region 11 and the trench 104 of the termination region 12 that become L1 > L2 by dry etching in one stroke can be formed in one process without using separate processes.

[0187] Further, according to the above-described embodiment, in a case where the angle of the angle between the bottom surface and the side surface of the trench 104A of the termination region 12 is α, 90° < α is satisfied. According to such a structure, the electric field concentrated in the corner portion on the inner peripheral side of the trench 104 can be moderated. Breakdown of the gate insulating film 6 is inhibited.

[0188] Further, according to the above-described embodiment, the gate electrode 70 is formed in a manner separated from the side surface on the inner peripheral side of the trench 104. According to such a structure, the value of W3 that is optimal in comparison of the manufacturing cost of the SiC semiconductor device and the resistance to melting can be adjusted.

[0189] Further, according to the above-described embodiment, the second gate electrode includes a separation gate electrode (gate electrode 70) formed in a manner separated from the side surface on the inner peripheral side of the trench 104, and a contact gate electrode (gate electrode 71, gate electrode 71A) formed in a manner in contact with the side surface on the inner peripheral side of the trench 104. According to such a structure, when a high voltage is applied, the electric field of the bottom of the trench 104 of the termination region 12 is larger than the electric field of the bottom of the trench 102 of the unit region 11. Thus, breakdown of the gate insulating film 6 is likely to occur in the termination region 12, and is relatively difficult to occur in the unit region 11 in which a large current flows.

[0190] Further, according to the above-described embodiment, the power conversion device is provided with: a conversion circuit 2201 that has the above-described semiconductor device and outputs a converted power from an input power; a drive circuit 2202 that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202. According to such a structure, when a high voltage is applied, the electric field of the bottom of the trench 104 of the termination region 12 is larger than the electric field of the bottom of the trench 102 of the unit region 11. Thus, breakdown of the gate insulating film 6 is likely to occur in the termination region 12, and is relatively difficult to occur in the unit region 11 in which a large current flows, and thus, heating at the breakdown site is inhibited, and as a result, melting of the gate electrode 7 can be inhibited.

[0191] According to the above-described embodiment, in the method of manufacturing the semiconductor device, the n-type drift layer 2 is formed on the upper surface of the n-type SiC substrate 1 of the first conductive type. Then, the base region 3 of the p-type of the second conductive type different from the first conductive type is formed on the surface layer of the n-type drift layer 2. Then, the n-type source region 4 of the first conductive type is locally formed on the surface layer of the p-type base region 3. Then, at least one trench 102 is formed in the cell region 11 in such a manner as to reach the n-type drift layer 2 from the upper surface of the n-type source region 4. Then, a trench 104 is formed in the termination region 12 surrounding the cell region 11 in such a manner as to reach the n-type drift layer 2 from the upper surface of the n-type source region 4. Then, the gate electrode 7 is formed in the trench 102 in such a manner as to be surrounded by the gate insulating film 6. Then, at least one gate electrode 70 is formed in the trench 104 in such a manner as to be surrounded by the gate insulating film 6. Then, the interlayer insulating film 8 is formed so as to cover the gate electrode 7 and the gate electrode 70. Then, the source electrode 9 is formed so as to be in contact with the n-type source region 4. Then, the drain electrode 10 is formed on the lower surface of the n-type SiC substrate 1 opposite to the upper surface. Here, the gate electrode 7 is electrically connected to the gate electrode 70. In addition, the depth of the trench 104 is deeper than the depth of the trench 102.

[0192] According to such a structure, when a high voltage is applied, the electric field at the bottom of the trench 104 of the termination region 12 is larger than the electric field at the bottom of the trench 102 of the cell region 11. Therefore, the breakdown of the gate insulating film 6 is likely to occur in the termination region 12 and is relatively difficult to occur in the cell region 11 in which a large current flows, and thus the heat generation at the breakdown site is suppressed, and as a result, the melting of the gate electrode 7 can be suppressed.

[0193] In addition, the order of the respective processes can be changed without particular limitation.

[0194] In addition, even when the above-described structure is appropriately added with other structures exemplified in the present specification, or even when the above-described structure is appropriately added with other structures in the present specification that are not mentioned, the same effects can be obtained.

[0195] In addition, according to the above-described embodiment, the formation of the trench 102 means that the trench 102 is formed using a first mask (for example, the mask 14). The formation of the trench 104 means that the trench 104 is formed using a second mask (for example, the mask 15) different from the mask 14. According to such a structure, the depth of the trench 104 in the termination region 12 can be formed deeper than the depth of the trench 102 in the cell region 11.

[0196] Further, according to the above-described embodiments, forming the second gate electrode means forming the gate electrode 70 so as to be separated from the side surface of the inner periphery side of the trench 104 by etching the inside of the trench 104. According to such a structure, the W3 can be controlled to an arbitrary length, and thus the value of the W3 can be adjusted to be optimal in comparison between the manufacturing cost and the resistance to melting of the SiC semiconductor device.

[0197] Further, according to the above-described embodiments, forming the second gate electrode means forming the gate electrode 70 so as to be separated from the side surface of the inner periphery side of the trench 104 by etching the inside of the trench 104. According to such a structure, the W3 can be controlled to an arbitrary length, and thus the value of the W3 can be adjusted to be optimal in comparison between the manufacturing cost and the resistance to melting of the SiC semiconductor device.

[0198] Further, according to the above-described embodiments, in the manufacturing method of the power conversion device, a conversion circuit 2201 that has the semiconductor device manufactured by the above-described manufacturing method and outputs converted power from input power is provided. Then, a drive circuit 2202 that outputs a drive signal for driving the semiconductor device to the semiconductor device is provided. Then, a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202 is provided. According to such a structure, when a high voltage is applied, the electric field at the bottom of the trench 104 of the termination region 12 is larger than the electric field at the bottom of the trench 102 of the cell region 11. Therefore, the breakdown of the gate insulating film 6 is likely to occur in the termination region 12 and is relatively difficult to occur in the cell region 11 in which a large current flows, and thus the heat generation at the breakdown site is suppressed, and as a result, the melting of the gate electrode 7 can be suppressed.

[0199] <Variations on the above-described embodiments>

[0200] In the above-described embodiments, the material, the material, the size, the shape, the relative arrangement relationship, or the conditions of implementation of each structural element are sometimes described, but they are one example in all the schemes and are not limiting.

[0201] Therefore, a large number of variations and equivalent schemes that are not illustrated can be assumed within the technical scope disclosed in the present application. For example, a case where at least one structural element is changed, a case where something is added or omitted, and a case where at least one structural element in at least one embodiment is extracted and combined with a structural element in another embodiment are included.

[0202] Further, in at least one embodiment described above, in a case where a material name or the like is described without being particularly specified, an alloy or the like including other additives in the material is included as long as there is no contradiction.

[0203] Further, in a case where "one" structural element is described in the above-described embodiment as long as there is no contradiction, "one or more" structural elements can be provided.

[0204] Further, each structural element in the above-described embodiment is a conceptual unit, and includes a case where one structural element is composed of a plurality of configurations, a case where one structural element corresponds to a part of a certain configuration, and a case where a plurality of structural elements are provided in one configuration within the technical scope disclosed in the present application.

[0205] Further, in each structural element in the above-described embodiment, a configuration having other configurations or shapes is included as long as the same function is exerted.

[0206] Further, the description in the present application is referred to for all purposes associated with the present technology, and is not considered as prior art.

[0207] Hereinafter, each aspect of the present disclosure is described as an appendix.

[0208] (Appendix 1)

[0209] A semiconductor device, wherein

[0210] The semiconductor device includes:

[0211] A SiC substrate of a first conductivity type;

[0212] A drift layer of a first conductivity type formed on an upper surface of the SiC substrate;

[0213] A base region of a second conductivity type different from the first conductivity type formed in a surface layer of the drift layer;

[0214] At least one first trench formed in a cell region in a manner reaching the drift layer from an upper surface of the base region;

[0215] A second trench formed in a termination region surrounding the cell region in a plan view in a manner reaching the drift layer from the upper surface of the base region;

[0216] A source region of the first conductivity type formed partially in a surface layer of the base region sandwiching the first trench;

[0217] a first gate electrode formed in the first trench surrounded by a gate insulating film;

[0218] at least one second gate electrode formed in the second trench surrounded by a gate insulating film;

[0219] an interlayer insulating film formed so as to cover the first gate electrode and the second gate electrode;

[0220] a source electrode formed so as to be in contact with the source region; and

[0221] a drain electrode formed on a lower surface of the SiC substrate opposite to the upper surface,

[0222] the first gate electrode and the second gate electrode are electrically connected,

[0223] the depth of the second trench is deeper than the depth of the first trench.

[0224] (Note 2)

[0225] The semiconductor device according to Note 1, in which

[0226] the width of the first trench in plan view is narrower than the width of the second trench in plan view.

[0227] (Note 3)

[0228] The semiconductor device according to Note 1 or 2, in which

[0229] in the case where an angle between a bottom surface and a side surface of the second trench of the terminal region is α, 90° < α is satisfied.

[0230] (Note 4)

[0231] The semiconductor device according to any one of Notes 1 to 3, in which

[0232] the second gate electrode is formed so as to be separated from a side surface on an inner periphery side of the second trench.

[0233] (Note 5)

[0234] The semiconductor device according to Note 4, in which

[0235] the second gate electrode includes a separate gate electrode formed so as to be separated from a side surface on an inner periphery side of the second trench, and a contact gate electrode formed so as to be in contact with the side surface on the inner periphery side of the second trench.

[0236] (Note 6)

[0237] The semiconductor device according to any one of the following notes 1 to 5,

[0238] The distance between the interlayer insulating film formed so as to cover the second gate electrode and the interlayer insulating film formed so as to cover the first gate electrode is larger than the distance between the interlayer insulating films formed so as to cover the first gate electrodes.

[0239] (Note 7)

[0240] The semiconductor device according to any one of the following notes 1 to 5,

[0241] The interlayer insulating film formed so as to cover the first gate electrode adjacent to the second gate electrode is connected to the interlayer insulating film formed so as to cover the second gate electrode.

[0242] (Note 8)

[0243] A power conversion device, wherein

[0244] The power conversion device comprises:

[0245] A conversion circuit having the semiconductor device according to claim 1 or 2, and outputs by converting an input power;

[0246] A drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and

[0247] A control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

[0248] (Note 9)

[0249] A method of manufacturing a semiconductor device, wherein

[0250] A drift layer of a first conductivity type is formed on an upper surface of a SiC substrate of the first conductivity type,

[0251] A base region of a second conductivity type different from the first conductivity type is formed in a surface layer of the drift layer,

[0252] A source region of the first conductivity type is locally formed in a surface layer of the base region,

[0253] At least one first groove is formed in the unit region in a manner reaching the drift layer from an upper surface of the source region,

[0254] A second groove is formed in a termination region surrounding the unit region in plan view in a manner reaching the drift layer from the upper surface of the source region,

[0255] In the first trench, a first gate electrode is formed so as to be surrounded by a gate insulating film,

[0256] In the second trench, at least one second gate electrode is formed so as to be surrounded by a gate insulating film,

[0257] An interlayer insulating film is formed so as to cover the first gate electrode and the second gate electrode,

[0258] A source electrode is formed so as to be in contact with the source region,

[0259] A drain electrode is formed on a lower surface of the SiC substrate which is opposite to the upper surface,

[0260] The first gate electrode and the second gate electrode are electrically connected,

[0261] The depth of the second trench is deeper than the depth of the first trench.

[0262] (Addendum 10)

[0263] The manufacturing method of the semiconductor device according to Addendum 9, wherein

[0264] The forming of the first trench means that the first trench is formed using a first mask,

[0265] The forming of the second trench means that the second trench is formed using a second mask which is different from the first mask.

[0266] (Addendum 11)

[0267] The manufacturing method of the semiconductor device according to Addendum 9 or 10, wherein

[0268] The forming of the second gate electrode means that the second gate electrode is formed so as to be separated from a side surface of an inner periphery side of the second trench by etching the inside of the second trench.

[0269] (Addendum 12)

[0270] The manufacturing method of the semiconductor device according to Addendum 11, wherein

[0271] The forming of the second gate electrode means that the second gate electrode is formed so as to be separated from a side surface of an inner periphery side of the second trench by dry etching the inside of the second trench and then removing the second gate electrode which is in contact with the side surface of the inner periphery side of the second trench by dry etching or wet etching.

[0272] (Addendum 13)

[0273] A manufacturing method of a power conversion device, wherein

[0274] A conversion circuit is provided with the semiconductor device manufactured by the manufacturing method described in any one of the above-mentioned Embodiments 9 to 12, and converts and outputs an input power,

[0275] A drive circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device is provided,

[0276] A control circuit for outputting a control signal for controlling the drive circuit to the drive circuit is provided.

[0277] Explanation of Reference Signs

[0278] 1 SiC substrate, 2 drift layer, 3 base region, 4 source region, 5 base region, 6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 source electrode, 10 drain electrode, 11 cell region, 12 terminal region, 13 mask, 14 mask, 15 mask, 15A mask, 16 mask, 17 mask, 18 mask, 18A inclined surface, 19 mask, 70 gate electrode, 71 gate electrode, 71A gate electrode, 72 electrode layer, 102 slot, 104 slot, 104A slot, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, 2300 load.

Claims

1. A semiconductor device, wherein, The semiconductor device includes: SiC substrate of the first conductivity type; A drift layer of the first conductivity type is formed on the upper surface of the SiC substrate; A base region of a second conductivity type, different from the first conductivity type, is formed on the surface of the drift layer; At least one first groove is formed in the cell region in such a manner that it extends from the upper surface of the base region into the drift layer; The second groove is formed in the terminal region surrounding the cell region when viewed from above, in such a way that it extends from the upper surface of the base region into the drift layer. The source region of the first conductivity type is locally formed by sandwiching the first trench in the surface layer of the base region; The first gate electrode is formed in the first trench in such a way that it is surrounded by a gate insulating film; At least one second gate electrode is formed within the second trench in such a manner that it is surrounded by a gate insulating film; An interlayer insulating film is formed covering the first gate electrode and the second gate electrode; A source electrode is formed in a manner that contacts the source region; as well as The drain electrode is formed on the lower surface of the SiC substrate, on the side opposite to the upper surface. The first gate electrode is electrically connected to the second gate electrode. The second groove is deeper than the first groove.

2. The semiconductor device according to claim 1, wherein, The width of the first slot when viewed from above is narrower than the width of the second slot when viewed from above.

3. The semiconductor device according to claim 1 or 2, wherein, When the angle between the bottom surface and the side surface of the second groove in the terminal region is α, 90° < α is satisfied.

4. The semiconductor device according to claim 1 or 2, wherein, The second gate electrode is formed in a manner that separates it from the side surface of the inner periphery of the second trench.

5. The semiconductor device according to claim 4, wherein, The second gate electrode includes a separation gate electrode formed in a manner separate from the side surface of the inner peripheral side of the second trench, and a contact gate electrode formed in a manner contacting the side surface of the inner peripheral side of the second trench.

6. The semiconductor device according to claim 1 or 2, wherein, The distance between the interlayer insulating film formed covering the second gate electrode and the interlayer insulating film formed covering the first gate electrode is greater than the distance between the interlayer insulating films formed covering the first gate electrode.

7. The semiconductor device according to claim 1 or 2, wherein, The interlayer insulating film formed covering the first gate electrode adjacent to the second gate electrode is connected to the interlayer insulating film formed covering the second gate electrode.

8. A power conversion device, wherein, The power conversion device includes: A conversion circuit having the semiconductor device as described in claim 1 or 2, and converting input power to output power; A driving circuit that outputs a driving signal for driving the semiconductor device to the semiconductor device; as well as A control circuit that outputs control signals for controlling the drive circuit to the drive circuit.

9. A method for manufacturing a semiconductor device, wherein, A drift layer of the first conductivity type is formed on the upper surface of the SiC substrate of the first conductivity type. A base region of a second conductivity type, different from the first conductivity type, is formed on the surface of the drift layer. A source region of the first conductivity type is locally formed on the surface layer of the base region. At least one first trench is formed in the cell region in such a manner that it extends from the upper surface of the source region into the drift layer. In the terminal region surrounding the cell region when viewed from above, a second trench is formed such that it extends from the upper surface of the source region into the drift layer. Within the first trench, a first gate electrode is formed such that it is surrounded by a gate insulating film. Within the second trench, at least one second gate electrode is formed such that it is surrounded by a gate insulating film. An interlayer insulating film is formed by covering the first gate electrode and the second gate electrode. The source electrode is formed in a manner that contacts the source region. A drain electrode is formed on the lower surface, which is the side opposite to the upper surface of the SiC substrate. The first gate electrode is electrically connected to the second gate electrode. The second groove is deeper than the first groove.

10. The method of manufacturing a semiconductor device according to claim 9, wherein, Forming the first groove means forming the first groove using a first mask. Forming the second groove means forming the second groove using a second mask that is different from the first mask.

11. The method of manufacturing a semiconductor device according to claim 9 or 10, wherein, The second gate electrode is formed by etching the second trench to separate it from the inner peripheral side of the second trench.

12. The method of manufacturing a semiconductor device according to claim 11, wherein, Forming the second gate electrode means performing dry etching in the second trench, and then performing dry etching or wet etching to remove the second gate electrode that is in contact with the side surface of the inner periphery of the second trench, so as to form the second gate electrode in a manner that separates it from the side surface of the inner periphery of the second trench.

13. A method for manufacturing a power conversion device, wherein, A conversion circuit is provided, which has a semiconductor device manufactured by the manufacturing method of claim 9 or 10, and converts the input power to an output. The configuration allows the drive signal used to drive the semiconductor device to be output to the drive circuit of the semiconductor device. The control circuit is configured to output control signals used to control the drive circuit to the drive circuit.

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