Semiconductor air gap spacer and manufacturing method thereof

Abstract

Embodiments of the present disclosure advantageously provide semiconductor components, particularly fin field effect transistors (FinFETs), and methods of making such components with improved effective capacitance (Ceff). The FinFET includes a gate structure in which an air gap is provided by recessing a high dielectric constant material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high dielectric constant dielectric layer and improving the effective capacitance (Ceff) of the component.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to semiconductor components and methods of fabrication. More particularly, embodiments of the present disclosure are directed to field effect transistors (FETs) in which an air gap is provided by recessing a high dielectric constant material within a gate structure, thereby increasing the effective capacitance (Ceff) of the component. BACKGROUND

[0002] Transistors are the key components of most integrated circuits. Since the drive current of a transistor and thus the speed of the transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Thus, a tradeoff between transistor size and speed exists, and "fin" field effect transistors (FinFETs) have been developed to address the conflicting goals of a transistor with maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the footprint of the transistor, and are now being applied in many integrated circuits.

[0003] However, as the feature size of transistor components continues to shrink to achieve greater circuit density and higher performance, parasitic capacitance and off-state leakage become problematic. Thus, there is a need for improved transistor component designs and fabrication to allow further reduction in component size while reducing these negative effects. SUMMARY

[0004] One aspect of the present disclosure is directed to a semiconductor component, comprising a semiconductor stack disposed on a substrate; a metal gate structure disposed on a top surface of the semiconductor stack, the metal gate structure having a bottom surface, a top surface, and lateral side surfaces; a high dielectric constant dielectric layer disposed between the bottom surface of the metal gate structure and the top surface of the semiconductor stack, and on bottom portions of the lateral side surfaces of the metal gate structure; a spacer layer extending along the lateral side surfaces of the metal gate structure, wherein the spacer layer is separated from the lateral side surfaces of the metal gate structure by: (a) the high dielectric constant dielectric layer disposed between the spacer layer and the metal gate structure on the bottom portions of the lateral side surfaces of the metal gate structure, and (b) an air gap disposed between the spacer layer and the metal gate structure over the bottom portions of the lateral side surfaces of the metal gate structure; and a gate cap material disposed on the top surface of the metal gate structure, the gate cap material extending over the air gap but not into the air gap. The air gap provides a reduced effective dielectric constant between the lateral side surfaces of the metal gate structure and the spacer layer.

[0005] Another aspect disclosed is directed to a replacement metal gate structure for a semiconductor device, including a gate metal fill; at least one work function metal layer surrounding a bottom surface and lateral side surfaces of the gate metal fill; a high-k dielectric layer surrounding the bottom surface and a bottom portion of the lateral side surfaces of the gate metal fill, the at least one work function layer disposed between the high-k dielectric layer and the gate metal fill; a spacer layer extending along the lateral side surfaces of the gate metal fill, the high-k dielectric layer disposed between the spacer layer and the at least one work function layer at a bottom portion of the lateral side surfaces of the gate metal fill, and an air gap disposed between the spacer layer and the at least one work function layer over the high-k dielectric layer, the air gap providing a reduced effective dielectric constant in the high-k dielectric layer and increasing an effective capacitance of the semiconductor structure; and a gate cap material disposed between the spacer layer and extending along a top surface of the metal gate fill and over the air gap.

[0006] Another aspect disclosed is directed to a method of forming a semiconductor structure, the method including providing a semiconductor stack on a surface of a substrate having a gate structure on a top surface of the semiconductor stack, a spacer structure along an outer lateral side of the gate structure, and a high-k dielectric layer disposed between the spacer structure and the gate structure; selectively removing at least a portion of the high-k dielectric layer to provide an opening between the spacer structure and the gate structure; and depositing a gate cap material on the top surface of the gate structure to block the opening and form an air gap between the spacer structure and the gate structure.

[0007] Another aspect disclosed is directed to a method of forming an air gap in a semiconductor structure, the method including providing a gate structure on a top surface of a semiconductor stack, the gate structure having a bottom surface, a top surface, and lateral side surfaces, a spacer structure extending along an outer lateral side of the gate structure, and a high-k dielectric layer disposed between the spacer structure and the gate structure along the outer lateral side of the gate structure; selectively removing at least a portion of the high-k dielectric layer to a depth along the outer lateral side of the gate structure between the top surfaces of the gate structure to provide an opening between the spacer structure and the gate structure; and depositing a gate cap material along the top surfaces of the gate structure and extending over the opening to block the opening and form an air gap between the spacer structure and the gate structure, the air gap providing a reduced effective dielectric constant in the high-k dielectric layer and increasing an effective capacitance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description, including certain embodiments, can be had by reference to the drawings. The drawings are for purposes of illustration only and are not intended to be limiting, as the scope of the disclosure can permit other effectively equivalent embodiments. The embodiments described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar components.

[0009] FIG. 1A Double cross-sectional views of a FinFET component having a dummy gate stack formed across a semiconductor stack are illustrated in accordance with one or more embodiments.

[0010] FIG. 1B Double cross-sectional views of a FinFET component having a dummy gate stack formed across a semiconductor stack are illustrated in accordance with one or more embodiments. FIG. 1A

[0011] FIG. 1C Double cross-sectional views of a FinFET component having a replacement metal gate (RMG) stack formed in accordance with one or more embodiments are illustrated. FIG. 1A

[0012] FIG. 1D Double cross-sectional views of a FinFET component having a replacement metal gate (RMG) stack formed in accordance with one or more embodiments are illustrated. FIG. 1C

[0013] FIG. 1E Double cross-sectional views of a FinFET component having a replacement metal gate (RMG) stack formed in accordance with one or more embodiments are illustrated. FIG. 1C

[0014] FIG. 1F Double cross-sectional views of a FinFET component having a replacement metal gate (RMG) stack formed in accordance with one or more embodiments are illustrated. FIG. 1E

[0015] FIG. 1G Double cross-sectional views of a FinFET component having a replacement metal gate (RMG) stack formed in accordance with one or more embodiments are illustrated. FIG. 1E

[0016] FIG. 1H Double cross-sectional views of a FinFET component having a replacement metal gate (RMG) stack formed in accordance with one or more embodiments are illustrated. FIG. 1G

[0017] FIG. 1I ​​​​​​​A cross-sectional view of a FinFET assembly according to one or more embodiments is shown after a cap layer has been disposed over a replacement metal gate (RMG) stack. FIG. 1G A cross-sectional view of a FinFET assembly according to one or more embodiments is shown after a cap layer has been disposed over a replacement metal gate (RMG) stack.

[0018] FIG. 1J A cross-sectional view of a FinFET assembly according to one or more embodiments is shown after a cap layer has been disposed over a replacement metal gate (RMG) stack. FIG. 1I A cross-sectional view of a FinFET assembly according to one or more embodiments is shown after a cap layer has been disposed over a replacement metal gate (RMG) stack.

[0019] FIG. 2 A cross-sectional view of a FinFET assembly according to one or more embodiments is shown after a cap layer has been disposed over a replacement metal gate (RMG) stack.

[0020] FIG. 3 A cross-sectional view of a FinFET assembly according to one or more embodiments is shown after a cap layer has been disposed over a replacement metal gate (RMG) stack. DETAILED DESCRIPTION

[0021] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0022] The term "about" as used herein means approximate or nearly and in the context of a stated value or range means a variation within ±15% or less of the value. For example, values that differ by ±14%, ±13%, ±12%, ±11%, ±10%, ±9%, ±8%, ±7%, ±6%, ±5%, ±4%, ±3%, ±2%, or ±1% would meet the definition of about.

[0023] As used in this specification and the appended claims, the terms "substrate" and "wafer" mean a surface or a portion thereof upon which is performed a process. Those skilled in the art will appreciate that references to a substrate can be taken merely to mean a portion of a substrate unless the context clearly indicates otherwise. Additionally, references to a substrate upon which a deposition is made can mean a bare substrate and a substrate having one or more films or features deposited or formed thereon. As used herein, "substrate" means any substrate or material surface formed on a substrate upon which film processing is performed during the fabrication of integrated devices. For example, the substrate surface upon which processing is performed can include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, any other suitable conductive material, and any other material, such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, without limitation, semiconductor wafers. Substrates can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, as described in more detail below in the disclosure, any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0024] The term "on" indicates that there is direct contact between components. The term "directly on" indicates that there is direct contact between components without intervening components.

[0025] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to mean any gaseous species that can react with a substrate surface.

[0026] "Epitaxy" is a process by which a deposited film is forced to achieve a high degree of crystallographic alignment with the substrate. Epitaxial growth is broadly defined as the condensation of gaseous precursors to form a film on a substrate. Liquid precursors can also be used. Gas phase precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. There are now several epitaxy techniques available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0027] Transistors are circuit components or elements that are often formed on semiconductor assemblies. Depending on the circuit design, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on semiconductor assemblies. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over a channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0028] As used herein, the term "field effect transistor" or "FET" represents a transistor that uses an electric field to control the electrical behavior of the element. A field effect transistor is a voltage-controlled element whose current-carrying capacity is changed by the application of an electric field. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain terminal and the source terminal is controlled by the electric field in the element, which is generated by the voltage difference between the body of the element and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which is the terminal that modulates the conductivity of the channel. The current entering the channel at the source (S) is conventionally denoted as IS, and the current entering the channel at the drain (D) is denoted as ID. The drain-to-source voltage is denoted as VDS. By applying a voltage to the gate (G), the current into the channel at the drain (i.e., ID) can be controlled.

[0029] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field effect transistor (FET) and is used in integrated circuits and high-speed switching applications. MOSFETs have an insulating gate whose voltage determines the conductivity of the element. This ability to vary conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulating the charge density by a metal-oxide-semiconductor (MOS) capacitor between the body electrode and the gate electrode, which is positioned above the body and insulated from all other element regions by a gate dielectric layer. In comparison to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate heavily doped region separated by a body region. These regions can be p-type or n-type, but they are both of the same type and of the opposite type as the body region. The source and drain (unlike the body) are heavily doped, as indicated by the "+" sign after the doping type.

[0030] If the MOSFET is n-channel or nMOS FET, the source and drain are n+ regions, and the body is a p-type substrate region. If the MOSFET is p-channel or pMOS FET, the source and drain are p+ regions, and the body is an n-type substrate region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers exit the channel.

[0031] An nMOS FET is constructed of n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is carried by electrons from the source to the drain via the induced n-type channel. Logic gates and other digital components implemented using NMOS are said to have NMOS logic. There are three modes of operation in NMOS, called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate static power when the circuit is idle, because DC current flows through the logic gate when the output is low.

[0032] A pMOS FET is constructed of p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (a negative voltage between the gate and source), a p-type channel of opposite polarity forms between the source and drain. Current is carried by holes from the source to the drain via the induced p-type channel. Logic gates and other digital components implemented using PMOS are said to have PMOS logic. PMOS technology is low cost and has good noise immunity.

[0033] In NMOS, the charge carriers are electrons, and in PMOS, the charge carriers are holes. When a high voltage is applied to the gate, NMOS will turn on, and PMOS will not turn on. Also, when a low voltage is applied in the gate, NMOS will not turn on, and PMOS will turn on. NMOS is considered faster than PMOS because the charge carriers in NMOS, which are electrons, travel twice as fast as holes, which are the charge carriers in PMOS. But PMOS components are more noise immune than NMOS components. Also, NMOS ICs will be smaller than PMOS ICs (which provide the same functionality) because NMOS can provide half the impedance that PMOS (which has the same geometry and operating conditions) can provide.

[0034] As used herein, the term "FinFET" stands for a MOSFET transistor built on a substrate with the gate placed on two, three, or four sides of the channel or wrapped around the channel, forming a double-gate structure. FinFET components have been given the generic name FinFET because the source / drain regions form a "fin" on the substrate. FinFET components have fast switching times and high current densities.

[0035] As used herein, the term "gate all-around (GAA)" is used to represent an electronic component, such as a transistor, in which the gate material surrounds all sides of a channel region. The channel region of a GAA transistor can include nanowires or nanosheets or nanoslices, strip channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA component has multiple horizontal nanowires or horizontal strips spaced vertically apart, such that the GAA transistor is a stacked horizontal gate-all-around (hGAA) transistor.

[0036] As used herein, the term "complementary field-effect transistor (CFET)" represents a transistor that includes an NMOS FET component and a PMOS FET component stacked on each other. Each of the NMOS FET component and the PMOS FET component forming the CFET is a GAA transistor or a hGAA transistor.

[0037] As used herein, the term "nanowire" represents a nanostructure having a diameter on the order of a nanometer (10 -9 A nanowire can also be defined as having a ratio of length to width greater than 1000. Alternatively, a nanowire can be defined as a structure having a thickness or diameter constrained to tens of nanometers or less and an unconstrained length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) components. As used herein, the term "nanosheet" represents a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm, or from 0.5 nm to 500 nm, or from 0.5 nm to 100 nm, or from 1 nm to 500 nm, or from 1 nm to 100 nm, or from 1 nm to 50 nm.

[0038] As used herein, the term "dielectric constant (K) value," also known as the permittivity, is a measure of the degree to which a material concentrates an electric flux. In electronic devices, the "dielectric constant value" represents the capacitance of a material relative to silicon dioxide. A "high dielectric constant value" or "high-k" dielectric generally represents a material having a higher dielectric constant than silicon dioxide, and is typically greater than about 3.9, and can be greater than about 7.0. A "low dielectric constant value" or "low-k" dielectric generally represents a material having a lower dielectric constant than silicon dioxide, and is typically less than about 3.9, and can be less than about 3.

[0039] As semiconductor component sizes continue to shrink, it is necessary to increase design complexity to maintain component performance. FinFET structures provide improved short channel performance over previous planar structures, but as component sizes decrease, parasitic capacitance from gate-to-source / drain capacitance and gate-to-source / drain contact capacitance has become increasingly problematic. Generally, the effective capacitance (Ceff) within a FinFET is dominated between the gate region and the contact region. Parasitic capacitance degrades component performance and occurs when parallel conductive lines are separated by a dielectric material. For example, in a transistor structure, the source and drain can be connected to vertical conductive material (e.g., conductive lines), and the gate can also be connected to vertical conductive material (e.g., conductive lines). These conductive materials can be two metal lines that extend parallel to each other and are separated by a dielectric material such as oxide. This structure can result in parasitic capacitance across the dielectric, which can slow component performance and increase power consumption.

[0040] Parasitic capacitance is dependent on the dielectric constant of the intervening material and the spacing between parallel conductive material structures (e.g., conductive lines). As component feature sizes shrink, there is less and less dielectric positioned between the conductive structures, which can increase parasitic capacitance. While the use of low dielectric constant materials is desirable to reduce parasitic capacitance, low dielectric constant materials suffer from undesirable leakage when thinned. For this reason, high dielectric constant materials have been used and are typically incorporated into replacement metal gate (RMG) structures in an effort to achieve further size reduction without increasing undesirable leakage, but at the cost of increasing parasitic capacitance.

[0041] According to one or more embodiments, semiconductor components and methods of fabrication are provided in which component performance, particularly effective capacitance (Ceff), is improved by reducing the effective dielectric constant of one or more material layers forming the semiconductor component. Common dielectric materials include silicon dioxide with a dielectric constant of about 3.9. This dielectric constant can not sufficiently overcome more closely spaced parallel conductive lines. Air is characterized by a dielectric constant of about 1.

[0042] According to one or more embodiments, a semiconductor device and manufacturing method are provided, wherein parasitic capacitance is reduced by decreasing the effective dielectric constant of one or more material layers of a replacement metal gate (RMG) structure between the source and drain regions. According to one or more embodiments, air gaps are disposed in or along the RMG stack to reduce parasitic capacitance and thus increase Ceff. According to one or more embodiments, one or more RMG stacks within a FinFET structure include a high-dielectric-constant dielectric layer disposed along the outer lateral side of the RMG stack, and the high-dielectric-constant dielectric layer is selectively etched to form one or more air gaps within the RMG stack, thereby reducing the effective dielectric constant of the high-dielectric-constant layer.

[0043] FIGS. 1A-1J This is a double cross-sectional view of the various stages of forming a FinFET component according to one or more embodiments. FIG. 1A As shown, the initial FinFET structure 100 is fabricated to have a dummy gate structure 110 formed on the top surface of a semiconductor stack 113 provided on a substrate 115. The semiconductor stack 113 and the dummy gate structure 110 can be formed using any known methods and materials. Furthermore, although... FIG. 1A A view is depicted in which three dummy gate structures 110 are formed on top of a semiconductor stack 113 having three fin structures 117, but this is only an example. Embodiments may provide any number of dummy gates 110 and fin structures 117. Furthermore, although the semiconductor stack 113 is depicted as having a certain number of layers directly disposed on the surface of the substrate 115, any number of layers may be provided, and may be disposed on the surface of the substrate 115 via one or more intermediate layers (not shown).

[0044] like FIG. 1B As shown more clearly, the dummy gate structure 110 is typically formed on the top layer 114 (e.g., a silicon layer) of the semiconductor stack 113 / fin structure 117 and typically comprises a polysilicon material 111. Although described herein as a polysilicon material, other suitable materials may alternatively be used in forming the dummy gate structure 110. Spacers 112 extend along the outer lateral side of the polysilicon material 111. The spacers 112 are formed of a dielectric material and may be formed of a high-dielectric-constant dielectric material (such as HfO2 and Si3N4) or a low-dielectric-constant dielectric material (such as SiOCN, SiOC, and SiO2). According to one or more embodiments, an oxide layer 119 is further disposed between the top layer 114 and the polysilicon material 111. The oxide layer 119 may be made of any suitable oxide material.

[0045] like FIG. 1CAs shown, a FinFET structure 200 is illustrated according to one or more embodiments after the dummy gate structure 110 is replaced with a replacement metal gate (RMG) structure 210. FIG. 1D An enlarged view of the RMG structure 210 is illustrated. It should be noted that while a certain number of layers and material types are shown and described in the formation of the RMG structure 210, this is not intended to be limiting. Additional layers may be added and / or one or more of the described layers may be eliminated according to known manufacturing and design practices for the RMG structure 210. As shown, according to one or more embodiments, the polysilicon material 111 forming the dummy gate structure 110 is removed by etching or other suitable removal processes, thereby leaving grooves between the spacers 112. FIG. 1D As shown, oxide layer 119 is also removed, or in some embodiments, oxide layer 119 may be retained. As... FIGS. 1C-1D In the illustrated embodiment, after the oxide layer 119 is removed, a gate oxide layer 121 is deposited on the top layer 114 (e.g., a silicon layer) of the semiconductor stack 113 / fin structure 117. According to one or more embodiments, the gate oxide layer 121 comprises one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon oxycarbide (SiOC). A high-dielectric-constant dielectric layer 116 is deposited over the gate oxide layer 121 and laterally along the interior of the spacer 112 (e.g., ...). FIG. 1D (Depicted in the view shown) Surface extension. According to one or more embodiments, the high-dielectric-constant dielectric layer 116 has a dielectric constant greater than about 10. In some embodiments, the high-dielectric-constant dielectric layer 116 comprises a metal oxide and may include one or more of hafnium oxide, zirconium oxide, aluminum oxide, nitrides thereof, and combinations thereof. According to one or more embodiments, one or more work function metals (WFM) 120 are layered in the RMG structure 210. The work function metals 120 may advantageously be incorporated to tune the threshold voltage (V). t The material may include, for example, one or more of TiN, TiAlC, and TaN. Gate metal filler 118 is then deposited to form an RMG structure 210 within the groove left by the dummy gate polysilicon material 111.

[0046] According to an embodiment, after formation, the RMG structure 210 undergoes chemical mechanical planarization (CMP) and is recessed to form a vertical cavity 124, for example, as shown in the example. FIGS. 1E-1F As shown. According to one or more embodiments, during the recess of the CMP and RMG structures 210, the high dielectric constant dielectric layer 116 is maintained laterally along the interior of the spacer 112 (e.g., preferably in...). FIG. 1F(As seen in the view shown) the appropriate location of the surface extension.

[0047] According to one or more embodiments, the high-dielectric-constant dielectric layer 116 is selectively removed to expose the inner surface of the spacer 112 and form an opening 126 between the recessed RMG structure 210 and the spacer 112. FIGS. 1G-1H The resulting structure is illustrated in the figure. According to an embodiment, the removal of the high dielectric constant dielectric layer 116 can be controlled to the desired depth based on component specifications and requirements.

[0048] like FIGS. 1A-1J As shown, gate cap material 128 is deposited within the vertical cavity 124 onto the surface of the recessed RMG structure 210 without entering the opening 126 to clamp or block the opening 126 and form an air gap 130. By forming the air gap 130 in the recessed region of the high-dielectric-constant dielectric layer 116, the effective dielectric constant is reduced by incorporating air (which has a dielectric constant of 1) into the removed portion of the high-dielectric-constant dielectric material layer, thereby improving the Ceff of the semiconductor device.

[0049] FIG. 2 The icons for various finned / gate structures of capacitor components are marked. C-mol refers to the capacitance caused by the spacer structure and its contact with the transistor source / drain. This component can usually be improved by using a lower dielectric constant dielectric material and a thicker spacer. C-do refers to the capacitance caused by direct overlap between the gate and the substrate, and can usually be improved by using a lower dielectric constant dielectric material and a thicker spacer. C-epi refers to the capacitance caused by gate EPI, and can usually be improved by using a lower dielectric constant dielectric material and a thicker spacer. C-Ox refers to the capacitance caused by the channel-gate dielectric, and can usually be improved by reducing the effective oxide thickness (EOT). With specific design, these capacitor components can be improved to positively impact Ceff.

[0050] According to one or more embodiments, at least a portion of the high dielectric constant dielectric layer 116 is removed and clamped or closed to form an air gap 130. FIG. 3The impact of various capacitive components on Ceff as the high-k dielectric layer 116 is recessed to different levels and replaced by air gaps is graphically illustrated in accordance with one or more embodiments. The first reference "Ref" bar depicts Ceff and individual capacitive components for a structure in which the high-k dielectric layer 116 has not been removed and no air gaps 130 are provided. The exemplary reference structure "Ref" shows a high-k dielectric layer 116 extending from the bottom to the top of the gate electrode with a total height of 25 nm, in which 0 nm is removed. Next, 7 nm of the high-k dielectric layer 116 has been removed, resulting in a 1% reduction in the impact on Ceff. Removing 12 nm of the high-k dielectric layer 116 results in a 2% reduction in the impact on Ceff. Removing 17 nm of the high-k dielectric layer 116 results in a 4% reduction in the impact on Ceff. Removing 24 nm of the high-k dielectric layer 116 results in a 7% reduction in the impact on Ceff. As demonstrated, once the removal depth reaches the recessed RMG structure 210 (e.g., 17 nm and 24 nm removal), the benefits of the high-k dielectric layer 116 become significant. As further demonstrated, C-Ox provides the largest impact on Ceff, followed by C-Epi, C-do, and C-Mol.

[0051] The effective capacitance within the chip (Ceff) is primarily between the gate and the contact area. Embodiments are provided in which the high-k dielectric layer disposed on the RMG sidewall is recessed and trapped or enclosed to form an air gap. The method of the present invention provides a simplified one-step process that effectively simplifies the component manufacturing flow and minimizes the reduction in Ceff. The component structure is further compatible with existing downstream processes. By forming an air gap within the RMG area, the capacitive reduction between the gate-contact (C-Mol), channel-gate dielectric (C-Ox), and gate-epitaxy (C-Epi) components of the total effective capacitance (Ceff) can be maximized.

[0052] For ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and terms of similar import, can be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the components in use or operation, in addition to the orientations depicted in the figures. For example, if a component or feature is depicted as being "below" or "beneath" another component or feature, it will be understood that, in some embodiments, the component or feature can be oriented above the other component or feature. Accordingly, the exemplary term "below" can encompass both an orientation of above and below. The components can be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein unless otherwise indicated herein or by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate materials and methods and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0054] Reference throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, appearances of the phrases, such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. In one or more embodiments, the particular feature, structure, material, or characteristic is combined in any suitable manner.

Claims

1. A semiconductor structure, comprising: A semiconductor stack disposed on a substrate; A metal gate structure is disposed on the top surface of the semiconductor stack, the metal gate structure having a bottom surface, a top surface and a lateral side surface; A high dielectric constant dielectric layer is disposed between the bottom surface of the metal gate structure and the top surface of the semiconductor stack, and on the bottom portion of the lateral side surfaces of the metal gate structure. A spacer layer extending along the lateral side surfaces of the metal gate structure, wherein the spacer layer is separated from the lateral side surfaces of the metal gate structure by: (a) a high dielectric constant dielectric layer disposed on the bottom portion of the lateral side surfaces of the metal gate structure between the spacer layer and the metal gate structure, and (b) an air gap disposed above the bottom portion of the lateral side surfaces of the metal gate structure between the spacer layer and the metal gate structure, the air gap providing a reduced effective dielectric constant between the lateral side surfaces of the metal gate structure and the spacer layer; as well as A gate cover material is disposed on the top surface of the metal gate structure, and the gate cover material extends above the air gap but does not extend into the air gap.

2. The semiconductor structure of claim 1, wherein the high dielectric constant dielectric layer has a dielectric constant greater than about 10.

3. The semiconductor structure of claim 1, wherein the high dielectric constant dielectric layer comprises a metal oxide.

4. The semiconductor structure of claim 3, wherein the high dielectric constant dielectric layer comprises one or more of hafnium oxide, zirconium oxide, aluminum oxide, and their nitrides.

5. The semiconductor structure of claim 1, wherein the spacers comprise a dielectric material.

6. The semiconductor structure of claim 5, wherein the spacers comprise a high dielectric constant dielectric material.

7. The semiconductor structure of claim 6, wherein the spacers comprise one or more of HfO2 and Si3N4.

8. The semiconductor structure of claim 5, wherein the spacers comprise a low dielectric constant dielectric material.

9. The semiconductor structure of claim 8, wherein the spacers comprise one or more of SiOCN, SiOC, and SiO2.

10. A replacement metal gate structure for a semiconductor component, comprising: Gate metal filler; At least one work function metal layer, the at least one work function metal layer surrounding the bottom surface and the lateral side surface of the gate metal filler; A high dielectric constant dielectric layer surrounds the bottom surface of the gate metal filler and the bottom portion of the lateral side surfaces, and the at least one work function layer is disposed between the high dielectric constant dielectric layer and the gate metal filler. A spacer layer extends along the lateral side surfaces of the gate metal filler, a high dielectric constant dielectric layer is disposed at the bottom portion of the lateral side surfaces of the gate metal filler between the spacer layer and the at least one work function layer, and an air gap is disposed above the high dielectric constant dielectric layer between the spacer layer and the at least one work function layer. as well as A gate cover material is disposed between the spacer layers and extends along the top surface of the metal gate filler and over the air gap.

11. The replacement metal gate structure as described in claim 10, wherein the high dielectric constant dielectric layer has a dielectric constant greater than about 10.

12. The alternative metal gate structure of claim 10, wherein the high dielectric constant dielectric layer comprises a metal oxide.

13. The alternative metal gate structure of claim 12, wherein the high dielectric constant dielectric layer comprises one or more of hafnium oxide, zirconium oxide, aluminum oxide, and their nitrides.

14. The replacement metal gate structure as claimed in claim 10, wherein the spacers comprise a dielectric material.

15. The replacement metal gate structure of claim 14, wherein the spacers comprise a high dielectric constant dielectric material.

16. The replacement metal gate structure as described in claim 15, wherein the spacers comprise one or more of HfO2 and Si3N4.

17. The replacement metal gate structure of claim 14, wherein the spacers comprise a low dielectric constant dielectric material.

18. The replacement metal gate structure of claim 17, wherein the spacers comprise one or more of SiOCN, SiOC, and SiO2.

19. A method for forming a semiconductor structure, the method comprising the following steps: A semiconductor stack is provided on the surface of a substrate, having a gate structure on the top surface of the semiconductor stack, a spacer structure extending along the outer lateral side of the gate structure, and a high dielectric constant dielectric layer disposed between the spacer structure and the gate structure. At least a portion of the high dielectric constant dielectric layer is selectively removed to provide an opening between the spacer structure and the gate structure; as well as A gate cap material is deposited on the top surface of the gate structure to block the opening and form an air gap between the spacer structure and the gate structure. This air gap provides a reduced effective dielectric constant in the high dielectric layer and increases the effective capacitance of the semiconductor structure.

20. The method of claim 19, At least a portion of the high dielectric constant dielectric layer extends from the top surface of the gate structure to the depth along the outer lateral sides of the gate structure, and the gate cap material extends along the top surface of the gate cap structure and over the opening.

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