A method for processing instruction pipeline of a processor and the processor

Abstract

The present disclosure provides a processor instruction pipeline processing method and a processor. A processor comprises a control module; the control module is configured to detect that a first instruction in preliminary decoding is a branch instruction, speculatively execute the branch instruction according to a branch prediction direction, and if a second instruction in preliminary decoding is detected before a result of the speculative execution of the first instruction is generated to be a function call instruction or a function return instruction, suspend all operations after preliminary decoding of the second instruction by an instruction processing pipeline and block an instruction fetching operation of a next instruction by the instruction processing pipeline until the result of the speculative execution of the first instruction is obtained; wherein the operations after preliminary decoding comprise stack or unstack operations of a return address stack (RAS) according to the second instruction. The technical solution herein can shield the pollution risk of the speculative execution of the branch instruction to the return address stack, thereby simplifying the hardware implementation logic of the return address stack, saving circuit area and power consumption.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, processor instruction pipeline technology, and more specifically, to a processor instruction pipeline processing method and a processor. Background Technology

[0002] To improve program execution performance, modern processor designs widely use branch prediction (BP) and return address stack (RAS) techniques.

[0003] Branch prediction is used to predict the outcome of branch instructions, speculatively executing subsequent instructions before obtaining the result of the current instruction. If the branch prediction is successful, the program flow is bubble-free, fully utilizing the efficiency of the pipeline; if the branch prediction is incorrect, the pipeline needs to be flushed, discarding the speculatively executed instructions, and then fetching and executing instructions from the correct target address. The return address stack technique is used to accelerate the execution efficiency of function calls and function returns. The return address stack stores the return address of a function call. During a function call, the corresponding return address is pushed onto the return address stack; during a function return, the target address is directly popped from the return address stack.

[0004] In scenarios where branch prediction and return address stack are used simultaneously, if the execution direction of the branch prediction is wrong, it is necessary not only to flush the instructions on the pipeline, but also to restore the internal stack and pointers of the return address stack to the correct state. This increases the complexity of the hardware, resulting in increased circuit area consumption and power consumption. Summary of the Invention

[0005] This disclosure provides a processor, including: a control module;

[0006] The control module is configured to: detect that the first instruction initially decoded is a branch instruction, speculatively execute the branch instruction according to the branch prediction direction; if the second instruction initially decoded is a function call instruction or a function return instruction is detected before the speculative execution result of the first instruction is generated, then suspend all operations of the instruction processing pipeline after the initial decoding of the second instruction and block the instruction processing pipeline from fetching the next instruction until the speculative execution result of the first instruction is obtained; wherein, the operations of the instruction processing pipeline after the initial decoding of the second instruction include: performing push or pop operations on the return address stack RAS according to the second instruction.

[0007] This disclosure provides an instruction pipeline processing method for a processor, the processor including a control module, the method comprising:

[0008] The control module detects that the first instruction in the initial decoding is a branch instruction, and speculatively executes the branch instruction according to the predicted branch direction;

[0009] If the control module detects that the second instruction, which is initially decoded, is a function call instruction or a function return instruction before the speculative execution result of the first instruction is generated, it will suspend all operations of the instruction processing pipeline after the initial decoding of the second instruction and block the instruction processing pipeline from fetching the next instruction until the speculative execution result of the first instruction is obtained.

[0010] The operations performed by the instruction processing pipeline after the initial decoding of the second instruction include: performing push or pop operations on the return address stack (RAS) according to the second instruction.

[0011] The processor and instruction pipeline processing method provided in this disclosure include a control module that detects that the first instruction initially decoded is a branch instruction and performs speculative execution of the branch instruction according to the direction of branch prediction. If, before the speculative execution result of the first instruction is generated, the second instruction initially decoded is detected to be a function call instruction or a function return instruction, then all operations after the initial decoding of the second instruction in the instruction processing pipeline are suspended, and the instruction fetch operation for the next instruction in the instruction processing pipeline is blocked until the speculative execution result of the first instruction is obtained. The operations after the initial decoding of the second instruction in the instruction processing pipeline include: pushing or popping the return address stack (RAS) according to the second instruction. That is, by blocking the related operations (including pushing or popping the return address stack) of the instruction processing pipeline on the function call instruction or function return instruction before obtaining the speculative execution result of the branch instruction, the control module can ensure that the return address stack is not polluted when a branch prediction error occurs (shielding the risk of pollution to the return address stack caused by the speculative execution of the branch instruction), thereby simplifying the hardware implementation logic of the return address stack and saving circuit area and power consumption.

[0012] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0013] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0014] Figure 1 This is a schematic diagram of the structure of a processor according to an embodiment of the present disclosure;

[0015] Figure 2 This is a schematic diagram of the structure of a control module according to an embodiment of the present disclosure;

[0016] Figure 3 This is a schematic flowchart of an instruction pipeline processing method for a processor according to an embodiment of the present disclosure. Detailed Implementation

[0017] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0018] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0019] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0020] Processor pipelined operation is a technique to improve CPU efficiency by processing instructions in parallel, similar to the division of labor on a factory assembly line. Instruction pipelined processing transforms a serial sequence of instructions into a parallel processing chain that overlaps in time and is hierarchically distributed in space, thereby increasing throughput. It breaks down the execution process of an instruction into multiple stages, each handled by a dedicated hardware unit. Different stages of different instructions can overlap in execution, thus increasing throughput. A pipelined architecture includes at least the following stages: Fetch (IF), Decode (ID), Execute (EX), Memory Access (MEM), and Write-Back (WB). The Fetch stage reads the instruction from memory into the instruction register. The Decode stage parses the instruction, determining the operation type and operands (such as register reads). The Execute stage performs arithmetic / logical operations using the ALU (Arithmetic Logic Unit) or calculates the memory address of the load / store instruction using the LSU (Load / Store Unit). The Memory Access stage accesses memory (only valid for instructions that require reading or writing memory, such as load / store instructions). The write-back phase writes the result back to the register.

[0021] Figure 1 A schematic diagram of a processor structure is shown. For example... Figure 1 As shown, one embodiment of this disclosure provides a processor, including: a control module;

[0022] The control module is configured to: detect that the first instruction initially decoded is a branch instruction, speculatively execute the branch instruction according to the branch prediction direction; if the second instruction initially decoded is a function call instruction or a function return instruction is detected before the speculative execution result of the first instruction is generated, then suspend all operations of the instruction processing pipeline after the initial decoding of the second instruction and block the instruction processing pipeline from fetching the next instruction until the speculative execution result of the first instruction is obtained; wherein, the operations of the instruction processing pipeline after the initial decoding of the second instruction include: performing push or pop operations on the return address stack RAS according to the second instruction.

[0023] In this embodiment, the processor control module detects that the first instruction initially decoded is a branch instruction and speculatively executes the branch instruction according to the branch prediction direction. If, before the speculative execution result of the first instruction is generated, the second instruction initially decoded is detected to be a function call instruction or a function return instruction, then all operations after the initial decoding of the second instruction in the instruction processing pipeline are paused, and the instruction processing pipeline's instruction fetch operation for the next instruction is blocked until the speculative execution result of the first instruction is obtained. The operations after the initial decoding of the second instruction in the instruction processing pipeline include: pushing or popping the return address stack (RAS) according to the second instruction. That is, by blocking the instruction processing pipeline's operations related to function call instructions or function return instructions (including pushing or popping the return address stack) before obtaining the speculative execution result of the branch instruction, the control module can ensure that the return address stack is not polluted when a branch prediction error occurs (shielding the risk of pollution to the return address stack caused by the speculative execution of branch instructions), thereby simplifying the hardware implementation logic of the return address stack and saving circuit area and power consumption.

[0024] Branch instructions are instructions that, during program execution, determine whether to change the program counter (PC) based on conditions generated at runtime (such as ALU flags or register comparison results). If the condition is met, execution jumps to the specified target address to continue (Take); otherwise, the next instruction is executed sequentially (Not-taken).

[0025] In one exemplary embodiment of this disclosure, the initial decoding is performed by classifying instructions according to their usage of pipeline resources during the instruction fetch stage of the instruction pipeline.

[0026] The instructions initially decoded are categorized as follows: control transfer instructions;

[0027] Control transfer instructions include: unconditional jump instructions, branch instructions, call instructions, or return instructions.

[0028] The instruction classification for initial decoding also includes: arithmetic instructions, memory access instructions, and system instructions.

[0029] These include arithmetic instructions such as integer arithmetic instructions and floating-point arithmetic instructions; memory access instructions such as load instructions and store instructions; and system instructions such as instructions for managing CPU state and instructions for handling instruction stream exceptions.

[0030] Instruction fetch (IF) can include multiple sub-operations (which can be executed in parallel or overlapped within a single cycle). These sub-operations include, for example, determining the program counter (PC) value for the next instruction to be executed, address translation, and initial decoding.

[0031] In an exemplary embodiment of this disclosure, the control module is further configured to: suspend all operations of the instruction processing pipeline after the initial decoding of the second instruction and block the instruction processing pipeline from fetching the next instruction until the speculative execution result of the first instruction is obtained; if it is determined that the speculative execution result of the first instruction is an incorrect speculative execution direction, then perform a flushing operation on the instruction processing pipeline. Flushing the instruction processing pipeline means invalidating all instructions on the entire "erroneous path" (branch prediction path) that has been speculatively fetched, decoded, or even partially executed, and resetting the pipeline to the correct branch address for re-fetching instructions.

[0032] In an exemplary embodiment of this disclosure, the control module is further configured to: suspend all operations of the instruction processing pipeline after the initial decoding of the second instruction and block the instruction processing pipeline from fetching the next instruction until the speculative execution result of the first instruction is obtained; if it is determined that the speculative execution result of the first instruction is correct in the speculative execution direction, then resume all operations of the instruction processing pipeline after the initial decoding of the second instruction and the fetching operation of the next instruction.

[0033] In this embodiment, the speculative execution result of a branch instruction includes: the speculative execution direction of the branch instruction is correct (correct branch prediction) or the speculative execution direction of the branch instruction is incorrect (incorrect branch prediction). When a branch prediction error occurs, the control module can flush the instruction processing pipeline to remove function call instructions or function return instructions that should not be executed, thus avoiding pollution of the return address stack by these instructions. This eliminates the need for complex logic to restore the contents and stack pointer of the return address stack, simplifying the hardware implementation logic of the return address stack. When a branch prediction is correct, the control module restores the instruction processing pipeline's processing of the function call instructions or function return instructions that need to be executed, as well as the instruction fetch operation for the next instruction, ensuring the normal operation of the instruction processing pipeline.

[0034] Figure 2 A schematic diagram of a control module is shown. Figure 2 As shown in an exemplary embodiment of this disclosure, the control module includes: an instruction fetch unit, a branch prediction unit, a branch monitoring unit, a return address stack processing unit, a decoding unit, an execution unit, and a counter;

[0035] The instruction fetch unit is configured to periodically fetch the next target instruction to be executed. If the counter is 0, the instruction fetch operation for the target instruction is executed normally, and the fetched target instruction is sent to the decoding unit. If the counter is not 0, the instruction fetch operation for the target instruction is paused when the result of the initial decoding determines that the target instruction is a function call instruction or a function return instruction. During the instruction fetch operation for the target instruction, if the result of the initial decoding determines that the target instruction is a branch instruction, a first enable signal is sent to the branch monitoring unit, and the target instruction is sent to the branch prediction unit. The next target instruction to be executed is determined according to the predicted branch execution direction. The instruction fetch operation includes an initial decoding operation and other operations to prepare for instruction decoding.

[0036] The branch prediction unit is configured to: predict the speculative execution direction of the received target instruction and feed back the predicted branch execution direction to the instruction fetching unit; wherein, the target instruction is a branch instruction;

[0037] The branch monitoring unit is configured to: upon receiving the first enable signal, increment the counter value by 1; upon receiving the speculative execution result of the branch instruction from the execution unit, decrement the counter value by 1 if the speculative execution direction is correct; and clear the counter value to 0 and flush the instruction processing pipeline if the speculative execution direction is incorrect.

[0038] The decoding unit is configured to: perform decoding operations on the received target instruction and send the decoded target instruction to the execution unit;

[0039] The execution unit is configured to: perform an execution operation on the received target instruction; when the target instruction is a branch instruction, determine the speculative execution result of the branch instruction and feed it back to the branch monitoring unit;

[0040] The counter value is initialized to 0 before the instruction fetch unit first fetches the target instruction.

[0041] In this embodiment, the control module includes multiple functional units: an instruction fetch unit, a branch prediction unit, a branch monitoring unit, a return address stack processing unit, a decoding unit, an execution unit, and a counter. These functional units are located at different stages of the instruction processing pipeline and execute in parallel. The instruction processing pipeline transforms a serial sequence of instructions into a parallel processing chain that overlaps in time and is hierarchically arranged in space, thereby improving throughput. It breaks down the execution process of an instruction into multiple stages, each of which is handled by a dedicated hardware unit. Different stages of different instructions can be executed overlappingly, thereby increasing throughput.

[0042] In this embodiment, the branch monitoring unit transmits relevant information about branch instructions (including the speculative execution status and result of the branch instruction) to the instruction fetch unit via a write counter. The instruction fetch unit determines whether it is in the speculative execution state of the branch instruction by reading the counter. When it is determined to be in the speculative execution state of the branch instruction (counter is not 0), it suspends all operations after the initial decoding of the call instruction or return instruction in the instruction processing pipeline and blocks the instruction fetch operation for the next instruction until the branch instruction is completed. Through the cooperation of multiple functional units, the control module can avoid the pollution of the return address stack by the speculative execution of branch instructions, simplify the hardware implementation logic of the return address stack, and save circuit area and power consumption.

[0043] In related technologies, when a program contains conditional branches and function calls occur within the branch structure, branch prediction and the return address stack are activated simultaneously. This is particularly problematic when conditional branches and function calls are nested; if branch prediction for a particular branch instruction fails, the recovery logic for the return address stack becomes extremely complex. This disclosure, however, uses a dedicated branch monitoring unit to collect various information (branch instruction fetch information and branch instruction execution result information). It utilizes counter increment / decrement logic to reflect the completion status of branch instructions. If the counter is non-zero, it indicates that there are still unexecuted branch instructions in the instruction processing pipeline. In this case, call or return instructions need to be delayed, thus avoiding the risk of polluting the return address stack due to speculative branch instruction execution. The embodiments of this disclosure, when faced with complex intertwined branch and call instructions, employ clever counter logic and a delayed fetch strategy, simplifying the hardware implementation of the return address stack and shielding it from the risks of branch prediction failures.

[0044] Figure 3 A flowchart illustrating a processor instruction pipeline processing method is shown. Figure 3 As shown, one embodiment of this disclosure provides a method for instruction pipeline processing of a processor, the processor including a control module, the method including:

[0045] Step S10: The control module detects that the first instruction of the initial decoding is a branch instruction, and speculatively executes the branch instruction according to the direction of the branch prediction.

[0046] Step S20: If the control module detects that the second instruction that has been initially decoded is a function call instruction or a function return instruction before the speculative execution result of the first instruction is generated, then it suspends all operations after the initial decoding of the second instruction in the instruction processing pipeline and blocks the instruction processing pipeline from fetching the next instruction until the speculative execution result of the first instruction is obtained.

[0047] The operations performed by the instruction processing pipeline after the initial decoding of the second instruction include: performing push or pop operations on the return address stack (RAS) according to the second instruction.

[0048] In the processor instruction pipeline processing method of this embodiment, the control module detects that the first instruction initially decoded is a branch instruction, and speculatively executes the branch instruction according to the direction of branch prediction. If, before the speculative execution result of the first instruction is generated, the second instruction initially decoded is detected to be a function call instruction or a function return instruction, then all operations after the initial decoding of the second instruction in the instruction processing pipeline are paused, and the instruction fetch operation for the next instruction in the instruction processing pipeline is blocked until the speculative execution result of the first instruction is obtained. The operations after the initial decoding of the second instruction in the instruction processing pipeline include: pushing or popping the return address stack (RAS) according to the second instruction. That is, by blocking the related operations (including pushing or popping the return address stack) of the instruction processing pipeline for function call instructions or function return instructions before obtaining the speculative execution result of the branch instruction, the control module can ensure that the return address stack is not polluted when a branch prediction error occurs (shielding the pollution risk brought by the speculative execution of the branch instruction to the return address stack), thereby simplifying the hardware implementation logic of the return address stack and saving circuit area and power consumption.

[0049] In an exemplary embodiment of this disclosure, the control module suspends all operations after the initial decoding of the second instruction by the instruction processing pipeline and blocks the instruction fetch operation of the instruction processing pipeline for the next instruction until the speculative execution result of the first instruction is obtained. The method further includes:

[0050] If it is determined that the speculative execution result of the first instruction is an incorrect speculative execution direction, then a flushing operation is performed on the instruction processing pipeline.

[0051] In an exemplary embodiment of this disclosure, the control module suspends all operations after the initial decoding of the second instruction by the instruction processing pipeline and blocks the instruction fetch operation of the instruction processing pipeline for the next instruction until the speculative execution result of the first instruction is obtained. The method further includes:

[0052] If it is determined that the speculative execution result of the first instruction is that the speculative execution direction is correct, then all operations after the initial decoding of the second instruction in the instruction processing pipeline, as well as the instruction fetch operation for the next instruction, are resumed.

[0053] In an exemplary embodiment of this disclosure, the control module includes: an instruction fetch unit, a branch prediction unit, a branch monitoring unit, a return address stack processing unit, a decoding unit, an execution unit, and a counter;

[0054] The control module detects that the first instruction in the initial decoding is a branch instruction, and speculatively executes the branch instruction according to the predicted branch direction. If, before the speculative execution result of the first instruction is generated, the second instruction in the initial decoding is detected to be a function call instruction or a function return instruction, then all operations after the initial decoding of the second instruction in the instruction processing pipeline are paused, and the instruction processing pipeline's instruction fetch operation for the next instruction is blocked until the speculative execution result of the first instruction is obtained, including:

[0055] The instruction fetch unit periodically fetches the next target instruction to be executed. If the counter is 0, the instruction fetch operation for the target instruction is executed normally, and the fetched target instruction is sent to the decoding unit. If the counter is not 0, the instruction fetch operation for the target instruction is paused when the result of the initial decoding determines that the target instruction is a function call instruction or a function return instruction. During the instruction fetch operation for the target instruction, if the result of the initial decoding determines that the target instruction is a branch instruction, a first enable signal is sent to the branch monitoring unit, and the target instruction is sent to the branch prediction unit. The next target instruction to be executed is determined according to the predicted branch execution direction. The instruction fetch operation includes: initial decoding operation and other operations to prepare for instruction decoding.

[0056] The branch prediction unit performs speculative execution direction prediction on the received target instruction and feeds back the predicted branch execution direction to the instruction fetching unit; wherein, the target instruction is a branch instruction;

[0057] When the branch monitoring unit receives the first enable signal, it increments the counter value by 1; when it receives the speculative execution result of the branch instruction from the execution unit, if the speculative execution direction is correct, it decrements the counter value by 1; if the speculative execution direction is incorrect, it clears the counter value to 0 and flushes the instruction processing pipeline.

[0058] The decoding unit performs decoding operations on the received target instruction and sends the decoded target instruction to the execution unit.

[0059] The execution unit performs an execution operation on the received target instruction; when the target instruction is a branch instruction, it determines the speculative execution result of the branch instruction and feeds it back to the branch monitoring unit;

[0060] The counter value is initialized to 0 before the instruction fetch unit first fetches the target instruction.

[0061] In this embodiment, the control module includes multiple functional units: an instruction fetch unit, a branch prediction unit, a branch monitoring unit, a return address stack processing unit, a decoding unit, an execution unit, and a counter. These functional units are located at different stages of the instruction processing pipeline and execute in parallel. A dedicated branch monitoring unit collects various information (instruction fetch information for branch instructions, execution result information for branch instructions). The counter's increment / decrement logic reflects the completion status of branch instructions. If the counter is non-zero, it indicates that there are still unexecuted branch instructions in the instruction processing pipeline. In this case, call instructions or return instructions need to be delayed, thereby avoiding the risk of pollution to the return address stack that might result from the speculative execution of branch instructions.

[0062] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0063] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A processor, comprising: The processor comprises: a control module; the control module is configured to detect that a first instruction in preliminary decoding is a branch instruction, to perform the branch instruction in a speculative execution direction according to branch prediction, and to suspend all operations of the instruction processing pipeline after preliminary decoding of a second instruction which is a function call instruction or a function return instruction and to block fetch operation of a next instruction by the instruction processing pipeline until a result of the speculative execution of the first instruction is obtained; wherein the operations of the instruction processing pipeline after preliminary decoding of the second instruction include stack push or stack pop operation of a return address stack (RAS) according to the second instruction.

2. The processor of claim 1, wherein: the control module is further configured to, after suspending all operations of the instruction processing pipeline after preliminary decoding of the second instruction and blocking fetch operation of a next instruction by the instruction processing pipeline until a result of the speculative execution of the first instruction is obtained, flush the instruction processing pipeline if it is determined that the result of the speculative execution of the first instruction is in a wrong speculative execution direction.

3. The processor of claim 1, wherein: the control module is further configured to, after suspending all operations of the instruction processing pipeline after preliminary decoding of the second instruction and blocking fetch operation of a next instruction by the instruction processing pipeline until a result of the speculative execution of the first instruction is obtained, resume all operations of the instruction processing pipeline after preliminary decoding of the second instruction and fetch operation of a next instruction by the instruction processing pipeline if it is determined that the result of the speculative execution of the first instruction is in a correct speculative execution direction.

4. The processor of claim 1, wherein: the control module comprises a fetch unit, a branch prediction unit, a branch monitoring unit, a return address stack processing unit, a decoding unit, an execution unit and a counter; the fetch unit is configured to periodically obtain a target instruction to be executed next, to perform fetch operation of the target instruction normally and send the target instruction on which the fetch operation is completed to the decoding unit if the counter is 0, and to suspend fetch operation of the target instruction if it is determined according to a result of preliminary decoding that the target instruction is a function call instruction or a function return instruction; during the fetch operation of the target instruction, if it is determined according to a result of preliminary decoding that the target instruction is a branch instruction, a first enable signal is sent to the branch monitoring unit and the target instruction is sent to the branch prediction unit, and a next target instruction to be executed is determined according to a predicted branch execution direction; wherein the fetch operation includes preliminary decoding operation and other operations for preparing instruction decoding; the branch prediction unit is configured to perform speculative execution direction prediction on the received target instruction, and to feed back the predicted branch execution direction to the fetch unit; wherein the target instruction is a branch instruction. The branch monitoring unit is configured to: receive the first enabling signal, increase the count value of the counter by 1; receive the speculative execution result of the branch instruction fed back by the execution unit, if the speculative execution direction is correct, decrease the count value of the counter by 1; if the speculative execution direction is incorrect, clear the count value of the counter to 0, and flush the instruction processing pipeline; The decoding unit is configured to: perform a decoding operation on the received target instruction, and send the target instruction after the decoding operation to the execution unit; The execution unit is configured to: perform an execution operation on the received target instruction; when the target instruction is a branch instruction, determine a speculative execution result of the branch instruction and feed back to the branch monitoring unit; The count value of the counter is initialized to 0 before the instruction fetching unit first acquires the target instruction.

5. The processor of claim 1, wherein: The preliminary decoding is performed on the instructions in the instruction fetching stage of the instruction pipeline according to the manner in which the instructions occupy the pipeline resources; The instruction classification in the preliminary decoding includes control transfer type instructions.

6. A method of instruction pipeline processing of a processor, the method comprising: The processor comprises a control module, and the method comprises: The control module detects that a first instruction in the preliminary decoding is a branch instruction, and speculatively executes the branch instruction according to a branch prediction direction; If the control module detects that a second instruction in the preliminary decoding is a function call instruction or a function return instruction before the speculative execution result of the first instruction is generated, the control module suspends all operations of the instruction processing pipeline after the preliminary decoding of the second instruction and blocks the instruction fetching operation of the instruction processing pipeline on a next instruction until the speculative execution result of the first instruction is obtained; The operations of the instruction processing pipeline after the preliminary decoding of the second instruction include stack push or stack pop operations of a return address stack (RAS) according to the second instruction.

7. The method of claim 6, wherein, after the control module suspends all operations of the instruction processing pipeline after the preliminary decoding of the second instruction and blocks the instruction fetching operation of the instruction processing pipeline on a next instruction until the speculative execution result of the first instruction is obtained, the method further comprises: If the control module determines that the speculative execution result of the first instruction is a speculative execution direction error, the control module flushes the instruction processing pipeline.

8. The method of claim 6, wherein, after the control module suspends all operations of the instruction processing pipeline after the preliminary decoding of the second instruction and blocks the instruction fetching operation of the instruction processing pipeline on a next instruction until the speculative execution result of the first instruction is obtained, the method further comprises: If the control module determines that the speculative execution result of the first instruction is a correct speculative execution direction, the control module resumes all operations of the instruction processing pipeline after the preliminary decoding of the second instruction and the instruction fetching operation of the instruction processing pipeline on a next instruction.

9. The method of claim 6, wherein: The control module comprises an instruction fetching unit, a branch prediction unit, a branch monitoring unit, a return address stack processing unit, a decoding unit, an execution unit, and a counter. ​ ​ The control module detects that the first instruction in the preliminary decoding is a branch instruction, and speculatively executes the branch instruction according to a predicted branch execution direction; if it is detected that a second instruction in the preliminary decoding is a function call instruction or a function return instruction before the result of the speculative execution of the first instruction is obtained, all operations of the instruction processing pipeline after the preliminary decoding of the second instruction are suspended, and the instruction fetching operation of the next instruction by the instruction processing pipeline is blocked until the result of the speculative execution of the first instruction is obtained, including: The instruction fetching unit periodically acquires a target instruction to be executed next, if the counter is 0, the instruction fetching operation of the target instruction is normally performed, and the target instruction after the instruction fetching operation is completed is sent to the decoding unit, if the counter is not 0, the instruction fetching operation of the target instruction is suspended when it is determined according to the result of the preliminary decoding that the target instruction is a function call instruction or a function return instruction; during the instruction fetching operation of the target instruction, if it is determined according to the result of the preliminary decoding that the target instruction is a branch instruction, a first enable signal is sent to the branch monitoring unit, and the target instruction is sent to the branch prediction unit, and the next target instruction to be executed is determined according to the predicted branch execution direction; wherein the instruction fetching operation includes the preliminary decoding operation and other operations for preparing the instruction decoding; The branch prediction unit performs the speculative execution direction prediction on the received target instruction, and feeds back the predicted branch execution direction to the instruction fetching unit; wherein the target instruction is a branch instruction; The branch monitoring unit receives the first enable signal, and increases the count value of the counter by 1; receives the result of the speculative execution of the branch instruction fed back by the execution unit, if the speculative execution direction is correct, decreases the count value of the counter by 1; if the speculative execution direction is incorrect, clears the count value of the counter to 0, and flushes the instruction processing pipeline; The decoding unit performs the decoding operation on the received target instruction, and sends the target instruction after the decoding operation is completed to the execution unit; The execution unit performs the execution operation on the received target instruction; when the target instruction is a branch instruction, the result of the speculative execution of the branch instruction is determined and fed back to the branch monitoring unit; The count value of the counter is initialized to 0 before the target instruction is acquired by the instruction fetching unit for the first time.

10. The method of claim 6, wherein: The preliminary decoding is performed on the instructions according to the occupation mode of the instructions to the pipeline resources in the instruction fetching stage of the instruction pipeline; The instruction classification in the preliminary decoding includes the control transfer type instruction.

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