Integrated circuit layout verification method and apparatus thereof

Abstract

The application discloses an integrated circuit layout verification method and device, and belongs to the technical field of integrated circuit design. The method comprises the following steps: obtaining arrangement information of selected target units from an integrated circuit layout; performing out-expanding processing on to-be-detected metal lines of the target units according to design rule spacing requirements, and generating an auxiliary layer pattern; performing copy processing on the auxiliary layer pattern according to the arrangement information, and forming an auxiliary layer pattern set covering all target unit regions; performing Boolean operation on the auxiliary layer pattern set and global metal lines on the same layer, and generating an identification layer; when the identification layer is empty, it is determined that the to-be-detected metal lines meet the design rule spacing requirements; and when the identification layer is not empty, a spacing violation region indicated by the identification layer is output. The application realizes efficient and accurate spacing violation detection, and improves the automation degree and reliability of design rule checking.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, specifically to an integrated circuit layout verification method and apparatus. Background Technology

[0002] Design Rule Check (DRC) is a process of verifying integrated circuit layouts using pre-defined geometric dimensions and spacing rules to ensure that the layout meets manufacturing requirements. In existing technologies, memory layouts, due to their structure of numerous repeating array cells and global cells interspersed, suffer from the following problems with traditional DRC methods: (1) Full layout verification requires a complete check after each local modification, consuming significant computational resources and time; (2) Manual cell-by-cell inspection requires m×n repetitions for m×n arrays, resulting in low efficiency and potential omissions; (3) Using Layout Versus Layout (LVL) to filter discrepancies requires additional data conversion, extending the verification cycle; (4) Real-time DRC technology cannot automatically identify the detection range and lacks a dynamic rule update mechanism, making it difficult to meet the design requirements of rapid iteration in high-density memory layouts. Summary of the Invention

[0003] This application provides an integrated circuit layout verification method and apparatus, which aims to solve the problem of low efficiency in detecting violations of spacing between target cells (including independent cells and array cells) and global metal lines in integrated circuit layouts, and to achieve rapid and accurate location of design rule violations.

[0004] Firstly, a method for verifying integrated circuit layouts is provided, including:

[0005] Obtain the layout information of the selected target cell from the integrated circuit layout;

[0006] According to the design rules and spacing requirements, the metal lines to be detected in the target unit are expanded outward to generate an auxiliary layer pattern; the auxiliary layer pattern is copied according to the arrangement information to form an auxiliary layer pattern set covering all target unit areas;

[0007] Perform a Boolean operation between the auxiliary layer graphic set and the global metal line of the same layer to generate an identifier layer;

[0008] When the identification layer is empty, it is determined that the metal line to be detected meets the design rule spacing requirements;

[0009] When the identifier layer is not empty, output the spacing violation area indicated by the identifier layer.

[0010] In some of these design approaches, when the target unit is an array unit, obtaining the arrangement information of the selected target unit includes:

[0011] The hierarchical structure of the integrated circuit layout is traversed to identify the arrangement pattern of the array units at the top layer to obtain array arrangement information; wherein, the array arrangement information includes the origin coordinates, number of rows, number of columns, row spacing, column spacing and rotation angle of the array units.

[0012] In some of these design approaches, the value of the outward expansion process in the step of generating the auxiliary layer graphic is determined according to the minimum spacing parameter defined in the design rule spacing requirements.

[0013] In some of these design approaches, the step of forming the auxiliary layer graphic set includes:

[0014] When the target unit is an array unit, the auxiliary layer graphics are copied to the corresponding position of the array in the top layer layout using a coordinate transformation algorithm based on the number of rows, number of columns, row spacing, column spacing and rotation angle in the array layout information, to obtain the set of auxiliary layer graphics.

[0015] When the target unit is an independent unit, the auxiliary layer graphics are mapped to the target position in the top layer layout according to the global transformation matrix of the unit in the top layer layout, thereby generating a corresponding set of auxiliary layer graphics.

[0016] In some of these design approaches, the Boolean operation is a logical AND operation, which is performed directly in the graphics processing engine of a pre-defined integrated circuit layout design software.

[0017] In some of these designs, the global metalline includes power metallines and signal metallines that run through the target cell region.

[0018] Some of these design approaches also include:

[0019] The system integrates an automated script into a real-time detection module of a pre-defined circuit layout design software. When a modification to the target cell or the metal line to be detected is detected, the system automatically triggers the expansion processing, copy processing, and Boolean operation process to achieve dynamic design rule checking.

[0020] In some of these design approaches, obtaining the array arrangement information of the selected array elements includes:

[0021] Starting from the top layer of the integrated circuit layout, the process recursively traverses downwards along the layout hierarchy until the target cell is identified.

[0022] During the hierarchical traversal, record the entire inheritance path from the top level to the target unit;

[0023] For each recorded inheritance path, obtain the layout information of the target unit in each level;

[0024] The layout information of each level is integrated to generate arrangement information representing the global position of the target unit in the top-level layout.

[0025] In some of these design approaches, when the target unit is an array unit, the arrangement information includes a list of array relationships of the array unit in the top-level layout;

[0026] When the target unit is an independent unit, the layout information includes the absolute coordinates and rotation angle of the independent unit in the top-level layout.

[0027] Secondly, an integrated circuit layout verification apparatus is also provided, comprising:

[0028] The layout analysis module is used to obtain the arrangement information of the selected target cell from the integrated circuit layout.

[0029] The auxiliary layer generation module is used to expand the metal lines to be detected in the target unit according to the spacing requirements of the design rules to generate an auxiliary layer pattern; and to copy the auxiliary layer pattern according to the arrangement information to form an auxiliary layer pattern set covering all target unit areas.

[0030] The violation detection module is used to perform Boolean operations on the auxiliary layer graphic set and the global metal line in the same layer to generate an identifier layer;

[0031] The result determination module is used to determine that the metal line to be detected meets the design rule spacing requirements when the identification layer is empty; and to output the spacing violation area indicated by the identification layer when the identification layer is not empty.

[0032] Thirdly, a computer-readable storage medium is also provided, on which a computer program is stored, which is loaded by a processor to perform the steps in any of the above-described methods or design schemes.

[0033] Beneficial effects:

[0034] The integrated circuit layout verification method proposed in this invention effectively solves the problem of detecting spacing violations between target cells and global metal lines. First, it acquires the precise layout information of the target cells, including the coordinate parameters of independent cells and the transformation relationship of array cells. Then, based on the spacing requirements of the design rule check, it performs outward expansion processing on the cell metal lines to generate auxiliary layer patterns, and automatically generates a set of auxiliary layer patterns covering the target cell area. Finally, it compares the spatial relationship between the auxiliary layer pattern set and the actual metal lines through Boolean operations to accurately identify spacing violation areas. This method overcomes the limitations of traditional detection methods in terms of efficiency and accuracy, achieving efficient and accurate spacing violation detection for different types of cells (including independent cells and array cells) in integrated circuit layouts, and improving the automation and reliability of design rule checks. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a flowchart illustrating an integrated circuit layout verification method provided in some embodiments of this application;

[0037] Figure 2 yes Figure 1 A schematic diagram of layers based on the integrated circuit layout verification method;

[0038] Figure 3 This is a schematic diagram illustrating the acquisition inheritance chain provided in some embodiments of this application;

[0039] Figure 4 This is a schematic diagram illustrating the acquisition of an array relationship list provided in some embodiments of this application;

[0040] Figure 5 This is a schematic diagram of the minimum spacing between two metal wires provided in some embodiments of this application;

[0041] Figure 6 This is a schematic diagram illustrating non-violation scenarios provided in some embodiments of this application;

[0042] Figure 7 This is a schematic diagram illustrating violation scenarios provided in some embodiments of this application;

[0043] Figure 8 This is a structural block diagram of an integrated circuit layout verification device provided in some embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0046] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0047] Integrated circuit layout verification is essential to ensure that chip designs fully comply with the process manufacturer's Design Rules (DRC), Electrical Rules (ERC), and Logic Function Consistency (LVS) before manufacturing. This prevents chip manufacturing failures or substandard performance due to design defects. As process nodes continue to shrink (e.g., 5nm, 3nm), transistor density increases exponentially, making the physical rules regarding metal interconnect spacing, width, and coverage extremely stringent. Any minor layout error (such as insufficient metal spacing, antenna effects, or potential conflicts) can cause short circuits, open circuits, or reliability issues during wafer fabrication. Statistics show that the first-time tape-out success rate of chips directly fabricated without verification is less than 30%, while rigorous layout verification can increase it to over 90%. Therefore, verification serves as a "technical bridge" connecting design and manufacturing, directly impacting chip yield, power consumption, and timing performance.

[0048] The current challenge in memory layout design lies in the complexity of the surrounding environment of metal traces caused by the stacked arrangement of high-density array cells and non-array global cells. Traditional DRC verification requires a full check of the entire layout, especially when modifying array cell metal traces, necessitating repeated execution of time-consuming and resource-intensive global DRC processes (such as Calibre or Argus toolchains). Existing solutions still suffer from additional data conversion overhead or the inability to dynamically adapt to rules, while manually checking the line spacing violations of an m×n array cell by cell is extremely inefficient and prone to omissions.

[0049] This application proposes an integrated circuit layout verification method. It recursively parses the top-level layout pattern (row and column count / step spacing) of the target cell using a script, and expands the metal lines to be detected according to the design rule spacing requirements to generate an auxiliary layer pattern. The auxiliary layer pattern is then copied according to the array layout information and subjected to a Boolean AND operation with the global metal lines on the same layer to directly output the violation coordinates. This application embeds the detection process into the layout design environment, solving the problems of redundant LVL preprocessing and lack of real-time rule adaptation in existing technologies.

[0050] On the one hand, this embodiment provides an integrated circuit layout verification method, such as... Figure 1 , Figure 2 As shown, it includes the following steps:

[0051] S101: Obtain the layout information of the selected target cell from the integrated circuit layout.

[0052] For example, when the target unit is an array unit, obtaining the arrangement information of the selected target unit includes: traversing the hierarchical structure of the integrated circuit layout and identifying the arrangement pattern of the array unit at the top layer to obtain array arrangement information; wherein, the array arrangement information includes the origin coordinates, number of rows, number of columns, row spacing, column spacing and rotation angle of the array unit.

[0053] Understandably, the geometric layout parameters of the memory array can be automatically extracted by traversing the layer hierarchy (from the bottom layer to the top layer) using a recursive algorithm.

[0054] like Figure 2 As shown, the array cell layout information obtained from the integrated circuit layout design includes the array's origin coordinates (Origin: X 1.2215, Y 1.153), number of rows (Rows 4), number of columns (Columns 4), row spacing (Delta Y 4), column spacing (Delta X 4), and rotation angle (Rotation R0).

[0055] For example, when the target unit is an array unit, the arrangement information includes a list of array relationships of the array units in the top-level layout; when the target unit is an independent unit, the arrangement information includes the absolute coordinates and rotation angle of the independent unit in the top-level layout.

[0056] Understandably, array cells are collections of cells formed by regular, repetitive arrangements, typically used in high-density structures such as memory (e.g., SRAM / DRAM). Independent cells are independent functional modules that do not repeat in the layout, typically used for analog circuits or special interfaces. Array cells can automatically generate an array relationship list containing parameters such as the number of rows and columns (e.g., 8×12), reference coordinates (X,Y), step spacing (ΔX,ΔY), and rotation angle (θ) by parsing the array structure of the top-level layout. Independent cells can directly extract their absolute positioning data (e.g., X = 10.5μm, Y = 20.3μm) and orientation parameters (e.g., rotation 45°) in the top-level coordinate system.

[0057] For example, obtaining the array layout information of the selected array unit includes: starting from the top layer of the integrated circuit layout, recursively traversing downwards along the layout hierarchy until the target unit is identified; during the hierarchical traversal, recording all inheritance paths from the top layer to the target unit; for each recorded inheritance path, obtaining the layout information of the target unit in each level; integrating the layout information of each level to generate layout information representing the global position of the target unit in the top layer layout.

[0058] like Figure 3 As shown, starting from the top cell, the system recursively traverses all cells in each layer (e.g., Cell A, Cell B, Cell C, Cell D, etc.) according to the layout hierarchy until it reaches the target cell or the bottom layer, recording each inheritance link from the top cell to the target cell (e.g., ...). Figure 3 The three links in the text are: “Top Cell→CellA→Cell aa→Traget cell”, “Top Cell→Cell C→Traget cell”, and “Top Cell→Cell D→Cell aa→Traget cell”.

[0059] like Figure 4 As shown, for each inheritance path, the layout information of the target unit in each level is obtained (the layout information includes geometric transformation information, such as translation, rotation, scaling, and other transformation matrices, such as...). Figure 4The transformations are defined as follows: "Tran11", "Tran12", "Tran13", etc. Tran11 represents the transformation of Cell aa relative to the target cell, Tran12 represents the transformation of Cell A relative to Cell aa, and Tran13 represents the transformation of the Top Cell relative to Cell A. Then, the layout information (transformation matrices, etc.) from each level is sequentially superimposed (matrix multiplication) to obtain the final transformation matrix representing the global position and orientation of the target cell in the top-level layout (e.g., ...). Figure 4 The "Final Trans1", "Final Trans2", and "Final Trans3" transformation matrices, along with their associated parameters, form an array relationship list. Each Final Trans matrix is ​​a matrix multiplication of the transformations (Tran11, Tran12, etc.) at each level of the inheritance path. For example, Final Trans1 = Tran13 × Tran12 × Tran11. This matrix operation maps the target cell from the local coordinate system (Target cell) layer by layer to the top-level global coordinate system (Top Cell). The generated information represents the global arrangement of the target cell in the top-level layout, such as... Figure 4 The parameters FinalTrans1, FinalTrans2, and FinalTrans3 are integrated across different inheritance paths. These parameters comprehensively and accurately describe the target cell's global position (coordinates) and orientation (rotation angle, etc.) in the top-level layout. They are the core content of the array relationship list and provide the precise positioning data of the target cell at the top level for subsequent operations such as layout design rule checking (DRC).

[0060] S102: Expand the metal lines to be detected in the target unit according to the spacing requirements of the design rules to generate an auxiliary layer pattern; copy the auxiliary layer pattern according to the arrangement information to form an auxiliary layer pattern set covering all target unit areas.

[0061] For example, in the step of generating the auxiliary layer graphic, the value of the outward expansion process is determined according to the minimum spacing parameter defined in the design rule spacing requirements.

[0062] Understandably, the expansion values ​​used when generating auxiliary layer patterns are not fixed values ​​preset by humans, but are dynamically calculated based on the minimum spacing parameters (such as the minimum spacing of metal lines, MinSpace) explicitly defined in the current layout design rule file. For example, if the design rule requires a minimum spacing of 0.1μm for a certain metal layer (Metal1.MinSpace = 0.1μm), the system will automatically adjust the expansion amount dynamically based on this value (e.g., the expansion amount equals the minimum spacing value of the metal layer, i.e., an expansion of 0.1μm forms the detection boundary), thereby ensuring that the generated auxiliary layer pattern can accurately cover all areas that may violate the minimum spacing rule. This dynamic association with design rules avoids the blindness of manually preset expansion values ​​and significantly improves the accuracy and automation of detection.

[0063] like Figure 2 As shown, the metal lines of the target unit to be detected (the unit where the purple metal line is located in the figure) are expanded outward (based on the preset design rules for inspection) to generate an auxiliary layer graphic (the graphic formed by the expansion of the purple line in the figure).

[0064] For example, the step of forming the auxiliary layer graph set includes:

[0065] When the target unit is an array unit, the auxiliary layer graphics are copied to the corresponding position of the array in the top layer layout using a coordinate transformation algorithm based on the number of rows, number of columns, row spacing, column spacing and rotation angle in the array layout information, to obtain the set of auxiliary layer graphics.

[0066] When the target unit is an independent unit, the auxiliary layer graphics are mapped to the target position in the top layer layout according to the global transformation matrix of the unit in the top layer layout (including translation, rotation angle and scaling parameters), and a corresponding set of auxiliary layer graphics is generated.

[0067] Understandably, the processing of array cells involves batch copying the auxiliary layer graphics using row and column parameters (number of rows / columns / spacing) and rotation angles to cover all array instances. The processing of independent cells involves direct single-step positioning based on the translation (X / Y coordinates) and rotation (θ angle) parameters of the transformation matrix (such as FinalTrans), without the need for copying. However, the generation of auxiliary layers for both types of cells (array cells and independent cells) depends on the top-level coordinate transformation, but independent cells do not need to consider array arrangement rules, simplifying the mapping logic.

[0068] like Figure 2 As shown, based on the obtained array layout information (such as the number of rows and columns, spacing, etc.), a single auxiliary layer graphic is copied to form a set of auxiliary layer graphics covering the target area (the entire array area) (the figure shows multiple auxiliary layer graphics distributed in various unit positions of the array).

[0069] S103: Perform Boolean operations on the auxiliary layer graphic set and the global metal lines on the same layer of the layout to generate an identifier layer.

[0070] For example, the Boolean operation is a logical AND operation, which is performed directly in the graphics processing engine of the preset integrated circuit layout design software.

[0071] Understandably, the auxiliary layer graphic set (i.e., the extended metal line area of ​​the array or independent cell) generated in step S102 is logically ANDed with the actual global traces of the same metal layer of the layout within the layout design software. Its purpose is to directly perform the calculation using the built-in graphics engine of the layout design software, avoiding the data conversion overhead of LVL (Layout Comparison) and Partial Layout (Partial Layout) in existing technologies. In existing technologies, LVL tools generate Partial Layout by comparing the old and new layouts; this application skips this step by directly extending the metal lines and performing a Boolean AND operation, thus avoiding the time-consuming data conversion problem of LVL.

[0072] For example, the global metal line includes power metal lines and signal metal lines that run through the target cell region.

[0073] As can be understood, global metal lines refer to power metal and signal metal lines that run through the target cell area (such as the area where the array cell is located) in the layout. These metal lines belong to the top or middle layer of global traces and together with the local metal lines within the array cell constitute the detection object. For example:

[0074] Power supply metal wires: typically wide-width, fixed-potential VDD / VSS power supply networks;

[0075] Signal metal lines: interconnect traces used to transmit logic signals.

[0076] During Boolean AND operations, by comparing the auxiliary layer pattern generated by expanding the array cells with these global metal lines, spacing violations or unexpected overlaps between array cells and power / signal lines can be detected simultaneously, thus covering various conflict scenarios of metal lines on the same layer in DRC rules. For example, when there is an overlap between the auxiliary layer pattern (the expanded metal line area) and the global metal lines, the AND operation result will generate a non-empty pattern. This overlap directly corresponds to two types of DRC violations:

[0077] Insufficient spacing: The distance between the extended area and the adjacent metal line is less than the minimum spacing specified in the design rules.

[0078] Unexpected overlap: The metal wire completely overlaps with the outer expansion area (risk of short circuit in the same layer of metal).

[0079] Example: If the spacing between metal lines is 0.1μm, and the AND operation between the auxiliary layer extending 0.1μm outward and the adjacent metal line results in a non-empty result, then a violation is determined.

[0080] like Figure 2 As shown, a Boolean logical AND operation is performed between the auxiliary layer graphic set and the global metal line (which is the object that performs operations with the auxiliary layer graphic) on the same layer of the layout to generate the identifier layer.

[0081] S104: When the identification layer is empty, it is determined that the metal line to be detected meets the design rule spacing requirements.

[0082] S105: When the identifier layer is not empty, output the spacing violation area indicated by the identifier layer.

[0083] Understandably, S104 and S105 are the result judgment and output steps of DRC detection. Specifically: S104 (Compliance Judgment): If the identifier layer generated by the Boolean operation has no graphic content (empty set), it means that the outer expansion area of ​​the target unit metal line does not overlap with the global metal line, the spacing fully meets the design rules, and no further processing is required; S105 (Violation Output): If the identifier layer contains graphics (not empty), then the coordinate area corresponding to the graphics is directly output, highlighting the specific location of insufficient spacing or short circuit (e.g., ...). Figure 5 (The red and white diagonal stripes mark the violation areas), guiding engineers to make precise corrections. Its function is to automatically complete compliance judgment by identifying the empty / non-empty status of the marker layer, replacing manual item-by-item checks; the non-empty marker layer is directly mapped to the layout interface, avoiding the inefficiency of traditional DRC tools that need to parse text reports.

[0084] like Figure 2 As shown, this illustrates the case when the identifier layer is not empty. The output identifies the spacing violation areas indicated by the identifier layer (the violation areas are displayed in a specific color in the figure, such as the part indicated by the arrow), which is presented to the user intuitively so that the layout can be corrected.

[0085] For example: if a power line is extended by 0.1μm and then ANDed with an adjacent signal line to generate a non-empty identifier layer, then the distance between the two lines is determined to be <0.1μm, and the routing needs to be adjusted.

[0086] like Figure 5 As shown in the figure, there are two metal wires, and the distance between them is the minimum spacing (Min Space) specified in the design rules.

[0087] like Figure 6 As shown, the non-violation case is when the target metal line is expanded outward according to "Min Space" (the light blue area in the figure represents the expanded part), and there is no overlap between the expanded graphic and the metal line of the same layer of the global unit. This indicates that the metal line spacing conforms to the design rules and there is no violation.

[0088] like Figure 7 As shown, the violation occurs when the expanded graphic (light blue) overlaps with the same-layer metal line (dark blue) of the global cell (marked with red and white diagonal stripes as the "violation area" in the diagram). This indicates that the metal line spacing is less than the minimum spacing specified in the design rules, resulting in a DRC violation. The specific operation involves expanding the target metal line to the minimum spacing and performing array processing, then performing a logical AND Boolean operation with the same-layer metal line of the global cell. The result of this operation is the violation area.

[0089] In some embodiments, the integrated circuit layout verification method further includes:

[0090] The system integrates an automated script into a real-time detection module of a pre-defined circuit layout design software. When a modification to the target cell or the metal line to be detected is detected, the system automatically triggers the expansion processing, copy processing, and Boolean operation process to achieve dynamic design rule checking.

[0091] Understandably, the Boolean operation detection process can be embedded into the real-time detection module of the layout design software through pre-written automated scripts (such as Skill scripts or Python scripts). When engineers are editing the layout, once the target cell or metal line is modified (such as moved, rotated, or added / removed traces), the system automatically triggers the complete DRC process of expansion → Boolean operation → identifier layer generation, achieving real-time feedback of "modification is detection," without the need to manually call external tools or perform a full layout scan. Its advantages are: overcoming the lag of traditional DRC tools that require manual running of checks; and achieving zero-switching operation by utilizing the design software's native API (such as Virtuoso's CIW interface), avoiding data export / import overhead.

[0092] For example, after an engineer adjusts the width of the array unit's power line, the script immediately detects any violations in the spacing between the unit and adjacent signal lines and marks them with a red warning box on the interface.

[0093] On the other hand, please refer to Figure 8 , Figure 8 This is a structural block diagram of an integrated circuit layout verification device provided in some embodiments of this application. This embodiment provides an integrated circuit layout verification device, including a layout parsing module 801, an auxiliary layer generation module 802, a violation detection module 803, and a result determination module 804.

[0094] For example, the layout parsing module 801 is used to obtain the arrangement information of the selected target cell from the integrated circuit layout.

[0095] For example, the auxiliary layer generation module 802 is used to expand the metal lines to be detected of the target unit according to the spacing requirements of the design rules to generate an auxiliary layer pattern; and to copy the auxiliary layer pattern according to the arrangement information to form an auxiliary layer pattern set covering all target unit areas.

[0096] For example, the violation detection module 803 is used to perform Boolean operations on the auxiliary layer graphic set and the global metal line of the same layer to generate an identifier layer.

[0097] For example, the result determination module 804 is used to determine that the metal line to be detected meets the design rule spacing requirements when the identification layer is empty; and to output the spacing violation area indicated by the identification layer when the identification layer is not empty.

[0098] Understandably, this embodiment addresses the efficiency issue of detecting violations in the spacing between target cells and global metal lines by constructing a hierarchical detection process: First, the layout analysis module extracts the topology information of the target cells. Then, the auxiliary layer generation module performs rule-driven outward replication processing on the cell metal lines to generate an auxiliary layer graphic set covering all target cells. Subsequently, the violation detection module uses parallel geometric computation technology to verify the spatial relationship between the auxiliary layer graphics and the global metal lines. Finally, the result judgment module accurately locates the violation position. Compared to traditional full-layout scanning methods, this application reduces the detection time complexity of target cells while ensuring a high violation detection rate.

[0099] This embodiment also provides a computer-readable storage medium having a computer program stored thereon, the computer program being loaded by a processor to execute the arrangement in any of the methods described above.

[0100] In the embodiments of this application, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0102] The above provides a detailed description of an integrated circuit layout verification method and apparatus provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for verifying integrated circuit layout, characterized in that, include: Obtain the layout information of the selected target cell from the integrated circuit layout; According to the design rules and spacing requirements, the metal lines to be detected in the target unit are expanded outward to generate an auxiliary layer pattern; The auxiliary layer graphics are copied according to the arrangement information to form a set of auxiliary layer graphics covering all target unit areas; Perform a Boolean operation between the auxiliary layer graphic set and the global metal line of the same layer to generate an identifier layer; When the identification layer is empty, it is determined that the metal line to be detected meets the design rule spacing requirements; When the identifier layer is not empty, output the spacing violation area indicated by the identifier layer; The step of forming the auxiliary layer graphic set includes: When the target unit is an array unit, the auxiliary layer graphics are copied to the corresponding position of the array in the top layer layout using a coordinate transformation algorithm based on the number of rows, number of columns, row spacing, column spacing and rotation angle in the array layout information, to obtain the set of auxiliary layer graphics. When the target unit is an independent unit, the auxiliary layer graphics are mapped to the target position in the top layer layout according to the global transformation matrix of the unit in the top layer layout, thereby generating a corresponding set of auxiliary layer graphics.

2. The integrated circuit layout verification method according to claim 1, characterized in that, When the target unit is an array unit, obtaining the arrangement information of the selected target unit includes: The hierarchical structure of the integrated circuit layout is traversed to identify the arrangement pattern of the array units at the top layer to obtain array arrangement information; wherein, the array arrangement information includes the origin coordinates, number of rows, number of columns, row spacing, column spacing and rotation angle of the array units.

3. The integrated circuit layout verification method according to claim 1, characterized in that, In the step of generating the auxiliary layer graphic, the value of the outward expansion process is determined according to the minimum spacing parameter defined in the design rule spacing requirements.

4. The integrated circuit layout verification method according to claim 1, characterized in that, The Boolean operation is a logical AND operation, which is executed directly in the graphics processing engine of the preset integrated circuit layout design software.

5. The integrated circuit layout verification method according to claim 1, characterized in that, The global metal lines include power metal lines and signal metal lines that run through the target unit region.

6. The integrated circuit layout verification method according to claim 1, characterized in that, Also includes: Real-time detection module integrated into preset circuit layout design software via automated scripts; When a modification is detected in the target unit or the metal line to be detected, the expansion processing, copy processing and Boolean operation process are automatically triggered to realize dynamic design rule checking.

7. The integrated circuit layout verification method according to claim 1, characterized in that, The process of obtaining the array arrangement information of the selected array unit includes: Starting from the top layer of the integrated circuit layout, the process recursively traverses downwards along the layout hierarchy until the target cell is identified. During the hierarchical traversal, record the entire inheritance path from the top level to the target unit; For each recorded inheritance path, obtain the layout information of the target unit in each level; The layout information of each level is integrated to generate the arrangement information representing the global position of the target unit in the top-level layout.

8. The integrated circuit layout verification method according to claim 1, characterized in that: When the target unit is an array unit, the arrangement information includes a list of array relationships of the array unit in the top-level layout; When the target unit is an independent unit, the layout information includes the absolute coordinates and rotation angle of the independent unit in the top-level layout.

9. An integrated circuit layout verification device, characterized in that, include: The layout analysis module is used to obtain the arrangement information of the selected target cell from the integrated circuit layout. The auxiliary layer generation module is used to expand the metal lines to be detected in the target unit according to the spacing requirements of the design rules, and generate an auxiliary layer pattern. The auxiliary layer graphics are copied according to the arrangement information to form a set of auxiliary layer graphics covering all target unit areas; The violation detection module is used to perform Boolean operations on the auxiliary layer graphic set and the global metal line in the same layer to generate an identifier layer; The result determination module is used to determine that the metal line to be detected meets the design rule spacing requirements when the identification layer is empty; and to output the spacing violation area indicated by the identification layer when the identification layer is not empty. The auxiliary layer generation module is used to copy the auxiliary layer graphics to the corresponding position of the array in the top layer layout using a coordinate transformation algorithm when the target unit is an array unit, based on the number of rows, number of columns, row spacing, column spacing and rotation angle in the array layout information, to obtain the auxiliary layer graphics set. When the target unit is an independent unit, the auxiliary layer graphics are mapped to the target position in the top layer layout according to the global transformation matrix of the unit in the top layer layout, thereby generating a corresponding set of auxiliary layer graphics.

Images