Semiconductor memory array, semiconductor memory and data processing method

Abstract

The invention discloses a semiconductor storage array, a semiconductor memory and a data processing method, and the semiconductor storage array comprises M rows and N columns of storage units, a power supply voltage line, M common word lines, N first selection gate lines and N bit lines, the m row and n column storage unit comprises a control sub-circuit and a storage sub-circuit; and the control sub-circuit is electrically connected with the mth common word line, the nth first selection gate line, the nth bit line and the connection node respectively, and is configured to store a signal of the nth bit line in the connection node during writing under the control of the signal lines of the mth common word line and the nth first selection gate line, or store the signal of the nth bit line in the connection node during reading. Reading a signal of the connection node to the nth bit line; and a storage sub-circuit electrically connected to the connection node and the power supply voltage line, respectively, and configured to store a voltage difference between signals of the connection node and the power supply voltage line.

Description

Technical Field

[0001] This article relates to the field of storage technology, and in particular to a semiconductor storage array, semiconductor memory, and data processing method. Background Technology

[0002] Electronic memory includes volatile memory and non-volatile memory. Volatile memory includes Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM, due to its high-speed read / write capabilities and relatively high integration density, is widely used in computer main memory and other electronic devices. Its working principle is to store data through the charge in capacitors. Because capacitors leak current over time, they need to be refreshed periodically to maintain data integrity.

[0003] DRAM comprises multiple memory cells. To increase DRAM's storage capacity, a three-dimensional DRAM technology has been proposed, which vertically stacks memory cells. This three-dimensional structure allows for higher storage capacity per unit wafer area. Currently, three-dimensional DRAM requires vertical word lines and horizontal bit lines to select memory cells. To control the word lines, three-dimensional DRAM uses a switch array, but the switch array adds extra processing steps, making the DRAM manufacturing process more complex. Summary of the Invention

[0004] This application provides a semiconductor memory array, a semiconductor memory, and a data processing method that can avoid setting up a switch array in DRAM, thus simplifying the DRAM process.

[0005] In a first aspect, this disclosure provides a semiconductor memory array, comprising: M rows and N columns of memory cells, power supply voltage lines, M common word lines, N first select gate lines, and N bit lines;

[0006] The storage unit in row m and column n includes: a control sub-circuit and a storage sub-circuit;

[0007] The control sub-circuit is electrically connected to the m-th common word line, the n-th first select gate line, the n-th bit line, and the connection node, respectively. It is configured to, under the control of the signal lines of the m-th common word line and the n-th first select gate line, store the signal of the n-th bit line in the connection node during writing, or read the signal of the connection node to the n-th bit line during reading.

[0008] The storage sub-circuit is electrically connected to the connection node and the power supply voltage line, respectively, and is configured to store the voltage difference between the signals of the connection node and the power supply voltage line.

[0009] In an exemplary embodiment, the control sub-circuit in the m-th row and n-th column memory cell includes: a first transistor and a second transistor;

[0010] The gate electrode of the first transistor is electrically connected to the m-th common word line, the first terminal of the first transistor is electrically connected to the connection node, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate electrode of the second transistor is electrically connected to the n-th first select gate line, and the second terminal of the second transistor is electrically connected to the n-th bit line, 1≤m≤M, 1≤n≤N.

[0011] In an exemplary embodiment, the storage sub-circuit in the m-th row and n-th column storage cell includes: a storage capacitor;

[0012] The first end of the storage capacitor is electrically connected to the power supply voltage line, and the second end of the storage capacitor is electrically connected to the connection node.

[0013] In an exemplary embodiment, the transistor includes: an active layer; the active layers of the first transistor and the second transistor located in the same memory cell are integral structures.

[0014] In an exemplary embodiment, the integrated structure of the active layer of the first transistor and the active layer of the second transistor located in the same memory cell includes: a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked together, wherein the plurality of first semiconductor layers and the plurality of second semiconductor layers are alternately arranged.

[0015] In an exemplary embodiment, it further includes: a bit line selection circuit, a bit line equalization circuit, N bit line power supply lines, N second selection gate lines, a bit line selection common word line, a bit line equalization common word line, and a pre-charge voltage line;

[0016] The bit line selection circuit is electrically connected to the bit line selection common word line, N bit line power supply lines, N first selection gate lines and N bit lines respectively, and is configured to provide the signals of the N bit line power supply lines to the N bit lines during writing and provide the signals of the N bit lines to the N bit line power supply lines during reading under the control of the signals of the bit line selection common word line and the N first selection gate lines.

[0017] The bit line equalization circuit is electrically connected to the bit line equalization common word line, the precharge voltage line, N bit lines and N second select gate lines respectively, and is configured to provide the precharge voltage line signal to the N bit lines under the control of the signals of the bit line equalization common word line and the N second select gate lines.

[0018] The signals of the first selection gate line n and the second selection gate line n are inverse signals.

[0019] In an exemplary embodiment, the bit line selection circuit includes: N selection sub-circuits;

[0020] The nth select sub-circuit is electrically connected to the bit line select common word line, the nth bit line power supply line, the nth first select gate line, and the nth bit line, respectively. It is configured to provide the signal of the nth bit line power supply line to the nth bit line during writing and provide the signal of the nth bit line to the nth bit line power supply line during reading, under the control of the signals of the bit line select common word line and the nth first select gate line.

[0021] In an exemplary embodiment, the nth selection sub-circuit includes: a third transistor and a fourth transistor;

[0022] The gate electrode of the third transistor is electrically connected to the bit line select common word line, the first electrode of the third transistor is electrically connected to the nth bit line power supply line, the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor, the gate electrode of the fourth transistor is electrically connected to the nth first select gate line, and the second electrode of the fourth transistor is electrically connected to the nth bit line.

[0023] In an exemplary embodiment, the bit line equalization circuit includes: N equalization sub-circuits;

[0024] The nth equalization sub-circuit is electrically connected to the bit line equalization common word line, the precharge voltage line, the nth bit line, and the nth second select gate line, and is configured to provide the precharge voltage line signal to the nth bit line under the control of the signals of the bit line equalization common word line and the nth second select gate line.

[0025] In an exemplary embodiment, the nth equalization sub-circuit includes: a fifth transistor and a sixth transistor;

[0026] The gate electrode of the fifth transistor is electrically connected to the bit line equalization common word line, the first electrode of the fifth transistor is electrically connected to the precharge voltage line, the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, the gate electrode of the sixth transistor is electrically connected to the nth second selection gate line, and the second electrode of the sixth transistor is electrically connected to the nth bit line.

[0027] In an exemplary embodiment, it further includes: a bit line selection circuit, a bit line equalization circuit, N bit line power supply lines, N second selection gate lines, and a pre-charge voltage line;

[0028] The bit line selection circuit is electrically connected to N bit line power supply lines, N first selection gate lines and N bit lines respectively, and is configured to provide the signals of the N bit line power supply lines to the N bit lines during writing and provide the signals of the N bit lines to the N bit line power supply lines during reading under the control of the signals of the N first selection gate lines.

[0029] The bit line equalization circuit is electrically connected to the precharge voltage line, N bit lines and N second selection gate lines respectively, and is configured to provide the precharge voltage line signal to the N bit lines under the control of the signal of the N second selection gate lines.

[0030] The signals of the first selection gate line n and the second selection gate line n are inverse signals.

[0031] In an exemplary embodiment, the bit line selection circuit includes: N selection sub-circuits;

[0032] The nth selector circuit is electrically connected to the nth bit line power supply line, the nth first select gate line, and the nth bit line, respectively. It is configured to provide the signal of the nth bit line power supply line to the nth bit line during writing and provide the signal of the nth bit line to the nth bit line power supply line during reading, under the control of the signal of the nth first select gate line.

[0033] In an exemplary embodiment, the nth selection sub-circuit includes: a fourth transistor;

[0034] The gate electrode of the fourth transistor is electrically connected to the nth first select gate line, the first electrode of the fourth transistor is electrically connected to the nth bit line power supply line, and the second electrode of the fourth transistor is electrically connected to the nth bit line.

[0035] In an exemplary embodiment, the bit line equalization circuit includes: N equalization sub-circuits;

[0036] The nth equalization sub-circuit is electrically connected to the pre-charge voltage line, the nth bit line, and the nth second selection gate line, and is configured to provide the pre-charge voltage line signal to the nth bit line under the control of the signal of the nth second selection gate line.

[0037] In an exemplary embodiment, the nth equalization sub-circuit includes: a sixth transistor;

[0038] The gate electrode of the sixth transistor is electrically connected to the nth second select gate line, the first electrode of the sixth transistor is electrically connected to the precharge voltage line, and the second electrode of the sixth transistor is electrically connected to the nth bit line.

[0039] In an exemplary embodiment, it includes: a substrate and a transistor device layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate;

[0040] The transistor device layer includes at least: a first transistor, a second transistor and a storage capacitor located in the memory cell; a third transistor and a fourth transistor located in the select sub-circuit; a fifth transistor and a sixth transistor located in the equalization sub-circuit; a bit line; a bit line power supply line and a pre-charge voltage line.

[0041] The first conductive layer includes at least: a first connecting electrode, a second connecting electrode, a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode, and a sixth connecting electrode; the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor on the substrate, the orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the second transistor on the substrate, the orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the substrate, the orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate, the orthographic projection of the fifth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fifth transistor on the substrate, and the orthographic projection of the sixth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate.

[0042] The second conductive layer includes at least: a first selection gate line, a second selection gate line, a seventh connection electrode, an eighth connection electrode, and a ninth connection electrode. The orthographic projection of the seventh connection electrode on the substrate at least partially overlaps with the orthographic projection of the first connection electrode on the substrate and is electrically connected to the first connection electrode. The orthographic projection of the eighth connection electrode on the substrate at least partially overlaps with the orthographic projection of the third connection electrode on the substrate and is electrically connected to the third connection electrode. The orthographic projection of the ninth connection electrode on the substrate at least partially overlaps with the orthographic projection of the fifth connection electrode on the substrate and is electrically connected to the fifth connection electrode. The second selection gate line is electrically connected to the sixth connection electrode. The first selection gate line is electrically connected to the second connection electrode and the fourth connection electrode, respectively.

[0043] The third conductive layer includes at least: a common word line, a bit line select common word line, and a bit line equalization common word line, wherein the common word line is electrically connected to the seventh connection electrode, the bit line select common word line is electrically connected to the eighth connection electrode, and the bit line equalization common word line is electrically connected to the ninth connection electrode.

[0044] In an exemplary embodiment, it includes: a substrate and a transistor device layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate;

[0045] The transistor device layer includes at least: a first transistor, a second transistor and a storage capacitor located in the memory cell; a fourth transistor located in the select sub-circuit; a sixth transistor located in the equalization sub-circuit; a bit line; a bit line power supply line and a pre-charge voltage line.

[0046] The first conductive layer includes at least: a first connecting electrode, a second connecting electrode, a fourth connecting electrode, and a sixth connecting electrode; the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor on the substrate, the orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the second transistor on the substrate, the orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate, and the orthographic projection of the sixth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate.

[0047] The second conductive layer includes at least: a first selection gate line, a second selection gate line, and a seventh connection electrode. The orthographic projection of the seventh connection electrode on the substrate at least partially overlaps with the orthographic projection of the first connection electrode on the substrate and is electrically connected to the first connection electrode. The second selection gate line is electrically connected to the sixth connection electrode, and the first selection gate line is electrically connected to the second connection electrode and the fourth connection electrode, respectively.

[0048] The third conductive layer includes at least a common word line, wherein the common word line is electrically connected to the seventh connecting electrode.

[0049] In an exemplary embodiment, storage cells located in adjacent columns of the same row are symmetrically arranged with respect to a first center line, wherein the first center line is the center line of two first selection gate lines connected to storage cells located in adjacent columns of the same row.

[0050] In an exemplary embodiment, adjacent selector circuits are arranged symmetrically with respect to the first center line, wherein the first center line is the center line of two first select gate lines connected to memory cells located in adjacent columns of the same row.

[0051] In an exemplary embodiment, adjacent equalization sub-circuits are arranged symmetrically with respect to the first center line, wherein the first center line is the center line of two first selection gate lines connected to memory cells located in adjacent columns of the same row.

[0052] In an exemplary embodiment, the N bit power supply lines are arranged in a stepped structure.

[0053] In a second aspect, this disclosure also provides a semiconductor memory, including: a plurality of stacked semiconductor memory array layers;

[0054] At least one semiconductor memory array layer includes: a first semiconductor memory array and a second semiconductor memory array, wherein the second semiconductor memory array is a reference semiconductor memory array for the first semiconductor memory array, and the first semiconductor memory array and the second semiconductor memory array are semiconductor memory arrays provided in any of the foregoing embodiments;

[0055] The region in the first semiconductor memory array where the N bit power lines form a stepped structure is adjacent to the region in the second semiconductor memory array where the N bit power lines form a stepped structure.

[0056] In an exemplary embodiment, at least one semiconductor memory array layer further includes: a sensing amplifier;

[0057] The sensing amplifier is electrically connected to the N bit line power supply lines in the first semiconductor memory array and the N bit line power supply lines in the second semiconductor memory array, respectively, and is located in the area where the N bit line power supply lines in the first semiconductor memory array and the N bit line power supply lines in the second semiconductor memory array are located.

[0058] In an exemplary embodiment, the semiconductor memory is a dynamic random access memory.

[0059] Thirdly, this disclosure also provides a data processing method, which is applied to the semiconductor memory array provided in any of the foregoing embodiments;

[0060] The control sub-circuit of the m-th row and n-th column memory cell, under the control of the signal lines of the m-th common word line and the n-th first select gate line, stores the signal of the n-th bit line in the connection node during writing, or reads the signal of the connection node to the n-th bit line during reading.

[0061] The storage sub-circuit of the m-th row and n-th column storage cell stores the voltage difference between the signal of the connection node and the signal of the power supply voltage line.

[0062] This disclosure provides a semiconductor memory array, a semiconductor memory, and a data processing method. The semiconductor memory array includes: M rows and N columns of memory cells, a power supply voltage line, M common word lines, N first select gate lines, and N bit lines. The m-th row and n-th column memory cell includes: a control sub-circuit and a storage sub-circuit. The control sub-circuit is electrically connected to the m-th common word line, the n-th first select gate line, the n-th bit line, and a connection node, and is configured to, under the control of the signal lines of the m-th common word line and the n-th first select gate line, store the signal of the n-th bit line in the connection node during writing, or read the signal of the connection node to the n-th bit line during reading. The storage sub-circuit is electrically connected to the connection node and the power supply voltage line, and is configured to store the voltage difference between the signals of the connection node and the power supply voltage line. This disclosure avoids setting up a switch array for the select word lines in the DRAM by sharing a common word line in the same row of memory cells and selecting through the common word line and the first select gate line, thus simplifying the DRAM process. Attached Figure Description

[0063] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0064] Figure 1 This is a schematic diagram of the structure of the semiconductor memory array provided in this disclosure;

[0065] Figure 2 This is a schematic diagram of the structure of the storage unit in the m-th row and n-th column;

[0066] Figure 3 The equivalent circuit diagram for the storage cell in the m-th row and n-th column;

[0067] Figure 4 This is a schematic diagram of the structure of the first transistor and the second transistor;

[0068] Figure 5 Schematic diagram of a semiconductor memory array Figure 1 ;

[0069] Figure 6 Schematic diagram of a semiconductor memory array Figure 2 ;

[0070] Figure 7 for Figure 5 A schematic diagram after the transistor device layer has been formed;

[0071] Figure 8 for Figure 5 A schematic diagram after the formation of the first conductive layer;

[0072] Figure 9 for Figure 5 A schematic diagram after the formation of the second conductive layer;

[0073] Figure 10 for Figure 5 A schematic diagram after the formation of the third conductive layer;

[0074] Figure 11 for Figure 6 A schematic diagram after the transistor device layer has been formed;

[0075] Figure 12 for Figure 6 A schematic diagram after the formation of the first conductive layer;

[0076] Figure 13 for Figure 6 A schematic diagram after the formation of the second conductive layer;

[0077] Figure 14 for Figure 6 A schematic diagram after the formation of the third conductive layer;

[0078] Figure 15A schematic diagram of the structure of the semiconductor memory array layer provided in this disclosure. Figure 1 ;

[0079] Figure 16 A schematic diagram of the structure of the semiconductor memory array layer provided in this disclosure. Figure 2 . Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0081] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0082] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0083] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0084] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0085] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0086] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0087] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0088] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0089] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0090] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0091] Figure 1 This is a schematic diagram of the structure of the semiconductor memory array provided in this disclosure. Figure 2 This is a schematic diagram of the storage unit in the m-th row and n-th column. (Example:) Figure 1 As shown, this disclosure provides a semiconductor memory array, including: M rows and N columns of memory cells 10, power supply voltage lines VCP, M common word lines CWL(1) to CWL(M), N first select gate lines SG(1) to SG(N) and N bit lines BL(1) to BL(N).

[0092] like Figure 2 As shown, the storage cell in the m-th row and n-th column includes a control sub-circuit 11 and a storage sub-circuit 12. The control sub-circuit 11 is electrically connected to the m-th common word line CWL(m), the n-th first select gate line SG(n), the n-th bit line BL(n), and the connection node N. It is configured to, under the control of the signal lines of the m-th common word line CWL(m) and the n-th first select gate line SG(n), store the signal of the n-th bit line BL(n) in the connection node N during writing, or read the signal of the connection node N into the n-th bit line BL(n) during reading. The storage sub-circuit is electrically connected to the connection node N and the power supply voltage line VCP, and is configured to store the voltage difference between the signals of the connection node N and the power supply voltage line VCP.

[0093] In an exemplary implementation, the common word line can be controlled by a decoder and a word line driver.

[0094] In an exemplary implementation, the first selected gate line can be controlled by a decoder and a word line driver.

[0095] This disclosure uses a common word line for memory cells in the same row, and selects the memory cell in the m-th row and n-th column by the m-th common word line CWL(m) and the n-th first select gate line SG(n), thus avoiding the need to set up a switch array for select word lines in DRAM and simplifying DRAM manufacturing process.

[0096] Figure 3 This is the equivalent circuit diagram for the storage cell in the m-th row and n-th column. In an exemplary embodiment, such as... Figure 3As shown, the control sub-circuit in the m-th row and n-th column memory cell includes: a first transistor T1 and a second transistor T2. The gate electrode of the first transistor T1 is electrically connected to the m-th common word line CWL(m), the first terminal of the first transistor T1 is electrically connected to the connection node N, the second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T2, the gate electrode of the second transistor T2 is electrically connected to the n-th first select gate line SG(n), and the second terminal of the second transistor T2 is electrically connected to the n-th bit line BL(n), where 1 ≤ m ≤ M and 1 ≤ n ≤ N.

[0097] In an exemplary embodiment, as in an exemplary embodiment, such as Figure 3 As shown, the storage sub-circuit in the m-th row and n-th column storage cell includes a storage capacitor C. The first terminal of the storage capacitor C is electrically connected to the power supply voltage line VCP, and the second terminal of the storage capacitor C is electrically connected to the connection node N.

[0098] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its on-state voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its off-state voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its on-state voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its off-state voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0099] In an exemplary embodiment, the first transistor T1 and the second transistor T2 are N-type transistors.

[0100] In an exemplary embodiment, the operation of the storage unit in the m-th row and n-th column may include:

[0101] When the signals of the m-th common word line CWL(m) and the n-th first selection gate line SG(n) are high, the first transistor T1 and the second transistor T2 are turned on, and node N is connected to the n-th bit line BL(n). This allows the signal of the n-th bit line BL(n) to be written to node N during writing, and the signal of node N to be written to the n-th bit line BL(n) during reading, meaning the memory cell in the m-th row and n-th column is selected. When at least one of the signals of the m-th common word line CWL(m) and the n-th first selection gate line SG(n) is low, at least one of the first transistor T1 and the second transistor T2 is turned off. During writing, the signal of the n-th bit line BL(n) cannot be written to node N, and during reading, the signal of node N cannot be written to the n-th bit line BL(n), meaning the memory cell in the m-th row and n-th column is not selected.

[0102] Figure 4This is a schematic diagram of the structure of the first transistor and the second transistor. In an exemplary embodiment, as shown... Figure 4 As shown, the transistor includes: an active layer; the active layer 21 of the first transistor and the active layer 22 of the second transistor, located in the same memory cell, are an integral structure. Among them, Figure 4 This is a side view of the first and second transistors.

[0103] In an exemplary embodiment, the integral structure of the active layer 21 of the first transistor and the active layer 22 of the second transistor located in the same memory cell includes: a plurality of first semiconductor layers 23 and a plurality of second semiconductor layers 24 stacked together, wherein the plurality of first semiconductor layers 23 and the plurality of second semiconductor layers 24 are alternately arranged.

[0104] In an exemplary embodiment, the material used to fabricate the first semiconductor layer 23 may be either amorphous silicon or polycrystalline silicon, and this disclosure does not impose any limitation on this.

[0105] In an exemplary embodiment, the material used to fabricate the second semiconductor layer 24 can be a metal oxide. For example, the metal oxide can include oxides of indium and tin, oxides of tungsten and indium, oxides of tungsten, indium, and zinc, oxides of titanium and indium, oxides of titanium, indium, and tin, oxides of indium and zinc, oxides of silicon and indium and tin, or oxides of indium or gallium and zinc. The second semiconductor layer can be a single layer, a double layer, or a multilayer; this disclosure does not limit the specific application of the invention.

[0106] In an exemplary embodiment, the channel regions of the active layers of the first transistor and the second transistor, as well as other parameters, determine the performance of the first transistor and the second transistor.

[0107] In an exemplary embodiment Figure 5 Schematic diagram of a semiconductor memory array Figure 1 .like Figure 5 As shown, the semiconductor memory array also includes: a bit line selection circuit 20, a bit line equalization circuit 30, N bit line power supply lines LBL(1) to LBL(N), N second selection gate lines CSG(1) to CSG(N), a bit line selection common word line BLSEL-CWL, a bit line equalization common word line BLEQ-CWL, and a precharge voltage line Vpre.

[0108] In an exemplary implementation, such as Figure 5As shown, the bit line selection circuit 20 is electrically connected to the bit line selection common word line BLSEL-CWL, N bit line power supply lines LBL(1) to LBL(N), N first select gate lines SG(1) to SG(N) and N bit lines BL(1) to BL(N), respectively. It is configured to provide the signals of the N bit line power supply lines LBL(1) to LBL(N) to the N bit lines BL(1) to BL(N) during writing and provide the signals of the N bit lines BL(1) to BL(N) to the N bit lines BL(1) to BL(N) during reading.

[0109] In an exemplary embodiment, the bit line equalization circuit 30 is electrically connected to the bit line equalization common word line BLEQ-CWL, the precharge voltage line Vpre, N bit lines BL(1) to BL(N) and N second select gate lines CSG(1) to CSG(N), and is configured to provide the precharge voltage line Vpre signal to the N bit lines BL(1) to BL(N) under the control of the signals of the bit line equalization common word line BLEQ-CWL and the N second select gate lines CSG(1) to CSG(N).

[0110] In an exemplary embodiment, the signal of the nth first selection gate line SG(n) and the signal of the nth second selection gate line CSG(n) are inverse signals. That is, when the signal of the nth first selection gate line SG(n) is a high-level signal, the signal of the nth second selection gate line CSG(n) is a low-level signal, and when the signal of the nth first selection gate line SG(n) is a low-level signal, the signal of the nth second selection gate line CSG(n) is a high-level signal.

[0111] In an exemplary embodiment, the bit line selection circuit 20 includes N selection sub-circuits 200. The nth selection sub-circuit 200 is electrically connected to the bit line selection common word line BLSEL-CWL, the nth bit line power supply line LBL(n), the nth first select gate line SG(n), and the nth bit line BL(n), respectively. It is configured to, under the control of the signals of the bit line selection common word line BLSEL-CWL and the nth first select gate line SG(n), provide the signal of the nth bit line power supply line LBL(n) to the nth bit line BL(n) during writing, and provide the signal of the nth bit line BL(n) to the nth bit line power supply line LBL(n) during reading.

[0112] In an exemplary implementation, such as Figure 5As shown, the nth selector circuit includes a third transistor T3 and a fourth transistor T4. The gate electrode of the third transistor T3 is electrically connected to the bit line select common word line BLSEL-CWL; the first electrode of the third transistor T3 is electrically connected to the nth bit line power supply line LBL(n); the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4; the gate electrode of the fourth transistor T4 is electrically connected to the nth first select gate line SG(n); and the second electrode of the fourth transistor T4 is electrically connected to the nth bit line BL(n).

[0113] In an exemplary embodiment, the third transistor T3 and the fourth transistor T4 are N-type transistors.

[0114] In an exemplary implementation, such as Figure 5 As shown, the bit line equalization circuit 30 includes N equalization sub-circuits 300. The nth equalization sub-circuit is electrically connected to the bit line equalization common word line BLEQ-CWL, the precharge voltage line Vpre, the nth bit line BL(n), and the nth second selection gate line CSG(n), and is configured to provide the precharge voltage line Vpre signal to the nth bit line BL(n) under the control of the signals from the bit line equalization common word line BLEQ-CWL and the nth second selection gate line CSG(n).

[0115] In an exemplary implementation, such as Figure 5 As shown, the nth equalization sub-circuit 300 includes a fifth transistor T5 and a sixth transistor T6. The gate electrode of the fifth transistor T5 is electrically connected to the bit line equalization common word line BLEQ-CWL; the first electrode of the fifth transistor T5 is electrically connected to the pre-charge voltage line Vpre; the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6; the gate electrode of the sixth transistor T6 is electrically connected to the nth second selection gate line CSG(n); and the second electrode of the sixth transistor T6 is electrically connected to the nth bit line BL(n).

[0116] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0117] Figure 6 Schematic diagram of a semiconductor memory array Figure 2 .like Figure 6 As shown, the semiconductor memory array also includes: a bit line selection circuit 20, a bit line equalization circuit 30, N bit line power supply lines LBL(1) to LBL(N), N second selection gate lines CSG(1) to CSG(N) and a precharge voltage line Vpre.

[0118] In an exemplary implementation, such as Figure 6As shown, the bit line selection circuit 20 is electrically connected to N bit line power supply lines LBL(1) to LBL(N), N first select gate lines SG(1) to SG(N), and N bit lines BL(1) to BL(N), respectively. It is configured to provide the signals of the N bit line power supply lines LBL(1) to LBL(N) to the N bit lines BL(1) to BL(N) during writing, and provide the signals of the N bit lines BL(1) to BL(N) to the N bit line power supply lines LBL(1) to LBL(N) during reading.

[0119] In an exemplary implementation, such as Figure 6 As shown, the bit line equalization circuit 30 is electrically connected to the precharge voltage line Vpre, N bit lines BL(1) to BL(N) and N second selection gate lines CSG(1) to CSG(N), and is configured to provide the signal of the precharge voltage line Vpre to the N bit lines BL(1) to BL(N) under the control of the signals of the N second selection gate lines CSG(1) to CSG(N).

[0120] In an exemplary embodiment, the signal of the nth first selection gate line SG(n) and the signal of the nth second selection gate line CSG(n) are inverse signals. That is, when the signal of the nth first selection gate line SG(n) is a high-level signal, the signal of the nth second selection gate line CSG(n) is a low-level signal, and when the signal of the nth first selection gate line SG(n) is a low-level signal, the signal of the nth second selection gate line CSG(n) is a high-level signal.

[0121] In an exemplary implementation, such as Figure 6 As shown, the bit line selection circuit includes N selection sub-circuits 200. The nth selection sub-circuit 200 is electrically connected to the nth bit line power supply line LBL(n), the nth first selection gate line SG(n), and the nth bit line BL(n), respectively. It is configured to, under the control of the signal of the nth first selection gate line SG(n), provide the signal of the nth bit line power supply line LBL(n) to the nth bit line BL(n) during writing, and provide the signal of the nth bit line BL(n) to the nth bit line power supply line LBL(n) during reading.

[0122] In an exemplary implementation, such as Figure 6 As shown, the nth selector circuit includes a fourth transistor T4. The gate electrode of the fourth transistor T4 is electrically connected to the nth first selector gate line SG(n), the first electrode of the fourth transistor T4 is electrically connected to the nth bit line power supply line LBL(n), and the second electrode of the fourth transistor T4 is electrically connected to the nth bit line BL(n).

[0123] In an exemplary embodiment, the fourth transistor T4 is an N-type transistor.

[0124] In an exemplary implementation, such as Figure 6 As shown, the bit line equalization circuit 30 includes N equalization sub-circuits 300. The nth equalization sub-circuit 300 is electrically connected to the pre-charge voltage line Vpre, the nth bit line BL(n), and the nth second selection gate line CSG(n), and is configured to provide the pre-charge voltage line Vpre signal to the nth bit line BL(n) under the control of the signal from the nth second selection gate line CSG(n).

[0125] In an exemplary implementation, such as Figure 6 As shown, the nth equalization sub-circuit includes a sixth transistor T6. The gate electrode of the sixth transistor T6 is electrically connected to the nth second selection gate line CSG(n), the first electrode of the sixth transistor T6 is electrically connected to the pre-charge voltage line Vpre, and the second electrode of the sixth transistor T6 is electrically connected to the nth bit line BL(n).

[0126] In an exemplary embodiment, the sixth transistor T6 is an N-type transistor.

[0127] In an exemplary embodiment Figure 5 The provided semiconductor memory array may include: a substrate and a transistor device layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate. Figure 7 for Figure 5 A schematic diagram after the transistor device layer has been formed. Figure 8 for Figure 5 A schematic diagram after the formation of the first conductive layer. Figure 9 for Figure 5 A schematic diagram after the formation of the second conductive layer. Figure 10 for Figure 5 A schematic diagram after the formation of the third conductive layer.

[0128] like Figure 7 As shown, the transistor device layer includes at least: a first transistor, a second transistor and a storage capacitor located in the memory cell 10, a third transistor and a fourth transistor located in the select sub-circuit 200, a fifth transistor and a sixth transistor located in the equalization sub-circuit 300, a bit line BL, a bit line power supply line LBL and a precharge voltage line Vpre.

[0129] Combination Figure 4 and Figure 8As shown, the first conductive layer includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, and a sixth connecting electrode 56; the orthographic projection of the first connecting electrode 51 on the substrate at least partially overlaps with the orthographic projection of the gate electrode 25 of the first transistor on the substrate, the orthographic projection of the second connecting electrode 52 on the substrate at least partially overlaps with the orthographic projection of the gate electrode 26 of the second transistor on the substrate, the orthographic projection of the third connecting electrode 53 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the substrate, the orthographic projection of the fourth connecting electrode 54 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate, the orthographic projection of the fifth connecting electrode 55 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fifth transistor on the substrate, and the orthographic projection of the sixth connecting electrode 56 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate.

[0130] like Figure 9 As shown, the second conductive layer includes at least: a first selection gate line SG, a second selection gate line CSG, a seventh connection electrode 57, an eighth connection electrode 58, and a ninth connection electrode 59. The orthographic projection of the seventh connection electrode 57 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate and is electrically connected to the first connection electrode 51. The orthographic projection of the eighth connection electrode 58 on the substrate at least partially overlaps with the orthographic projection of the third connection electrode 53 on the substrate and is electrically connected to the third connection electrode 53. The orthographic projection of the ninth connection electrode 59 on the substrate at least partially overlaps with the orthographic projection of the fifth connection electrode 55 on the substrate and is electrically connected to the fifth connection electrode 55. The second selection gate line CSG is electrically connected to the sixth connection electrode 56. The first selection gate line SG is electrically connected to the second connection electrode 52 and the fourth connection electrode 54, respectively.

[0131] Combination Figure 9 and Figure 10 As shown, the third conductive layer includes at least: a common word line (CWL), a bit line select common word line (BLSEL-CWL), and a bit line equalization common word line (BLEQ-CWL). The common word line (CWL) is electrically connected to the seventh connecting electrode 57, the bit line select common word line (BLSEL-CWL) is electrically connected to the eighth connecting electrode 58, and the bit line equalization common word line (BLEQ-CWL) is electrically connected to the ninth connecting electrode 59.

[0132] In an exemplary embodiment Figure 6 The provided semiconductor memory array may include: a substrate and a transistor device layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate. Figure 11 for Figure 6 A schematic diagram after the transistor device layer has been formed. Figure 12 for Figure 6A schematic diagram after the formation of the first conductive layer. Figure 13 for Figure 6 A schematic diagram after the formation of the second conductive layer. Figure 14 for Figure 6 A schematic diagram after the formation of the third conductive layer.

[0133] like Figure 11 As shown, the transistor device layer includes at least: a first transistor, a second transistor and a storage capacitor located in the memory cell 10, a fourth transistor located in the select sub-circuit 200, a sixth transistor located in the equalization sub-circuit 300, a bit line BL, a bit line power supply line LBL and a pre-charge voltage line Vpre.

[0134] like Figure 12 As shown, the first conductive layer includes at least: a first connecting electrode 51, a second connecting electrode 52, a fourth connecting electrode 54, and a sixth connecting electrode 56; the orthographic projection of the first connecting electrode 51 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor on the substrate, the orthographic projection of the second connecting electrode 52 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the second transistor on the substrate, the orthographic projection of the fourth connecting electrode 54 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate, and the orthographic projection of the sixth connecting electrode 56 on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate.

[0135] like Figure 13 As shown, the second conductive layer includes at least: a first selection gate line SG, a second selection gate line CSG, and a seventh connection electrode 57. The orthographic projection of the seventh connection electrode 57 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate, and is electrically connected to the first connection electrode 51. The second selection gate line CSG is electrically connected to the sixth connection electrode 56, and the first selection gate line SG is electrically connected to the second connection electrode 52 and the fourth connection electrode 54, respectively.

[0136] like Figure 14 As shown, the third conductive layer includes at least a common word line CWL. The common word line CWL is electrically connected to the seventh connecting electrode 57.

[0137] In exemplary embodiments, the substrate can be a silicon substrate or other suitable substrate materials such as silicon, germanium, or silicon-germanium compounds, for example, doped or undoped single-crystal silicon substrates, polycrystalline silicon substrates, etc., and this application does not specifically limit this. Exemplarily, the substrate can be a wafer after front-end of line (FEOL) processing.

[0138] In an exemplary embodiment, the material of at least one of the first conductive layer, the second conductive layer, and the third conductive layer can be a metallic conductive material, specifically including but not limited to one or more of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), and ruthenium (Ru).

[0139] In an exemplary embodiment, an insulating layer is provided between the second conductive layer and the third conductive layer, and the insulating layer has through holes. Figure 5 The common word line in the provided semiconductor memory array is electrically connected to the seventh connection electrode 57 through a via in the insulating layer, the bit line select common word line BLSEL-CWL is electrically connected to the eighth connection electrode 58 through a via in the insulating layer, and the bit line equalization common word line BLEQ-CWL is electrically connected to the ninth connection electrode 59 through a via in the insulating layer. Figure 6 The common word line CWL in the provided semiconductor memory array is electrically connected to the seventh connection electrode 57 through a via in the insulating layer.

[0140] In an exemplary embodiment, the N bit power lines in the semiconductor memory array are arranged in a stepped structure. Because the N bit power lines are arranged in a stepped structure, the number of bit power lines depends on the length of the stepped structure, thereby achieving maximum area efficiency.

[0141] In an exemplary embodiment, the number of common word lines in the semiconductor memory array provided by this disclosure depends on the load of the common word lines and the transistor fabrication process, which can expand the application range of semiconductor memory arrays.

[0142] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the spacing L1 of the common word line connecting adjacent rows of memory cells depends on the spacing of the memory cells in the y direction.

[0143] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the spacing L2 of the first selection gate line connecting adjacent column storage cells depends on the spacing of the cells in the x-direction.

[0144] In an exemplary embodiment, the area of ​​the semiconductor memory array provided in this disclosure depends on the size of each memory cell and the size of the stepped structure of the N bit line power supply lines, and is not limited by the size of the common word line.

[0145] In an exemplary implementation, such as Figure 7 and Figure 10 As shown, the storage cells 10 located in adjacent columns of the same row are symmetrically arranged with respect to the first center line, wherein the first center line is the center line of the two first selection gate lines connected to the storage cells 10 located in adjacent columns of the same row.

[0146] In an exemplary implementation, such as Figure 7 and Figure 10 As shown, the adjacent select sub-circuits 200 are symmetrically arranged with respect to the first center line, wherein the first center line is the center line of the two first select gate lines connected to the memory cells located in adjacent columns of the same row.

[0147] In an exemplary implementation, such as Figure 7 and Figure 10 As shown, the adjacent equalization sub-circuits 300 are symmetrically arranged with respect to the first center line, wherein the first center line is the center line of the two first selection gate lines connected to the memory cells located in adjacent columns of the same row.

[0148] Figure 15 A schematic diagram of the structure of the semiconductor memory array layer provided in this disclosure. Figure 1 , Figure 16 A schematic diagram of the structure of the semiconductor memory array layer provided in this disclosure. Figure 2 . Figure 15 Based on semiconductor memory array Figure 5 The provided semiconductor memory array will be used as an example for illustration. Figure 16 Based on semiconductor memory array Figure 6 The provided semiconductor memory array will be used as an example for illustration.

[0149] This disclosure also provides a semiconductor memory, including: a plurality of stacked semiconductor memory array layers. For example... Figure 15 and Figure 16 As shown, at least one semiconductor memory array layer includes: a first semiconductor memory array 1 and a second semiconductor memory array 2, wherein the second semiconductor memory array 2 is a reference semiconductor memory array of the first semiconductor memory array 1, and the first semiconductor memory array 1 and the second semiconductor memory array 2 are semiconductor memory arrays provided in any of the foregoing embodiments.

[0150] The region R1 in the first semiconductor memory array 1, where the N bit power supply lines LBL(1) to LBL(N) form a stepped structure, is adjacent to the region R2 in the second semiconductor memory array 2, where the N bit power supply lines LBL(1) to LBL(N) form a stepped structure.

[0151] In an exemplary embodiment, at least one semiconductor memory array layer further includes a sensing amplifier 40. The sensing amplifier 40 is electrically connected to N bit line power supply lines LBL(1) to LBL(N) in the first semiconductor memory array 1 and N bit line power supply lines LBL(1) to LBL(N) in the second semiconductor memory array 2, and is located within the region R where the N bit line power supply lines LBL(1) to LBL(N) in the first semiconductor memory array 1 and the N bit line power supply lines LBL(1) to LBL(N) in the second semiconductor memory array 2 are located.

[0152] This disclosure reduces the sensing mismatch problem by electrically connecting a sensing amplifier to N bit line power supply lines in a first semiconductor memory array and N bit line power supply lines in a second semiconductor memory array, which serves as a reference semiconductor memory array for the first semiconductor memory array, respectively. The sensing amplifier is located within the regions where the N bit line power supply lines in the first semiconductor memory array and the N bit line power supply lines in the second semiconductor memory array are located.

[0153] In an exemplary embodiment, the semiconductor memory is a dynamic random access memory (DRAM).

[0154] This disclosure also provides a data processing method, applied to the semiconductor memory array provided in any of the foregoing embodiments, the data processing method comprising the following steps:

[0155] Step S1: Under the control of the signal lines of the m-th row and n-th column memory cell, the control sub-circuit stores the signal of the n-th bit line in the connection node during writing, or reads the signal of the connection node to the n-th bit line during reading.

[0156] Step S2: The storage sub-circuit of the m-th row and n-th column storage cell stores the voltage difference between the signal of the connection node and the signal of the power supply voltage line.

[0157] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0158] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0159] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0160] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor memory array, characterized in that, include: M rows and N columns of memory cells, power supply voltage lines, M common word lines, N first select gate lines and N bit lines; The storage unit in row m and column n includes: a control sub-circuit and a storage sub-circuit; The control sub-circuit is electrically connected to the m-th common word line, the n-th first select gate line, the n-th bit line, and the connection node, respectively. It is configured to, under the control of the signal lines of the m-th common word line and the n-th first select gate line, store the signal of the n-th bit line in the connection node during writing, or read the signal of the connection node to the n-th bit line during reading. The storage sub-circuit is electrically connected to the connection node and the power supply voltage line, respectively, and is configured to store the voltage difference between the signals of the connection node and the power supply voltage line.

2. The semiconductor memory array according to claim 1, characterized in that, The control sub-circuit in the m-th row and n-th column memory cell includes: a first transistor and a second transistor; The gate electrode of the first transistor is electrically connected to the m-th common word line, the first terminal of the first transistor is electrically connected to the connection node, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate electrode of the second transistor is electrically connected to the n-th first select gate line, and the second terminal of the second transistor is electrically connected to the n-th bit line, 1≤m≤M, 1≤n≤N.

3. The semiconductor memory array according to claim 2, characterized in that, The storage sub-circuit in the storage cell at row m and column n includes: a storage capacitor; The first end of the storage capacitor is electrically connected to the power supply voltage line, and the second end of the storage capacitor is electrically connected to the connection node.

4. The semiconductor memory array according to claim 3, characterized in that, Transistors include: Active layer; The active layer of the first transistor and the active layer of the second transistor, located in the same memory cell, are a single structure.

5. The semiconductor memory array according to claim 4, characterized in that, The integrated structure of the active layer of the first transistor and the active layer of the second transistor located in the same memory cell includes: a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked together, wherein the plurality of first semiconductor layers and the plurality of second semiconductor layers are alternately arranged.

6. The semiconductor memory array according to claim 1, characterized in that, Also includes: Bit line selection circuit, bit line equalization circuit, N bit line power supply lines, N second selection gate lines, bit line selection common word line, bit line equalization common word line and precharge voltage line; The bit line selection circuit is electrically connected to the bit line selection common word line, N bit line power supply lines, N first selection gate lines and N bit lines respectively, and is configured to provide the signals of the N bit line power supply lines to the N bit lines during writing and provide the signals of the N bit lines to the N bit line power supply lines during reading under the control of the signals of the bit line selection common word line and the N first selection gate lines. The bit line equalization circuit is electrically connected to the bit line equalization common word line, the precharge voltage line, N bit lines and N second select gate lines respectively, and is configured to provide the precharge voltage line signal to the N bit lines under the control of the signals of the bit line equalization common word line and the N second select gate lines. The signals of the first selection gate line n and the second selection gate line n are inverse signals.

7. The semiconductor memory array according to claim 6, characterized in that, The bit line selection circuit includes: N selection sub-circuits; The nth select sub-circuit is electrically connected to the bit line select common word line, the nth bit line power supply line, the nth first select gate line, and the nth bit line, respectively. It is configured to provide the signal of the nth bit line power supply line to the nth bit line during writing and provide the signal of the nth bit line to the nth bit line power supply line during reading, under the control of the signals of the bit line select common word line and the nth first select gate line.

8. The semiconductor memory array according to claim 7, characterized in that, The nth selector circuit includes: the third transistor and the fourth transistor; The gate electrode of the third transistor is electrically connected to the bit line select common word line, the first electrode of the third transistor is electrically connected to the nth bit line power supply line, the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor, the gate electrode of the fourth transistor is electrically connected to the nth first select gate line, and the second electrode of the fourth transistor is electrically connected to the nth bit line.

9. The semiconductor memory array according to claim 8, characterized in that, The bit-line equalization circuit includes: N equalization sub-circuits; The nth equalization sub-circuit is electrically connected to the bit line equalization common word line, the precharge voltage line, the nth bit line, and the nth second select gate line, and is configured to provide the precharge voltage line signal to the nth bit line under the control of the signals of the bit line equalization common word line and the nth second select gate line.

10. The semiconductor memory array according to claim 9, characterized in that, The nth equalization sub-circuit includes: the fifth transistor and the sixth transistor; The gate electrode of the fifth transistor is electrically connected to the bit line equalization common word line, the first electrode of the fifth transistor is electrically connected to the precharge voltage line, the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, the gate electrode of the sixth transistor is electrically connected to the nth second selection gate line, and the second electrode of the sixth transistor is electrically connected to the nth bit line.

11. The semiconductor memory array according to claim 1, characterized in that, Also includes: Bit line selection circuit, bit line equalization circuit, N bit line power supply lines, N second selection gate lines and pre-charge voltage lines; The bit line selection circuit is electrically connected to N bit line power supply lines, N first selection gate lines and N bit lines respectively, and is configured to provide the signals of the N bit line power supply lines to the N bit lines during writing and provide the signals of the N bit lines to the N bit line power supply lines during reading under the control of the signals of the N first selection gate lines. The bit line equalization circuit is electrically connected to the precharge voltage line, N bit lines and N second selection gate lines respectively, and is configured to provide the precharge voltage line signal to the N bit lines under the control of the signal of the N second selection gate lines. The signals of the first selection gate line n and the second selection gate line n are inverse signals.

12. The semiconductor memory array according to claim 11, characterized in that, The bit line selection circuit includes: N selection sub-circuits; The nth selector circuit is electrically connected to the nth bit line power supply line, the nth first select gate line, and the nth bit line, respectively. It is configured to provide the signal of the nth bit line power supply line to the nth bit line during writing and provide the signal of the nth bit line to the nth bit line power supply line during reading, under the control of the signal of the nth first select gate line.

13. The semiconductor memory array according to claim 12, characterized in that, The nth selector circuit includes: the fourth transistor; The gate electrode of the fourth transistor is electrically connected to the nth first select gate line, the first electrode of the fourth transistor is electrically connected to the nth bit line power supply line, and the second electrode of the fourth transistor is electrically connected to the nth bit line.

14. The semiconductor memory array according to claim 13, characterized in that, The bit-line equalization circuit includes: N equalization sub-circuits; The nth equalization sub-circuit is electrically connected to the pre-charge voltage line, the nth bit line, and the nth second selection gate line, and is configured to provide the pre-charge voltage line signal to the nth bit line under the control of the signal of the nth second selection gate line.

15. The semiconductor memory array according to claim 14, characterized in that, The nth equalization sub-circuit includes: the sixth transistor; The gate electrode of the sixth transistor is electrically connected to the nth second select gate line, the first electrode of the sixth transistor is electrically connected to the precharge voltage line, and the second electrode of the sixth transistor is electrically connected to the nth bit line.

16. The semiconductor memory array according to claim 10, characterized in that, include: A substrate and a transistor device layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate; The transistor device layer includes at least: a first transistor, a second transistor and a storage capacitor located in the memory cell; a third transistor and a fourth transistor located in the select sub-circuit; a fifth transistor and a sixth transistor located in the equalization sub-circuit; a bit line; a bit line power supply line and a pre-charge voltage line. The first conductive layer includes at least: a first connecting electrode, a second connecting electrode, a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode, and a sixth connecting electrode; the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor on the substrate, the orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the second transistor on the substrate, the orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the substrate, the orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate, the orthographic projection of the fifth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fifth transistor on the substrate, and the orthographic projection of the sixth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate. The second conductive layer includes at least: a first selection gate line, a second selection gate line, a seventh connection electrode, an eighth connection electrode, and a ninth connection electrode. The orthographic projection of the seventh connection electrode on the substrate at least partially overlaps with the orthographic projection of the first connection electrode on the substrate and is electrically connected to the first connection electrode. The orthographic projection of the eighth connection electrode on the substrate at least partially overlaps with the orthographic projection of the third connection electrode on the substrate and is electrically connected to the third connection electrode. The orthographic projection of the ninth connection electrode on the substrate at least partially overlaps with the orthographic projection of the fifth connection electrode on the substrate and is electrically connected to the fifth connection electrode. The second selection gate line is electrically connected to the sixth connection electrode. The first selection gate line is electrically connected to the second connection electrode and the fourth connection electrode, respectively. The third conductive layer includes at least: a common word line, a bit line select common word line, and a bit line equalization common word line, wherein the common word line is electrically connected to the seventh connection electrode, the bit line select common word line is electrically connected to the eighth connection electrode, and the bit line equalization common word line is electrically connected to the ninth connection electrode.

17. The semiconductor memory array according to claim 15, characterized in that, include: A substrate and a transistor device layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate; The transistor device layer includes at least: a first transistor, a second transistor and a storage capacitor located in the memory cell; a fourth transistor located in the select sub-circuit; a sixth transistor located in the equalization sub-circuit; a bit line; a bit line power supply line and a pre-charge voltage line. The first conductive layer includes at least: a first connecting electrode, a second connecting electrode, a fourth connecting electrode, and a sixth connecting electrode; the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor on the substrate, the orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the second transistor on the substrate, the orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fourth transistor on the substrate, and the orthographic projection of the sixth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate. The second conductive layer includes at least: a first selection gate line, a second selection gate line, and a seventh connection electrode. The orthographic projection of the seventh connection electrode on the substrate at least partially overlaps with the orthographic projection of the first connection electrode on the substrate and is electrically connected to the first connection electrode. The second selection gate line is electrically connected to the sixth connection electrode, and the first selection gate line is electrically connected to the second connection electrode and the fourth connection electrode, respectively. The third conductive layer includes at least a common word line, wherein the common word line is electrically connected to the seventh connecting electrode.

18. The semiconductor memory array according to claim 16 or 17, characterized in that, The memory cells located in adjacent columns of the same row are arranged symmetrically with respect to the first center line, wherein the first center line is the center line of the two first selection gate lines connected to the memory cells located in adjacent columns of the same row.

19. The semiconductor memory array according to claim 16 or 17, characterized in that, The adjacent select sub-circuits are arranged symmetrically with respect to the first center line, wherein the first center line is the center line of the two first select gate lines connected to the memory cells located in adjacent columns of the same row.

20. The semiconductor memory array according to claim 16 or 17, characterized in that, The adjacent equalization sub-circuits are arranged symmetrically with respect to the first center line, wherein the first center line is the center line of the two first selection gate lines connected to the memory cells located in adjacent columns of the same row.

21. The semiconductor memory array according to claim 6 or 11, characterized in that, The N bit power supply lines are arranged in a stepped structure.

22. A semiconductor memory, characterized in that, include: Multiple stacked semiconductor memory array layers; At least one semiconductor memory array layer includes: a first semiconductor memory array and a second semiconductor memory array, wherein the second semiconductor memory array is a reference semiconductor memory array for the first semiconductor memory array, and the first semiconductor memory array and the second semiconductor memory array are semiconductor memory arrays as described in any one of claims 1 to 20; The region in the first semiconductor memory array where the N bit power lines form a stepped structure is adjacent to the region in the second semiconductor memory array where the N bit power lines form a stepped structure.

23. The semiconductor memory according to claim 22, characterized in that, At least one semiconductor memory array layer further includes: a sense amplifier; The sensing amplifier is electrically connected to the N bit line power supply lines in the first semiconductor memory array and the N bit line power supply lines in the second semiconductor memory array, respectively, and is located in the area where the N bit line power supply lines in the first semiconductor memory array and the N bit line power supply lines in the second semiconductor memory array are located.

24. The semiconductor memory according to claim 22, characterized in that, The semiconductor memory is a dynamic random access memory.

25. A data processing method, characterized in that, Applied to a semiconductor memory array as described in any one of claims 1 to 21, The control sub-circuit of the m-th row and n-th column memory cell, under the control of the signal lines of the m-th common word line and the n-th first select gate line, stores the signal of the n-th bit line in the connection node during writing, or reads the signal of the connection node to the n-th bit line during reading. The storage sub-circuit of the m-th row and n-th column storage cell stores the voltage difference between the signal of the connection node and the signal of the power supply voltage line.

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