A packaging structure combining a high-rigidity substrate and a printed circuit board, and its fabrication method.

Abstract

This invention provides a packaging structure combining a high-rigidity substrate and a printed circuit board, comprising: an asymmetric high-rigidity core layer packaging substrate; a buffer substrate located at the bottom of the high-rigidity packaging substrate; the buffer substrate consisting of at least two sub-buffer material layers or sub-BT core layers with different coefficients of thermal expansion, the coefficients of thermal expansion of which are distributed in a gradient increasing manner from top to bottom; the lower layer of the buffer substrate is coupled to the printed circuit board via solder balls. The solution provided in this application achieves coupling between the asymmetric high-rigidity core layer packaging substrate and the printed circuit board through the buffer substrate with a gradient distribution of coefficients of thermal expansion. By buffering the difference in thermal expansion through progressively increasing coefficients of thermal expansion, the risk of interface delamination is effectively reduced. This solution alleviates the stress concentration problem caused by the difference in coefficients of thermal expansion between the glass substrate and the printed circuit board, and improves the reliability of the packaging structure.

Description

Technical Field

[0001] This application relates to the field of electronic packaging technology, and more specifically, to a packaging structure combining a high-rigidity substrate and a printed circuit board, and a method for preparing the same. Background Technology

[0002] In conventional packaging structures, the electronic component carrier die (substrate) with a core layer carries the chip on top and is coupled to the printed circuit board (PCB) on the bottom layer. The ball-mounting process precisely places solder balls on the pads, a key process for achieving the electromechanical connection between the chip and the substrate. With the development of high-performance AI chips, the demands for high-frequency signal loss and large sizes resulting from system-in-package (SiP) have led to the development of advanced packaging technologies using glass substrates, leveraging their low dielectric constant, high rigidity, low coefficient of thermal expansion, and high mechanical stability. Currently, glass substrates are increasingly replacing organic (resin-core) BT core substrates.

[0003] While using a glass substrate as the core layer in a packaging substrate offers the aforementioned advantages, the immature manufacturing process and high technology and equipment costs have hindered the rapid market adoption of glass packaging substrates. In specialized glass packaging substrate structures, placing the core layer in the lower region of the substrate can achieve fan-out circuitry, reduce the number of layers, and decrease substrate warping. However, the glass substrate, with its low coefficient of thermal expansion, is located at the bottom and interconnected with the printed circuit board (PCB) via solder balls. The PCB, on the other hand, often has a higher coefficient of thermal expansion. When the difference in thermal expansion coefficients is too significant, the packaging substrate may experience thermal stress concentration and interface delamination under high temperatures. This can lead to stress concentration at the interface between the solder balls and the substrate or PCB, repeated shear stress on the solder balls causing fatigue and crack formation, solder joint breakage or electrical failure, and warping of the packaging structure due to non-uniform expansion. Summary of the Invention

[0004] The purpose of this application is to provide a packaging structure that combines a high-rigidity substrate and a printed circuit board and its preparation method, which has the advantages of alleviating the stress concentration problem caused by the difference in thermal expansion coefficients between the glass substrate and the printed circuit board and improving the reliability of the packaging structure.

[0005] This application provides a packaging structure combining a high-rigidity substrate and a printed circuit board. The technical solution is as follows: an asymmetrical high-rigidity core layer packaging substrate, the top layer of which is used to carry chips or electronic components, and the bottom layer is connected to a buffer substrate; the buffer substrate is located at the bottom of the high-rigidity packaging substrate and is electrically connected through through-holes; the buffer substrate is composed of at least two material layers with different coefficients of thermal expansion, and the coefficients of thermal expansion are distributed in a gradient increasing manner from top to bottom; the bottom layer of the packaging structure is coupled to the printed circuit board through solder balls.

[0006] Furthermore, this application also proposes that the buffer substrate includes a sub-buffer 1 layer, a sub-resin core 1 layer, a sub-BT Core 1 layer, a sub-buffer 2 layer, a sub-BTCore 2 layer, and a sub-buffer 3 layer stacked sequentially, wherein the thermal expansion coefficients of each layer satisfy the following relationship: sub-buffer 3 layer > sub-buffer 2 layer > sub-buffer 1 layer, and sub-BT Core 2 layer > sub-BT Core 1 layer.

[0007] Furthermore, this application also proposes that the buffer substrate includes a sub-Buffer 1 layer, a sub-BTCore 1 layer and a sub-Buffer 2 layer stacked in sequence, wherein the thermal expansion coefficients of each layer satisfy the relationship: sub-Buffer 2 layer _ sub-BTCore 1 layer _ sub-Buffer 1 layer.

[0008] Furthermore, this application also proposes that the buffer layer material is a non-conductive material composed of organic, inorganic, or composite materials, including an insulating adhesive film or a non-conductive film (NCF); and the BT Core layer material is an organic or composite material.

[0009] Furthermore, this application proposes that the high-rigidity core layer is a glass substrate with a coefficient of thermal expansion of 3~4 ppm / ℃; the printed circuit board has a coefficient of thermal expansion of 30~60 ppm / ℃; the sub-buffer 1 layer, sub-buffer 2 layer, and sub-buffer 3 layer have coefficients of thermal expansion of 5~10 ppm / ℃, 10~15 ppm / ℃, and 15~25 ppm / ℃, respectively; and the sub-BT Core 1 layer and sub-BT Core 2 layer have coefficients of thermal expansion of 8~10 ppm / ℃ and 12~15 ppm / ℃, respectively.

[0010] Furthermore, this application also proposes that the overall thickness of the buffer substrate is less than the thickness of the asymmetric packaging substrate and the printed circuit board.

[0011] Furthermore, this application also proposes that the upper layer linewidth and line spacing of the asymmetric packaging substrate are smaller than the lower layer linewidth and line spacing, and the upper layer copper thickness is smaller than the lower layer copper thickness, thereby realizing a fan-out circuit design.

[0012] Furthermore, this application also proposes that the thermal expansion coefficient distribution of the overall packaging structure from the chip to the printed circuit board is as follows: chip → dielectric layer → glass substrate → sub-buffer 1 layer → sub-BT Core 1 layer → sub-buffer 2 layer → printed circuit board, and the corresponding expansion coefficients are as follows: low → medium → low → low → medium → high → high.

[0013] Furthermore, this application also proposes that the coefficient of thermal expansion of the buffer substrate exhibits a gradient relationship from top to bottom: low → medium → high.

[0014] Furthermore, this application also proposes a method for fabricating the above-mentioned packaging structure, comprising: fabricating an asymmetric packaging substrate and a buffer substrate respectively; connecting the two through alignment and via processes; mounting a chip on the top layer of the packaging substrate, and coupling the bottom layer to the printed circuit board through solder balls. The buffer substrate consists of at least two material layers with different coefficients of thermal expansion, the coefficients of thermal expansion of which increase in a gradient from top to bottom.

[0015] As can be seen from the above, the packaging structure and its fabrication method that combine a high-rigidity substrate and a printed circuit board provided in this application, the asymmetric high-rigidity core layer packaging substrate is coupled with the printed circuit board through a buffer substrate with a gradient thermal expansion coefficient distribution. By buffering the thermal expansion difference through the progressively increasing thermal expansion coefficient value, the risk of interface delamination is effectively reduced. It has the advantages of alleviating the stress concentration problem caused by the difference in thermal expansion coefficient between the glass substrate and the printed circuit board and improving the reliability of the packaging structure. Attached Figure Description

[0016] Figure 1 A schematic diagram of the first prior art packaging provided;

[0017] Figure 2 A schematic diagram of a second prior art packaging is provided;

[0018] Figure 3 A schematic diagram of the third prior art packaging provided;

[0019] Figure 4 A schematic diagram of the fourth prior art packaging is provided;

[0020] Figure 5 A schematic diagram of the packaging structure of the high-rigidity substrate and printed circuit board provided in this application;

[0021] Figure 6A schematic diagram of another high-rigidity substrate and printed circuit board packaging structure provided in this application;

[0022] In the figure, 100 is the packaging substrate; 101 is the first dielectric layer; 102 is the glass substrate; and 103 is the second dielectric layer.

[0023] 1. Chip; 200. Buffer substrate; 201. Sub-Buffer 1 layer; 202. Sub-BT Core 1 layer; 203. Sub-Buffer 2 layer; 204. Sub-BT Core 2 layer; 205. Sub-Buffer 3 layer;

[0024] 300. Printed circuit boards. Detailed Implementation

[0025] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] like Figures 1-4 In conventional packaging structures, electronic component carrier wafers with a core layer, such as glass or resin core substrates, have a top layer supporting the chip and a dielectric layer, and a bottom layer coupled to the printed circuit board. Solder balls are precisely placed on the solder pads using a ball-mounting process. Figure 1 This is a key process for achieving electromechanical connections between the chip and the substrate. With the development of high-performance AI chips, the demands for high-frequency signal loss and large-size applications resulting from system-in-package (SiP) are increasing. The low dielectric constant (3.8 at 1 GHz), high rigidity (≥70 GPa), low coefficient of thermal expansion (3~4 ppm / ℃), and high mechanical stability (thickness up to 100 μm) of glass substrates have enabled the establishment of a technological pinnacle in advanced packaging. Currently, glass substrates are showing a trend of replacing organic BT Core substrates, such as... Figure 2 .

[0027] While using glass substrates as the core layer in a packaging substrate offers the aforementioned advantages, the immature manufacturing processes and high technology and equipment costs have hindered the rapid market adoption of glass packaging substrates. Currently, many packaging plants and substrate manufacturers are investing in this area to overcome these challenges. In special glass packaging substrate structures, asymmetric packaging substrates place the core layer in the lower layer of the packaging substrate, such as... Figure 3 and other structural combinations, such as Figure 4 Placing the glass core layer at the bottom of the packaging substrate enables fan-out circuit design, reduces the number of layers, and reduces substrate warping. However, the glass substrate with a low coefficient of thermal expansion (CTE) is located at the bottom of the substrate and is interconnected with the printed circuit board by solder balls. The coefficient of thermal expansion (z-axis) of the printed circuit board is often higher, such as 30~60 ppm / ℃. When the difference in the coefficients of thermal expansion between the two is too significant, the packaging substrate may experience thermal stress concentration and interface delamination under high temperature environments (such as 260℃ Reflow). This can lead to stress concentration at the interface between the solder balls and the substrate or printed circuit board, repeated shear stress on the solder balls causing solder ball fatigue and crack formation, solder joint breakage or electrical failure, and warping of the packaging structure due to non-uniform expansion.

[0028] In existing technologies, the packaging structure uses a glass substrate with a low coefficient of thermal expansion as the core layer, with its bottom directly connected to a printed circuit board with a high coefficient of thermal expansion via solder balls. Due to the significant difference in their coefficients of thermal expansion, severe thermal stress concentration occurs at the interface under high-temperature processes or temperature cycling conditions, leading to frequent problems such as solder joint fatigue cracks, interface delamination, and structural warping. This is particularly pronounced in large-size system-in-package applications, where the contact area between the substrate and the printed circuit board increases, making reliability issues caused by thermal expansion mismatch even more significant.

[0029] Thermodynamic analysis of the thermal expansion coefficient of multilayer materials reveals a gradual stress transition through gradient changes. Based on this, a buffer structure with a gradient distribution of thermal expansion coefficients is proposed to be constructed between the packaging substrate and the printed circuit board, decomposing the originally abrupt difference in thermal expansion into multiple intermediate transition stages.

[0030] Therefore, this application proposes a packaging structure that combines a high-rigidity substrate and a printed circuit board, such as... Figure 5The package substrate 100 includes an asymmetric, high-rigidity core layer, the top layer of which is used to carry the chip 1, and the bottom layer is connected to the buffer substrate 200. The buffer substrate 200 is located at the bottom of the high-rigidity package substrate 100 and is electrically connected through through-holes. The buffer substrate 200 is composed of at least two material layers with different coefficients of thermal expansion, and the coefficients of thermal expansion are distributed in a gradient increasing manner from top to bottom. The bottom layer of the buffer substrate 200 is coupled to the printed circuit board 300 through solder balls.

[0031] The packaging substrate 100 of the asymmetric high-rigidity core layer includes a first dielectric layer 101, a glass substrate 102, and a second dielectric layer 103, wherein the second dielectric layer 103 is thinner; in another embodiment, the packaging substrate 100 of the asymmetric high-rigidity core layer includes only the first dielectric layer 101 and the glass substrate 102.

[0032] The asymmetric high-rigidity core layer packaging substrate 100 refers to a rigid substrate with differentiated upper and lower structures. Specifically, it can be achieved by using a composite structure with fine circuitry in the top bearing area and a reinforcing layer in the bottom connection area. Its asymmetric design can simultaneously meet the requirements of high-precision component mounting and mechanical support. The multi-layer gradient structure of the buffer substrate 200 refers to a transitional structure formed by stacking material layers with progressively increasing coefficients of thermal expansion. Specifically, it can be achieved by alternating lamination of organic insulating films and inorganic filler materials, forming stress buffer zones through progressively increasing coefficients of thermal expansion. The gradient increasing distribution of coefficients of thermal expansion means that the coefficients of expansion of each material layer form a continuous or stepwise increasing sequence from top to bottom of the substrate along the vertical direction. Specifically, it can be achieved by selecting composite materials with different resin matrix and filler ratios. This distribution pattern can effectively decompose the abrupt changes in thermal expansion between the substrate and the printed circuit board 300.

[0033] Specifically, the top region of the packaging substrate 100 with its asymmetric high-rigidity core layer carries the chip 1 through a fine circuit layout, while the bottom region is electrically interconnected with the buffer substrate 200 through vias. When heated, the multi-layered gradient structure of the buffer substrate 200 involves the upper low-expansion material deforming in coordination with the high-rigidity substrate, the middle transition material absorbing some stress, and the lower high-expansion material expanding synchronously with the printed circuit board 300. This step-by-step transition mechanism disperses the shear stress generated by thermal expansion differences to the interfaces of each material, preventing stress concentration at a single solder joint interface. The via connection method ensures signal transmission continuity while allowing each material layer to expand freely in the planar direction, further reducing internal structural stress.

[0034] Through the above technical solutions, this application effectively reduces the thermal stress concentration at the interface between the packaging substrate 100 and the printed circuit board 300, preventing the propagation of microcracks at the solder ball interface caused by repeated thermal expansion differences. The introduction of a multi-layer gradient buffer structure allows thermal expansion deformation to be absorbed layer by layer in the vertical direction, avoiding electrical connection failures caused by structural warping. The through-hole interconnect method maintains electrical performance while providing free expansion space in the planar direction for each material layer, improving the long-term reliability of the packaging structure under temperature cycling conditions.

[0035] like Figure 5 This application further proposes that the buffer substrate 200 includes a sub-buffer 1 layer 201, a sub-BT Core 1 layer 202, a sub-buffer 2 layer 203, a sub-BT Core 2 layer 204 and a sub-buffer 3 layer 205 stacked sequentially, wherein the thermal expansion coefficients of each layer satisfy the following relationship: the sub-buffer 3 layer 205 is greater than the sub-buffer 2 layer 203, the sub-buffer 2 layer 203 is greater than the sub-buffer 1 layer 201, and the sub-BT Core 2 layer 204 is greater than the sub-BT Core 1 layer 202.

[0036] The buffer substrate 200 is a stress-reducing layer made of non-conductive material, specifically an insulating adhesive film or a non-conductive film, used to disperse the thermal expansion difference stress between the encapsulation substrate 100 and the printed circuit board 300. The BT Core layer is a supporting structure layer made of organic or composite materials, specifically a bismaleimide triazine resin substrate, used to enhance the mechanical strength of the buffer substrate and participate in the thermal expansion coefficient gradient distribution. The increasing thermal expansion coefficient gradient distribution means that the thermal expansion coefficient of each layer gradually increases from the encapsulation substrate 100 towards the printed circuit board 300, which can be achieved by selecting composite materials with different component ratios to form a smooth thermal expansion transition zone.

[0037] In one embodiment, the buffer substrate 200 constructs a five-layer composite structure by alternately stacking buffer layers and BT Core layers. The buffer layers increase in thermal expansion coefficient from sub-Buffer 1 layer 201 to sub-Buffer 3 layer 205, and the BT Core layers increase in thermal expansion coefficient from sub-BT Core 1 layer 202 to sub-BT Core 2 layer 204. This arrangement ensures that sub-Buffer 1 layer 201, closest to the packaging substrate 100, has the lowest thermal expansion coefficient, matching the low thermal expansion coefficient of the glass substrate 102; the intermediate BT Core layers provide structural support and participate in the transition of thermal expansion coefficients; and sub-Buffer 3 layer 205, closest to the printed circuit board 300, has the highest thermal expansion coefficient, matching the high thermal expansion coefficient of the printed circuit board 300. The materials of each layer are vertically electrically connected through vias. During thermal expansion, the gradually increasing difference in thermal expansion coefficients disperses interfacial shear stress, preventing stress concentration at a single material interface.

[0038] This solution employs a five-layer alternating stack design to achieve a stepped transition in the coefficient of thermal expansion while ensuring structural strength. Compared to the traditional three-layer buffer structure, this increases the thermal stress dispersion paths and reduces the risk of interface delamination. In existing technologies, the BT Core layer is typically used as an independent support layer without participating in the gradient design of the coefficient of thermal expansion. This solution innovatively incorporates the coefficient of thermal expansion of the BT Core layer into an increasing sequence, further optimizing the overall thermal expansion matching.

[0039] Through the above technical solution, this application effectively reduces the interfacial shear stress between the packaging substrate 100 and the printed circuit board 300 caused by the difference in thermal expansion coefficients, avoiding cracks or fractures of the solder balls due to stress concentration during high-temperature reflow soldering. The five-layer gradient structure allows thermal expansion deformation to be gradually released between the multi-layer interfaces, reducing the probability of solder joint failure compared to traditional structures. At the same time, the alternating arrangement of BT Core layers enhances the bending resistance of the buffer substrate, reducing warpage during temperature cycling tests.

[0040] In another embodiment, this application proposes a buffer substrate structure comprising a sub-Buffer 1 layer 201, a sub-BT Core 1 layer 202, and a sub-Buffer 2 layer 203 stacked sequentially, wherein the thermal expansion coefficients of each layer satisfy the following relationship: the thermal expansion coefficient of the sub-Buffer 2 layer 203 is higher than that of the sub-BT Core 1 layer 202, and the thermal expansion coefficient of the sub-BT Core 1 layer 202 is higher than that of the sub-Buffer 1 layer 201.

[0041] The buffer substrate 200 refers to a multi-layered composite structure disposed between the packaging substrate 100 and the printed circuit board 300. Specifically, it can be constructed using layers of organic, inorganic, or non-conductive composite materials to achieve a gradient transition in the coefficient of thermal expansion. The sub-buffer layer 1 201 is the bottom buffer material in direct contact with the packaging substrate 100. Specifically, it can be an insulating adhesive film with a coefficient of thermal expansion of 5-10 ppm / ℃, whose low expansion characteristics are used to match the glass substrate 102 of the packaging substrate 100. The sub-BT Core layer 1 202 is an intermediate support layer disposed between sub-buffer layer 1 201 and sub-buffer layer 203. Specifically, it can be an organic composite material with a coefficient of thermal expansion of 8-10 ppm / ℃, whose expansion coefficient is between that of the upper and lower buffer layers to form a transition. The sub-buffer layer 203 is the upper buffer material in contact with the printed circuit board 300. Specifically, it can be a non-conductive film with a coefficient of thermal expansion of 10-15 ppm / ℃, whose higher expansion characteristics are used to gradually approach the expansion coefficient of the printed circuit board 300.

[0042] Specifically, the buffer substrate achieves stress dispersion through a stepped distribution of the thermal expansion coefficients of the three layers. When the package structure is heated, the low expansion characteristics of the glass substrate 102 and the sub-Buffer 1 layer 201 are matched, reducing stress abrupt changes at the interface; the expansion coefficient of the intermediate sub-BT Core 1 layer 202 is higher than that of the sub-Buffer 1 layer 201 but lower than that of the sub-Buffer 2 layer 203, forming a gradual transition zone; the higher expansion coefficient of the sub-Buffer 2 layer 203 gradually approaches the characteristics of the printed circuit board 300, allowing the thermal expansion difference to be released step by step in the multilayer structure. This gradient distribution avoids the abrupt expansion difference that occurs when the glass substrate 102 and the printed circuit board 300 are in direct contact in the traditional structure, allowing thermal stress to be absorbed and dispersed layer by layer inside the buffer substrate.

[0043] This solution uses a precise expansion gradient design of three layers of materials to form an intermediate expansion transition zone between the glass substrate 102 and the printed circuit board 300, effectively reducing the stress concentration at the interface.

[0044] Through the above technical solution, this application solves the risk of interface delamination caused by the difference in thermal expansion coefficient between the glass substrate 102 and the printed circuit board 300, avoids cracks or fractures of the solder balls caused by shear stress concentration in high temperature environment, and suppresses the non-uniform expansion and warping phenomenon of the packaging structure when heated.

[0045] This application further proposes that the buffer layer material is composed of a non-conductive material made of organic, inorganic or composite materials, including an insulating adhesive film or a non-conductive film; and the core layer material is composed of organic or composite materials.

[0046] The buffer layer material refers to a non-conductive dielectric layer with a function of regulating the coefficient of thermal expansion. Specifically, it can be implemented using polyimide-based insulating adhesive films or epoxy resin-based non-conductive films. The gradient regulation of thermal expansion behavior is achieved through the combination of the flexibility of the polymer chain segments of organic materials and the rigidity of inorganic fillers. The core layer material refers to the substrate layer that serves as the supporting structure. Specifically, it can be implemented using glass fiber reinforced epoxy resin composite materials or carbon fiber reinforced polyphenylene ether composite materials. The synergistic optimization of the coefficient of thermal expansion and mechanical strength is achieved through the fiber orientation distribution and the resin matrix ratio.

[0047] Specifically, the use of non-conductive materials in the buffer layer avoids the risk of interlayer short circuits. The insulating adhesive film absorbs interfacial shear stress through the elastic deformation of polymer chain segments, and the inorganic filler dispersion system in the non-conductive film can adjust the coefficient of thermal expansion. When the core layer uses organic composite materials, the fiber reinforcement phase and the resin matrix form an interlocking structure, and stress dispersion is achieved through the differential deformation of fibers and resin when thermally expanded. When the encapsulation structure undergoes temperature changes, the thermal expansion gradient formed by the buffer layer and the core layer causes each layer of material to deform step by step in a preset order. The buffer layer absorbs the thermal expansion displacement of the lower printed circuit board through elastic deformation, and the core layer inhibits the deformation transmission to the upper glass substrate 102 through the synergistic effect of fibers and resin, thereby eliminating the sudden change in thermal stress between the glass substrate 102 and the printed circuit board 300.

[0048] This solution constructs a multi-layered thermal expansion transition zone by combining a non-conductive buffer layer with an organic composite core layer. This allows the difference in thermal expansion coefficients to be gradually released through the deformation of multiple material levels, preventing stress from accumulating at specific interfaces.

[0049] Through the above technical solutions, this application effectively mitigates the risk of interface delamination caused by the difference in thermal expansion coefficients between the glass substrate 102 and the printed circuit board 300, suppresses the concentration of shear stress at the solder joints, and prevents electrical failure caused by microcracks in the solder balls during temperature cycling. Meanwhile, the selection of non-conductive materials avoids the risk of interlayer short circuits, and the processability of organic composite materials ensures the molding accuracy of the multilayer structure.

[0050] This application further proposes that the high-rigidity core layer is a glass substrate 102 with a coefficient of thermal expansion of 3~4 ppm / ℃; the printed circuit board has a coefficient of thermal expansion of 30~60 ppm / ℃; the sub-buffer 1 layer 201, sub-buffer 2 layer 203, and sub-buffer 3 layer 205 have coefficients of thermal expansion of 5~10 ppm / ℃, 10~15 ppm / ℃, and 15~25 ppm / ℃, respectively; and the sub-BTCore 1 layer 202 and sub-BT Core 2 layer 204 have coefficients of thermal expansion of 8~10 ppm / ℃ and 12~15 ppm / ℃, respectively.

[0051] The high-rigidity core layer refers to a glass substrate 102 with high mechanical strength, specifically made of glass material with a thickness of 100 micrometers. Its coefficient of thermal expansion is much lower than that of the printed circuit board material, serving to support the chip and maintain structural stability. The buffer substrate 200 is a transitional structure composed of multiple layers of materials, specifically achieved by alternating stacks of insulating adhesive films and non-conductive films, with the coefficients of thermal expansion of each layer increasing in a gradient to gradually absorb the differences in thermal expansion between different materials. The BT core layer is a support layer composed of organic composite materials, specifically a composite of bismaleimide resin and glass fiber. Its coefficient of thermal expansion is between that of the glass substrate 102 and the printed circuit board 300, serving to coordinate the expansion behavior of adjacent material layers.

[0052] Specifically, a multi-layer buffer structure achieves a gradient transition in the coefficient of thermal expansion between the glass substrate 102 and the printed circuit board 300. The low coefficient of thermal expansion of the glass substrate 102 contrasts significantly with the high coefficient of thermal expansion of the printed circuit board 300, and the intermediate buffer substrate 200 forms a transition zone through progressively increasing coefficients of thermal expansion. For example, the coefficient of thermal expansion of sub-buffer 1 layer 201 is slightly higher than that of the glass substrate 102 but lower than that of the printed circuit board 300, which initially alleviates interface stress; the coefficients of thermal expansion of sub-buffer 2 layer 203 and sub-buffer 3 layer 205 gradually increase, forming an intermediate buffer layer; the coefficients of thermal expansion of sub-BT Core 1 layer 202 and sub-BT Core 2 layer 204 further fill the gap between the coefficients of thermal expansion between the glass substrate 102 and the printed circuit board 300. The difference in the coefficients of thermal expansion of each layer is controlled within the tolerable range between adjacent layers, avoiding stress concentration caused by abrupt changes in the coefficients of thermal expansion of a single layer, thereby achieving a continuous thermal expansion transition from the glass substrate 102 to the printed circuit board 300.

[0053] This solution inserts a multi-layered gradient buffer structure, namely a buffer substrate 200, between the glass substrate 102 and the printed circuit board 300, allowing the coefficient of thermal expansion to gradually transition from 3~4 ppm / ℃ to 30~60 ppm / ℃, effectively dispersing thermal stress. Existing technologies do not employ this layered gradient design, leading to a higher risk of delamination or cracking at solder joints. This solution, however, minimizes the expansion differences between adjacent material layers by precisely controlling the range of thermal expansion coefficients for each layer.

[0054] Through the above technical solution, this application effectively reduces the interface stress concentration problem caused by the difference in thermal expansion coefficients between the glass substrate 102 and the printed circuit board 300. In high-temperature process environments, such as during 260°C reflow soldering, the multi-layer buffer structure gradually absorbs the expansion deformation of different material layers, avoiding shear stress concentration at the solder ball interface. This significantly reduces the risk of solder ball delamination, suppresses the formation of microcracks inside the solder joint or at the interface, and thus improves the reliability of the packaging structure under thermal cycling conditions.

[0055] This application further proposes that the overall thickness of the buffer substrate 200 is less than the thickness of the asymmetric packaging substrate 100 and the printed circuit board.

[0056] The overall thickness of the buffer substrate 200 refers to the total vertical dimension of the intermediate structure composed of multiple layers of materials with different coefficients of thermal expansion. This thickness can be achieved by controlling the number of layers and the thickness of each layer, for example, by optimizing the lamination process or selecting ultra-thin material layers for stacking. The thickness of the asymmetric packaging substrate 100 refers to the total vertical dimension of the packaging substrate 100, including the glass substrate 102 and the upper and lower dielectric layers. This thickness can be achieved, for example, by adjusting the thickness of the glass substrate 102 or the number of dielectric layers. The thickness of the printed circuit board 300 refers to the total vertical dimension of the substrate structure containing multiple conductive and insulating layers, for example, by forming a standardized thickness using conventional lamination processes.

[0057] Specifically, the thickness of the buffer substrate 200 is limited to a level lower than that of the asymmetric packaging substrate 100 and the printed circuit board 300. This allows the buffer substrate 200 to mitigate differences in thermal expansion coefficients without excessively increasing the vertical distance of the signal transmission path. By keeping the total thickness of the buffer substrate 200 low, the signal transmission path from chip 1 to the printed circuit board 300 remains compact, avoiding high-frequency signal attenuation or increased delay due to excessively thick intermediate layers. In the buffer substrate composed of multilayer gradient materials, the thickness of each material layer is optimized to ensure a continuous transition of thermal expansion coefficients within a finite total thickness, while maintaining the integrity of the signal transmission path.

[0058] Through the above technical solution, this application avoids excessive extension of the signal transmission path by controlling the thickness of the buffer substrate 200 while ensuring the gradient transition of the thermal expansion coefficient. This solves the problem of high-frequency signal loss caused by excessive thickness of the intermediate layer, while maintaining the fan-out circuit design advantage of the asymmetric packaging substrate 100 and ensuring the electrical connection stability between the chip and the printed circuit board.

[0059] This application further proposes an asymmetric packaging substrate 100 with an upper layer linewidth and line spacing smaller than the lower layer linewidth and line spacing, and an upper layer copper thickness smaller than the lower layer copper thickness, thereby realizing a fan-out circuit design.

[0060] In this context, the asymmetric packaging substrate 100 refers to a substrate type where the upper and lower layers of the packaging substrate 100 differ in structural parameters. Specifically, a glass substrate 102 can be used as the core material, and this can be achieved by adjusting the dielectric layer thickness distribution. This differentiated design between the upper and lower layers balances thermal stress distribution and signal transmission requirements. Smaller upper layer linewidth and spacing means that the conductor width and spacing between adjacent conductors in the upper layer are smaller than the corresponding parameters in the lower layer. This can be achieved using photolithography to form micron-level linewidth and spacing, meeting the high-density interconnection requirements of chip 1. A thinner upper layer copper layer means that the metal thickness of the upper conductive layer is less than that of the lower conductive layer. This can be achieved by using electroplating to control the copper deposition thickness of different layers in stages, improving high-frequency signal transmission efficiency by reducing the impedance of the upper layer lines. A fan-out circuit design refers to a distribution pattern where the lines extending outward from the chip exhibit a decreasing density. This can be achieved by progressively increasing the linewidth and spacing layer by layer and increasing the gradient change in copper layer thickness, reducing signal transmission loss by shortening the electrical connection path.

[0061] Specifically, the upper layer uses smaller line widths, spacing, and copper thickness to form a high-density wiring area, meeting the fine interconnection requirements of chips or electronic components, while reducing line impedance to adapt to high-frequency signal transmission characteristics. The lower layer uses larger line widths, spacing, and copper thickness to form a support structure, enhancing the substrate's mechanical strength to resist deformation caused by thermal expansion, and utilizing the thick copper layer to improve current carrying capacity and heat dissipation efficiency. The gradient change in line width, spacing, and copper thickness from the upper to the lower layer forms a fan-out circuit structure, resulting in a uniform distribution of electrical connection paths between the chip and the printed circuit board from dense to sparse. This shortens the signal transmission distance and alleviates local stress concentration caused by differences in thermal expansion coefficients through the gradient transition of line distribution density.

[0062] This solution achieves functional partitioning of upper and lower layers through asymmetric design. The upper layer utilizes high-density wiring to adapt to the interconnect characteristics of the chip, while the lower layer has a reinforced structure to resist thermal stress deformation. At the same time, the gradient distribution of the fan-out lines effectively disperses the thermal expansion differences at the interface, avoiding solder joint failure caused by stress concentration.

[0063] Through the above technical solutions, this application solves the problem of thermal stress concentration caused by the difference in thermal expansion coefficients between the packaging substrate 100 and the printed circuit board. By optimizing signal transmission efficiency through asymmetrical circuit and copper thickness design, the electrical connection path is shortened and signal loss is reduced. At the same time, the gradient distribution of the fan-out circuit alleviates stress concentration at the interface, thereby improving the reliability and stability of the packaging structure.

[0064] like Figure 6This application further proposes that the overall thermal expansion coefficient distribution of the packaging structure from the chip to the printed circuit board is as follows: chip 1 → first dielectric layer 101 → glass substrate 102 → sub-buffer 1 layer 201 → sub-BT Core 1 layer 202 → sub-buffer 2 layer 203 → printed circuit board 300, and the corresponding expansion coefficients are low → medium → low → low → medium → high.

[0065] In this context, chip 1 refers to a semiconductor device, specifically a silicon-based chip, whose low coefficient of thermal expansion matches the dielectric layer to reduce interfacial stress. The dielectric layer is an insulating material layer located beneath chip 1, specifically made of polyimide or epoxy resin, with a moderate coefficient of thermal expansion serving as a transition layer between chip 1 and the glass substrate 102. The glass substrate 102 is the core layer of the encapsulation substrate 100, specifically made of glass with a low coefficient of thermal expansion, used to maintain structural rigidity and reduce expansion differences with the dielectric layer. Sub-Buffer 1 layer 201 is a first buffer layer, specifically made of a non-conductive film material with a low coefficient of thermal expansion, used to reduce abrupt changes in the coefficient of thermal expansion between the glass substrate 102 and sub-BT Core 1 layer 202. Sub-BT Core 1 layer 202 is a first organic composite material substrate, specifically made of BT resin with a moderate coefficient of thermal expansion, serving as an intermediate buffer layer between the glass substrate 102 and sub-Buffer 2 layer 203. Among them, sub-Buffer 2 layer 203 refers to the second buffer layer, which can be implemented using an insulating adhesive film material with a high coefficient of thermal expansion, to match the high coefficient of thermal expansion of the printed circuit board 300 and release interface stress.

[0066] Specifically, chip 1 is connected to glass substrate 102 via a first dielectric layer 101. The moderate coefficient of thermal expansion of the first dielectric layer 101 forms an initial transition between chip 1 and glass substrate 102. The low coefficient of thermal expansion of glass substrate 102 maintains the rigidity of the packaging substrate 100, and the sub-buffer 1 layer 201 below it further reduces the difference in coefficient of thermal expansion, avoiding stress concentration between glass substrate 102 and sub-BT Core 1 layer 202. The moderate coefficient of thermal expansion of sub-BT Core 1 layer 202 serves as an intermediate transition layer, forming a gradient increasing relationship with the high coefficient of thermal expansion of sub-buffer 2 layer 203, causing the coefficient of thermal expansion to gradually increase from glass substrate 102 to printed circuit board 300. Under high-temperature conditions, the difference in thermal expansion between the materials in each layer is released step by step through gradient distribution, avoiding shear stress at a single interface.

[0067] Compared to existing technologies, conventional packaging structures typically connect a glass substrate 102 with a low coefficient of thermal expansion (CTE) to a printed circuit board 300 with a high CTE directly using solder balls. This results in stress concentration at the interface due to the significant difference in CTE between the two components. This application introduces a multi-layered gradient structure consisting of sub-Buffer 1 layer 201, sub-BT Core 1 layer 202, and sub-Buffer 2 layer 203. This disperses the CTE difference across multiple interfaces and achieves step-by-step buffering through a stepped distribution, thereby reducing the risk of solder joint failure.

[0068] Through the above technical solution, this application effectively reduces the risk of interface delamination caused by the difference in thermal expansion coefficients between the glass substrate 102 and the printed circuit board 300, reduces the generation of microcracks inside the solder joints, and suppresses the warping deformation of the packaging structure under high temperature environment, thereby improving the overall reliability.

[0069] This application further proposes that the thermal expansion coefficient distribution of the buffer substrate 200 has a gradient relationship from top to bottom: low → medium → high.

[0070] The gradient relationship of thermal expansion coefficient distribution from low to medium to high from top to bottom refers to the gradual increase of the thermal expansion coefficients of different material layers of the Buffer substrate 200 along the vertical direction. Specifically, this can be achieved by stacking organic insulating adhesive films, non-conductive films, or composite materials. For example, it can be achieved by alternately stacking sub-Buffer 1 layer 201 with a low thermal expansion coefficient, sub-BT Core 1 layer 202 with a medium thermal expansion coefficient, and sub-Buffer 2 layer 203 with a high thermal expansion coefficient. This gradient distribution avoids interface stress concentration caused by abrupt changes in thermal expansion coefficients by matching the differences in expansion coefficients between adjacent materials layer by layer.

[0071] The gradient-increasing coefficient of thermal expansion (CTE) distribution achieves continuity through layered material transitions. Specifically, layers of materials with different CTE values ​​can be arranged sequentially. For example, the bottom layer uses a sub-Buffer 3 layer 205 with a CTE of 15-25 ppm / ℃, the middle layer uses a sub-BT Core 2 layer 204 with a CTE of 12-15 ppm / ℃, and the top layer uses a sub-Buffer 1 layer 201 with a CTE of 5-10 ppm / ℃. This structure creates a stress-buffered transition zone by progressively bridging the difference in CTE between the high-rigidity substrate and the printed circuit board.

[0072] Specifically, the buffer substrate 200 is composed of multiple layers of materials. The top layer, with its low coefficient of thermal expansion, matches the low coefficient of thermal expansion of the high-rigidity substrate. The middle layer, with its medium coefficient of thermal expansion, serves as a transition layer, while the bottom layer, with its high coefficient of thermal expansion, matches the high coefficient of thermal expansion of the printed circuit board. Under high-temperature conditions, the deformation caused by thermal expansion in each layer is progressively distributed through a gradient, limiting the deformation differences between adjacent layers to a tolerable range. For example, as the temperature rises, the bottom layer with its high coefficient of thermal expansion expands preferentially, followed by the middle layer, with the top layer expanding the least. This forms a bottom-up deformation transmission path, dispersing the shear stress at the interfaces.

[0073] Compared to existing technologies, traditional packaging structures using a single material or disordered layered structure for the Buffer substrate 200 cannot achieve a continuous transition in the coefficient of thermal expansion. For example, in existing technologies, directly connecting a substrate with a low coefficient of thermal expansion to a printed circuit board with a high coefficient of thermal expansion results in the solder joint experiencing extremely high shear stress due to the expansion difference between the two. This solution, however, uses a gradient distribution of coefficients of thermal expansion layers to gradually absorb the expansion difference between adjacent material layers, preventing stress concentration at a single interface.

[0074] Through the above technical solution, this application can effectively reduce the risk of interface delamination caused by the difference in thermal expansion coefficients between the packaging substrate 100 and the printed circuit board 300, reduce fatigue cracks in solder joints caused by repeated thermal cycling, and improve the reliability of the packaging structure in high-temperature environments. This solution, through matching the expansion coefficients of the layer transitions, allows thermal stress to be uniformly distributed in the multilayer structure, thereby avoiding solder joint breakage or electrical failure.

[0075] This application further proposes a fabrication method that includes separately fabricating an asymmetric packaging substrate 100 and a buffer substrate 200, connecting the two through alignment and via processes, mounting a chip on the top layer of the packaging substrate 100, and coupling the bottom layer to the printed circuit board 300 via solder balls. The buffer substrate 200 consists of at least two material layers with different coefficients of thermal expansion, the coefficients of thermal expansion of which increase in a gradient from top to bottom.

[0076] The asymmetric packaging substrate 100 refers to a substrate with differentiated structures between its upper and lower layers. Specifically, this can be achieved by using a design where the upper layer has a smaller linewidth and spacing than the lower layer, and a thinner copper layer than the lower layer. This structure enables fan-out circuit layouts and reduces the number of substrate layers. The buffer substrate 200 refers to a stress-reducing structure composed of multiple layers of materials, specifically organic, inorganic, or composite materials, with the thermal expansion coefficients of each layer arranged in a gradient to match the thermal expansion differences between adjacent components. Through-hole technology refers to forming through-channels through mechanical drilling or laser drilling. Specifically, electroplating filling technology can be used to achieve interlayer electrical interconnection, ensuring the integrity of the signal transmission path. Solder ball coupling refers to arranging an array of solder balls on the bottom of the substrate using surface mount technology. Specifically, reflow soldering technology can be used to achieve mechanical connection and electrical conduction with the printed circuit board 300.

[0077] Specifically, the fabrication process involves independently fabricating an asymmetric packaging substrate 100 and a buffer substrate 200. This separate fabrication method optimizes the process parameters of both, avoiding yield losses during composite structure fabrication. The asymmetric packaging substrate 100 supports the chip 1 through fine upper lines and reinforces the structure with thicker lower lines. The buffer substrate 200 forms a thermal expansion transition zone through the stacking of gradient thermal expansion coefficient material layers. A high-precision alignment device is then used to laminate the two substrates together, and vertical interconnection is achieved through vias. This process ensures connection reliability while avoiding the extension of signal transmission paths. Finally, the chip 1 is mounted on top of the packaging substrate 100, and the bottom is connected to the printed circuit board 300 via a solder ball array, forming a complete packaging structure. During this process, the gradient thermal expansion coefficient distribution of the buffer substrate 200 absorbs the stress generated by the difference in thermal expansion layer by layer, preventing stress concentration at the solder ball interface. The separate fabrication of the asymmetric packaging substrate 100 effectively improves the overall process yield.

[0078] Compared to existing technologies, traditional packaging substrates use an integrated structure to directly connect to the printed circuit board 300. The single material layer of this traditional substrate struggles to match the difference in thermal expansion coefficients between the high-rigidity substrate and the printed circuit board 300, leading to stress concentration at the interface under high-temperature conditions. This solution, however, uses separate fabrication of the asymmetric packaging substrate 100 and the gradient buffer substrate 200. This retains the high-rigidity substrate's advantage in supporting the chip 1 while achieving a gradual transition in thermal expansion coefficients through a multi-layer buffer structure. In existing technologies, the substrate and buffer layer typically employ simultaneous lamination processes, which can easily lead to interlayer misalignment due to differences in material shrinkage rates. The separate fabrication method in this solution allows for independent control of process parameters, enabling the selection of high-quality components for assembly, significantly improving fabrication efficiency.

[0079] Through the above technical solutions, this application effectively reduces the accumulation of thermal stress at the interface between the packaging substrate and the printed circuit board, preventing microcracks or interface delamination in the solder balls during high-temperature reflow soldering. The separate fabrication process allows for independent quality inspection and screening of the asymmetric substrate and the buffer substrate, avoiding resource waste caused by the overall scrapping of the composite structure. The buffer substrate with a gradient thermal expansion coefficient distribution forms a thermal expansion transition zone through the orderly arrangement of material layers, ensuring the integrity of the signal transmission path while maintaining structural stability. This method also provides flexible structural combination methods, allowing adjustment of the number of layers and material combinations of the buffer substrate according to different chip packaging requirements, achieving customized packaging structure design.

[0080] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A packaging structure combining a high-rigidity substrate and a printed circuit board, characterized in that, include: An asymmetric, high-rigidity core layer packaging substrate, with its top layer used to carry chips or electronic components and its bottom layer connected to the buffer substrate; The buffer substrate is located at the bottom of the high-rigidity core layer packaging substrate and is electrically connected through through-holes; The buffer substrate consists of at least two sub-buffer layers or sub-BT core layers with different coefficients of thermal expansion, and the coefficients of thermal expansion are distributed in a gradient increasing manner from top to bottom. The lower layer of the buffer substrate is coupled to the printed circuit board via solder balls.

2. The packaging structure according to claim 1, characterized in that, The buffer substrate comprises a sub-buffer 1 layer, a sub-BT Core 1 layer, a sub-buffer 2 layer, a sub-BT Core 2 layer, and a sub-buffer 3 layer stacked sequentially, wherein the thermal expansion coefficients of each layer satisfy the following relationship: Sub-Buffer 3 > Sub-Buffer 2 > Sub-Buffer 1, and Sub-BT Core 2 layer > Sub-BT Core 1 layer.

3. The packaging structure according to claim 1, characterized in that, The buffer substrate comprises a sub-buffer 1 layer, a sub-BT Core 1 layer, and a sub-buffer 2 layer stacked sequentially, wherein the thermal expansion coefficients of each layer satisfy the following relationship: Sub-Buffer 2 layers > Sub-BT Core 1 layer > Sub-Buffer 1 layer.

4. The packaging structure according to claim 2 or 3, characterized in that: The sub-buffer layer material is a non-conductive material composed of organic, inorganic, or composite materials, including insulating adhesive films or non-conductive films; The material of the sub-BT Core layer is organic or composite material.

5. The packaging structure according to claim 2, characterized in that: The high-rigidity core layer is a glass substrate with a thermal expansion coefficient of 3~4 ppm / ℃; The coefficient of thermal expansion of the printed circuit board is 30~60 ppm / ℃; The coefficients of thermal expansion of the sub-buffer 1, sub-buffer 2, and sub-buffer 3 are 5~10 ppm / ℃, 10~15 ppm / ℃, and 15~25 ppm / ℃, respectively. The coefficients of thermal expansion of the sub-BT Core 1 layer and the sub-BT Core 2 layer are 8~10 ppm / ℃ and 12~15 ppm / ℃, respectively.

6. The packaging structure according to claim 1, characterized in that, The overall thickness of the buffer substrate is less than the thickness of the high-rigidity core layer packaging substrate and the printed circuit board.

7. The packaging structure according to claim 1, characterized in that, The asymmetric high-rigidity Core layer packaging substrate has a lower linewidth and line spacing on the upper layer than on the lower layer, and a lower copper thickness on the upper layer than on the lower layer, thus realizing a fan-out circuit design.

8. The packaging structure according to claim 1, characterized in that, The thermal expansion coefficient distribution of the entire packaging structure from the chip to the printed circuit board is as follows: chip → dielectric layer → glass substrate → sub-buffer 1 layer → sub-BT Core 1 layer → sub-buffer 2 layer → printed circuit board, with the corresponding expansion coefficients being: low → medium → low → low → medium → high → high.

9. The packaging structure according to claim 1, characterized in that, The coefficient of thermal expansion of the buffer substrate is distributed in a gradient from top to bottom, from low to medium to high.

10. A method for preparing the packaging structure as described in claim 1, characterized in that, include: Asymmetric packaging substrate and buffer substrate were fabricated separately; The two are connected by alignment and through-hole technology; The chip is mounted on the top layer of the packaging substrate, and the bottom layer is coupled to the printed circuit board through solder balls. The buffer substrate is composed of at least two material layers with different coefficients of thermal expansion, and the coefficients of thermal expansion are distributed in a gradient increasing manner from top to bottom.

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