Semiconductor structure, forming method thereof and wafer bonding method

Abstract

The embodiment of the invention provides a semiconductor structure, a forming method thereof and a wafer bonding method, and the forming method of the semiconductor structure comprises the steps: providing a wafer on which a semiconductor device is formed; forming a blind hole in the wafer; depositing a first metal material in the blind hole to form a silicon through hole; and removing the first metal material deposited on the surface of the wafer, and flattening the surface of the wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and relates to but not limited to a semiconductor structure, a forming method thereof, and a wafer bonding method. BACKGROUND

[0002] In a via middle process, after a through silicon via (TSV) structure is manufactured, wafer bonding is performed. In the wafer bonding process, unevenness of a wafer surface can cause bonding deviation, and affect electrical and thermodynamic properties of the wafer after bonding, thereby affecting reliability of an entire stacked chip. SUMMARY

[0003] Therefore, the embodiments of the present application provide a semiconductor structure, a forming method thereof, and a wafer bonding method.

[0004] In a first aspect, the embodiments of the present application provide a forming method of a semiconductor structure, and the method comprises the following steps.

[0005] providing a wafer on which a semiconductor device is formed;

[0006] forming a blind hole in the wafer;

[0007] depositing a first metal material in the blind hole to form a through silicon via;

[0008] removing the first metal material deposited on the wafer surface, and planarizing the wafer surface.

[0009] In a second aspect, the embodiments of the present application provide a wafer bonding method, and the method comprises the following steps.

[0010] providing a first wafer and a second wafer;

[0011] mixing bonding the first wafer and the second wafer.

[0012] In a third aspect, the embodiments of the present application provide a semiconductor structure, and the semiconductor structure comprises the following steps.

[0013] a wafer on which a semiconductor device is formed;

[0014] a through silicon via formed in the wafer;

[0015] a bonding pad electrically connected to the through silicon via.

[0016] The semiconductor structure and the forming method thereof, and the wafer bonding method provided by the embodiments of the present application, wherein a blind hole is first formed in the wafer; then a first metal material is deposited in the blind hole to form a through silicon via; then the first metal material deposited on the surface of the wafer is removed, and the surface of the wafer is planarized; finally, a bonding pad is formed on the planarized surface of the wafer; thus, it can be seen that the planarization is performed after the through silicon via is formed, and the bonding pad is formed on the planarized surface of the wafer; compared with the related art, only once planarization is performed after the through silicon via is formed, and the surface of the wafer is planar when the bonding pad is finally formed, so that the manufacturing process of the wafer is simplified, and the deviation in the wafer bonding process caused by the uneven surface of the wafer is reduced, thereby effectively improving the reliability of the stacked chip. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 An implementation flowchart of a forming method of a semiconductor structure provided by the embodiments of the present application is shown;

[0018] Figures 1B-1C A top view of the position relationship between the blind hole and the semiconductor device provided by the embodiments of the present application is shown;

[0019] Figures 2A-2D A forming process diagram of a semiconductor structure provided by the embodiments of the present application is shown;

[0020] Figure 2E A structure diagram of a wafer provided by the embodiments of the present application is shown;

[0021] Figure 3 An implementation flowchart of another forming method of a semiconductor structure provided by the embodiments of the present application is shown;

[0022] Figures 4A-4D A forming process diagram of a semiconductor structure provided by the embodiments of the present application is shown;

[0023] Figure 5 An implementation flowchart of a third forming method of a semiconductor structure provided by the embodiments of the present application is shown;

[0024] Figures 6A-6D A forming process diagram of a bonding pad provided by the embodiments of the present application is shown;

[0025] Figure 7 An implementation flowchart of a wafer bonding method provided by the embodiments of the present application is shown;

[0026] Figure 8 A structure diagram of a mixed bonding area formed by the wafer bonding method provided by the embodiments of the present application is shown.

[0027] The signs in the drawings are explained as follows:

[0028] 10 - wafer; 11 - substrate; 12 / 14 - semiconductor device; 121 - memory device; 122 / M1 / M2 / M3 - metal interconnection layer; CT - contact hole; V1 / V2 - via; 124 - interlayer dielectric layer; 125 - barrier layer; 13 - blind hole; 15 - through-silicon via; 15a - isolation layer; 151 - insulating layer; 152 - barrier layer; 153 - seed layer; 15b - conductive layer; 16 - hard mask layer; 17a / 17b / 17c - via; 18a / 18b / 18c - bonding pad; 81 - first wafer; 82 - second wafer; 83 - hybrid bonding area. DETAILED DESCRIPTION

[0029] Example embodiments of the present application will now be described in detail with reference to the accompanying drawings. Although example embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application.

[0031] In the drawings, the size of layers, devices, and the like, and the relative sizes of the same, can be exaggerated for clarity. Like reference numbers in different drawings can represent the same element.

[0032] It is to be understood that the terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, devices, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, devices, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] High Bandwidth Memory (HBM) technology is developed for more capacity and wider bandwidth of system IC, and the development of such technology cannot be separated from the use of TSV technology; according to the difference of the corresponding integrated circuit front-end-of-line (FEOL) and back-end-of-line (BEOL) of the TSV manufacturing sequence, the through silicon via technology is divided into via first, via middle and via last; among them, the via middle technology is a technology for manufacturing through silicon via after the completion of transistor manufacturing, and the aperture of the technology is smaller and the density is higher, which greatly increases the transmission bandwidth between chip layers, and therefore is widely used.

[0034] In the via middle process, after the completion of the manufacture of the through silicon via structure, the wafer is thinned and wafer bonding is performed. During wafer bonding, unevenness of the wafer surface can cause bonding deviation, affecting the electrical, thermodynamic and other properties of the bonded wafer, thereby affecting the reliability of the entire stacked chip.

[0035] Based on the above problems in the related art, the embodiments of the present application provide a semiconductor structure and a forming method thereof, and a wafer bonding method. First, a blind hole is formed in the wafer; then a first metal material is deposited in the blind hole to form a through silicon via; then the first metal material deposited on the surface of the wafer is removed, and the surface of the wafer is planarized; finally, a bonding pad is formed on the planarized wafer surface. As can be seen, planarization is performed after the formation of the through silicon via, and the bonding pad is formed on the planarized wafer surface. Compared with the related art, only one planarization is needed after the formation of the through silicon via, and the wafer surface is flat when the bonding pad is finally formed. Not only is the wafer manufacturing process simplified, but also the deviation caused by unevenness of the wafer surface during wafer bonding is reduced, thereby effectively improving the reliability of the stacked chip.

[0036] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of the present application, the schematic diagram will be partially enlarged without the general proportion for the convenience of description, and the schematic diagram is only an example, which should not limit the protection scope of the present application herein.

[0037] Figure 1 The implementation flowchart of the forming method of the semiconductor structure provided by the embodiments of the present application is shown as Figure 1 The method comprises:

[0038] Step S101, providing a wafer formed with a semiconductor device.

[0039] In some embodiments, a wafer refers to a wafer used to fabricate semiconductor circuits, such as a silicon wafer. The fabrication process of a silicon wafer includes: first, dissolving high-purity polycrystalline silicon and then doping it with silicon crystal seed crystals; then slowly pulling out the polycrystalline silicon to form cylindrical single-crystal silicon; finally, grinding, polishing, and slicing the silicon ingot to form a wafer. The main processing methods for wafers are wafer fabrication and batch fabrication.

[0040] In some embodiments, a semiconductor device is an electronic device whose conductivity lies between that of a good conductor and an insulator. It utilizes the unique electrical properties of semiconductor materials to perform specific functions, such as generating, controlling, receiving, converting, amplifying signals, and performing energy conversion. For example, a semiconductor device can be a crystal diode or a transistor (e.g., a bipolar transistor or a field-effect transistor). The semiconductor device can be a multilayer metal structure composed of two or more independent metal layers.

[0041] Step S102: Form blind vias in the wafer.

[0042] In practice, step S102 may involve forming a blind via with a preset depth at a preset location on the wafer surface; the preset depth can be determined based on factors such as the thickness of the wafer or the thickness of the wafer to be bonded. Since the blind via will undergo wafer thinning in subsequent processes, in some embodiments, step S102 may also form a through-hole in the wafer.

[0043] In some embodiments, the preset position can be determined based on factors such as the number and location of semiconductor devices. For example, the preset position can be determined based on the number of semiconductor devices.

[0044] Scenario 1: When there is only one semiconductor device, the blind vias are arranged on any side of the semiconductor device, such as the front, back, left, or right side. Figure 1B As shown, blind holes 13 are arranged on the left side of semiconductor device 12.

[0045] Scenario 2: When there are two or more semiconductor devices, the blind vias are arranged on the left or right side of the semiconductor devices, refer to... Figure 1C Blind hole 13 is located to the right of semiconductor device 12 and semiconductor device 14.

[0046] Here, blind vias can be formed by etching, for example, the etching process can be at least one of dry etching, wet etching or auxiliary electrochemical etching to form blind vias in the wafer.

[0047] Step S103: Deposit a first metal material within the blind via to form a through-silicon via;

[0048] Here, the "depositing" step can use a chemical plating (CP) process in addition to a chemical vapor deposition (CVD) process and a physical vapor deposition (PVD) process, so that the first metal material can fill the blind hole and form a conductive layer on the wafer surface and the inner wall of the blind hole.

[0049] The through-silicon via technology is a technical solution for realizing interconnection of stacked chips in a three-dimensional (3D) integrated circuit. The through-silicon via technology can maximize the density of chips stacked in the three-dimensional direction, shorten the interconnection lines between chips, and minimize the size, thereby effectively realizing 3D chip stacking and manufacturing chips with more complex structures, more powerful performance, and more cost efficiency.

[0050] Here, the first metal material is used to fill the blind hole and form a conductive layer of the through-silicon via, and the conductive layer is used to realize electrical connection between two wafers after wafer bonding. Therefore, the first metal material can be any conductive metal material, such as tungsten (W), aluminum (Al), copper (Cu), and the like. Generally, different deposition processes are used for different conductive materials. When tungsten is used as a conductive material, a CVD method is used; when aluminum is used as a conductive material, a CVD method and a PVD method are used; and when copper is used as a conductive material, a CP method is used.

[0051] In step S104, the first metal material deposited on the wafer surface is removed, and the wafer surface is planarized.

[0052] In actual applications, after the through-silicon via is formed, the wafer upper surface will deposit excess first metal material, so that the wafer upper surface forms some protrusions and grooves. Therefore, the excess first metal material deposited on the wafer surface needs to be removed. The removal process can be etching, grinding, polishing, or the like.

[0053] In some embodiments, the planarization is a technology for flattening the wafer surface, which can improve the performance of the wafer or chip. The planarization of the wafer surface includes planarizing the wafer surface by a chemical mechanical grinding process.

[0054] In the embodiments of the present application, after the through-silicon via is formed, planarization is performed by a chemical mechanical grinding process. Compared with related technologies, only one planarization is needed after the through-silicon via is formed, and the wafer surface is flat when the bonding pad is formed subsequently. Therefore, the wafer manufacturing process is simplified, and the deviation caused by the uneven wafer surface in the wafer bonding process is reduced, thereby effectively improving the reliability of the stacked chip.

[0055] Next, please refer to Figures 2A-2DFurther details of steps S101-S104 are provided.

[0056] Referring first to Figure 2A , the wafer 10 includes semiconductor devices 12; next referring to Figure 2B , a blind via 13 is formed at a predetermined location on the wafer surface by an etching process; then referring to Figure 2C , a first metal material, such as copper (Cu), is deposited in the blind via 13 by a CP process to form a through-silicon via 15; after the through-silicon via is formed, the wafer surface is also coated with excess first metal material, which can cause defects such as pits or bumps on the wafer surface, so in Figure 2D , an etching, grinding, polishing, or other process is used to remove the first metal material deposited on the wafer 10 surface and to planarize the wafer 10 surface.

[0057] Figures 2A-2E In some embodiments, the semiconductor devices 12 include memory devices, metal interconnection layers M1, M2, and M3, and contact holes CT, vias V1 and V2. The contact holes CT are connection channels between the memory devices, such as transistors, and the metal interconnection layer M1. The via V1 is a connection channel between the metal interconnection layer M1 and the metal interconnection layer M2 formed on an inter metal dielectric layer 1 (IMD). The via V2 is a connection channel between the metal interconnection layer M2 and the metal interconnection layer M3 formed on an IMD2.

[0058] In some embodiments, the process of forming the through-silicon via 15 can use a via last process, i.e., the through-silicon via 15 is formed after the device structure is formed, so as to avoid contamination of the through-silicon via caused by metal deposition during the formation of the device structure.

[0059] In the embodiments of the present application, a memory device is used as an example for illustration. The semiconductor devices include memory devices, such as transistors, so that the formation in step S101 includes:

[0060] Step S111, providing a substrate;

[0061] Here, the substrate can be a silicon substrate. In other embodiments, the substrate can include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), gallium indium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0062] Step S112, forming the semiconductor device on the substrate; wherein the semiconductor device comprises a memory device and a metal interconnection layer.

[0063] In some embodiments, the memory device in the semiconductor device can be a transistor, and the metal interconnection layer can form a wire to connect different memory devices to form a circuit by a metal conductive material. When forming the metal interconnection layer in the embodiments of the present application, the resistivity of the interconnection material, the step coverage and surface flatness of the deposition process, electromigration and stress, etc. need to be considered. Using a material with low resistivity as the interconnection can reduce the loss and RC delay of the chip, and improve the speed of the chip, wherein the RC delay refers to the signal delay caused by resistance (R) and capacitance (C) in the charging and discharging process. The materials that can be used as interconnection metals in the metal interconnection layer include tungsten (W), copper (Cu), aluminum (Al), etc.

[0064] Reference is made below to Figure 2E Further understanding of step S111 and step S112.

[0065] In Figure 2E In the embodiment, the wafer 10 comprises a substrate 11 and a semiconductor device 12, and the semiconductor device 12 is located on the upper surface of the substrate 11, wherein the substrate 11 comprises a shallow trench structure (STI). The semiconductor device 12 in the embodiment comprises a memory device 121 and a metal interconnection layer 122, wherein the metal interconnection layer 122 comprises a metal interconnection layer M1 (first metal layer), M2 (second metal layer) and M3 (third metal layer). The contact hole CT is used to realize the electrical connection between the memory device 121 and the metal interconnection layer M1, the via V1 is used to realize the electrical connection between the metal interconnection layer M1 and the metal interconnection layer M2, and the via V2 is used to realize the electrical connection between the metal interconnection layer M2 and the metal interconnection layer M3.

[0066] In the process of the through silicon via, in the wafer bonding (Wafer On Wafer Bonding) in the packaging process, the wafer hybrid bonding (Wafer On Wafer Hybrid Boding) cannot be performed due to the unevenness of the surface passivation layer of the wafer. The unevenness of the surface passivation layer of the wafer is caused by the unevenness of the wafer surface in the wafer bonding process, etc. After the electroplating process, the interlayer dielectric layer and the passivation layer formed in sequence also have unevenness.

[0067] The embodiments of the present application also provide a forming method of a semiconductor structure, wherein the through silicon via is formed in the middle of the through silicon via process, and reference is made to Figure 3 , comprising:

[0068] Step S301, providing a wafer formed with a semiconductor device;

[0069] Here, in the embodiments of the present application, after the interlayer dielectric layer is formed, the passivation layer can not be formed, and thus the surface of the wafer can be the interlayer dielectric layer.

[0070] In step S302, the wafer is etched with the preset position of the wafer surface as the etching starting point, and a blind hole is formed in the wafer.

[0071] In some embodiments, the processing technology of the blind hole can adopt a deep reactive ion etching technology (DRIE) or a laser drilling technology. The DRIE technology is a combination of polymer passivation layer deposition and etching of single crystal silicon, and the two processes are alternately performed in cycles, so as to avoid the mutual influence between deposition and etching, ensure the stability and reliability of the passivation layer, and thus form a high aspect ratio structure with a steep sidewall.

[0072] In step S303, a first metal material is deposited in the blind hole to form a through silicon via.

[0073] In the embodiments of the present application, the through silicon via can be prepared after the FEOL and middle of line (MOL) processes and before the BEOL process.

[0074] In some embodiments, the implementation of step S303 includes:

[0075] In step S331, an insulating layer covering the inner wall of the blind hole is deposited on the inner wall of the blind hole.

[0076] Here, the insulating layer is used to prevent the conductive between the first metal material (forming a conductive layer) and the substrate in the subsequent process, and to protect the substrate from being damaged. The material of the insulating layer in the embodiments of the present application includes silicon oxide (such as SiO2), silicon nitride (such as Si3N4), etc. The deposition of the insulating layer often adopts a PECVD method, a thermal oxidation technology or a vacuum vapor deposition technology. Among them, the PECVD method has high deposition rate, low process temperature and strong film layer covering ability, and is widely used for depositing insulating layer materials such as SiO2 and Si3N4; the thermal oxidation technology is used for depositing silicon dioxide; and the vacuum vapor deposition technology is used for depositing p-xylene material.

[0077] In some embodiments, after the insulating layer covering the inner wall of the blind hole is deposited, a barrier layer and a seed layer are sequentially deposited, that is, the deposition sequence on the inner wall of the blind hole is: first, the insulating layer is deposited on the inner wall of the blind hole; then, the barrier layer is deposited on the insulating layer; and finally, the seed layer is deposited on the barrier layer.

[0078] The barrier layer is used to prevent the diffusion of the first metal material in the subsequent process and to improve the adhesion strength of the seed layer. The commonly used materials of the barrier layer can be titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium, vanadium nitride, niobium, or niobium nitride, etc. The deposition of the barrier layer can be performed by PVD method, CVD method, or plasma enhanced magnetron sputtering (PEMS) technology, etc.

[0079] The seed layer is used to provide a bridging effect for the subsequent formation of the conductive layer in the through silicon via. The material of the seed layer can be any conductive material, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or any combination thereof. The seed layer can be made by using one or more deposition methods which are the same as those for the barrier layer.

[0080] Step S332, after forming the insulating layer, depositing a first metal material to form a conductive layer of the through silicon via.

[0081] In some embodiments, the conductive layer is used for electrical conduction. The conductive material in the conductive layer can be the same as or different from the conductive material in the seed layer. Generally, the material of the conductive layer is copper (Cu) metal.

[0082] Step S304, removing the first metal material deposited on the surface of the wafer and planarizing the surface of the wafer.

[0083] Here, the planarization is performed by using a chemical mechanical polishing (CMP) technique. In the implementation, first, the material on the surface of the wafer reacts chemically with oxidants, catalysts, etc. in the polishing liquid to form a soft layer which is relatively easy to remove; then the soft layer is removed by the mechanical action of the abrasive in the polishing liquid and the polishing pad, so that the surface of the workpiece is exposed again; after that, the chemical reaction and mechanical action are repeated, and the workpiece surface is polished in the alternating process of chemical action and mechanical action.

[0084] Next, please refer to Figures 4A-4D Further details of steps S301 to S304 are described.

[0085] Reference is made to Figure 4A The wafer 10 includes a substrate 11, a semiconductor device 12, and an interlayer dielectric layer 124, wherein the surface of the wafer 10 is the interlayer dielectric layer 124. In Figure 4B In the wafer 10, a blind hole 13 is formed in the wafer 10 by sequentially etching the interlayer dielectric layer 124 and the substrate 11 at a predetermined position on the upper surface of the wafer 10 by using the DRIE technology; then, reference is made to Figure 4CIn the left drawing of FIG. 1, the isolation layer 15a and the conductive layer 15b are sequentially deposited in the blind hole 13 by one or more deposition processes, such as a CVD process or a PVD process, thereby forming the through-silicon via 15.

[0086] Further, the steps S331-S332 can be understood with reference to Figure 4C Further, the steps S331-S332 can be understood with reference to Figure 4C In the right drawing of FIG. 1, the formation of the through-silicon via includes: depositing, on the inner wall of the blind hole 13, an insulation layer 151, a barrier layer 152, a seed layer 153 and a conductive layer 15b, wherein the insulation layer 151, the barrier layer 152 and the seed layer 153 form the isolation layer 15a.

[0087] In the process of forming the through-silicon via, the wafer surface is deposited with a variety of redundant materials, such as materials in the insulation layer, the barrier layer, the seed layer and the conductive layer, and thus further processing is required for the wafer surface. Figure 4D In the process of forming the through-silicon via, the wafer surface is deposited with a variety of redundant materials, such as materials in the insulation layer, the barrier layer, the seed layer and the conductive layer, and thus further processing is required for the wafer surface.

[0088] The embodiments of the present application further include a third method for forming a semiconductor structure, with reference to Figure 5 The method includes:

[0089] In step S501, a wafer with a semiconductor device formed thereon is provided.

[0090] In step S502, a blind hole is formed in the wafer.

[0091] In step S503, a first metal material is deposited in the blind hole to form a through-silicon via.

[0092] In step S504, the first metal material deposited on the wafer surface is removed, and the wafer surface is planarized.

[0093] In step S505, a bonding pad is formed on the planarized wafer surface.

[0094] In actual applications, wafer bonding refers to a technology of combining two mirror-polished wafers of the same or different materials closely through chemical and physical actions, so that the atoms at the wafer interface react to form covalent bonds to become an integrated whole, and the bonding interface reaches a specific bonding strength.

[0095] In the embodiments of the present application, the CMP process is used to planarize the wafer surface after forming the TSV via, and then the bonding pad is formed on the planarized wafer surface. Thus, compared with the related art, only one planarization process is needed, and the wafer surface is planar after forming the bonding pad, thus simplifying the process flow.

[0096] In some embodiments, the implementation of step S505 comprises:

[0097] Step S551, depositing a barrier layer on the planarized wafer surface;

[0098] Here, the barrier layer is an isolation layer formed between the upper and lower layers of materials, preventing the upper and lower layers of materials from diffusing into each other, and improving the adhesion between the upper and lower layers of materials and the barrier layer material. The barrier layer metal requires low contact resistance, good sidewall and step coverage, and high barrier property. In the embodiments of the present application, the barrier layer uses materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc. The deposition process of the barrier layer includes CVD or PVD.

[0099] Step S552, depositing a hard mask layer on the surface of the barrier layer;

[0100] The hard mask process technology refers to a technology of transferring a pattern to a hard mask layer (also referred to as an intermediate layer) by using a very thin photoresist, and then transferring the pattern to the bottom layer of thin film material through the intermediate layer.

[0101] In some embodiments, the material of the hard mask layer can be silicon dioxide, silicon nitride, silicon carbide, or tantalum oxide, etc. The hard mask layer can be prepared by using a plasma enhanced chemical vapor deposition (PECVD) or CVD method.

[0102] Step S553, patterning the hard mask layer, etching the surface of the barrier layer by using the mask pattern, to form a via hole exposing the metal interconnection layer and the blind hole;

[0103] Here, the patterning refers to a process of transferring a pattern from a photoresist layer to a hard mask layer. The commonly used process of patterning is dry etching, including plasma etching (PE), plasma sputtering etching (PSE), or reaction ion etching (RIE), etc.

[0104] In some embodiments, the process of etching the mask pattern can be dry etching, and one or more etching processes can be used, which are the same as the patterning process.

[0105] In some embodiments, the via fabrication technique can be the same as the blind via fabrication technique in S102, including using dry etching or wet etching to etch the upper surface of the metal interconnect layer and the upper surface of the silicon via to form the via.

[0106] Step S554: A second metal material is deposited in the through hole to form a bonding pad.

[0107] In some embodiments, the second metallic material is the same as the first metallic material. The "deposition" process may employ one or more processes similar to those used for depositing the first metallic material.

[0108] Please refer to the following. Figures 6A-6D Steps S551 to S553 are described in further detail.

[0109] refer to Figure 6A First, a barrier layer 125 is deposited on the upper surface of the interlayer dielectric layer 124 using CVD or PVD methods; then, Figure 6B In this process, a hard mask layer 16 is deposited on the upper surface of the barrier layer 125 using PECVD or CVD methods; then, the hard mask layer 16 is patterned by dry etching; further, the upper surface of the barrier layer 125 is etched using the mask pattern to form... Figure 6C The first via 17a, the second via 17b, and the third via 17c of the metal interconnect layer 122 and the through silicon via 15 are exposed respectively; finally, the first via 17a, the second via 17b, and the third via 17c are filled with a second metal material to form Figure 6D The first bonding pad 18a, the second bonding pad 18b and 18c are in the middle.

[0110] In some embodiments, the filling process is different when the second metal material being filled is different. For example, when tungsten is used as the conductive material, the CVD method is used; when aluminum is used as the conductive material, the CVD method and PVD method are used; and when copper is used as the conductive material, the CP method is used.

[0111] In addition, refer to Figure 6C It can be seen that the first via 17a can expose the silicon via 15, and the second vias 17b and 17c can expose the metal interconnect layer 122; Reference Figure 6D It can be seen that the first bonding pad 17a and the through silicon via 15 are electrically connected, and the second bonding pads 17b and 17c are electrically connected to the metal interconnect layer 122.

[0112] In this embodiment, firstly, a barrier layer is deposited on the planarized wafer surface; secondly, the surface of the barrier layer is etched to form a via that exposes the metal interconnect layer and the blind via; then, a second metal material is deposited in the via; finally, a CMP process is performed on the wafer surface to remove excess second metal material, thereby forming a bonding pad with a smooth surface.

[0113] In some embodiments, assuming that the surface on which the bonding pad is located is a first surface, after step S505, the method further comprises:

[0114] Step S506, thinning the wafer on which the bonding pad is formed to a preset thickness from a second surface opposite to the first surface.

[0115] Here, the preset thickness refers to the wafer thickness required in the later packaging, which is different according to different later packaging processes. The wafer thinning is for 3D packaging, and after the wafer thinning, the aperture and thickness ratio of the formed through hole is ensured to be within a reasonable range, and the thickness of the final packaging can be acceptable.

[0116] In some embodiments, the wafer thinning method can adopt mechanical grinding, dry etching or wet etching, etc. In order to prevent the wafer from warping, sagging, surface damage expansion, wafer cracking and other problems after thinning, in the implementation, on the one hand, a layer of glass (or silicon material) bearing material is pasted on the wafer surface before thinning as a bearing support for fixing and strengthening the ultra-thin wafer; on the other hand, a sheet-shaped object with an area and thickness comparable to that of the wafer is placed on the periphery of the wafer, so that the wafer in the middle is uniformly stressed during the thinning process. Thus, a wafer with no edge damage, no cracks and uniform thickness can be obtained.

[0117] In the embodiments of the present application, the wafer needs to be thinned to a preset thickness after forming the through silicon via and the bonding pad. Through the wafer thinning process, the heat dissipation effect of the chip can be improved.

[0118] Based on Figure 6D , the embodiments of the present application provide a semiconductor structure, comprising:

[0119] a wafer 10 on which a semiconductor device 12 is formed;

[0120] a through silicon via 15 formed in the wafer;

[0121] a first bonding pad 18a electrically connected with the through silicon via.

[0122] In some embodiments, continuing to refer to Figure 6D , the wafer 10 comprises a substrate 11 and a semiconductor device 12 formed on the substrate 11; wherein the semiconductor device comprises a memory device 121 and a metal interconnection layer 122.

[0123] Continuing to refer to Figure 6D , the semiconductor device 12 is formed in an interlayer dielectric layer 124, and the through silicon via 15 penetrates the substrate 11 and the interlayer dielectric layer 124.

[0124] In some embodiments, referring to Figure 6CThe through-silicon via 15 includes an isolation layer 15a and a conductive layer 15b, wherein the isolation layer 15a includes an insulating layer 151, a barrier layer 152 and a seed layer 153.

[0125] In some embodiments, the bonding pad is formed of a second metal material.

[0126] In the embodiments of the present application, a wafer bonding method is also provided, which refers to Figure 7 The method comprises the following steps:

[0127] In step S701, a first wafer and a second wafer are provided, wherein the first wafer and the second wafer can be made by the method provided in the above embodiments.

[0128] Here, the first wafer and the second wafer can be the same wafer or different wafers. The conductive materials in the bonding pads formed in the first wafer and the second wafer can be the same or different.

[0129] In step S702, the first wafer and the second wafer are mixedly bonded to form a mixed bonding area.

[0130] Here, the mixed bonding area is formed by welding the corresponding bonding pads in the first wafer and the second wafer. Common welding processes include reflow soldering (RS) and thermal compression bonding (TCB).

[0131] The wafer bonding method will be described in detail below. Figure 8

[0132] In the wafer in Figure 8 , two wafers are included, including a first wafer 81 and a second wafer 82; the first wafer 81 and the second wafer 82 can be made by the method provided in the above embodiments, and the first wafer 81 and the second wafer 82 can be the same or different; the first wafer 81 and the second wafer 82 both include a bonding pad structure, and the structure of the bonding pad can refer to Figure 6D ; the conductive materials in the bonding pads formed in the first wafer 81 and the second wafer 82 can be the same or different. By using the RS welding process or the TCB welding process, the corresponding bonding pads in the first surface of the wafer 81 and the first surface of the wafer 82 can be welded together to form a mixed bonding area 83.

[0133] In the embodiments of the present application, after the TSV through-silicon via is formed, the wafer surface is planarized by using the CMP process to form a flat wafer surface, and then a bonding pad with a flat surface is prepared, so that wafer bonding can be realized at one time, and the process flow is simplified.

[0134] ​The semiconductor structure in the embodiments of the present application is similar to the forming method of the semiconductor structure in the above embodiments. For technical features not disclosed in detail in the embodiments of the present application, refer to the above embodiments for understanding. The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0135] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A wafer; the wafer includes: a substrate; a semiconductor device and an interlayer dielectric layer on the substrate; wherein the semiconductor device includes a memory device and a metal interconnect layer; the metal interconnect layer includes a first metal layer, a second metal layer and a third metal layer, the metal interconnect layer being located within the interlayer dielectric layer; Through-silicon vias formed in the wafer; The first bonding pad is electrically connected to the through-silicon via; The through-silicon via extends through the substrate and the interlayer dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The through-silicon via includes an insulating layer and a conductive layer formed of a first metal material; the first bonding pad is formed of a second metal material.

3. The semiconductor structure according to claim 2, characterized in that, The second metal material is the same as the first metal material.

4. The semiconductor structure according to claim 2, characterized in that, The second metal material is different from the first metal material.

5. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a second bonding pad, which is electrically connected to the metal interconnect layer.

6. The semiconductor structure according to claim 5, characterized in that, The second bonding pad is formed using the second metal material.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a barrier layer that covers the interlayer dielectric layer, and the first bonding pad extends through the barrier layer.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a contact hole connecting the memory device and the first metal layer; the semiconductor structure also includes a through-hole connecting the first metal layer and the second metal layer or connecting the second metal layer and the third metal layer.

9. A semiconductor bonding structure, characterized in that, It is obtained by bonding using the semiconductor structure as described in any one of claims 1-8.

10. The semiconductor bonding structure according to claim 9, characterized in that, The semiconductor structure is bonded using a hybrid bonding method.

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