Layered packaging structure and layered packaging method of power device

Abstract

The invention relates to a layered packaging structure and a layered packaging method of a power device. The layered packaging structure of the power device comprises a driving circuit layer, a power circuit layer and a chip layer which are stacked in sequence, the driving circuit layer can be electrically connected with the power circuit layer through a first hole, and the driving circuit layer can be electrically connected with the chip layer through a second hole and a third hole. Therefore, the driving loop layer can drive the chip layer so as to enable the power device to work. Compared with a traditional scheme of realizing electrical connection based on a bonding wire, the layered packaging structure of the power device is a three-dimensional space layout structure, conductive circuits do not exist between the layers, inter-layer electric field concentration can be avoided, electrical connection between the layers depends on the first hole, the second hole and the third hole, and the reliability of the power device is improved. Therefore, the direct connection between the driving loop layer and the power loop layer, the direct connection between the driving loop layer and the chip layer, and the direct connection between the power loop layer and the chip layer are realized.

Description

Technical Field

[0001] This application relates to the field of power device technology, and in particular to a layered packaging structure and layered packaging method for power devices. Background Technology

[0002] With the rapid development of the new energy industry, SiC (Silicon Carbide) power devices have shown great advantages in high-voltage, high-frequency, and high-temperature applications due to their excellent properties such as high breakdown electric field strength, high electron saturation drift velocity, and high thermal conductivity. However, traditional SiC power module packaging technology results in relatively high parasitic inductance. Summary of the Invention

[0003] Therefore, it is necessary to provide a layered packaging structure and method for power devices that can reduce parasitic inductance.

[0004] In a first aspect, a layered packaging structure for a power device is provided, comprising: a drive circuit layer, a power circuit layer, and a chip layer stacked sequentially.

[0005] The drive circuit layer has a first hole and a second hole, and the power circuit layer has a third hole. All three holes are filled with conductive paste. The projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the projection of the third hole.

[0006] The driving circuit layer is connected to the power circuit layer through the first hole, the driving circuit layer is connected to the chip layer through the second and third holes, and the power circuit layer is connected to the chip layer through the third hole; the driving circuit layer is used to drive the chip layer.

[0007] In one embodiment, the drive loop layer includes: a first drive loop layer and a second drive loop layer stacked sequentially;

[0008] The first drive circuit layer is positioned further away from the power circuit layer than the second drive circuit layer.

[0009] The first hole includes a first sub-hole on the first drive circuit layer and a second sub-hole on the second drive circuit layer, and the projection of the first sub-hole on the second drive circuit layer coincides with the second sub-hole;

[0010] The first driving circuit layer is connected to the power circuit layer via the first sub-via and the second sub-via, and the second driving circuit layer is connected to the chip layer via the second and the third via; both the first driving circuit layer and the second driving circuit layer are used to drive the chip layer.

[0011] In one embodiment, the first drive circuit layer includes: a first ceramic plate and a first drive circuit circuit integrated on the first ceramic plate;

[0012] The signal line of the first drive circuit extends to the first sub-hole;

[0013] The second drive circuit layer includes: a second ceramic plate and a second drive circuit circuit integrated on the second ceramic plate;

[0014] The signal line of the second drive circuit extends to the second hole.

[0015] In one embodiment, the first drive circuit circuit includes a first upper bridge circuit and a first lower bridge circuit that are independently configured, and the second drive circuit circuit includes a second upper bridge circuit and a second lower bridge circuit that are independently configured.

[0016] Wherein, the projection of the circuit region where the first upper bridge circuit is located on the second drive circuit circuit coincides with the circuit region where the second upper bridge circuit is located, and the projection of the circuit region where the first lower bridge circuit is located on the second drive circuit circuit coincides with the circuit region where the second lower bridge circuit is located; wherein, the distance between the first upper bridge circuit and the first lower bridge circuit is greater than or equal to the insulation distance under the preset voltage requirement.

[0017] The signal line of the first upper bridge circuit extends to the first upper bridge hole in the first sub-hole, and the signal line of the first lower bridge circuit extends to the first lower bridge hole in the first sub-hole; the signal line of the second upper bridge circuit extends to the second upper bridge hole in the second hole, and the signal line of the second lower bridge circuit extends to the second lower bridge hole in the second hole.

[0018] In one embodiment, the power loop layer includes: a third upper bridge loop and a third lower bridge loop that are independently configured, and a third ceramic plate that integrates the third upper bridge loop and the third lower bridge loop;

[0019] Signal lines and power lines are routed perpendicularly; the signal lines include the signal lines of the first drive circuit and the signal lines of the second drive circuit, and the power lines include the power lines of the third upper bridge circuit and the power lines of the third lower bridge circuit.

[0020] The signal line of the third upper bridge circuit extends to the third upper bridge hole in the third hole, and the signal line of the third lower bridge circuit extends to the third lower bridge hole in the third hole.

[0021] Secondly, a layered packaging method for power devices includes:

[0022] A drive circuit layer and a power circuit layer are provided; wherein, the drive circuit layer has a first hole and a second hole, and the power circuit layer has a third hole, and the first hole, the second hole and the third hole are all filled with conductive paste;

[0023] The drive circuit layer and the power circuit layer are stacked to obtain a laminated structure; wherein the projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the third hole.

[0024] In an environment with a temperature range of 600℃-900℃, a laminated structure is sintered to obtain a low-temperature co-fired ceramic plate;

[0025] Prepare the chip layer and stack the low-temperature co-fired ceramic plate with the chip layer;

[0026] Power devices are obtained by sintering low-temperature co-fired ceramic plates and chip layers.

[0027] In one embodiment, the fabrication steps of the drive loop layer and the power loop layer include:

[0028] Prepare and formulate ceramic slurry based on ceramic powder and slurry;

[0029] Prepare the first and second carrier membranes;

[0030] Using a casting machine, ceramic slurry is uniformly coated onto a first carrier film and a second carrier film to obtain a first green ceramic tape and a second green ceramic tape.

[0031] Drill holes in the first green porcelain strip to form the first hole and the second hole;

[0032] Drill a hole in the second green porcelain strip to form a third hole;

[0033] The first, second, and third holes were filled with conductive paste.

[0034] The drive circuit is printed on the first green ceramic tape to form a drive circuit layer;

[0035] Power circuits are printed on the second green ceramic tape to form a power circuit layer.

[0036] In one embodiment, the drilling method is one of mechanical punching, laser drilling, or photolithography drilling.

[0037] In one embodiment, the first carrier membrane includes a first sub-carrier membrane and a second sub-carrier membrane, and the first green ceramic tape includes a first sub-green ceramic tape and a second green ceramic tape.

[0038] The steps of drilling holes in the first green porcelain strip to form the first and second holes include:

[0039] Drill holes in the first piece of raw porcelain to form the first hole;

[0040] A hole is drilled in the second sub-green ceramic belt to form a second sub-hole and a second hole; wherein, the first hole includes a connection between the first sub-hole and the second sub-hole, and the projection of the first sub-hole on the second sub-green ceramic belt coincides with the second sub-hole.

[0041] In one embodiment, after the step of stacking the drive circuit layer and the power circuit layer to obtain a laminated structure, and before the step of sintering the laminated structure, the method further includes:

[0042] Place the laminated structure in air or an inert gas;

[0043] The heating temperature of the laminated structure is increased at a preset rate of change until the temperature of the laminated structure is maintained within the range of 300℃-500℃.

[0044] The layered packaging structure of the aforementioned power device includes: a drive circuit layer, a power circuit layer, and a chip layer stacked sequentially. Through a first via, the drive circuit layer can be electrically connected to the power circuit layer; through a second and third via, the drive circuit layer can be electrically connected to the chip layer. This allows the drive circuit layer to drive the chip layer, enabling the power device to operate. Compared to traditional solutions based on bonding wires for electrical connections, this layered packaging structure for power devices is a three-dimensional spatial layout structure. There are no conductive lines between the layers, avoiding electric field concentration between layers. The electrical connections between the layers rely on the first, second, and third vias, thereby achieving direct connections between the drive circuit layer and the power circuit layer, between the drive circuit layer and the chip layer, and between the power circuit layer and the chip layer. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is one of the structural block diagrams of a layered packaging structure for a power device according to an embodiment;

[0047] Figure 2 This is a second structural block diagram of a layered packaging structure for a power device according to an embodiment;

[0048] Figure 3 The third structural block diagram of a layered packaging structure for a power device according to one embodiment;

[0049] Figure 4 This is a structural block diagram of the first drive loop layer in one embodiment;

[0050] Figure 5 This is a structural block diagram of the second drive loop layer in one embodiment;

[0051] Figure 6 This is a schematic diagram of the substrate of the first driving loop layer and the second driving loop layer in one embodiment;

[0052] Figure 7 This is a structural block diagram of a power loop layer according to one embodiment;

[0053] Figure 8 This is a schematic diagram of a substrate for a power loop layer according to one embodiment;

[0054] Figure 9 This is a flowchart of a layered packaging method for a power device according to one embodiment. Detailed Implementation

[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0057] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements or circuits, but these elements or circuits are not limited by these terms. These terms are only used to distinguish one element or circuit from another. For example, without departing from the scope of this application, a first upper-bridge circuit may be referred to as a second upper-bridge circuit, and similarly, a second upper-bridge circuit may be referred to as a first upper-bridge circuit. Both the first upper-bridge circuit and the second upper-bridge circuit are upper-bridge circuits, but they are not the same upper-bridge circuit.

[0058] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0059] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0061] In traditional packaging, power devices suffer from electromagnetic compatibility issues, limiting their power density improvement. When power devices consist of multiple chips, thermal management becomes more difficult, leading to uneven junction temperatures and consequently reduced reliability.

[0062] Existing SiC power modules generally employ electrical connections using copper or aluminum wires with a diameter of 12-20μm. This connection method generates significant voltage spikes at high switching frequencies. Furthermore, when the drive circuit and main power circuit of the power module are routed on the same plane, severe electromagnetic coupling problems arise, and the ringing amplitude of the drive signal rising edge exceeds 30% of the power supply voltage. To reduce electromagnetic coupling, most power modules adopt a multilayer design, often using organic substrates such as FR-4 (Flame Retardant 4) or BT (Bismaleimide Triazine Resin Substrate) or DBC (Direct Bonded Copper Ceramic Substrate). However, organic substrates experience significantly increased dielectric losses at high temperatures and frequencies, and their reliability is poor. While DBC substrates have higher thermal conductivity, their multilayer routing capabilities are limited, making it difficult to integrate complex circuits.

[0063] In the prior art, excessively long lead bonding length of power modules can lead to parasitic inductance in the drive circuit being in the range of 5-10nH and stray inductance in the main circuit being in the range of ≥10nH. Furthermore, at high switching frequencies, switching losses account for a large proportion of the total losses.

[0064] Furthermore, the wire bonds of power modules are prone to fatigue fracture during power cycling; and the current carrying capacity of wire bonds is limited by the size of the solder pads. Moreover, the height of the bonding wires limits the thickness of the power module.

[0065] In a specific embodiment, such as Figure 1As shown, a layered packaging structure 10 for a power device is provided, comprising: a drive circuit layer 102, a power circuit layer 104, and a chip layer 106 stacked sequentially.

[0066] The drive circuit layer has a first hole 108 and a second hole 110, and the power circuit layer has a third hole 112. All three holes are filled with conductive paste. The projection of the second hole on the drive circuit layer onto the power circuit layer coincides with that of the third hole. The conductive paste is a low dielectric constant ceramic paste.

[0067] The driving circuit layer is connected to the power circuit layer through the first hole, the driving circuit layer is connected to the chip layer through the second and third holes, and the power circuit layer is connected to the chip layer through the third hole; the driving circuit layer is used to drive the chip layer.

[0068] The first hole is filled with conductive paste, allowing electrical signals between the drive circuit layer and the power circuit layer to be transmitted through it. Similarly, the second and third holes are also filled with conductive paste, meaning that electrical signal transmission is supported between them. Therefore, the drive circuit layer can be connected to the chip layer via the second and third holes, and the power circuit layer can be connected to the chip layer via the third hole. It should be noted that there is at least one first, second, and third hole.

[0069] The larger the contact area between the conductive paste in the second hole and the conductive paste in the third hole, the higher the reliability of the electrical connection between the second hole and the third hole. The projection of the second hole on the power circuit layer coincides with the third hole, which can maximize the contact area between the conductive paste in the second hole and the conductive paste in the third hole, thereby maximizing the reliability of the electrical connection between the second hole and the third hole and ensuring the correct transmission of electrical signals.

[0070] The aforementioned layered packaging structure for power devices includes: a drive circuit layer, a power circuit layer, and a chip layer stacked sequentially. Through a first via, the drive circuit layer can be electrically connected to the power circuit layer; through a second and third via, the drive circuit layer can be electrically connected to the chip layer. This allows the drive circuit layer to drive the chip layer, enabling the power device to operate. Compared to traditional solutions based on bonding wires for electrical connections, this layered packaging structure for power devices is a three-dimensional spatial layout structure. There are no conductive lines between the layers, avoiding electric field concentration between layers. The electrical connections between layers rely on the first, second, and third vias, thereby achieving direct connections between the drive circuit layer and the power circuit layer, between the drive circuit layer and the chip layer, and between the power circuit layer and the chip layer.

[0071] The layered packaging structure of this power device allows for a creepage distance of ≥1.5mm between the power circuit layer and the drive circuit layer, meeting the high- and low-voltage isolation requirements of safety regulations for power devices. Compared with traditional solutions based on bonded wires for electrical connections, this hole-based direct connection solution generates lower parasitic inductance, eliminates fatigue fracture of bonded wires during power cycling, and improves the cyclic reliability of the power device; moreover, the small height occupied by the holes facilitates the miniaturization design of the power device.

[0072] In a specific embodiment, such as Figure 2 and Figure 3 As shown, the drive circuit layer includes: a first drive circuit layer 1022 and a second drive circuit layer 1024 stacked sequentially.

[0073] The first drive circuit layer is positioned further away from the power circuit layer than the second drive circuit layer.

[0074] The first hole includes a first sub-hole 1082 on the first drive circuit layer and a second sub-hole 1084 on the second drive circuit layer, and the projection of the first sub-hole on the second drive circuit layer coincides with the second sub-hole.

[0075] The first driving circuit layer is connected to the power circuit layer via the first sub-via and the second sub-via, and the second driving circuit layer is connected to the chip layer via the second and the third via; both the first driving circuit layer and the second driving circuit layer are used to drive the chip layer.

[0076] The first driving circuit layer is the G (Gate) driving circuit layer. The first driving circuit layer is used to output the first driving signal to the gate of the chip layer to control the rising or falling edge of the gate voltage of the chip layer, thereby realizing the fast switching of the chip layer.

[0077] The second driving circuit layer is a KS (Kelvin Source) driving circuit layer. The stacked driving circuit layer is used to output the second driving signal to the chip layer to control the switching of the chip layer.

[0078] Since the first drive circuit layer and the power circuit layer are at the same potential, the first drive circuit layer needs to establish an electrical connection with the power circuit layer. Since the second drive circuit layer is located between the second drive circuit layer and the power circuit layer, the first sub-hole on the first drive circuit layer needs to establish an electrical connection with the second sub-hole on the second drive circuit layer in order to achieve the electrical connection between the first drive circuit layer and the power circuit layer.

[0079] The larger the contact area between the conductive paste in the first sub-hole and the conductive paste in the second sub-hole, the higher the reliability of the electrical connection between the first and second sub-holes. The projection of the first sub-hole on the second drive circuit layer coincides with the second sub-hole, which maximizes the contact area between the conductive paste in the first and second sub-holes, thereby maximizing the reliability of the electrical connection between the first and second sub-holes and ensuring the correct transmission of the first drive signal.

[0080] Furthermore, since an electrical connection has already been established between the first driving circuit layer and the power circuit layer, the second hole can be provided only on the second driving circuit layer, so that the second driving circuit layer is connected to the chip layer through the second hole and the third hole, and the first driving circuit layer is electrically connected to the chip layer through the electrical connection relationship of the first driving circuit layer-power circuit layer-chip layer, thereby reducing the process complexity of the layered packaging structure of the power device.

[0081] Based on the electrical connection scheme of direct hole connection, the propagation delay of this power device's layered packaging structure is ≤1ns, enabling switching drive of the power device within 100ns. Furthermore, this layered packaging structure of the power device has low switching losses and can support high-frequency operation up to 150kHz.

[0082] In one embodiment, such as Figure 2 As shown, the chip layer includes a copper-clad ceramic substrate 1062 and a chip 1064.

[0083] Copper-clad ceramic substrates can be AMB boards (Active Metal Brazed Copper Clad Ceramic Substrate). AMB boards are high-performance electronic packaging materials that achieve a high-strength bond between the copper layer and the ceramic substrate through an active metal brazing process. AMB boards can withstand more than 3000 thermal cycles (-40℃ to 125℃) and have an insulation withstand voltage exceeding 10kV / mm. They can operate stably for extended periods in high-temperature environments above 175℃, demonstrating high reliability. Power devices equipped with AMB boards are suitable for harsh outdoor or automotive environments.

[0084] In a specific embodiment, such as Figure 4 As shown, the first driving circuit layer includes: a first ceramic plate and a first driving circuit circuit integrated on the first ceramic plate.

[0085] The signal line of the first drive circuit extends to the first sub-hole.

[0086] The signal line of the first drive circuit extends to the first sub-hole, so that the output end of the signal line of the first drive circuit contacts the first sub-hole, thereby guiding the drive signal of the first drive circuit to the first sub-hole through the first sub-hole, and then transmitting the drive signal of the first drive circuit to the power circuit layer through the first sub-hole and the second sub-hole.

[0087] like Figure 5 As shown, the second drive circuit layer includes: a second ceramic plate and a second drive circuit circuit integrated on the second ceramic plate.

[0088] The signal line of the second drive circuit extends to the second hole.

[0089] The signal line of the second drive circuit extends to the second hole, so that the output end of the signal line of the second drive circuit contacts the second hole, thereby guiding the drive signal of the second drive circuit into the second hole, and then transmitting the drive signal of the second drive circuit to the chip layer through the second hole.

[0090] The wiring structure of the signal lines and ground lines in the first and second drive circuits can both be parallel wiring structures. When using 100μm thick electrolytic copper foil and a line width of 200μm, according to transmission line theory, when the line length is ≤5mm, the characteristic impedance can be controlled within the range of 50±5Ω, so that when the signal rise time is ≤5ns, low distortion signal transmission can still be maintained.

[0091] In a specific embodiment, such as Figure 4 and Figure 5 As shown, the first drive circuit includes an independently configured first upper bridge circuit and a first lower bridge circuit, and the second drive circuit includes an independently configured second upper bridge circuit and a second lower bridge circuit.

[0092] Wherein, the projection of the circuit region where the first upper bridge circuit is located on the second drive circuit coincides with the circuit region where the second upper bridge circuit is located, and the projection of the circuit region where the first lower bridge circuit is located on the second drive circuit coincides with the circuit region where the second lower bridge circuit is located; wherein, the distance between the first upper bridge circuit and the first lower bridge circuit is greater than or equal to the insulation distance under the preset voltage requirement.

[0093] The signal line of the first upper bridge circuit extends to the first upper bridge hole in the first sub-hole, and the signal line of the first lower bridge circuit extends to the first lower bridge hole in the first sub-hole; the signal line of the second upper bridge circuit extends to the second upper bridge hole in the second hole, and the signal line of the second lower bridge circuit extends to the second lower bridge hole in the second hole.

[0094] The preset voltage requirement can be the insulation withstand voltage requirement of the power circuit layer. In one embodiment, the insulation withstand voltage requirement of the power circuit layer is above 2500V, then the preset voltage requirement can be set to above 2500V accordingly.

[0095] The first drive circuit is configured as a first upper bridge circuit and a first lower bridge circuit, and the first upper bridge circuit and the first lower bridge circuit are integrated into a... Figure 6 On the substrate shown, the stray inductance of the first drive circuit can be reduced. Similarly, the second drive circuit is configured as a second upper bridge circuit and a second lower bridge circuit, and the second upper bridge circuit and the second lower bridge circuit are integrated on a substrate as shown. Figure 6 On the substrate shown, the stray inductance of the second drive circuit can be reduced so that the inductance of the drive circuit layer is reduced to less than 6nH.

[0096] In one embodiment, the first ceramic plate can be formed by low-pressure sintering of three green ceramic strips with different dielectric constants, the total thickness of the first ceramic plate is 200μm, and the dielectric strength is ≥8kV / mm.

[0097] In one embodiment, the second ceramic plate can also be formed by low-pressure sintering of three green ceramic strips with different dielectric constants, with a total thickness of 150 μm and a dielectric strength ≥8 kV / mm.

[0098] In a specific embodiment, such as Figure 7 As shown, the power circuit layer includes: a third upper bridge circuit and a third lower bridge circuit that are independently configured, and a third ceramic plate that integrates the third upper bridge circuit and the third lower bridge circuit.

[0099] The signal lines and power lines are routed vertically; the signal lines include the signal lines of the first drive circuit and the signal lines of the second drive circuit, and the power lines include the power lines of the third upper bridge circuit and the power lines of the third lower bridge circuit.

[0100] The signal line of the third upper bridge circuit extends to the third upper bridge hole in the third hole, and the signal line of the third lower bridge circuit extends to the third lower bridge hole in the third hole.

[0101] The vertical wiring structure between the first and second drive loop circuits and the circuits on the power loop layer can reduce crosstalk between the circuits on the power loop layer and the drive loop circuits (i.e., the first and second drive loop circuits).

[0102] Similar to the first upper bridge circuit and the first lower bridge circuit, the third upper bridge circuit and the third lower bridge circuit are set up separately and integrated into a single circuit, such as... Figure 8 On the substrate shown, stray inductance of the power circuit layer can be reduced, voltage spikes can be reduced, and voltage oscillations of power devices during turn-off can be effectively suppressed.

[0103] In one embodiment, the first drive circuit layer, the second drive circuit layer, and the power circuit layer can all use 100μm thick electrolytic copper foil as the conductive medium. This copper foil has a purity of ≥99.9% and a conductivity of up to 5.9×10⁻⁶. 7 S / m can control the on-resistance of the line to below 1mΩ, thereby ensuring the current carrying capacity of the first drive circuit layer, the second drive circuit layer and the power circuit layer.

[0104] In one embodiment, the power circuit layer can use a 90μm thick electrolytic copper foil as the conductive medium. Thinner electrolyte copper foil is more conducive to the miniaturization design of power devices.

[0105] In one embodiment, the first ceramic plate, the second ceramic plate, and the third ceramic plate can be fabricated based on LTCC technology (Low-Temperature Co-fired Ceramic). LTCC refers to a ceramic-based multilayer integration technology sintered at temperatures below 900°C. The first ceramic plate, the second ceramic plate, and the third ceramic plate fabricated based on LTCC technology have high insulation, low dielectric loss, and good thermal conductivity, thereby improving the reliability of power devices.

[0106] In one embodiment, the pins beneath the power loop layer can be connected to the surface of the chip layer via a sintering process to form a 25 μm thick sintered silver layer. This sintering process has a shear strength ≥45 MPa, and the thermal conductivity of the power device obtained based on this process is ≥150 W / m·K, which is three times the thermal conductivity of conventional solder.

[0107] The power device adopts a dual-bus stacked structure with separate upper and lower bridge circuits, and also uses LTCC multilayer copper foil to form coupling capacitors, which can reduce the layout stray inductance to less than 3nH.

[0108] In one embodiment, components can be embedded in the drive loop layer and / or power loop layer to integrate components such as capacitors and resistors that can realize RC circuits (resistor-capacitance circuits) on the drive loop layer and / or power loop layer, thereby reducing the peak voltage of the module.

[0109] In a specific embodiment, such as Figure 9 As shown, a layered packaging method for power devices includes:

[0110] S902 provides a drive circuit layer and a power circuit layer; wherein the drive circuit layer has a first hole and a second hole, the power circuit layer has a third hole, and the first hole, the second hole and the third hole are all filled with conductive paste.

[0111] S904, the drive circuit layer and the power circuit layer are stacked to obtain a laminated structure; wherein, the projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the third hole.

[0112] A laminated structure can be obtained by stacking the drive circuit layer and the power circuit layer using a laminator. Specifically, the drive circuit layer and the power circuit layer are pressed together under a temperature environment of 50-100℃ and a pressure environment of 5-30MPa to form a tight bond and an integral laminated structure.

[0113] During the lamination process, it is necessary to control the uniformity of pressure to avoid interlayer bubbles or misalignment in the laminated structure, thereby ensuring the structural integrity of the power devices after subsequent sintering.

[0114] S906 is sintered in an environment with a temperature range of 600℃-900℃ to obtain a low-temperature co-fired ceramic plate.

[0115] In an environment with a temperature range of 600℃-900℃, the laminated structure can be insulated. The shortest insulation time can be 1 hour and the longest can be 4 hours. Insulation can sinter and densify the ceramic powder of the laminated structure, and at the same time, it can sinter the metal paste on the laminated structure to form conductive lines and through holes.

[0116] When the difference between the sintering shrinkage rate of the ceramic and the metal in a low-temperature co-fired ceramic plate is ≥1%, stress will be generated, leading to warping or cracking of the low-temperature co-fired ceramic plate. Therefore, shrinkage control is required during the sintering process to ensure that the difference between the sintering shrinkage rate of the ceramic and the metal in the laminated structure is <1%.

[0117] S908, prepare the chip layer and stack the low-temperature co-fired ceramic plate with the chip layer.

[0118] S910, sintering low-temperature co-fired ceramic plate and chip layer to obtain power device.

[0119] The layered packaging method described above can be used to obtain power devices based on direct hole connections. There are no conductive lines between the layers of such power devices, which can avoid the concentration of electric fields between layers. The electrical connection between the layers depends on the first hole, the second hole, and the third hole, thereby realizing the direct connection between the drive circuit layer and the power circuit layer, the direct connection between the drive circuit layer and the chip layer, and the direct connection between the power circuit layer and the chip layer.

[0120] In one embodiment, the step of sintering a low-temperature co-fired ceramic plate and a chip layer to obtain a power device includes:

[0121] The combined module is obtained by sintering a low-temperature co-fired ceramic plate and a chip layer.

[0122] The three modules are soldered onto a base plate to obtain a power device.

[0123] In one embodiment, the step of determining the chip layer includes:

[0124] Prepare the chip circuit and AMB board.

[0125] Sinter the chip circuit and AMB board to obtain the chip layer.

[0126] In one specific embodiment, the fabrication steps of the above-mentioned drive loop layer and power loop layer include:

[0127] Prepare and formulate ceramic slurry based on ceramic powder and slurry.

[0128] The ceramic powder must be selected based on its ability to withstand low-temperature sintering, such as glass ceramics (e.g., composites of borosilicate glass with Al2O3 and SiO2), cordierite (2MgO·2Al2O3·5SiO2), spinel (MgAl2O4), and other low-melting-point ceramics. The glass phase, in particular, can melt at low temperatures, promoting ceramic densification. The particle size of the ceramic powder needs to be controlled within the submicron range (1-5 μm) to reduce the sintering temperature and ensure density.

[0129] Ceramic powder is mixed with an organic binder, plasticizer, and solvent, and then ball-milled to form a uniform ceramic slurry, i.e., a casting slurry. The viscosity of the ceramic slurry needs to be precisely controlled; for example, the viscosity can be controlled within the range of 1000-5000 cP. The organic binder can be polyvinyl alcohol or acrylate.

[0130] Prepare a first carrier membrane and a second carrier membrane. Both the first and second carrier membranes can be PET (Polyethylene Terephthalate) films.

[0131] Using a casting machine, ceramic slurry is uniformly coated onto a first carrier film and a second carrier film to obtain a first green ceramic tape and a second green ceramic tape.

[0132] Using a casting machine, ceramic slurry is uniformly coated onto a first carrier film and a second carrier film, respectively. After drying to remove the solvent, a first green ceramic tape and a second green ceramic tape of uniform thickness are formed. The drying temperature can be within the range of 60-100℃.

[0133] The thickness of the first and second green porcelain strips can be adjusted according to requirements. Generally, the thickness of the first and second green porcelain strips is any value within the range of 10-200μm. The thickness of the first and second green porcelain strips must ensure a smooth surface, free of bubbles or cracks, and their mechanical properties must meet the requirements of subsequent processing. Among these mechanical properties is flexibility.

[0134] Drill holes in the first green porcelain strip to form the first hole and the second hole.

[0135] A third hole is formed by drilling holes in the second green ceramic tape. The diameters of the first, second, and third holes can be any value within the range of 50-300 μm.

[0136] Conductive paste is filled into the first, second, and third holes respectively for interlayer electrical connection.

[0137] Conductive pastes can be metal pastes. These include silver pastes, copper pastes, etc. The metal paste needs to match the sintering shrinkage rate of the ceramic powder to prevent cracking of the power devices.

[0138] The first, second, and third holes can be filled using screen printing or inkjet printing.

[0139] The drive circuit is printed on the first green ceramic tape to form a drive circuit layer.

[0140] Power circuits are printed on the second green ceramic tape to form a power circuit layer.

[0141] In one specific embodiment, the drilling method is one of mechanical punching, laser drilling, or photolithography drilling.

[0142] Mechanical punching presses can reach speeds of 100-500 punches per minute, making them suitable for continuous production and facilitating low-cost, large-scale production.

[0143] Laser drilling is highly adaptable to various materials. CO2 lasers have a high absorption rate for ceramics and glass, making them suitable for through-hole processing of LTCC green ceramic tapes. Furthermore, laser drilling is a non-contact, green manufacturing process that eliminates physical tool wear and generates no cutting debris, making it environmentally friendly.

[0144] Photolithography can achieve ultra-precision machining with hole diameters of 0.1-5μm and hole spacing of ±0.1μm. Furthermore, by replicating through a mask, photolithography can ensure that the size error of each hole in multiple power devices is <±5%, resulting in high process accuracy.

[0145] In one specific embodiment, the first carrier membrane includes a first sub-carrier membrane and a second sub-carrier membrane, and the first green ceramic tape includes a first sub-green ceramic tape and a second green ceramic tape;

[0146] The steps of drilling holes in the first green porcelain strip to form the first and second holes include:

[0147] Drill holes in the first piece of raw porcelain to form the first hole;

[0148] A hole is drilled in the second sub-green ceramic belt to form a second sub-hole and a second hole; wherein, the first hole includes a connection between the first sub-hole and the second sub-hole, and the projection of the first sub-hole on the second sub-green ceramic belt coincides with the second sub-hole.

[0149] Forming the second sub-hole only in the second sub-green ceramic strip can reduce the manufacturing complexity of power devices.

[0150] Therefore, the low-temperature co-fired ceramic (LTCC) comprises a first driving circuit layer corresponding to the first green ceramic strip, a second driving circuit layer corresponding to the second green ceramic strip, and a power circuit layer corresponding to the second green ceramic strip. Each layer consists of ceramic and wiring circuitry. After the three layers are fabricated, they are laminated to form an LTCC board, which is then sintered onto the chip layer to form a power device. The chip layer includes an AMB board and a chip sintered on the AMB board.

[0151] In one specific embodiment, after the step of stacking the drive circuit layer and the power circuit layer to obtain a laminated structure, and before the step of sintering the laminated structure, the method further includes:

[0152] Place the laminated structure in air or an inert gas.

[0153] When the conductive paste is silver, the laminate can be co-fired in air. When the conductive paste is copper, the laminate can be co-fired in an inert gas such as nitrogen to avoid oxidation of the conductive paste.

[0154] The heating temperature of the laminated structure is increased at a preset rate of change until the temperature of the laminated structure is maintained within the range of 300℃-500℃.

[0155] The preset change rate can be 1-5℃ / min. Placing the laminated structure in a slowly heating environment can drive the organic binder in the laminated structure to be removed, thereby avoiding the rapid decomposition of the organic binder in the high-temperature environment of subsequent sintering, which would lead to cracking of the preform and improve the process reliability of the layered packaging method for power devices.

[0156] In one specific embodiment, the step of sintering a low-temperature co-fired ceramic plate and a chip layer to obtain a power device further includes:

[0157] Sintering low-temperature co-fired ceramic plates and chip layers yields a co-fired structure.

[0158] Power devices are obtained by performing at least one of the following processes on the co-fired structure: cutting, surface metallization, and surface mounting.

[0159] The surface metallization process includes plating gold or nickel onto the surface of the co-fired structure.

[0160] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0161] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0162] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A layered packaging structure for a power device, characterized in that, include: The driving circuit layer, power circuit layer, and chip layer are stacked in sequence. The drive circuit layer has a first hole and a second hole, and the power circuit layer has a third hole, all of which are filled with conductive paste; the projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the projection of the third hole. The driving circuit layer is connected to the power circuit layer through the first hole, the driving circuit layer is connected to the chip layer through the second hole and the third hole, and the power circuit layer is connected to the chip layer through the third hole; the driving circuit layer is used to drive the chip layer.

2. The layered packaging structure of the power device according to claim 1, characterized in that, The drive circuit layer includes: a first drive circuit layer and a second drive circuit layer stacked sequentially; The first drive circuit layer is located further away from the power circuit layer than the second drive circuit layer. The first hole includes a first sub-hole on the first drive circuit layer and a second sub-hole on the second drive circuit layer, and the projection of the first sub-hole on the second drive circuit layer coincides with the second sub-hole; The first driving circuit layer is connected to the power circuit layer via the first sub-via and the second sub-via, and the second driving circuit layer is connected to the chip layer via the second sub-via and the third sub-via; both the first driving circuit layer and the second driving circuit layer are used to drive the chip layer.

3. The layered packaging structure of the power device according to claim 2, characterized in that, The first drive circuit layer includes: a first ceramic plate and a first drive circuit circuit integrated on the first ceramic plate; The signal line of the first drive circuit extends to the first sub-hole; The second drive circuit layer includes: a second ceramic plate and a second drive circuit circuit integrated on the second ceramic plate; The signal line of the second drive circuit extends to the second hole.

4. The layered packaging structure of the power device according to claim 3, characterized in that, The first drive circuit includes an independently configured first upper bridge circuit and a first lower bridge circuit, and the second drive circuit includes an independently configured second upper bridge circuit and a second lower bridge circuit. Wherein, the projection of the circuit region where the first upper bridge circuit is located on the second drive circuit coincides with the circuit region where the second upper bridge circuit is located, and the projection of the circuit region where the first lower bridge circuit is located on the second drive circuit coincides with the circuit region where the second lower bridge circuit is located; wherein, the distance between the first upper bridge circuit and the first lower bridge circuit is greater than or equal to the insulation distance under the preset voltage requirement. The signal line of the first upper bridge circuit extends to the first upper bridge hole in the first sub-hole, and the signal line of the first lower bridge circuit extends to the first lower bridge hole in the first sub-hole; the signal line of the second upper bridge circuit extends to the second upper bridge hole in the second hole, and the signal line of the second lower bridge circuit extends to the second lower bridge hole in the second hole.

5. The layered packaging structure of the power device according to claim 4, characterized in that, The power circuit layer includes: a third upper bridge circuit and a third lower bridge circuit that are independently configured, and a third ceramic plate that integrates the third upper bridge circuit and the third lower bridge circuit; The signal lines and power lines are routed perpendicularly; wherein, the signal lines include the signal lines of the first drive circuit and the signal lines of the second drive circuit, and the power lines include the power lines of the third upper bridge circuit and the power lines of the third lower bridge circuit; The signal line of the third upper bridge circuit extends to the third upper bridge hole in the third hole, and the signal line of the third lower bridge circuit extends to the third lower bridge hole in the third hole.

6. A layered packaging method for power devices, characterized in that, include: A drive circuit layer and a power circuit layer are provided; wherein the drive circuit layer has a first hole and a second hole, the power circuit layer has a third hole, and the first hole, the second hole and the third hole are all filled with conductive paste; The drive circuit layer and the power circuit layer are stacked to obtain a laminated structure; wherein the projection of the second hole on the drive circuit layer onto the power circuit layer coincides with the third hole. The laminated structure is sintered in an environment with a temperature range of 600℃-900℃ to obtain a low-temperature co-fired ceramic plate; Prepare the chip layer and stack the low-temperature co-fired ceramic plate with the chip layer; The power device is obtained by sintering the low-temperature co-fired ceramic plate and the chip layer.

7. The layered packaging method for power devices according to claim 6, characterized in that, The fabrication steps of the drive circuit layer and the power circuit layer include: Prepare and formulate ceramic slurry based on ceramic powder and slurry; Prepare the first and second carrier membranes; The ceramic slurry is uniformly coated onto the first carrier film and the second carrier film using a casting machine to obtain the first green ceramic tape and the second green ceramic tape respectively. Drill holes in the first green ceramic strip to form the first hole and the second hole; Drill a hole in the second green ceramic strip to form the third hole; The first hole, the second hole, and the third hole are respectively filled with conductive paste; A drive circuit layer is formed by printing a drive circuit on the first green ceramic tape. Power circuits are printed on the second green ceramic tape to form a power circuit layer.

8. The layered packaging method for power devices according to claim 7, characterized in that, The drilling method is one of mechanical punching, laser drilling, or photolithography drilling.

9. The layered packaging method for power devices according to claim 7, characterized in that, The first carrier membrane includes a first sub-carrier membrane and a second sub-carrier membrane, and the first green ceramic tape includes a first sub-green ceramic tape and a second green ceramic tape; The step of drilling holes in the first green ceramic strip to form a first hole and a second hole includes: Drill a hole in the first sub-porcelain strip to form the first sub-hole; A hole is drilled in the second green ceramic strip to form a second sub-hole and a second hole; wherein, the first hole includes a connection between the first sub-hole and the second sub-hole, and the projection of the first sub-hole on the second green ceramic strip coincides with the second sub-hole.

10. The layered packaging method for power devices according to claim 6, characterized in that, After the step of stacking the drive circuit layer and the power circuit layer to obtain a laminated structure, and before the step of sintering the laminated structure, the method further includes: Place the laminated structure in air or an inert gas; The heating temperature of the laminated structure is increased at a preset rate of change until the temperature of the laminated structure is maintained within the temperature range of 300℃-500℃.

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