Stacking structure and stacking method based on wafer level packaging

Abstract

The invention discloses a stacking structure and a stacking method based on wafer level packaging, and relates to the technical field of semiconductor packaging, and the stacking structure based on wafer level packaging comprises at least one wafer comprising an upper rewiring layer and an upper metal bonding pad group; when all wafers are applied in an up-and-down stacking posture to form an integral wafer structure, the lowermost wafer is electrically connected with the metal bonding pad groups through the lower rewiring layer on the lower surface of the lowermost wafer, the metal bonding pad groups on the upper surfaces of all the wafers are used for arranging surface-mounted components and chips and bonding leads, and the upper and lower adjacent wafers are interconnected through the metal bonding pad groups on the opposite surfaces of the upper and lower adjacent wafers. And the metal bonding pad group on the lower surface of the lowermost wafer is used for realizing external connection. According to the invention, a surface-mounted component or a circuit substrate is used as an interconnection piece, so that vertical transmission can be realized on the basis of improving the space utilization rate, parasitic inductance can be reduced, the frequency range can be widened, and the design freedom degree can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a stacking structure and a stacking method based on wafer-level packaging. BACKGROUND

[0002] Wafer-level packaging refers to packaging and testing at the wafer level, and an independent wafer-level package is obtained after packaging and testing, which can be directly used without further packaging. The wafer-level package can accommodate multiple chips, and the upper and lower surfaces of the wafer-level package can be bonded, wire-bonded, and surface-mounted, or can be provided with a solder ball array or a micro-bump array to realize the stacking of wafer-level packages.

[0003] Currently, there are mainly two methods for adding surface-mounted components in wafer-level packaging: One method is to make a redistribution layer on the upper surface of the wafer-level package, distribute solder paste, and then normally place the components to realize welding through reflow soldering. This method occupies a large amount of space on the upper surface of the wafer, and since the surface-mounted components cannot be used for vertical transmission, the number of interfaces for two-layer wafer stacking is reduced.

[0004] Another method is to embed the components in the wafer, and make a redistribution layer on the electrodes of the components to lead out the electrodes of the surface-mounted components. Since the via holes in the wafer cannot be too high, the wafer may not be able to accommodate high-height capacitors. At the same time, since the electrodes of the surface-mounted components are often tinned, embedding such electrodes in the wafer may cause serious reliability risks during subsequent module assembly due to the liquefaction of the tin on the surface.

[0005] Therefore, how to use surface-mounted components as a medium for vertical interconnection to realize vertical interconnection and improve the layout density of wafer-level packaging stacking modules is a problem that needs to be solved. SUMMARY

[0006] To solve the above technical problems, the present application provides a stacking structure and a stacking method based on wafer-level packaging.

[0007] To achieve the above purpose, the present application adopts the following technical solutions: The present application provides a stacking structure based on wafer-level packaging, comprising at least one wafer: Each wafer comprises an upper redistribution layer and an upper metal pad group; The upper redistribution layer is electrically connected and arranged on the upper surface of the wafer; The upper metal pad group is electrically connected and arranged on the upper surface of the upper redistribution layer; Based on the application of each wafer in a stacked manner, when the overall wafer structure is formed, the lowermost wafer in the overall wafer structure is electrically connected with the lower redistribution layer and the metal pad group on the lower surface; the metal pad group arranged on the upper surface of each wafer in the overall wafer structure is used to arrange the surface-mounted component, chip, and wire bonding; the upper and lower adjacent wafers are connected through the metal pad groups arranged on the opposite surfaces; and the metal pad group on the lower surface of the lowermost wafer in the overall wafer structure is used to realize external connection.

[0008] Further, the overall wafer structure further comprises an external pad group and a stacking pad group: The external pad group is arranged on the upper surface of each wafer in the overall wafer structure, and each wafer is wire-bonded with a target connection module through the external pad group on the upper surface; The stacking pad group is arranged on the upper surface of the upper redistribution layer of the uppermost wafer in the overall wafer structure, and the overall wafer structure is electrically connected with a target chip through the stacking pad group on the upper surface of the uppermost wafer.

[0009] Further, the interlayer between the upper and lower adjacent wafers in the overall wafer structure comprises a vertical interconnection: The vertical interconnection has welding contact points at both ends, and the two welding contact points are respectively welded with the metal pad groups on the opposite surfaces of the upper and lower adjacent wafers, thereby realizing the interconnection of the upper and lower wafers.

[0010] Further, after the wafer stacking is realized by using the vertical interconnection, the center axes of the wafers are collinear.

[0011] Further, the central axis of the vertical interconnection after welding is perpendicular to the center symmetry line of each wafer.

[0012] Further, the metal pad group on the lower surface of the lowermost wafer in the overall wafer structure is used to connect with the wafer interconnection, and the connection between the wafer interconnection and the external element realizes the connection between the external element and the overall wafer structure.

[0013] Further, the wafer interconnection includes but is not limited to solder, glue, micro-bump, metal wire, surface-mounted component, and vertically arranged circuit substrate.

[0014] Further, the vertical interconnection includes but is not limited to surface-mounted capacitor, surface-mounted inductor, surface-mounted resistor, radio frequency filter, and miniaturized passive circuit.

[0015] Another aspect of the present application provides a stacking method based on a wafer packaging and stacking module, which realizes the stacking by the following steps for each wafer with embedded chips and manufactured redistribution layer and metal pad group: Step S1, select a wafer as an upper wafer, use a solder paste printer to distribute solder paste to each metal pad of the upper wafer, and use a chip mounter to vertically place the vertical interconnects with fixtures on each pad of the upper wafer, and then use reflow soldering to realize welding; Step S2, select a wafer as a lower wafer, correspond each vertical interconnect of the upper wafer to each pad of the lower wafer, and then through wafer stacking to wafer process, flip the upper wafer on the lower wafer, and the central axis of the vertical interconnect is perpendicular to the center symmetry line of each wafer after flipping; Step S3, based on the preset ambient temperature, use random vibration to powder the fixture, and use a blowing device to remove all fixtures; Step S4, repeat steps S1 to S3 until all wafers have been stacked.

[0016] The beneficial effects brought by the above technical solutions are: (1) The surface-mounted device is vertically welded in the present application, so that the surface-mounted device becomes a vertical interconnection medium, and then vertical stacking interconnection is realized on the basis of improving the utilization rate of space; (2) The present application uses surface-mounted devices as vertical interconnects and circuit boards as wafer interconnects, which can realize rational use of space, reduce parasitic inductance, broaden the frequency range, and improve design freedom; (3) The present application can be compatible with various post-micro-assembly processes, improving production efficiency while ensuring reliability. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a cross-sectional schematic diagram of a wafer-level packaging stacking module based on two wafers in the embodiment and a vertical capacitor with a fixture; Figure 2 It is a cross-sectional schematic diagram of a wafer-level packaging stacking module based on a single wafer in the embodiment; Figure 3 It is a schematic diagram of a wafer-level packaging stacking module based on a vertically arranged circuit board in the embodiment; Figure 4 It is a schematic diagram of a microsystem based on multiple wafer-level packaging stacking modules in the embodiment. DETAILED DESCRIPTION

[0018] The technical solutions of the present application will be described in detail below with reference to the drawings.

[0019] Embodiment one: A stacking structure based on wafer-level packaging includes two wafers 1: Each wafer includes an upper redistribution layer 2, a lower redistribution layer 3, an upper metal pad group, and a lower metal pad group; The upper redistribution layer 2 is electrically connected to the upper surface of the wafer 1, and the lower redistribution layer 3 is electrically connected to the lower surface of the wafer 1. The upper metal pad group is electrically connected to the upper surface of the upper redistribution layer 2, and the lower metal pad group is electrically connected to the lower surface of the lower redistribution layer 3. Each wafer includes at least one through hole 5 penetrating through the upper and lower redistribution layers thereof, and the upper and lower redistribution layers 2 and 3 are electrically connected based on the through hole 5. Specifically, in the embodiment, a silicon wafer is selected as a wafer substrate, a silicon cavity structure slightly larger than the size of the embedded chip and a through hole are precisely etched on the whole silicon adapter plate through deep silicon etching. After sputtering a seed layer, copper is electroplated on the silicon through hole wall, and a metal layer is uniformly electroplated on the cavity and the surface of the silicon wafer. The embedded chip 9 is bonded in the silicon cavity through the D2W (chip-to-wafer stacking) process, wherein the bonding of the embedded chip adopts nano-silver glue with good electrical and thermal conductivity. After the chip is embedded, the pads on the surface of the chip and a surface of the wafer are substantially at the same height, and then the unhardened polyimide (PI) glue is distributed on the surface through spin coating and is planarized; then the PI is hardened at a certain temperature. After the PI is hardened, the photoetching is used to complete the patterning, the lower metal is windowed, and then the new metal layer is electroplated; the PI coating, photoetching patterning, and electroplating processes are repeated to manufacture the upper and lower redistribution layers and the metal pad group on the two surfaces of each wafer.

[0020] Reference Figure 1 When the two-wafer stacking posture is applied to form a two-layer wafer-level packaging stacking structure, the specific steps are as follows: first, select one wafer as the upper wafer, and the other wafer as the lower wafer; distribute solder paste on each pad surface of the metal pad group on the upper surface of the upper wafer layer, and then place the 01005 specification capacitor 11 with a light tool 10 and a metal cylinder 12 with a height of 0.4 mm as vertical interconnection pieces on the corresponding single pad, wherein the material of the light tool 10 is polypropylene, and the material of the metal cylinder 12 includes but is not limited to pure copper, Pb90Sn10, and surface metallized alumina ceramic. After the 01005 specification capacitor 11 and the metal cylinder 12 are placed, reflow soldering is performed to realize welding, and then the light tool 10 is powdered by using random vibration based on an environmental temperature of -55°C, and the light tool 10 is completely removed by using a blowing device to realize vertical welding of the 01005 specification capacitor 11 and the metal cylinder 12 with a height of 0.4 mm.

[0021] After arranging the vertical interconnect (capacitor + metal copper column) on the upper wafer surface, the metal pads on the upper surface can also be used to normally arrange surface-mounted components and various chips on this surface, which means that the presence of the vertical interconnect (capacitor + metal copper column) does not affect the chip bonding and wire bonding; Then, the upper wafer is flipped on the upper surface of the lower wafer through the wafer stacking (W2W) process to form a two-layer wafer-level packaging stacking structure, and the surface-mounted components 4 arranged on the metal pad group on the upper surface of the lower wafer can be used during the flipping of the upper wafer. After stacking, the surface-mounted components 4 can be arranged on the metal pad group on the upper surface of the upper wafer, or the external pad group 6 can be electrically connected and arranged on the upper surface of each wafer; the metal pad group on the lower surface of the lower wafer can also be connected with the wafer interconnect 8, and based on the connection between the wafer interconnect 8 and the external element, the connection between the external element and the two-layer wafer-level packaging stacking structure is realized, and in this embodiment, the wafer interconnect 8 is selected as a solder ball array; Finally, by segmenting the two-layer wafer-level packaging stacking structure, a two-wafer layer stacking module unit can be obtained, and when further integrating this module unit, the module unit can be soldered on a substrate through the wafer interconnect 8, and external wire bonding can also be performed through the external pad group 6, and further, the surface-mounted components 4 can be further stacked on the solderable (adhesive) area on the upper surface of the surface-mounted components 4.

[0022] Further, when integrating small-sized radio frequency module chips using the above two-layer wafer-level packaging stacking structure, the lower wafer is embedded with radio frequency devices, and the upper wafer is embedded with switches, filters, and control circuits; by changing the horizontal installation of the surface-mounted capacitors to vertical installation, vertical stacking interconnection is realized, that is, the two ends of the capacitor are respectively connected to the metal pads on the opposite surfaces of the adjacent upper and lower wafers, and the capacitor and the parallel metal copper column together form a vertical channel, wherein the capacitor provides an AC coupling path to realize radio frequency cross-layer transmission, and the capacitor is directly integrated on the signal path to form an embedded high-pass or band-pass filter to suppress low-frequency noise and DC bias interference; the solder balls or copper columns provide support, heat dissipation, and transmission.

[0023] Embodiment two: A wafer-level packaging stacking structure includes a wafer 1: The wafers each include an upper redistribution layer 2, a lower redistribution layer 3, an upper metal pad group, and a lower metal pad group; The upper redistribution layer 2 is electrically connected and arranged on the upper surface of the wafer 1, and the lower redistribution layer 3 is electrically connected and arranged on the lower surface of the wafer 1; The upper metal pad group is electrically connected and arranged on the upper surface of the upper redistribution layer 2, and the lower metal pad group is electrically connected and arranged on the lower surface of the lower redistribution layer 3; The wafer includes at least one through hole 5 penetrating the upper redistribution layer and the lower redistribution layer, and the upper redistribution layer 2 and the lower redistribution layer 3 are electrically connected based on the through hole 5. Specifically, referring to Figure 2 In this embodiment, a silicon wafer is selected as a wafer substrate to form a wafer-level packaging structure. The specific steps are as follows: first, the method for manufacturing a multi-layer wiring and related pads in the first embodiment is used to manufacture the upper redistribution layer, the lower redistribution layer and the metal pad group on the two surfaces of the wafer in this embodiment, and a direction mark 13 is manufactured on the upper redistribution layer. After the wafer layer is prepared, a 01005-specification capacitor 11 and a resistor 14 are arranged on the upper redistribution layer 2 through a conventional surface mounting process; In this embodiment, the metalized area 15 on the upper surface of the electrode of the 01005-specification capacitor 11 is designed in shape, so that the shape tends to be a square, which is convenient for the combination with the external micro-bumps, and at this time, the upper surface of the electrode of the resistor 14 is not used as an interface for welding or bonding with the external environment; Then, the metal pad group on the lower surface of the wafer is connected with the wafer interconnect 8, and based on the connection of the wafer interconnect 8 with the external elements, the connection of the external elements with the wafer-level packaging structure is achieved. In this embodiment, the wafer interconnect 8 is selected as a solder ball array. Finally, the wafer-level packaging structure is segmented to obtain a wafer module unit. In use, the wafer module unit is first inverted and mounted on a substrate through the wafer interconnect 8; and then, the wafer module unit is wire-bonded with other wafer-level packaging modules (regarded as external modules) inverted on the same substrate through the external pads 6 arranged on the upper surface of the upper redistribution layer 2. Due to the different heights of the micro-bumps on the bottom of the external modules, the external modules can be directly inverted on the wafer module unit, that is, part of the micro-bumps on the bottom of the external modules are combined with the stacked pad group 7 arranged on the upper surface of the upper redistribution layer of the wafer, and the other part of the micro-bumps are combined with the metalized area 15.

[0024] Embodiment three A stacked structure based on wafer-level packaging includes a wafer 1: Each wafer includes an upper redistribution layer 2, a lower redistribution layer 3, an upper metal pad group and a lower metal pad group; The upper redistribution layer 2 is electrically connected and arranged on the upper surface of the wafer 1, and the lower redistribution layer 3 is electrically connected and arranged on the lower surface of the wafer 1; The upper metal pad group is electrically connected and arranged on the upper surface of the upper redistribution layer 2, and the lower metal pad group is electrically connected and arranged on the lower surface of the lower redistribution layer 3; Each wafer includes at least one through hole 5 penetrating the upper redistribution layer and the lower redistribution layer, and the upper redistribution layer 2 and the lower redistribution layer 3 are electrically connected based on the through hole 5. Specifically, referring to Figure 3 In this embodiment, a silicon wafer is selected as the wafer substrate to form a one-layer wafer-level packaging structure based on the vertically arranged circuit substrate. The specific steps are as follows: first, the method for manufacturing the multi-layer wiring and the related pad in Embodiment 1 is used to manufacture the upper redistribution layer, the lower redistribution layer, and the metal pad group on the two surfaces of the wafer in this embodiment. After the wafer surface is prepared, the 0201 specification capacitor 16 is arranged on the upper redistribution layer 2 through the conventional surface mounting process. At the same time of arranging the 0201 specification capacitor 16, the external pad group 6 can also be electrically connected and arranged on the upper surface of the upper redistribution layer 2, so that the wafer is wire-bonded with the target wafer-level packaging module through the external pad group 6 on the upper surface; the stacking pad group 15 can also be electrically connected and arranged on the upper surface of the upper redistribution layer 2 of the wafer, and the first chip 18 with the micro-bump 17 is flip-chip mounted on the upper redistribution layer 2; Then, the metal pad group on the lower surface of the wafer is connected with the wafer interconnect 8. Based on the connection of the wafer interconnect 8 with the external element, the connection of the external element with the one-layer wafer-level packaging structure based on the vertically arranged circuit substrate is realized. In this embodiment, the wafer interconnect 8 is selected as the first vertically arranged circuit substrate 19 and the second vertically arranged circuit substrate 20. The second vertically arranged circuit substrate 20 includes the second chip 21 and the first gold wire 22. The second chip 21 is adhered to the second vertically arranged circuit substrate 20 through conductive adhesive, and the first gold wire 22 is used to connect the pad of the second chip 21 with the second vertically arranged circuit substrate 20. Finally, the one-layer wafer-level packaging structure based on the vertically arranged circuit substrate is segmented to obtain a one-layer wafer module unit based on the vertically arranged circuit substrate.

[0025] Further, referring to Figure 4 Since the end face of the second vertically arranged circuit substrate 20 has a weldable port, a plurality of one-layer wafer module units based on the vertically arranged circuit substrate are welded on the mainboard 23 through the weldable port. The mainboard 23 has multiple layers of circuits, which can realize the connection between the module units 24, and the module units 24 can be interconnected through the second gold wire 25.

[0026] The above is only a preferred embodiment of the present application, and does not limit the present application. Any simple modification, change, and equivalent structural change made according to the technical essence of the present application to the above embodiment are still within the protection scope of the technical solution of the present application.

Claims

1. A stacked structure based on wafer level packaging, characterized by, The application relates to a wafer structure. Each wafer comprises an upper redistribution layer (2) and an upper metal pad group; The upper redistribution layer (2) is electrically connected to the upper surface of the wafer (1); The upper metal pad group is electrically connected to the upper surface of the upper redistribution layer (2); When the wafers are stacked in the above-down manner, the lowermost wafer in the wafer structure is electrically connected to the lower redistribution layer (3) and the metal pad group on the lower surface; the metal pad groups on the upper surfaces of the wafers are used for arranging surface-mounted components (4), chips and wire bonds; the upper and lower adjacent wafers are interconnected through the metal pad groups arranged on the opposite surfaces; and the metal pad group on the lower surface of the lowermost wafer is used for external connection.

2. The wafer level package based stacked structure of claim 1, wherein, The wafer structure further comprises an external pad group (6) and a stacking pad group (7); The external pad group (6) is electrically connected to the upper surface of each wafer in the wafer structure, and the upper surface of each wafer is wire-bonded to a target connection module through the external pad group (6); The stacking pad group (7) is electrically connected to the upper surface of the uppermost wafer in the wafer structure, and the wafer structure is electrically connected to a target chip through the stacking pad group (7) on the upper surface of the uppermost wafer.

3. The wafer level package based stacked structure of claim 1, wherein, The wafer structure further comprises a vertical interconnection between the adjacent wafers; The vertical interconnection has two welding contact points, and the two welding contact points are welded to the metal pad groups on the opposite surfaces of the upper and lower adjacent wafers, thereby realizing the interconnection between the upper and lower wafers.

4. The wafer level package based stacked structure of claim 3, wherein, After the wafers are stacked by the vertical interconnection, the central axes of the wafers are collinear.

5. The wafer level package based stacked structure of claim 4, wherein, The central axis of the vertical interconnection is perpendicular to the central symmetry line of each wafer after welding.

6. The wafer level package based stacked structure of claim 1, wherein, The metal pad group on the lower surface of the lowermost wafer in the wafer structure is connected to the wafer interconnection, and the wafer interconnection (8) is connected to an external component, thereby realizing the connection between the external component and the wafer structure.

7. The wafer level package based stacked structure of claim 6, wherein, The wafer interconnection (8) comprises but is not limited to solder, glue, micro-bump, metal wire, surface-mounted component and vertically arranged circuit substrate.

8. The wafer level package based stacked structure of claim 3, wherein, The vertical interconnection comprises but is not limited to surface-mounted capacitor, surface-mounted inductor, surface-mounted resistor, radio frequency filter and miniaturized passive circuit.

9. A stacking method for the stacked module based on the wafer level package according to any one of claims 1 to 8, characterized by, The wafers with embedded chips, redistribution layers and metal pad groups are stacked according to the following steps: Step S1: selecting a wafer as an upper wafer, dispensing solder paste on each metal pad of the upper wafer by using a solder paste printer, and vertically placing a vertical interconnection with a jig on each pad of the upper wafer by using a chip mounter, thereby realizing welding by using reflow soldering; Step S2: selecting a wafer as a lower wafer, corresponding the vertical interconnection of the upper wafer to the pad of the lower wafer, and then inverting the upper wafer on the lower wafer by wafer stacking technology, and the central axis of the vertical interconnection is perpendicular to the central symmetry line of each wafer after inversion; Step S3: based on a preset environmental temperature, making the jig powder by using random vibration, and removing all jigs by using a blowing device. Step S4, steps S1 to S3 are repeatedly performed until all wafers have completed stacking.

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