Timing window shielding circuit and trigger for anti-radiation integrated circuit
By introducing a timing window shielding circuit into the radiation-hardened integrated circuit, and using a protection pulse generation module and a signal shielding logic module to isolate the SET pulse, the SET sensitivity problem of the control signal line is solved, achieving efficient and low-overhead SET protection, which is suitable for various process nodes and circuit structures.
Patent Information
- Application Number
- CN202511705754.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2045-11-20
AI Technical Summary
In existing radiation-hardened integrated circuit designs, control signal lines are sensitive to single-event transient (SET) pulses, leading to single-event upsets (SEUs). Furthermore, traditional filtering techniques introduce excessive signal delays or overhead, making it difficult to meet high-performance requirements.
A timing window shielding circuit is adopted, including a protection pulse generation module and a signal shielding logic module. By generating a protection pulse synchronized with the system clock, the SET pulse is isolated within the timing sensitive window. The design is implemented by standard digital units. The protection window is extremely short and only opens after the clock edge, so it does not affect the timing performance of the circuit.
It effectively eliminates single-event upsets caused by SET pulses, has strong circuit design versatility, low overhead, is suitable for various process nodes, meets the requirements of high-performance radiation-hardened integrated circuits, and has high robustness.
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Figure CN121173255A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of integrated circuit hardening design, and relates to a timing window shielding circuit and a flip-flop for a radiation-hardened integrated circuit. BACKGROUND
[0002] In the electronic system of high-reliability application fields such as aerospace, integrated circuits (ICs) are always under the severe test of space radiation environment. High-energy particles (such as protons and heavy ions) in the space radiation environment incident to semiconductor devices will cause single event effects (SEEs), and SET pulses are one of the main causes of circuit soft errors. SET pulses appear as a short glitch of the voltage or current of the internal nodes of the circuit, and when they propagate to the clock or control signal end (such as reset and set) of the timing circuit (such as flip-flop and latch), they will bring disastrous consequences.
[0003] The most sensitive moment of the flip-flop to the SET pulse occurs near the active transition edge (such as the rising edge) of the clock signal. During this period, the latch inside the flip-flop is in the critical phase of sampling and state updating (i.e. the setup time and hold time window), and the circuit node stability is the worst. If a SET pulse appears on the control signal line at this time, the pulse is extremely easy to be mistaken by the flip-flop as a valid control command (such as a valid reset signal) and be captured, and then the flip-flop output state will occur an unexpected and permanent error flip, i.e. single event upset (SEU), which may eventually lead to the failure of the entire electronic system.
[0004] In the existing circuit-level redundancy hardening (such as DICE structure) design, although it can improve the anti-SEU capability of the storage unit itself, the global control signal path such as reset and set is usually not designed with the same degree of redundancy, and it is still a weak link sensitive to SET, which cannot solve the SET problem on the control signal line; and the traditional filtering technology uses simple RC filtering or glitch detection logic to achieve hardening, which can filter some SET pulses, but will introduce significant signal delay, affecting the highest working frequency of the circuit, and the filtering threshold is also easily affected by process, voltage and temperature (PVT) changes, and the reliability is not high. Many traditional hardening schemes either have too much overhead in performance (speed, area and power consumption) or cannot accurately and efficiently protect the most dangerous period, and the performance and reliability are in conflict, which is difficult to meet the application requirements of modern high-performance radiation-hardened integrated circuits. SUMMARY
[0005] In view of the problems in the prior art, the application provides a timing window shielding circuit for an anti-radiation integrated circuit, a hardened flip-flop and a Flash cell data storage method, which can accurately, efficiently and with low overhead shield SET interference in a timing sensitive window, and meet the application requirements of modern high-performance anti-radiation integrated circuits.
[0006] In order to achieve the above object, the embodiments of the application adopt the following technical solutions: In one aspect, the application provides a timing window shielding circuit for an anti-radiation integrated circuit, which comprises a protection pulse generation module and a signal shielding logic module, an input end of the protection pulse generation module is used to access a system clock signal, an output end of the protection pulse generation module is connected to one input end of the signal shielding logic module, another input end of the signal shielding logic module is used to access a to-be-protected signal of the integrated circuit, and an output end of the signal shielding logic module is used to output a SET shielded signal. The protection pulse generation module is used to generate a protection pulse synchronized with the system clock, and the signal shielding logic module is used to shield a SET pulse of the to-be-protected signal in a protection window provided by the protection pulse. The width of the protection pulse satisfies T_d >= T_setup + T_hold + T_margin, T_d is the width of the protection pulse, T_setup is the shortest time for which the to-be-protected signal must be kept stable before the effective transition edge of the clock signal arrives, T_hold is the shortest time for which the to-be-protected signal must be kept stable after the effective transition edge of the clock signal arrives, and T_margin is an additional time buffer based on the sum of the shortest times T_setup and T_hold.
[0007] In one embodiment, the protection pulse generation module comprises a delay unit and a logic combination unit, the delay unit comprises an even number of inverters connected in series, and an input end of the delay unit is used to access the system clock signal. The logic combination unit comprises an AND gate and an inverter, an input end of the inverter of the logic combination unit is connected to an output end of the delay unit, an output end of the inverter of the logic combination unit is connected to one input end of the AND gate, another input end of the AND gate is used to access the system clock signal, and an output end of the AND gate is used to output the protection pulse.
[0008] In one embodiment, the delay unit comprises four inverters connected in series.
[0009] In one embodiment, the protection pulse generation module generates a protection pulse with a width equal to a fixed delay generated by the delay unit in each clock cycle.
[0010] In one of the embodiments, the protection window is opened when the protection pulse is high, and the protection window is closed when the protection pulse is low.
[0011] In one of the embodiments, the signal shielding logic module comprises an AND gate and an inverter, the input of the inverter of the signal shielding logic module is connected to the output of the protection pulse generation module, the output of the inverter of the signal shielding logic module is connected to one input of the AND gate, and the other input of the AND gate is used to input the signal to be protected; when the protection window is closed, the signal output by the AND gate completely follows the signal to be protected; and when the protection window is opened, the signal output by the AND gate is forced to be invalid.
[0012] In another aspect, a hardened flip-flop is also provided, comprising the timing window shielding circuit for the radiation-hardened integrated circuit described above, and the timing window shielding circuit is integrated in the signal path of the flip-flop to be protected, and the timing window shielding circuit is used to isolate the SET pulse in the signal path to be protected; the signal path to be protected comprises a reset signal path and a set signal path.
[0013] One of the technical solutions described above has the following advantages and beneficial effects: The timing window shielding circuit for the radiation-hardened integrated circuit and the flip-flop described above solve the SET problem from the "time domain" angle, directly act on the root cause of the error, i.e. the timing sensitive window, make the protection strategy accurate, and effectively eliminate most single event upsets caused by SET pulses. The circuit design has strong universality, can be used as an independent circuit architecture without relying on a specific circuit structure, and can be flexibly applied to various timing circuits that need to be protected; since the protection window is extremely short and is only opened after the clock edge, it will not change the setup time and hold time of the original circuit, has no effect on the system operating frequency and timing performance, has almost zero performance overhead, and perfectly solves the problem of performance degradation caused by traditional filtering technology. The designed circuit is entirely realized by standard digital cells, the circuit structure is simple, the area and power consumption overhead is extremely low, and the circuit is easy to integrate at various process nodes, has good low-power and low-cost characteristics. Moreover, the width of the protection pulse is determined by the physical size of the delay chain, is less affected by environmental factors, is stable and reliable in operation, can accurately and efficiently shield the SET interference in the timing sensitive window with low overhead, and meets the application requirements of modern high-performance radiation-hardened integrated circuits. BRIEF DESCRIPTION OF DRAWINGS
[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0015] Figure 1 A module structure diagram of a timing window shielding circuit for an anti-radiation integrated circuit in an embodiment; Figure 2 A module principle diagram of a delay unit in an embodiment; Figure 3 A circuit diagram of a logic combination unit in an embodiment; Figure 4 A simulation waveform diagram of a protection pulse generation in an embodiment; Figure 5 A circuit diagram of a signal shielding logic module in an embodiment; Figure 6 A schematic diagram of one of the overall structures of a timing window shielding circuit in an embodiment; Figure 7 A simulation waveform diagram of a protected signal generation in an embodiment. DETAILED DESCRIPTION
[0016] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.
[0017] It should be noted that the term "embodiment" mentioned herein means that the specific features, structures or characteristics described in conjunction with the embodiments can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used herein refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.
[0018] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0019] In one embodiment, as shown in FIG. 1, the timing window shielding circuit for the anti-radiation integrated circuit includes a signal shielding logic module 1, a delay unit 2, a logic combination unit 3, and a protection pulse generation 4. Figure 1As shown, a timing window shielding circuit for anti-radiation integrated circuit is provided, which comprises a protection pulse generation module and a signal shielding logic module. An input end of the protection pulse generation module is connected to a system clock signal, and an output end of the protection pulse generation module is connected to an input end of the signal shielding logic module. Another input end of the signal shielding logic module is connected to a signal to be protected of the integrated circuit, and an output end of the signal shielding logic module is used to output a SET shielded signal. The protection pulse generation module is used to generate a protection pulse synchronized with the system clock, and the signal shielding logic module is used to isolate the SET pulse of the signal to be protected within the protection window provided by the protection pulse.
[0020] wherein the width of the protection pulse satisfies: T_d≥T_setup+T_hold+T_margin, T_d is the width of the protection pulse, T_setup is the shortest time for which the input signal to be protected must remain stable before the effective transition edge of the clock signal arrives, T_hold is the shortest time for which the input signal to be protected must continue to remain stable after the effective transition edge of the clock signal arrives, and T_margin is an additional time buffer based on the sum of the shortest times T_setup and T_hold.
[0021] It can be understood that the core design concept of the embodiment is to establish a dynamic protection window synchronized with the effective edge of the clock for the timing circuit, and to actively shield all changes of the input signal within the dynamic protection window, so as to fundamentally eliminate the possibility of SET pulse sampling.
[0022] The protection pulse generation module serves as the "clock" of the protection window, and is used to generate a protection pulse precisely synchronized with the system clock. The signal shielding logic module serves as the "executor" of the protection window, and is used to isolate the sensitive signal within the protection window.
[0023] The timing window shielding circuit for the anti-radiation integrated circuit solves the SET problem from the "time domain" perspective, directly acts on the root of error occurrence, i.e. the timing sensitive window, makes the protection strategy accurate, and can effectively eliminate most single event upsets caused by SET pulses. The circuit design has strong universality and can be used as an independent circuit architecture without relying on specific circuit structures. It can be flexibly applied to various timing circuits that need protection, such as but not limited to DICE flip-flop, TMR (Triple Modular Redundancy) system, latch and shift register, etc., and has high universality. Since the protection window is very short and only opens after the clock edge, it does not change the setup time and hold time of the original circuit, has no effect on the system operating frequency and timing performance, and has almost zero performance overhead, perfectly solving the problem of performance degradation caused by traditional filtering technology. The designed circuit is realized by standard digital cells, the circuit structure is simple, the area and power consumption overhead is extremely low, and it is easy to integrate at various process nodes, with good low-power and low-cost characteristics. Moreover, the width of the protection pulse is determined by the physical size of the delay chain, which is less affected by environmental factors, stable and reliable in operation, and has high robustness, which is more suitable for application in harsh radiation environments.
[0024] In one embodiment, the protection pulse generation module includes a delay unit and a logic combination unit. The delay unit includes an even number of inverters connected in series, and an input end of the delay unit is used to access a system clock signal. The logic combination unit includes an AND gate and an inverter, an input end of the inverter of the logic combination unit is connected to an output end of the delay unit, an output end of the inverter of the logic combination unit is connected to one input end of the AND gate, the other input end of the AND gate is used to access the system clock signal, and an output end of the AND gate is used to output the protection pulse.
[0025] Specifically, the protection pulse generation module includes a delay unit and a logic combination unit, as shown in Figure 2 The delay unit is composed of multiple levels of logic gates (preferably an even number of inverters connected in series), which is used to generate a fixed delay (denoted as T_d) for the input clock signal CLK (i.e. the system clock signal) of the integrated circuit and output a delayed clock signal (denoted as CLK_d). The delay unit adopts an inverter chain implementation, which ensures that the fixed delay T_d has consistent process, voltage and temperature (PVT) characteristics with the timing parameters (such as setup time and hold time) of the flip-flop itself. When the sensitive window of the flip-flop is widened or narrowed due to environmental changes (such as space radiation), the width of the protection window provided by the delay unit can adaptively change, so that reliable protection can be provided under various working conditions, greatly improving the robustness of the integrated circuit. At the same time, the design of the delay unit is essentially based on standard digital cells, and the circuit structure is simple, which is easy to transplant and integrate at different process nodes.
[0026] As shown in Figure 3As shown, the logic combination unit can be composed of an AND gate and an inverter, the first input of the AND gate is connected to the original clock signal CLK, and the second input of the AND gate is connected to the inverted signal N_CLK_d of the delayed clock signal CLK_d (obtained through an inverter between the delay unit and the AND gate). Figure 3 In the figure, the terminal circuits with the same signal name are connected, and the same applies hereinafter. The working principle is as follows: When the active edge (taking the rising edge as an example) of the original clock signal CLK arrives, the clock signal CLK immediately becomes high level, while the delayed clock signal CLK_d is still low level due to the delay, and the inverted signal N_CLK_d is high level. At this time, the two inputs of the logic combination unit are both high level, and the output protection pulse (which can be denoted as GPulse) becomes high level. In some embodiments, when the protection pulse is high level, the protection window is opened; when the protection pulse is low level, the protection window is closed. It can be understood that the embodiment defines that when the protection pulse GPulse is high level, it indicates that the protection window is opened; when the protection pulse GPulse is low level, it indicates that the protection window is closed, thereby efficiently and accurately indicating the opening and closing of the protection window, and improving the subsequent shielding efficiency (eliminating the re-judgment operation of whether the protection window is opened).
[0027] In some embodiments, after a fixed delay T_d, the delayed clock signal CLK_d becomes high level, the inverted signal N_CLK_d becomes low level, and the output of the logic combination unit becomes low level, and the protection window is closed. Thus, the protection pulse generation module generates a protection pulse with a width equal to the fixed delay generated by the delay unit in each clock cycle, that is, a protection pulse GPulse with a width equal to the fixed delay T_d in each clock cycle. Figure 4 The clock signal CLK generates a delayed clock signal CLK_d through four inverters in series under smic55nm process, 25° and tt process angle, and generates a protection pulse GPulse through the protection pulse generation module. Figure 3 The circuit shown generates a waveform diagram of the protection pulse GPulse.
[0028] In one embodiment, the signal shielding logic module includes an AND gate and an inverter, the input of the inverter of the signal shielding logic module is connected to the output of the protection pulse generation module, the output of the inverter of the signal shielding logic module is connected to one input of the AND gate, and the other input of the AND gate is used to input the to-be-protected signal. When the protection window is closed, the signal output by the AND gate completely follows the to-be-protected signal; when the protection window is opened, the signal output by the AND gate is forced to be invalid level.
[0029] Specifically, the signal shielding logic module adopts an AND gate (AND) as the main module structure. The integrated circuit to be protected signals (such as but not limited to data signal D and reset signal R) and the inverse signal N_Gpulse of the protection pulse GPulse (obtained by an inverter) are used as the two input signals of the signal shielding logic module. The working principle of the signal shielding logic module is as follows: In the normal period (the protection pulse GPulse is low): the inverse signal N_GPulse of the protection pulse GPulse is high, and the output of the signal shielding logic module completely follows the original input signal (i.e. the to-be-protected signal). In the protection period (the protection pulse GPulse is high): the inverse signal N_GPulse of the protection pulse GPulse is low, and the output of the signal shielding logic module is forced to be logic '0' (or invalid level), regardless of whether there is a SET pulse on the original input signal, it is effectively shielded. Take the protection of the reset signal R as an example, the circuit diagram of the signal shielding module is shown in Figure 5 .
[0030] In some embodiments, the above-mentioned timing window shielding circuit can be integrated into (for example, directly connected between the to-be-protected signal and its back-end processing circuit, so that the to-be-protected signal passes through the timing window shielding circuit before connecting to the back-end processing circuit) the reset signal path and the set signal path of the anti-radiation DICE flip-flop (rising edge jump type). Take the protection of the reset signal R as an example: the external reset signal R is connected to the signal shielding logic module, and the output of the shielded reset signal RMasked is connected to the DICE latch unit of the anti-radiation DICE flip-flop. This circuit structure not only maintains the high reliability of the DICE flip-flop itself, but also greatly solves the SET sensitivity problem of the control signal path.
[0031] In one embodiment, the delay unit includes four inverters connected in series. It can be understood that, Figure 6 an embodiment example of the delay unit using four inverters connected in series to protect the reset signal R is shown, Figure 7 a simulation waveform diagram of the timing shielding circuit protecting the reset signal is also shown. Near the effective edge of the clock (taking the rising edge as an example), an error pulse (SET pulse) is injected into the flip-flop reset signal to generate the disturbed reset signal R_SET. The protected reset signal RMasked can be obtained through the timing window shielding circuit. Those skilled in the art can understand that the specific number of inverters connected in series in the delay unit can be adjusted according to the process node of the applied integrated circuit and the required fixed delay T_d, and the simulation method can be used to determine whether the protection effect is accurate and meets the expected requirements.
[0032] In the above embodiment, the width of the protection pulse GPulse (i.e. the fixed delay T_d) is a key technical parameter, and its design needs to satisfy: T_d ≥ T_setup + T_hold + T_margin, to ensure that the timing sensitive window of the protected timing unit in the applied integrated circuit is completely covered. Among them, T_setup refers to the shortest time that the input signal to be protected (for example, but not limited to, data signal D and reset signal R) needs to be kept stable before the active transition edge (such as rising edge) of the clock signal CLK arrives; T_hold refers to the shortest time that the input signal to be protected needs to continue to be kept stable after the active transition edge of the clock signal CLK arrives; T_margin is an additional time buffer based on the sum of the shortest times T_setup and T_hold. This design margin of increasing the time buffer T_margin is to cope with the process deviation, environmental change and signal integrity of the integrated circuit, and the design margin is added to ensure that the protection window can completely cover the sensitive period of the protected timing circuit in the worst case, thereby further greatly improving the robustness and reliability of the circuit.
[0033] The fixed delay T_d can be precisely configured by adjusting the number of inverters and the size of transistors in the delay unit, to ensure that its width T_d (i.e. the width of the protection pulse) can completely cover the timing sensitive window of the protected timing circuit under all process, voltage and temperature (PVT) conditions. The specific number of inverters and the size of transistors required to achieve the desired fixed delay T_d can be determined by conventional circuit simulation means.
[0034] In one embodiment, a hardened flip-flop is also provided, which includes the timing window shielding circuit for the radiation-hardened integrated circuit described above. The timing window shielding circuit is integrated in the protected signal path of the flip-flop, and is used to isolate the SET pulse in the protected signal path; the protected signal path includes a reset signal path and a set signal path.
[0035] It can be understood that at least one of the reset signal path and the set signal path in the hardened flip-flop of the embodiment integrates the timing window shielding circuit for the radiation-hardened integrated circuit described above (other signal paths that also need protection can also integrate the timing window shielding circuit in the same way), and the specific explanation and description can be understood in the same way as the description of the timing window shielding circuit for the radiation-hardened integrated circuit described above. Moreover, the composition of the existing other circuit units of the hardened flip-flop and their connection relationship can be understood in the same way as the existing circuit composition of the circuit units in the existing hardened flip-flop, and will not be expanded here.
[0036] The above reinforced flip-flop can effectively eliminate most single event upsets caused by SET pulses by integrating the above timing window shielding circuit for radiation-resistant integrated circuits in the signal path to be protected, thereby improving the single event upset resistance of the flip-flop.
[0037] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.
[0038] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and all of them belong to the protection scope of the present application.
Claims
1. A timing window shielding circuit for radiation-hardened integrated circuits, characterized in that, It includes a protection pulse generation module and a signal shielding logic module. The input terminal of the protection pulse generation module is used to receive the system clock signal. The output terminal of the protection pulse generation module is connected to one input terminal of the signal shielding logic module. The other input terminal of the signal shielding logic module is used to receive the signal to be protected of the integrated circuit. The output terminal of the signal shielding logic module is used to output the signal after SET shielding. The protection pulse generation module is used to generate a protection pulse synchronized with the system clock, and the signal shielding logic module is used to perform SET pulse isolation on the signal to be protected within the protection window provided by the protection pulse. The width of the protection pulse satisfies: T_d ≥ T_setup + T_hold + T_margin, where T_d is the width of the protection pulse, T_setup is the shortest time during which the input signal to be protected must remain stable before the effective transition edge of the clock signal arrives, T_hold is the shortest time during which the input signal to be protected must continue to remain stable after the effective transition edge of the clock signal arrives, and T_margin is an additional buffer time added on top of the sum of the shortest times T_setup and T_hold.
2. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 1, characterized in that, The protection pulse generation module includes a delay unit and a logic combination unit. The delay unit includes an even number of inverters connected in series. The input of the delay unit is used to connect to the system clock signal. The logic combination unit includes an AND gate and an inverter. The input of the inverter in the logic combination unit is connected to the output of the delay unit. The output of the inverter in the logic combination unit is connected to one input of the AND gate. The other input of the AND gate is used to input the system clock signal. The output of the AND gate is used to output a protection pulse.
3. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 2, characterized in that, The delay unit consists of four inverters connected in series.
4. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 2 or 3, characterized in that, The protection pulse generation module generates a protection pulse with a width exactly equal to the fixed delay generated by the delay unit in each clock cycle.
5. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 4, characterized in that, The protection window is open when the protection pulse is high; the protection window is closed when the protection pulse is low.
6. The timing window shielding circuit for radiation-hardened integrated circuits according to claim 1, characterized in that, The signal shielding logic module includes an AND gate and an inverter. The input of the inverter in the signal shielding logic module is connected to the output of the protection pulse generation module. The output of the inverter in the signal shielding logic module is connected to one input of the AND gate, and the other input of the AND gate is used to input the signal to be protected. When the protection window is closed, the signal output by the AND gate completely follows the signal to be protected. When the protection window is open, the signal output by the AND gate is forced to an invalid level.
7. A ruggedized trigger, characterized in that, The timing window shielding circuit for radiation-resistant integrated circuits as described in any one of claims 1 to 6 is integrated into the signal path to be protected of the trigger, and the timing window shielding circuit is used to isolate the SET pulse in the signal path to be protected. The signal path to be protected includes the reset signal path and the set signal path.